1 /* $NetBSD: if_stge.c,v 1.69 2019/05/28 07:41:49 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.69 2019/05/28 07:41:49 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int, uint16_t *); 282 static int stge_mii_writereg(device_t, int, int, uint16_t); 283 static void stge_mii_statchg(struct ifnet *); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 struct mii_data * const mii = &sc->sc_mii; 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pci_intr_handle_t ih; 381 const char *intrstr = NULL; 382 bus_space_tag_t iot, memt; 383 bus_space_handle_t ioh, memh; 384 bus_dma_segment_t seg; 385 prop_data_t data; 386 int ioh_valid, memh_valid; 387 int i, rseg, error; 388 const struct stge_product *sp; 389 uint8_t enaddr[ETHER_ADDR_LEN]; 390 char intrbuf[PCI_INTRSTR_LEN]; 391 392 callout_init(&sc->sc_tick_ch, 0); 393 394 sp = stge_lookup(pa); 395 if (sp == NULL) { 396 printf("\n"); 397 panic("ste_attach: impossible"); 398 } 399 400 sc->sc_rev = PCI_REVISION(pa->pa_class); 401 402 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 403 404 /* 405 * Map the device. 406 */ 407 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 408 PCI_MAPREG_TYPE_IO, 0, 409 &iot, &ioh, NULL, NULL) == 0); 410 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 411 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 412 &memt, &memh, NULL, NULL) == 0); 413 414 if (memh_valid) { 415 sc->sc_st = memt; 416 sc->sc_sh = memh; 417 } else if (ioh_valid) { 418 sc->sc_st = iot; 419 sc->sc_sh = ioh; 420 } else { 421 aprint_error_dev(self, "unable to map device registers\n"); 422 return; 423 } 424 425 sc->sc_dmat = pa->pa_dmat; 426 427 /* Enable bus mastering. */ 428 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 429 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 430 PCI_COMMAND_MASTER_ENABLE); 431 432 /* power up chip */ 433 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 434 error != EOPNOTSUPP) { 435 aprint_error_dev(self, "cannot activate %d\n", error); 436 return; 437 } 438 /* 439 * Map and establish our interrupt. 440 */ 441 if (pci_intr_map(pa, &ih)) { 442 aprint_error_dev(self, "unable to map interrupt\n"); 443 return; 444 } 445 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 446 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc, 447 device_xname(self)); 448 if (sc->sc_ih == NULL) { 449 aprint_error_dev(self, "unable to establish interrupt"); 450 if (intrstr != NULL) 451 aprint_error(" at %s", intrstr); 452 aprint_error("\n"); 453 return; 454 } 455 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 456 457 /* 458 * Allocate the control data structures, and create and load the 459 * DMA map for it. 460 */ 461 if ((error = bus_dmamem_alloc(sc->sc_dmat, 462 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 463 0)) != 0) { 464 aprint_error_dev(self, 465 "unable to allocate control data, error = %d\n", error); 466 goto fail_0; 467 } 468 469 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 470 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 471 BUS_DMA_COHERENT)) != 0) { 472 aprint_error_dev(self, 473 "unable to map control data, error = %d\n", error); 474 goto fail_1; 475 } 476 477 if ((error = bus_dmamap_create(sc->sc_dmat, 478 sizeof(struct stge_control_data), 1, 479 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 480 aprint_error_dev(self, 481 "unable to create control data DMA map, error = %d\n", 482 error); 483 goto fail_2; 484 } 485 486 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 487 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 488 0)) != 0) { 489 aprint_error_dev(self, 490 "unable to load control data DMA map, error = %d\n", 491 error); 492 goto fail_3; 493 } 494 495 /* 496 * Create the transmit buffer DMA maps. Note that rev B.3 497 * and earlier seem to have a bug regarding multi-fragment 498 * packets. We need to limit the number of Tx segments on 499 * such chips to 1. 500 */ 501 for (i = 0; i < STGE_NTXDESC; i++) { 502 if ((error = bus_dmamap_create(sc->sc_dmat, 503 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 504 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 505 aprint_error_dev(self, 506 "unable to create tx DMA map %d, error = %d\n", 507 i, error); 508 goto fail_4; 509 } 510 } 511 512 /* 513 * Create the receive buffer DMA maps. 514 */ 515 for (i = 0; i < STGE_NRXDESC; i++) { 516 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 517 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 518 aprint_error_dev(self, 519 "unable to create rx DMA map %d, error = %d\n", 520 i, error); 521 goto fail_5; 522 } 523 sc->sc_rxsoft[i].ds_mbuf = NULL; 524 } 525 526 /* 527 * Determine if we're copper or fiber. It affects how we 528 * reset the card. 529 */ 530 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 531 AC_PhyMedia) 532 sc->sc_usefiber = 1; 533 else 534 sc->sc_usefiber = 0; 535 536 /* 537 * Reset the chip to a known state. 538 */ 539 stge_reset(sc); 540 541 /* 542 * Reading the station address from the EEPROM doesn't seem 543 * to work, at least on my sample boards. Instead, since 544 * the reset sequence does AutoInit, read it from the station 545 * address registers. For Sundance 1023 you can only read it 546 * from EEPROM. 547 */ 548 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 549 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 550 STGE_StationAddress0) & 0xff; 551 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress0) >> 8; 553 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress1) & 0xff; 555 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress1) >> 8; 557 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress2) & 0xff; 559 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress2) >> 8; 561 sc->sc_stge1023 = 0; 562 } else { 563 data = prop_dictionary_get(device_properties(self), 564 "mac-address"); 565 if (data != NULL) { 566 /* 567 * Try to get the station address from device 568 * properties first, in case the EEPROM is missing. 569 */ 570 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 571 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 572 (void)memcpy(enaddr, prop_data_data_nocopy(data), 573 ETHER_ADDR_LEN); 574 } else { 575 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 576 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 577 stge_read_eeprom(sc, 578 STGE_EEPROM_StationAddress0 + i, 579 &myaddr[i]); 580 myaddr[i] = le16toh(myaddr[i]); 581 } 582 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 583 } 584 sc->sc_stge1023 = 1; 585 } 586 587 aprint_normal_dev(self, "Ethernet address %s\n", 588 ether_sprintf(enaddr)); 589 590 /* 591 * Read some important bits from the PhyCtrl register. 592 */ 593 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 594 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595 596 /* 597 * Initialize our media structures and probe the MII. 598 */ 599 mii->mii_ifp = ifp; 600 mii->mii_readreg = stge_mii_readreg; 601 mii->mii_writereg = stge_mii_writereg; 602 mii->mii_statchg = stge_mii_statchg; 603 sc->sc_ethercom.ec_mii = mii; 604 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 605 ether_mediastatus); 606 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 607 MII_OFFSET_ANY, MIIF_DOPAUSE); 608 if (LIST_FIRST(&mii->mii_phys) == NULL) { 609 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 610 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 611 } else 612 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 613 614 ifp = &sc->sc_ethercom.ec_if; 615 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 616 ifp->if_softc = sc; 617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 618 ifp->if_ioctl = stge_ioctl; 619 ifp->if_start = stge_start; 620 ifp->if_watchdog = stge_watchdog; 621 ifp->if_init = stge_init; 622 ifp->if_stop = stge_stop; 623 IFQ_SET_READY(&ifp->if_snd); 624 625 /* 626 * The manual recommends disabling early transmit, so we 627 * do. It's disabled anyway, if using IP checksumming, 628 * since the entire packet must be in the FIFO in order 629 * for the chip to perform the checksum. 630 */ 631 sc->sc_txthresh = 0x0fff; 632 633 /* 634 * Disable MWI if the PCI layer tells us to. 635 */ 636 sc->sc_DMACtrl = 0; 637 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 638 sc->sc_DMACtrl |= DMAC_MWIDisable; 639 640 /* 641 * We can support 802.1Q VLAN-sized frames and jumbo 642 * Ethernet frames. 643 * 644 * XXX Figure out how to do hw-assisted VLAN tagging in 645 * XXX a reasonable way on this chip. 646 */ 647 sc->sc_ethercom.ec_capabilities |= 648 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 649 ETHERCAP_VLAN_HWTAGGING; 650 651 /* 652 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 653 */ 654 sc->sc_ethercom.ec_if.if_capabilities |= 655 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 656 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 657 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 658 659 /* 660 * Attach the interface. 661 */ 662 if_attach(ifp); 663 if_deferred_start_init(ifp, NULL); 664 ether_ifattach(ifp, enaddr); 665 666 #ifdef STGE_EVENT_COUNTERS 667 /* 668 * Attach event counters. 669 */ 670 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 671 NULL, device_xname(self), "txstall"); 672 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 673 NULL, device_xname(self), "txdmaintr"); 674 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 675 NULL, device_xname(self), "txindintr"); 676 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 677 NULL, device_xname(self), "rxintr"); 678 679 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "txseg1"); 681 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "txseg2"); 683 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "txseg3"); 685 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "txseg4"); 687 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "txseg5"); 689 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "txsegmore"); 691 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 692 NULL, device_xname(self), "txcopy"); 693 694 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 695 NULL, device_xname(self), "rxipsum"); 696 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 697 NULL, device_xname(self), "rxtcpsum"); 698 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 699 NULL, device_xname(self), "rxudpsum"); 700 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 701 NULL, device_xname(self), "txipsum"); 702 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 703 NULL, device_xname(self), "txtcpsum"); 704 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 705 NULL, device_xname(self), "txudpsum"); 706 #endif /* STGE_EVENT_COUNTERS */ 707 708 /* 709 * Make sure the interface is shutdown during reboot. 710 */ 711 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 712 pmf_class_network_register(self, ifp); 713 else 714 aprint_error_dev(self, "couldn't establish power handler\n"); 715 716 return; 717 718 /* 719 * Free any resources we've allocated during the failed attach 720 * attempt. Do this in reverse order and fall through. 721 */ 722 fail_5: 723 for (i = 0; i < STGE_NRXDESC; i++) { 724 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 725 bus_dmamap_destroy(sc->sc_dmat, 726 sc->sc_rxsoft[i].ds_dmamap); 727 } 728 fail_4: 729 for (i = 0; i < STGE_NTXDESC; i++) { 730 if (sc->sc_txsoft[i].ds_dmamap != NULL) 731 bus_dmamap_destroy(sc->sc_dmat, 732 sc->sc_txsoft[i].ds_dmamap); 733 } 734 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 735 fail_3: 736 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 737 fail_2: 738 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 739 sizeof(struct stge_control_data)); 740 fail_1: 741 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 742 fail_0: 743 return; 744 } 745 746 /* 747 * stge_shutdown: 748 * 749 * Make sure the interface is stopped at reboot time. 750 */ 751 static bool 752 stge_shutdown(device_t self, int howto) 753 { 754 struct stge_softc *sc = device_private(self); 755 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 756 757 stge_stop(ifp, 1); 758 stge_reset(sc); 759 return true; 760 } 761 762 static void 763 stge_dma_wait(struct stge_softc *sc) 764 { 765 int i; 766 767 for (i = 0; i < STGE_TIMEOUT; i++) { 768 delay(2); 769 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 770 DMAC_TxDMAInProg) == 0) 771 break; 772 } 773 774 if (i == STGE_TIMEOUT) 775 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 776 } 777 778 /* 779 * stge_start: [ifnet interface function] 780 * 781 * Start packet transmission on the interface. 782 */ 783 static void 784 stge_start(struct ifnet *ifp) 785 { 786 struct stge_softc *sc = ifp->if_softc; 787 struct mbuf *m0; 788 struct stge_descsoft *ds; 789 struct stge_tfd *tfd; 790 bus_dmamap_t dmamap; 791 int error, firsttx, nexttx, opending, seg, totlen; 792 uint64_t csum_flags; 793 794 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 795 return; 796 797 /* 798 * Remember the previous number of pending transmissions 799 * and the first descriptor we will use. 800 */ 801 opending = sc->sc_txpending; 802 firsttx = STGE_NEXTTX(sc->sc_txlast); 803 804 /* 805 * Loop through the send queue, setting up transmit descriptors 806 * until we drain the queue, or use up all available transmit 807 * descriptors. 808 */ 809 for (;;) { 810 uint64_t tfc; 811 bool have_vtag; 812 uint16_t vtag; 813 814 /* 815 * Grab a packet off the queue. 816 */ 817 IFQ_POLL(&ifp->if_snd, m0); 818 if (m0 == NULL) 819 break; 820 821 /* 822 * Leave one unused descriptor at the end of the 823 * list to prevent wrapping completely around. 824 */ 825 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 826 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 827 break; 828 } 829 830 /* 831 * See if we have any VLAN stuff. 832 */ 833 have_vtag = vlan_has_tag(m0); 834 if (have_vtag) 835 vtag = vlan_get_tag(m0); 836 837 /* 838 * Get the last and next available transmit descriptor. 839 */ 840 nexttx = STGE_NEXTTX(sc->sc_txlast); 841 tfd = &sc->sc_txdescs[nexttx]; 842 ds = &sc->sc_txsoft[nexttx]; 843 844 dmamap = ds->ds_dmamap; 845 846 /* 847 * Load the DMA map. If this fails, the packet either 848 * didn't fit in the alloted number of segments, or we 849 * were short on resources. For the too-many-segments 850 * case, we simply report an error and drop the packet, 851 * since we can't sanely copy a jumbo packet to a single 852 * buffer. 853 */ 854 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 855 BUS_DMA_NOWAIT); 856 if (error) { 857 if (error == EFBIG) { 858 printf("%s: Tx packet consumes too many " 859 "DMA segments, dropping...\n", 860 device_xname(sc->sc_dev)); 861 IFQ_DEQUEUE(&ifp->if_snd, m0); 862 m_freem(m0); 863 continue; 864 } 865 /* 866 * Short on resources, just stop for now. 867 */ 868 break; 869 } 870 871 IFQ_DEQUEUE(&ifp->if_snd, m0); 872 873 /* 874 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 875 */ 876 877 /* Sync the DMA map. */ 878 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 879 BUS_DMASYNC_PREWRITE); 880 881 /* Initialize the fragment list. */ 882 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 883 tfd->tfd_frags[seg].frag_word0 = 884 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 885 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 886 totlen += dmamap->dm_segs[seg].ds_len; 887 } 888 889 #ifdef STGE_EVENT_COUNTERS 890 switch (dmamap->dm_nsegs) { 891 case 1: 892 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 893 break; 894 case 2: 895 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 896 break; 897 case 3: 898 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 899 break; 900 case 4: 901 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 902 break; 903 case 5: 904 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 905 break; 906 default: 907 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 908 break; 909 } 910 #endif /* STGE_EVENT_COUNTERS */ 911 912 /* 913 * Initialize checksumming flags in the descriptor. 914 * Byte-swap constants so the compiler can optimize. 915 */ 916 csum_flags = 0; 917 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 918 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 919 csum_flags |= TFD_IPChecksumEnable; 920 } 921 922 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 923 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 924 csum_flags |= TFD_TCPChecksumEnable; 925 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 926 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 927 csum_flags |= TFD_UDPChecksumEnable; 928 } 929 930 /* 931 * Initialize the descriptor and give it to the chip. 932 * Check to see if we have a VLAN tag to insert. 933 */ 934 935 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 936 TFD_FragCount(seg) | csum_flags | 937 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 938 TFD_TxDMAIndicate : 0); 939 if (have_vtag) { 940 #if 0 941 struct ether_header *eh = 942 mtod(m0, struct ether_header *); 943 uint16_t etype = ntohs(eh->ether_type); 944 printf("%s: xmit (tag %d) etype %x\n", 945 ifp->if_xname, *mtod(n, int *), etype); 946 #endif 947 tfc |= TFD_VLANTagInsert | 948 #ifdef STGE_VLAN_CFI 949 TFD_CFI | 950 #endif 951 TFD_VID(vtag); 952 } 953 tfd->tfd_control = htole64(tfc); 954 955 /* Sync the descriptor. */ 956 STGE_CDTXSYNC(sc, nexttx, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 959 /* 960 * Kick the transmit DMA logic. 961 */ 962 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 963 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 964 965 /* 966 * Store a pointer to the packet so we can free it later. 967 */ 968 ds->ds_mbuf = m0; 969 970 /* Advance the tx pointer. */ 971 sc->sc_txpending++; 972 sc->sc_txlast = nexttx; 973 974 /* 975 * Pass the packet to any BPF listeners. 976 */ 977 bpf_mtap(ifp, m0, BPF_D_OUT); 978 } 979 980 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 981 /* No more slots left; notify upper layer. */ 982 ifp->if_flags |= IFF_OACTIVE; 983 } 984 985 if (sc->sc_txpending != opending) { 986 /* 987 * We enqueued packets. If the transmitter was idle, 988 * reset the txdirty pointer. 989 */ 990 if (opending == 0) 991 sc->sc_txdirty = firsttx; 992 993 /* Set a watchdog timer in case the chip flakes out. */ 994 ifp->if_timer = 5; 995 } 996 } 997 998 /* 999 * stge_watchdog: [ifnet interface function] 1000 * 1001 * Watchdog timer handler. 1002 */ 1003 static void 1004 stge_watchdog(struct ifnet *ifp) 1005 { 1006 struct stge_softc *sc = ifp->if_softc; 1007 1008 /* 1009 * Sweep up first, since we don't interrupt every frame. 1010 */ 1011 stge_txintr(sc); 1012 if (sc->sc_txpending != 0) { 1013 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1014 ifp->if_oerrors++; 1015 1016 (void) stge_init(ifp); 1017 1018 /* Try to get more packets going. */ 1019 stge_start(ifp); 1020 } 1021 } 1022 1023 /* 1024 * stge_ioctl: [ifnet interface function] 1025 * 1026 * Handle control requests from the operator. 1027 */ 1028 static int 1029 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1030 { 1031 struct stge_softc *sc = ifp->if_softc; 1032 int s, error; 1033 1034 s = splnet(); 1035 1036 error = ether_ioctl(ifp, cmd, data); 1037 if (error == ENETRESET) { 1038 error = 0; 1039 1040 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1041 ; 1042 else if (ifp->if_flags & IFF_RUNNING) { 1043 /* 1044 * Multicast list has changed; set the hardware filter 1045 * accordingly. 1046 */ 1047 stge_set_filter(sc); 1048 } 1049 } 1050 1051 /* Try to get more packets going. */ 1052 stge_start(ifp); 1053 1054 splx(s); 1055 return (error); 1056 } 1057 1058 /* 1059 * stge_intr: 1060 * 1061 * Interrupt service routine. 1062 */ 1063 static int 1064 stge_intr(void *arg) 1065 { 1066 struct stge_softc *sc = arg; 1067 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1068 uint32_t txstat; 1069 int wantinit; 1070 uint16_t isr; 1071 1072 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1073 IS_InterruptStatus) == 0) 1074 return (0); 1075 1076 for (wantinit = 0; wantinit == 0;) { 1077 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1078 if ((isr & sc->sc_IntEnable) == 0) 1079 break; 1080 1081 /* Host interface errors. */ 1082 if (isr & IS_HostError) { 1083 printf("%s: Host interface error\n", 1084 device_xname(sc->sc_dev)); 1085 wantinit = 1; 1086 continue; 1087 } 1088 1089 /* Receive interrupts. */ 1090 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) { 1091 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1092 stge_rxintr(sc); 1093 if (isr & IS_RFDListEnd) { 1094 printf("%s: receive ring overflow\n", 1095 device_xname(sc->sc_dev)); 1096 /* 1097 * XXX Should try to recover from this 1098 * XXX more gracefully. 1099 */ 1100 wantinit = 1; 1101 } 1102 } 1103 1104 /* Transmit interrupts. */ 1105 if (isr & (IS_TxDMAComplete | IS_TxComplete)) { 1106 #ifdef STGE_EVENT_COUNTERS 1107 if (isr & IS_TxDMAComplete) 1108 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1109 #endif 1110 stge_txintr(sc); 1111 } 1112 1113 /* Statistics overflow. */ 1114 if (isr & IS_UpdateStats) 1115 stge_stats_update(sc); 1116 1117 /* Transmission errors. */ 1118 if (isr & IS_TxComplete) { 1119 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1120 for (;;) { 1121 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1122 STGE_TxStatus); 1123 if ((txstat & TS_TxComplete) == 0) 1124 break; 1125 if (txstat & TS_TxUnderrun) { 1126 sc->sc_txthresh++; 1127 if (sc->sc_txthresh > 0x0fff) 1128 sc->sc_txthresh = 0x0fff; 1129 printf("%s: transmit underrun, new " 1130 "threshold: %d bytes\n", 1131 device_xname(sc->sc_dev), 1132 sc->sc_txthresh << 5); 1133 } 1134 if (txstat & TS_MaxCollisions) 1135 printf("%s: excessive collisions\n", 1136 device_xname(sc->sc_dev)); 1137 } 1138 wantinit = 1; 1139 } 1140 1141 } 1142 1143 if (wantinit) 1144 stge_init(ifp); 1145 1146 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1147 sc->sc_IntEnable); 1148 1149 /* Try to get more packets going. */ 1150 if_schedule_deferred_start(ifp); 1151 1152 return (1); 1153 } 1154 1155 /* 1156 * stge_txintr: 1157 * 1158 * Helper; handle transmit interrupts. 1159 */ 1160 static void 1161 stge_txintr(struct stge_softc *sc) 1162 { 1163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1164 struct stge_descsoft *ds; 1165 uint64_t control; 1166 int i; 1167 1168 ifp->if_flags &= ~IFF_OACTIVE; 1169 1170 /* 1171 * Go through our Tx list and free mbufs for those 1172 * frames which have been transmitted. 1173 */ 1174 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1175 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1176 ds = &sc->sc_txsoft[i]; 1177 1178 STGE_CDTXSYNC(sc, i, 1179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1180 1181 control = le64toh(sc->sc_txdescs[i].tfd_control); 1182 if ((control & TFD_TFDDone) == 0) 1183 break; 1184 1185 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1186 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1187 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1188 m_freem(ds->ds_mbuf); 1189 ds->ds_mbuf = NULL; 1190 } 1191 1192 /* Update the dirty transmit buffer pointer. */ 1193 sc->sc_txdirty = i; 1194 1195 /* 1196 * If there are no more pending transmissions, cancel the watchdog 1197 * timer. 1198 */ 1199 if (sc->sc_txpending == 0) 1200 ifp->if_timer = 0; 1201 } 1202 1203 /* 1204 * stge_rxintr: 1205 * 1206 * Helper; handle receive interrupts. 1207 */ 1208 static void 1209 stge_rxintr(struct stge_softc *sc) 1210 { 1211 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1212 struct stge_descsoft *ds; 1213 struct mbuf *m, *tailm; 1214 uint64_t status; 1215 int i, len; 1216 1217 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1218 ds = &sc->sc_rxsoft[i]; 1219 1220 STGE_CDRXSYNC(sc, i, 1221 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1222 1223 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1224 1225 if ((status & RFD_RFDDone) == 0) 1226 break; 1227 1228 if (__predict_false(sc->sc_rxdiscard)) { 1229 STGE_INIT_RXDESC(sc, i); 1230 if (status & RFD_FrameEnd) { 1231 /* Reset our state. */ 1232 sc->sc_rxdiscard = 0; 1233 } 1234 continue; 1235 } 1236 1237 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1238 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1239 1240 m = ds->ds_mbuf; 1241 1242 /* 1243 * Add a new receive buffer to the ring. 1244 */ 1245 if (stge_add_rxbuf(sc, i) != 0) { 1246 /* 1247 * Failed, throw away what we've done so 1248 * far, and discard the rest of the packet. 1249 */ 1250 ifp->if_ierrors++; 1251 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1252 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1253 STGE_INIT_RXDESC(sc, i); 1254 if ((status & RFD_FrameEnd) == 0) 1255 sc->sc_rxdiscard = 1; 1256 if (sc->sc_rxhead != NULL) 1257 m_freem(sc->sc_rxhead); 1258 STGE_RXCHAIN_RESET(sc); 1259 continue; 1260 } 1261 1262 #ifdef DIAGNOSTIC 1263 if (status & RFD_FrameStart) { 1264 KASSERT(sc->sc_rxhead == NULL); 1265 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1266 } 1267 #endif 1268 1269 STGE_RXCHAIN_LINK(sc, m); 1270 1271 /* 1272 * If this is not the end of the packet, keep 1273 * looking. 1274 */ 1275 if ((status & RFD_FrameEnd) == 0) { 1276 sc->sc_rxlen += m->m_len; 1277 continue; 1278 } 1279 1280 /* 1281 * Okay, we have the entire packet now... 1282 */ 1283 *sc->sc_rxtailp = NULL; 1284 m = sc->sc_rxhead; 1285 tailm = sc->sc_rxtail; 1286 1287 STGE_RXCHAIN_RESET(sc); 1288 1289 /* 1290 * If the packet had an error, drop it. Note we 1291 * count the error later in the periodic stats update. 1292 */ 1293 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1294 RFD_RxAlignmentError | RFD_RxFCSError | 1295 RFD_RxLengthError)) { 1296 m_freem(m); 1297 continue; 1298 } 1299 1300 /* 1301 * No errors. 1302 * 1303 * Note we have configured the chip to not include 1304 * the CRC at the end of the packet. 1305 */ 1306 len = RFD_RxDMAFrameLen(status); 1307 tailm->m_len = len - sc->sc_rxlen; 1308 1309 /* 1310 * If the packet is small enough to fit in a 1311 * single header mbuf, allocate one and copy 1312 * the data into it. This greatly reduces 1313 * memory consumption when we receive lots 1314 * of small packets. 1315 */ 1316 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1317 struct mbuf *nm; 1318 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1319 if (nm == NULL) { 1320 ifp->if_ierrors++; 1321 m_freem(m); 1322 continue; 1323 } 1324 nm->m_data += 2; 1325 nm->m_pkthdr.len = nm->m_len = len; 1326 m_copydata(m, 0, len, mtod(nm, void *)); 1327 m_freem(m); 1328 m = nm; 1329 } 1330 1331 /* 1332 * Set the incoming checksum information for the packet. 1333 */ 1334 if (status & RFD_IPDetected) { 1335 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1336 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1337 if (status & RFD_IPError) 1338 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1339 if (status & RFD_TCPDetected) { 1340 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1341 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1342 if (status & RFD_TCPError) 1343 m->m_pkthdr.csum_flags |= 1344 M_CSUM_TCP_UDP_BAD; 1345 } else if (status & RFD_UDPDetected) { 1346 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1347 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1348 if (status & RFD_UDPError) 1349 m->m_pkthdr.csum_flags |= 1350 M_CSUM_TCP_UDP_BAD; 1351 } 1352 } 1353 1354 m_set_rcvif(m, ifp); 1355 m->m_pkthdr.len = len; 1356 1357 /* 1358 * Pass this up to any BPF listeners, but only 1359 * pass if up the stack if it's for us. 1360 */ 1361 #ifdef STGE_VLAN_UNTAG 1362 /* 1363 * Check for VLAN tagged packets 1364 */ 1365 if (status & RFD_VLANDetected) 1366 vlan_set_tag(m, RFD_TCI(status)); 1367 1368 #endif 1369 #if 0 1370 if (status & RFD_VLANDetected) { 1371 struct ether_header *eh; 1372 uint16_t etype; 1373 1374 eh = mtod(m, struct ether_header *); 1375 etype = ntohs(eh->ether_type); 1376 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1377 ifp->if_xname, (uint16_t) RFD_TCI(status), 1378 etype); 1379 } 1380 #endif 1381 /* Pass it on. */ 1382 if_percpuq_enqueue(ifp->if_percpuq, m); 1383 } 1384 1385 /* Update the receive pointer. */ 1386 sc->sc_rxptr = i; 1387 } 1388 1389 /* 1390 * stge_tick: 1391 * 1392 * One second timer, used to tick the MII. 1393 */ 1394 static void 1395 stge_tick(void *arg) 1396 { 1397 struct stge_softc *sc = arg; 1398 int s; 1399 1400 s = splnet(); 1401 mii_tick(&sc->sc_mii); 1402 stge_stats_update(sc); 1403 splx(s); 1404 1405 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1406 } 1407 1408 /* 1409 * stge_stats_update: 1410 * 1411 * Read the TC9021 statistics counters. 1412 */ 1413 static void 1414 stge_stats_update(struct stge_softc *sc) 1415 { 1416 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1417 bus_space_tag_t st = sc->sc_st; 1418 bus_space_handle_t sh = sc->sc_sh; 1419 1420 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1421 1422 ifp->if_ipackets += 1423 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1424 1425 ifp->if_ierrors += 1426 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1427 1428 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1429 1430 ifp->if_opackets += 1431 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1432 1433 ifp->if_collisions += 1434 bus_space_read_4(st, sh, STGE_LateCollisions) + 1435 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1436 bus_space_read_4(st, sh, STGE_SingleColFrames); 1437 1438 ifp->if_oerrors += 1439 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1440 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1441 } 1442 1443 /* 1444 * stge_reset: 1445 * 1446 * Perform a soft reset on the TC9021. 1447 */ 1448 static void 1449 stge_reset(struct stge_softc *sc) 1450 { 1451 uint32_t ac; 1452 int i; 1453 1454 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1455 1456 /* 1457 * Only assert RstOut if we're fiber. We need GMII clocks 1458 * to be present in order for the reset to complete on fiber 1459 * cards. 1460 */ 1461 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1462 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1463 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1464 (sc->sc_usefiber ? AC_RstOut : 0)); 1465 1466 delay(50000); 1467 1468 for (i = 0; i < STGE_TIMEOUT; i++) { 1469 delay(5000); 1470 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1471 AC_ResetBusy) == 0) 1472 break; 1473 } 1474 1475 if (i == STGE_TIMEOUT) 1476 printf("%s: reset failed to complete\n", 1477 device_xname(sc->sc_dev)); 1478 1479 delay(1000); 1480 } 1481 1482 /* 1483 * stge_init: [ ifnet interface function ] 1484 * 1485 * Initialize the interface. Must be called at splnet(). 1486 */ 1487 static int 1488 stge_init(struct ifnet *ifp) 1489 { 1490 struct stge_softc *sc = ifp->if_softc; 1491 bus_space_tag_t st = sc->sc_st; 1492 bus_space_handle_t sh = sc->sc_sh; 1493 struct stge_descsoft *ds; 1494 int i, error = 0; 1495 1496 /* 1497 * Cancel any pending I/O. 1498 */ 1499 stge_stop(ifp, 0); 1500 1501 /* 1502 * Reset the chip to a known state. 1503 */ 1504 stge_reset(sc); 1505 1506 /* 1507 * Initialize the transmit descriptor ring. 1508 */ 1509 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1510 for (i = 0; i < STGE_NTXDESC; i++) { 1511 sc->sc_txdescs[i].tfd_next = htole64( 1512 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1513 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1514 } 1515 sc->sc_txpending = 0; 1516 sc->sc_txdirty = 0; 1517 sc->sc_txlast = STGE_NTXDESC - 1; 1518 1519 /* 1520 * Initialize the receive descriptor and receive job 1521 * descriptor rings. 1522 */ 1523 for (i = 0; i < STGE_NRXDESC; i++) { 1524 ds = &sc->sc_rxsoft[i]; 1525 if (ds->ds_mbuf == NULL) { 1526 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1527 printf("%s: unable to allocate or map rx " 1528 "buffer %d, error = %d\n", 1529 device_xname(sc->sc_dev), i, error); 1530 /* 1531 * XXX Should attempt to run with fewer receive 1532 * XXX buffers instead of just failing. 1533 */ 1534 stge_rxdrain(sc); 1535 goto out; 1536 } 1537 } else 1538 STGE_INIT_RXDESC(sc, i); 1539 } 1540 sc->sc_rxptr = 0; 1541 sc->sc_rxdiscard = 0; 1542 STGE_RXCHAIN_RESET(sc); 1543 1544 /* Set the station address. */ 1545 for (i = 0; i < 6; i++) 1546 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1547 CLLADDR(ifp->if_sadl)[i]); 1548 1549 /* 1550 * Set the statistics masks. Disable all the RMON stats, 1551 * and disable selected stats in the non-RMON stats registers. 1552 */ 1553 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1554 bus_space_write_4(st, sh, STGE_StatisticsMask, 1555 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1556 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1557 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1558 (1U << 21)); 1559 1560 /* Set up the receive filter. */ 1561 stge_set_filter(sc); 1562 1563 /* 1564 * Give the transmit and receive ring to the chip. 1565 */ 1566 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1567 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1568 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1569 1570 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1571 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1572 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1573 1574 /* 1575 * Initialize the Tx auto-poll period. It's OK to make this number 1576 * large (255 is the max, but we use 127) -- we explicitly kick the 1577 * transmit engine when there's actually a packet. 1578 */ 1579 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1580 1581 /* ..and the Rx auto-poll period. */ 1582 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1583 1584 /* Initialize the Tx start threshold. */ 1585 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1586 1587 /* RX DMA thresholds, from linux */ 1588 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1589 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1590 1591 /* 1592 * Initialize the Rx DMA interrupt control register. We 1593 * request an interrupt after every incoming packet, but 1594 * defer it for 32us (64 * 512 ns). When the number of 1595 * interrupts pending reaches 8, we stop deferring the 1596 * interrupt, and signal it immediately. 1597 */ 1598 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1599 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1600 1601 /* 1602 * Initialize the interrupt mask. 1603 */ 1604 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1605 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1606 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1607 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1608 1609 /* 1610 * Configure the DMA engine. 1611 * XXX Should auto-tune TxBurstLimit. 1612 */ 1613 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1614 DMAC_TxBurstLimit(3)); 1615 1616 /* 1617 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1618 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1619 * empty again. 1620 */ 1621 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1622 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1623 1624 /* 1625 * Set the maximum frame size. 1626 */ 1627 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1628 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1629 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1630 ETHER_VLAN_ENCAP_LEN : 0)); 1631 1632 /* 1633 * Initialize MacCtrl -- do it before setting the media, 1634 * as setting the media will actually program the register. 1635 * 1636 * Note: We have to poke the IFS value before poking 1637 * anything else. 1638 */ 1639 sc->sc_MACCtrl = MC_IFSSelect(0); 1640 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1641 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1642 #ifdef STGE_VLAN_UNTAG 1643 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1644 #endif 1645 1646 if (sc->sc_rev >= 6) { /* >= B.2 */ 1647 /* Multi-frag frame bug work-around. */ 1648 bus_space_write_2(st, sh, STGE_DebugCtrl, 1649 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1650 1651 /* Tx Poll Now bug work-around. */ 1652 bus_space_write_2(st, sh, STGE_DebugCtrl, 1653 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1654 /* XXX ? from linux */ 1655 bus_space_write_2(st, sh, STGE_DebugCtrl, 1656 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1657 } 1658 1659 /* 1660 * Set the current media. 1661 */ 1662 if ((error = ether_mediachange(ifp)) != 0) 1663 goto out; 1664 1665 /* 1666 * Start the one second MII clock. 1667 */ 1668 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1669 1670 /* 1671 * ...all done! 1672 */ 1673 ifp->if_flags |= IFF_RUNNING; 1674 ifp->if_flags &= ~IFF_OACTIVE; 1675 1676 out: 1677 if (error) 1678 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1679 return (error); 1680 } 1681 1682 /* 1683 * stge_drain: 1684 * 1685 * Drain the receive queue. 1686 */ 1687 static void 1688 stge_rxdrain(struct stge_softc *sc) 1689 { 1690 struct stge_descsoft *ds; 1691 int i; 1692 1693 for (i = 0; i < STGE_NRXDESC; i++) { 1694 ds = &sc->sc_rxsoft[i]; 1695 if (ds->ds_mbuf != NULL) { 1696 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1697 ds->ds_mbuf->m_next = NULL; 1698 m_freem(ds->ds_mbuf); 1699 ds->ds_mbuf = NULL; 1700 } 1701 } 1702 } 1703 1704 /* 1705 * stge_stop: [ ifnet interface function ] 1706 * 1707 * Stop transmission on the interface. 1708 */ 1709 static void 1710 stge_stop(struct ifnet *ifp, int disable) 1711 { 1712 struct stge_softc *sc = ifp->if_softc; 1713 struct stge_descsoft *ds; 1714 int i; 1715 1716 /* 1717 * Stop the one second clock. 1718 */ 1719 callout_stop(&sc->sc_tick_ch); 1720 1721 /* Down the MII. */ 1722 mii_down(&sc->sc_mii); 1723 1724 /* 1725 * Disable interrupts. 1726 */ 1727 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1728 1729 /* 1730 * Stop receiver, transmitter, and stats update. 1731 */ 1732 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1733 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1734 1735 /* 1736 * Stop the transmit and receive DMA. 1737 */ 1738 stge_dma_wait(sc); 1739 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1740 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1741 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1742 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1743 1744 /* 1745 * Release any queued transmit buffers. 1746 */ 1747 for (i = 0; i < STGE_NTXDESC; i++) { 1748 ds = &sc->sc_txsoft[i]; 1749 if (ds->ds_mbuf != NULL) { 1750 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1751 m_freem(ds->ds_mbuf); 1752 ds->ds_mbuf = NULL; 1753 } 1754 } 1755 1756 /* 1757 * Mark the interface down and cancel the watchdog timer. 1758 */ 1759 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1760 ifp->if_timer = 0; 1761 1762 if (disable) 1763 stge_rxdrain(sc); 1764 } 1765 1766 static int 1767 stge_eeprom_wait(struct stge_softc *sc) 1768 { 1769 int i; 1770 1771 for (i = 0; i < STGE_TIMEOUT; i++) { 1772 delay(1000); 1773 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1774 EC_EepromBusy) == 0) 1775 return (0); 1776 } 1777 return (1); 1778 } 1779 1780 /* 1781 * stge_read_eeprom: 1782 * 1783 * Read data from the serial EEPROM. 1784 */ 1785 static void 1786 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1787 { 1788 1789 if (stge_eeprom_wait(sc)) 1790 printf("%s: EEPROM failed to come ready\n", 1791 device_xname(sc->sc_dev)); 1792 1793 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1794 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1795 if (stge_eeprom_wait(sc)) 1796 printf("%s: EEPROM read timed out\n", 1797 device_xname(sc->sc_dev)); 1798 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1799 } 1800 1801 /* 1802 * stge_add_rxbuf: 1803 * 1804 * Add a receive buffer to the indicated descriptor. 1805 */ 1806 static int 1807 stge_add_rxbuf(struct stge_softc *sc, int idx) 1808 { 1809 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1810 struct mbuf *m; 1811 int error; 1812 1813 MGETHDR(m, M_DONTWAIT, MT_DATA); 1814 if (m == NULL) 1815 return (ENOBUFS); 1816 1817 MCLGET(m, M_DONTWAIT); 1818 if ((m->m_flags & M_EXT) == 0) { 1819 m_freem(m); 1820 return (ENOBUFS); 1821 } 1822 1823 m->m_data = m->m_ext.ext_buf + 2; 1824 m->m_len = MCLBYTES - 2; 1825 1826 if (ds->ds_mbuf != NULL) 1827 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1828 1829 ds->ds_mbuf = m; 1830 1831 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1832 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1833 if (error) { 1834 printf("%s: can't load rx DMA map %d, error = %d\n", 1835 device_xname(sc->sc_dev), idx, error); 1836 panic("stge_add_rxbuf"); /* XXX */ 1837 } 1838 1839 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1840 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1841 1842 STGE_INIT_RXDESC(sc, idx); 1843 1844 return (0); 1845 } 1846 1847 /* 1848 * stge_set_filter: 1849 * 1850 * Set up the receive filter. 1851 */ 1852 static void 1853 stge_set_filter(struct stge_softc *sc) 1854 { 1855 struct ethercom *ec = &sc->sc_ethercom; 1856 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1857 struct ether_multi *enm; 1858 struct ether_multistep step; 1859 uint32_t crc; 1860 uint32_t mchash[2]; 1861 1862 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1863 if (ifp->if_flags & IFF_BROADCAST) 1864 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1865 1866 /* XXX: ST1023 only works in promiscuous mode */ 1867 if (sc->sc_stge1023) 1868 ifp->if_flags |= IFF_PROMISC; 1869 1870 if (ifp->if_flags & IFF_PROMISC) { 1871 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1872 goto allmulti; 1873 } 1874 1875 /* 1876 * Set up the multicast address filter by passing all multicast 1877 * addresses through a CRC generator, and then using the low-order 1878 * 6 bits as an index into the 64 bit multicast hash table. The 1879 * high order bits select the register, while the rest of the bits 1880 * select the bit within the register. 1881 */ 1882 1883 memset(mchash, 0, sizeof(mchash)); 1884 1885 ETHER_LOCK(ec); 1886 ETHER_FIRST_MULTI(step, ec, enm); 1887 if (enm == NULL) { 1888 ETHER_UNLOCK(ec); 1889 goto done; 1890 } 1891 1892 while (enm != NULL) { 1893 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1894 /* 1895 * We must listen to a range of multicast addresses. 1896 * For now, just accept all multicasts, rather than 1897 * trying to set only those filter bits needed to match 1898 * the range. (At this time, the only use of address 1899 * ranges is for IP multicast routing, for which the 1900 * range is big enough to require all bits set.) 1901 */ 1902 ETHER_UNLOCK(ec); 1903 goto allmulti; 1904 } 1905 1906 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1907 1908 /* Just want the 6 least significant bits. */ 1909 crc &= 0x3f; 1910 1911 /* Set the corresponding bit in the hash table. */ 1912 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1913 1914 ETHER_NEXT_MULTI(step, enm); 1915 } 1916 ETHER_UNLOCK(ec); 1917 1918 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1919 1920 ifp->if_flags &= ~IFF_ALLMULTI; 1921 goto done; 1922 1923 allmulti: 1924 ifp->if_flags |= IFF_ALLMULTI; 1925 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1926 1927 done: 1928 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1929 /* 1930 * Program the multicast hash table. 1931 */ 1932 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1933 mchash[0]); 1934 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1935 mchash[1]); 1936 } 1937 1938 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1939 sc->sc_ReceiveMode); 1940 } 1941 1942 /* 1943 * stge_mii_readreg: [mii interface function] 1944 * 1945 * Read a PHY register on the MII of the TC9021. 1946 */ 1947 static int 1948 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1949 { 1950 1951 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val); 1952 } 1953 1954 /* 1955 * stge_mii_writereg: [mii interface function] 1956 * 1957 * Write a PHY register on the MII of the TC9021. 1958 */ 1959 static int 1960 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1961 { 1962 1963 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, 1964 val); 1965 } 1966 1967 /* 1968 * stge_mii_statchg: [mii interface function] 1969 * 1970 * Callback from MII layer when media changes. 1971 */ 1972 static void 1973 stge_mii_statchg(struct ifnet *ifp) 1974 { 1975 struct stge_softc *sc = ifp->if_softc; 1976 1977 if (sc->sc_mii.mii_media_active & IFM_FDX) 1978 sc->sc_MACCtrl |= MC_DuplexSelect; 1979 else 1980 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1981 1982 /* XXX 802.1x flow-control? */ 1983 1984 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1985 } 1986 1987 /* 1988 * sste_mii_bitbang_read: [mii bit-bang interface function] 1989 * 1990 * Read the MII serial port for the MII bit-bang module. 1991 */ 1992 static uint32_t 1993 stge_mii_bitbang_read(device_t self) 1994 { 1995 struct stge_softc *sc = device_private(self); 1996 1997 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1998 } 1999 2000 /* 2001 * stge_mii_bitbang_write: [mii big-bang interface function] 2002 * 2003 * Write the MII serial port for the MII bit-bang module. 2004 */ 2005 static void 2006 stge_mii_bitbang_write(device_t self, uint32_t val) 2007 { 2008 struct stge_softc *sc = device_private(self); 2009 2010 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2011 val | sc->sc_PhyCtrl); 2012 } 2013