1 /* $NetBSD: if_stge.c,v 1.62 2016/12/15 09:28:05 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.62 2016/12/15 09:28:05 ozaki-r Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int); 282 static void stge_mii_writereg(device_t, int, int, int); 283 static void stge_mii_statchg(struct ifnet *); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 pci_intr_handle_t ih; 380 const char *intrstr = NULL; 381 bus_space_tag_t iot, memt; 382 bus_space_handle_t ioh, memh; 383 bus_dma_segment_t seg; 384 prop_data_t data; 385 int ioh_valid, memh_valid; 386 int i, rseg, error; 387 const struct stge_product *sp; 388 uint8_t enaddr[ETHER_ADDR_LEN]; 389 char intrbuf[PCI_INTRSTR_LEN]; 390 391 callout_init(&sc->sc_tick_ch, 0); 392 393 sp = stge_lookup(pa); 394 if (sp == NULL) { 395 printf("\n"); 396 panic("ste_attach: impossible"); 397 } 398 399 sc->sc_rev = PCI_REVISION(pa->pa_class); 400 401 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 402 403 /* 404 * Map the device. 405 */ 406 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 407 PCI_MAPREG_TYPE_IO, 0, 408 &iot, &ioh, NULL, NULL) == 0); 409 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 410 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 411 &memt, &memh, NULL, NULL) == 0); 412 413 if (memh_valid) { 414 sc->sc_st = memt; 415 sc->sc_sh = memh; 416 } else if (ioh_valid) { 417 sc->sc_st = iot; 418 sc->sc_sh = ioh; 419 } else { 420 aprint_error_dev(self, "unable to map device registers\n"); 421 return; 422 } 423 424 sc->sc_dmat = pa->pa_dmat; 425 426 /* Enable bus mastering. */ 427 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 428 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 429 PCI_COMMAND_MASTER_ENABLE); 430 431 /* power up chip */ 432 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 433 error != EOPNOTSUPP) { 434 aprint_error_dev(self, "cannot activate %d\n", error); 435 return; 436 } 437 /* 438 * Map and establish our interrupt. 439 */ 440 if (pci_intr_map(pa, &ih)) { 441 aprint_error_dev(self, "unable to map interrupt\n"); 442 return; 443 } 444 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 445 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 446 if (sc->sc_ih == NULL) { 447 aprint_error_dev(self, "unable to establish interrupt"); 448 if (intrstr != NULL) 449 aprint_error(" at %s", intrstr); 450 aprint_error("\n"); 451 return; 452 } 453 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 454 455 /* 456 * Allocate the control data structures, and create and load the 457 * DMA map for it. 458 */ 459 if ((error = bus_dmamem_alloc(sc->sc_dmat, 460 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 461 0)) != 0) { 462 aprint_error_dev(self, 463 "unable to allocate control data, error = %d\n", error); 464 goto fail_0; 465 } 466 467 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 468 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 469 BUS_DMA_COHERENT)) != 0) { 470 aprint_error_dev(self, 471 "unable to map control data, error = %d\n", error); 472 goto fail_1; 473 } 474 475 if ((error = bus_dmamap_create(sc->sc_dmat, 476 sizeof(struct stge_control_data), 1, 477 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 478 aprint_error_dev(self, 479 "unable to create control data DMA map, error = %d\n", 480 error); 481 goto fail_2; 482 } 483 484 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 485 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 486 0)) != 0) { 487 aprint_error_dev(self, 488 "unable to load control data DMA map, error = %d\n", 489 error); 490 goto fail_3; 491 } 492 493 /* 494 * Create the transmit buffer DMA maps. Note that rev B.3 495 * and earlier seem to have a bug regarding multi-fragment 496 * packets. We need to limit the number of Tx segments on 497 * such chips to 1. 498 */ 499 for (i = 0; i < STGE_NTXDESC; i++) { 500 if ((error = bus_dmamap_create(sc->sc_dmat, 501 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 502 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 503 aprint_error_dev(self, 504 "unable to create tx DMA map %d, error = %d\n", 505 i, error); 506 goto fail_4; 507 } 508 } 509 510 /* 511 * Create the receive buffer DMA maps. 512 */ 513 for (i = 0; i < STGE_NRXDESC; i++) { 514 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 515 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 516 aprint_error_dev(self, 517 "unable to create rx DMA map %d, error = %d\n", 518 i, error); 519 goto fail_5; 520 } 521 sc->sc_rxsoft[i].ds_mbuf = NULL; 522 } 523 524 /* 525 * Determine if we're copper or fiber. It affects how we 526 * reset the card. 527 */ 528 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 529 AC_PhyMedia) 530 sc->sc_usefiber = 1; 531 else 532 sc->sc_usefiber = 0; 533 534 /* 535 * Reset the chip to a known state. 536 */ 537 stge_reset(sc); 538 539 /* 540 * Reading the station address from the EEPROM doesn't seem 541 * to work, at least on my sample boards. Instead, since 542 * the reset sequence does AutoInit, read it from the station 543 * address registers. For Sundance 1023 you can only read it 544 * from EEPROM. 545 */ 546 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 547 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 548 STGE_StationAddress0) & 0xff; 549 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 550 STGE_StationAddress0) >> 8; 551 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress1) & 0xff; 553 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress1) >> 8; 555 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress2) & 0xff; 557 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress2) >> 8; 559 sc->sc_stge1023 = 0; 560 } else { 561 data = prop_dictionary_get(device_properties(self), 562 "mac-address"); 563 if (data != NULL) { 564 /* 565 * Try to get the station address from device 566 * properties first, in case the EEPROM is missing. 567 */ 568 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 569 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 570 (void)memcpy(enaddr, prop_data_data_nocopy(data), 571 ETHER_ADDR_LEN); 572 } else { 573 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 574 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 575 stge_read_eeprom(sc, 576 STGE_EEPROM_StationAddress0 + i, 577 &myaddr[i]); 578 myaddr[i] = le16toh(myaddr[i]); 579 } 580 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 581 } 582 sc->sc_stge1023 = 1; 583 } 584 585 aprint_normal_dev(self, "Ethernet address %s\n", 586 ether_sprintf(enaddr)); 587 588 /* 589 * Read some important bits from the PhyCtrl register. 590 */ 591 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 592 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 593 594 /* 595 * Initialize our media structures and probe the MII. 596 */ 597 sc->sc_mii.mii_ifp = ifp; 598 sc->sc_mii.mii_readreg = stge_mii_readreg; 599 sc->sc_mii.mii_writereg = stge_mii_writereg; 600 sc->sc_mii.mii_statchg = stge_mii_statchg; 601 sc->sc_ethercom.ec_mii = &sc->sc_mii; 602 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 603 ether_mediastatus); 604 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 605 MII_OFFSET_ANY, MIIF_DOPAUSE); 606 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 607 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 608 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 609 } else 610 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 611 612 ifp = &sc->sc_ethercom.ec_if; 613 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 614 ifp->if_softc = sc; 615 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 616 ifp->if_ioctl = stge_ioctl; 617 ifp->if_start = stge_start; 618 ifp->if_watchdog = stge_watchdog; 619 ifp->if_init = stge_init; 620 ifp->if_stop = stge_stop; 621 IFQ_SET_READY(&ifp->if_snd); 622 623 /* 624 * The manual recommends disabling early transmit, so we 625 * do. It's disabled anyway, if using IP checksumming, 626 * since the entire packet must be in the FIFO in order 627 * for the chip to perform the checksum. 628 */ 629 sc->sc_txthresh = 0x0fff; 630 631 /* 632 * Disable MWI if the PCI layer tells us to. 633 */ 634 sc->sc_DMACtrl = 0; 635 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 636 sc->sc_DMACtrl |= DMAC_MWIDisable; 637 638 /* 639 * We can support 802.1Q VLAN-sized frames and jumbo 640 * Ethernet frames. 641 * 642 * XXX Figure out how to do hw-assisted VLAN tagging in 643 * XXX a reasonable way on this chip. 644 */ 645 sc->sc_ethercom.ec_capabilities |= 646 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 647 ETHERCAP_VLAN_HWTAGGING; 648 649 /* 650 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 651 */ 652 sc->sc_ethercom.ec_if.if_capabilities |= 653 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 654 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 655 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 656 657 /* 658 * Attach the interface. 659 */ 660 if_attach(ifp); 661 if_deferred_start_init(ifp, NULL); 662 ether_ifattach(ifp, enaddr); 663 664 #ifdef STGE_EVENT_COUNTERS 665 /* 666 * Attach event counters. 667 */ 668 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 669 NULL, device_xname(self), "txstall"); 670 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 671 NULL, device_xname(self), "txdmaintr"); 672 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 673 NULL, device_xname(self), "txindintr"); 674 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 675 NULL, device_xname(self), "rxintr"); 676 677 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 678 NULL, device_xname(self), "txseg1"); 679 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "txseg2"); 681 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "txseg3"); 683 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "txseg4"); 685 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "txseg5"); 687 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "txsegmore"); 689 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "txcopy"); 691 692 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 693 NULL, device_xname(self), "rxipsum"); 694 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 695 NULL, device_xname(self), "rxtcpsum"); 696 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 697 NULL, device_xname(self), "rxudpsum"); 698 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 699 NULL, device_xname(self), "txipsum"); 700 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 701 NULL, device_xname(self), "txtcpsum"); 702 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 703 NULL, device_xname(self), "txudpsum"); 704 #endif /* STGE_EVENT_COUNTERS */ 705 706 /* 707 * Make sure the interface is shutdown during reboot. 708 */ 709 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 710 pmf_class_network_register(self, ifp); 711 else 712 aprint_error_dev(self, "couldn't establish power handler\n"); 713 714 return; 715 716 /* 717 * Free any resources we've allocated during the failed attach 718 * attempt. Do this in reverse order and fall through. 719 */ 720 fail_5: 721 for (i = 0; i < STGE_NRXDESC; i++) { 722 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 723 bus_dmamap_destroy(sc->sc_dmat, 724 sc->sc_rxsoft[i].ds_dmamap); 725 } 726 fail_4: 727 for (i = 0; i < STGE_NTXDESC; i++) { 728 if (sc->sc_txsoft[i].ds_dmamap != NULL) 729 bus_dmamap_destroy(sc->sc_dmat, 730 sc->sc_txsoft[i].ds_dmamap); 731 } 732 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 733 fail_3: 734 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 735 fail_2: 736 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 737 sizeof(struct stge_control_data)); 738 fail_1: 739 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 740 fail_0: 741 return; 742 } 743 744 /* 745 * stge_shutdown: 746 * 747 * Make sure the interface is stopped at reboot time. 748 */ 749 static bool 750 stge_shutdown(device_t self, int howto) 751 { 752 struct stge_softc *sc = device_private(self); 753 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 754 755 stge_stop(ifp, 1); 756 stge_reset(sc); 757 return true; 758 } 759 760 static void 761 stge_dma_wait(struct stge_softc *sc) 762 { 763 int i; 764 765 for (i = 0; i < STGE_TIMEOUT; i++) { 766 delay(2); 767 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 768 DMAC_TxDMAInProg) == 0) 769 break; 770 } 771 772 if (i == STGE_TIMEOUT) 773 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 774 } 775 776 /* 777 * stge_start: [ifnet interface function] 778 * 779 * Start packet transmission on the interface. 780 */ 781 static void 782 stge_start(struct ifnet *ifp) 783 { 784 struct stge_softc *sc = ifp->if_softc; 785 struct mbuf *m0; 786 struct stge_descsoft *ds; 787 struct stge_tfd *tfd; 788 bus_dmamap_t dmamap; 789 int error, firsttx, nexttx, opending, seg, totlen; 790 uint64_t csum_flags; 791 792 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 793 return; 794 795 /* 796 * Remember the previous number of pending transmissions 797 * and the first descriptor we will use. 798 */ 799 opending = sc->sc_txpending; 800 firsttx = STGE_NEXTTX(sc->sc_txlast); 801 802 /* 803 * Loop through the send queue, setting up transmit descriptors 804 * until we drain the queue, or use up all available transmit 805 * descriptors. 806 */ 807 for (;;) { 808 struct m_tag *mtag; 809 uint64_t tfc; 810 811 /* 812 * Grab a packet off the queue. 813 */ 814 IFQ_POLL(&ifp->if_snd, m0); 815 if (m0 == NULL) 816 break; 817 818 /* 819 * Leave one unused descriptor at the end of the 820 * list to prevent wrapping completely around. 821 */ 822 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 823 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 824 break; 825 } 826 827 /* 828 * See if we have any VLAN stuff. 829 */ 830 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 831 832 /* 833 * Get the last and next available transmit descriptor. 834 */ 835 nexttx = STGE_NEXTTX(sc->sc_txlast); 836 tfd = &sc->sc_txdescs[nexttx]; 837 ds = &sc->sc_txsoft[nexttx]; 838 839 dmamap = ds->ds_dmamap; 840 841 /* 842 * Load the DMA map. If this fails, the packet either 843 * didn't fit in the alloted number of segments, or we 844 * were short on resources. For the too-many-segments 845 * case, we simply report an error and drop the packet, 846 * since we can't sanely copy a jumbo packet to a single 847 * buffer. 848 */ 849 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 850 BUS_DMA_NOWAIT); 851 if (error) { 852 if (error == EFBIG) { 853 printf("%s: Tx packet consumes too many " 854 "DMA segments, dropping...\n", 855 device_xname(sc->sc_dev)); 856 IFQ_DEQUEUE(&ifp->if_snd, m0); 857 m_freem(m0); 858 continue; 859 } 860 /* 861 * Short on resources, just stop for now. 862 */ 863 break; 864 } 865 866 IFQ_DEQUEUE(&ifp->if_snd, m0); 867 868 /* 869 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 870 */ 871 872 /* Sync the DMA map. */ 873 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 874 BUS_DMASYNC_PREWRITE); 875 876 /* Initialize the fragment list. */ 877 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 878 tfd->tfd_frags[seg].frag_word0 = 879 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 880 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 881 totlen += dmamap->dm_segs[seg].ds_len; 882 } 883 884 #ifdef STGE_EVENT_COUNTERS 885 switch (dmamap->dm_nsegs) { 886 case 1: 887 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 888 break; 889 case 2: 890 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 891 break; 892 case 3: 893 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 894 break; 895 case 4: 896 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 897 break; 898 case 5: 899 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 900 break; 901 default: 902 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 903 break; 904 } 905 #endif /* STGE_EVENT_COUNTERS */ 906 907 /* 908 * Initialize checksumming flags in the descriptor. 909 * Byte-swap constants so the compiler can optimize. 910 */ 911 csum_flags = 0; 912 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 913 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 914 csum_flags |= TFD_IPChecksumEnable; 915 } 916 917 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 918 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 919 csum_flags |= TFD_TCPChecksumEnable; 920 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 921 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 922 csum_flags |= TFD_UDPChecksumEnable; 923 } 924 925 /* 926 * Initialize the descriptor and give it to the chip. 927 * Check to see if we have a VLAN tag to insert. 928 */ 929 930 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 931 TFD_FragCount(seg) | csum_flags | 932 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 933 TFD_TxDMAIndicate : 0); 934 if (mtag) { 935 #if 0 936 struct ether_header *eh = 937 mtod(m0, struct ether_header *); 938 u_int16_t etype = ntohs(eh->ether_type); 939 printf("%s: xmit (tag %d) etype %x\n", 940 ifp->if_xname, *mtod(n, int *), etype); 941 #endif 942 tfc |= TFD_VLANTagInsert | 943 #ifdef STGE_VLAN_CFI 944 TFD_CFI | 945 #endif 946 TFD_VID(VLAN_TAG_VALUE(mtag)); 947 } 948 tfd->tfd_control = htole64(tfc); 949 950 /* Sync the descriptor. */ 951 STGE_CDTXSYNC(sc, nexttx, 952 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 953 954 /* 955 * Kick the transmit DMA logic. 956 */ 957 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 958 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 959 960 /* 961 * Store a pointer to the packet so we can free it later. 962 */ 963 ds->ds_mbuf = m0; 964 965 /* Advance the tx pointer. */ 966 sc->sc_txpending++; 967 sc->sc_txlast = nexttx; 968 969 /* 970 * Pass the packet to any BPF listeners. 971 */ 972 bpf_mtap(ifp, m0); 973 } 974 975 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 976 /* No more slots left; notify upper layer. */ 977 ifp->if_flags |= IFF_OACTIVE; 978 } 979 980 if (sc->sc_txpending != opending) { 981 /* 982 * We enqueued packets. If the transmitter was idle, 983 * reset the txdirty pointer. 984 */ 985 if (opending == 0) 986 sc->sc_txdirty = firsttx; 987 988 /* Set a watchdog timer in case the chip flakes out. */ 989 ifp->if_timer = 5; 990 } 991 } 992 993 /* 994 * stge_watchdog: [ifnet interface function] 995 * 996 * Watchdog timer handler. 997 */ 998 static void 999 stge_watchdog(struct ifnet *ifp) 1000 { 1001 struct stge_softc *sc = ifp->if_softc; 1002 1003 /* 1004 * Sweep up first, since we don't interrupt every frame. 1005 */ 1006 stge_txintr(sc); 1007 if (sc->sc_txpending != 0) { 1008 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1009 ifp->if_oerrors++; 1010 1011 (void) stge_init(ifp); 1012 1013 /* Try to get more packets going. */ 1014 stge_start(ifp); 1015 } 1016 } 1017 1018 /* 1019 * stge_ioctl: [ifnet interface function] 1020 * 1021 * Handle control requests from the operator. 1022 */ 1023 static int 1024 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1025 { 1026 struct stge_softc *sc = ifp->if_softc; 1027 int s, error; 1028 1029 s = splnet(); 1030 1031 error = ether_ioctl(ifp, cmd, data); 1032 if (error == ENETRESET) { 1033 error = 0; 1034 1035 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1036 ; 1037 else if (ifp->if_flags & IFF_RUNNING) { 1038 /* 1039 * Multicast list has changed; set the hardware filter 1040 * accordingly. 1041 */ 1042 stge_set_filter(sc); 1043 } 1044 } 1045 1046 /* Try to get more packets going. */ 1047 stge_start(ifp); 1048 1049 splx(s); 1050 return (error); 1051 } 1052 1053 /* 1054 * stge_intr: 1055 * 1056 * Interrupt service routine. 1057 */ 1058 static int 1059 stge_intr(void *arg) 1060 { 1061 struct stge_softc *sc = arg; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 uint32_t txstat; 1064 int wantinit; 1065 uint16_t isr; 1066 1067 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1068 IS_InterruptStatus) == 0) 1069 return (0); 1070 1071 for (wantinit = 0; wantinit == 0;) { 1072 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1073 if ((isr & sc->sc_IntEnable) == 0) 1074 break; 1075 1076 /* Host interface errors. */ 1077 if (isr & IS_HostError) { 1078 printf("%s: Host interface error\n", 1079 device_xname(sc->sc_dev)); 1080 wantinit = 1; 1081 continue; 1082 } 1083 1084 /* Receive interrupts. */ 1085 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1086 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1087 stge_rxintr(sc); 1088 if (isr & IS_RFDListEnd) { 1089 printf("%s: receive ring overflow\n", 1090 device_xname(sc->sc_dev)); 1091 /* 1092 * XXX Should try to recover from this 1093 * XXX more gracefully. 1094 */ 1095 wantinit = 1; 1096 } 1097 } 1098 1099 /* Transmit interrupts. */ 1100 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1101 #ifdef STGE_EVENT_COUNTERS 1102 if (isr & IS_TxDMAComplete) 1103 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1104 #endif 1105 stge_txintr(sc); 1106 } 1107 1108 /* Statistics overflow. */ 1109 if (isr & IS_UpdateStats) 1110 stge_stats_update(sc); 1111 1112 /* Transmission errors. */ 1113 if (isr & IS_TxComplete) { 1114 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1115 for (;;) { 1116 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1117 STGE_TxStatus); 1118 if ((txstat & TS_TxComplete) == 0) 1119 break; 1120 if (txstat & TS_TxUnderrun) { 1121 sc->sc_txthresh++; 1122 if (sc->sc_txthresh > 0x0fff) 1123 sc->sc_txthresh = 0x0fff; 1124 printf("%s: transmit underrun, new " 1125 "threshold: %d bytes\n", 1126 device_xname(sc->sc_dev), 1127 sc->sc_txthresh << 5); 1128 } 1129 if (txstat & TS_MaxCollisions) 1130 printf("%s: excessive collisions\n", 1131 device_xname(sc->sc_dev)); 1132 } 1133 wantinit = 1; 1134 } 1135 1136 } 1137 1138 if (wantinit) 1139 stge_init(ifp); 1140 1141 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1142 sc->sc_IntEnable); 1143 1144 /* Try to get more packets going. */ 1145 if_schedule_deferred_start(ifp); 1146 1147 return (1); 1148 } 1149 1150 /* 1151 * stge_txintr: 1152 * 1153 * Helper; handle transmit interrupts. 1154 */ 1155 static void 1156 stge_txintr(struct stge_softc *sc) 1157 { 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 struct stge_descsoft *ds; 1160 uint64_t control; 1161 int i; 1162 1163 ifp->if_flags &= ~IFF_OACTIVE; 1164 1165 /* 1166 * Go through our Tx list and free mbufs for those 1167 * frames which have been transmitted. 1168 */ 1169 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1170 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1171 ds = &sc->sc_txsoft[i]; 1172 1173 STGE_CDTXSYNC(sc, i, 1174 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1175 1176 control = le64toh(sc->sc_txdescs[i].tfd_control); 1177 if ((control & TFD_TFDDone) == 0) 1178 break; 1179 1180 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1181 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1182 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1183 m_freem(ds->ds_mbuf); 1184 ds->ds_mbuf = NULL; 1185 } 1186 1187 /* Update the dirty transmit buffer pointer. */ 1188 sc->sc_txdirty = i; 1189 1190 /* 1191 * If there are no more pending transmissions, cancel the watchdog 1192 * timer. 1193 */ 1194 if (sc->sc_txpending == 0) 1195 ifp->if_timer = 0; 1196 } 1197 1198 /* 1199 * stge_rxintr: 1200 * 1201 * Helper; handle receive interrupts. 1202 */ 1203 static void 1204 stge_rxintr(struct stge_softc *sc) 1205 { 1206 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1207 struct stge_descsoft *ds; 1208 struct mbuf *m, *tailm; 1209 uint64_t status; 1210 int i, len; 1211 1212 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1213 ds = &sc->sc_rxsoft[i]; 1214 1215 STGE_CDRXSYNC(sc, i, 1216 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1217 1218 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1219 1220 if ((status & RFD_RFDDone) == 0) 1221 break; 1222 1223 if (__predict_false(sc->sc_rxdiscard)) { 1224 STGE_INIT_RXDESC(sc, i); 1225 if (status & RFD_FrameEnd) { 1226 /* Reset our state. */ 1227 sc->sc_rxdiscard = 0; 1228 } 1229 continue; 1230 } 1231 1232 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1233 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1234 1235 m = ds->ds_mbuf; 1236 1237 /* 1238 * Add a new receive buffer to the ring. 1239 */ 1240 if (stge_add_rxbuf(sc, i) != 0) { 1241 /* 1242 * Failed, throw away what we've done so 1243 * far, and discard the rest of the packet. 1244 */ 1245 ifp->if_ierrors++; 1246 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1247 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1248 STGE_INIT_RXDESC(sc, i); 1249 if ((status & RFD_FrameEnd) == 0) 1250 sc->sc_rxdiscard = 1; 1251 if (sc->sc_rxhead != NULL) 1252 m_freem(sc->sc_rxhead); 1253 STGE_RXCHAIN_RESET(sc); 1254 continue; 1255 } 1256 1257 #ifdef DIAGNOSTIC 1258 if (status & RFD_FrameStart) { 1259 KASSERT(sc->sc_rxhead == NULL); 1260 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1261 } 1262 #endif 1263 1264 STGE_RXCHAIN_LINK(sc, m); 1265 1266 /* 1267 * If this is not the end of the packet, keep 1268 * looking. 1269 */ 1270 if ((status & RFD_FrameEnd) == 0) { 1271 sc->sc_rxlen += m->m_len; 1272 continue; 1273 } 1274 1275 /* 1276 * Okay, we have the entire packet now... 1277 */ 1278 *sc->sc_rxtailp = NULL; 1279 m = sc->sc_rxhead; 1280 tailm = sc->sc_rxtail; 1281 1282 STGE_RXCHAIN_RESET(sc); 1283 1284 /* 1285 * If the packet had an error, drop it. Note we 1286 * count the error later in the periodic stats update. 1287 */ 1288 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1289 RFD_RxAlignmentError | RFD_RxFCSError | 1290 RFD_RxLengthError)) { 1291 m_freem(m); 1292 continue; 1293 } 1294 1295 /* 1296 * No errors. 1297 * 1298 * Note we have configured the chip to not include 1299 * the CRC at the end of the packet. 1300 */ 1301 len = RFD_RxDMAFrameLen(status); 1302 tailm->m_len = len - sc->sc_rxlen; 1303 1304 /* 1305 * If the packet is small enough to fit in a 1306 * single header mbuf, allocate one and copy 1307 * the data into it. This greatly reduces 1308 * memory consumption when we receive lots 1309 * of small packets. 1310 */ 1311 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1312 struct mbuf *nm; 1313 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1314 if (nm == NULL) { 1315 ifp->if_ierrors++; 1316 m_freem(m); 1317 continue; 1318 } 1319 nm->m_data += 2; 1320 nm->m_pkthdr.len = nm->m_len = len; 1321 m_copydata(m, 0, len, mtod(nm, void *)); 1322 m_freem(m); 1323 m = nm; 1324 } 1325 1326 /* 1327 * Set the incoming checksum information for the packet. 1328 */ 1329 if (status & RFD_IPDetected) { 1330 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1331 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1332 if (status & RFD_IPError) 1333 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1334 if (status & RFD_TCPDetected) { 1335 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1336 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1337 if (status & RFD_TCPError) 1338 m->m_pkthdr.csum_flags |= 1339 M_CSUM_TCP_UDP_BAD; 1340 } else if (status & RFD_UDPDetected) { 1341 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1342 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1343 if (status & RFD_UDPError) 1344 m->m_pkthdr.csum_flags |= 1345 M_CSUM_TCP_UDP_BAD; 1346 } 1347 } 1348 1349 m_set_rcvif(m, ifp); 1350 m->m_pkthdr.len = len; 1351 1352 /* 1353 * Pass this up to any BPF listeners, but only 1354 * pass if up the stack if it's for us. 1355 */ 1356 #ifdef STGE_VLAN_UNTAG 1357 /* 1358 * Check for VLAN tagged packets 1359 */ 1360 if (status & RFD_VLANDetected) 1361 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1362 1363 #endif 1364 #if 0 1365 if (status & RFD_VLANDetected) { 1366 struct ether_header *eh; 1367 u_int16_t etype; 1368 1369 eh = mtod(m, struct ether_header *); 1370 etype = ntohs(eh->ether_type); 1371 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1372 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1373 etype); 1374 } 1375 #endif 1376 /* Pass it on. */ 1377 if_percpuq_enqueue(ifp->if_percpuq, m); 1378 } 1379 1380 /* Update the receive pointer. */ 1381 sc->sc_rxptr = i; 1382 } 1383 1384 /* 1385 * stge_tick: 1386 * 1387 * One second timer, used to tick the MII. 1388 */ 1389 static void 1390 stge_tick(void *arg) 1391 { 1392 struct stge_softc *sc = arg; 1393 int s; 1394 1395 s = splnet(); 1396 mii_tick(&sc->sc_mii); 1397 stge_stats_update(sc); 1398 splx(s); 1399 1400 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1401 } 1402 1403 /* 1404 * stge_stats_update: 1405 * 1406 * Read the TC9021 statistics counters. 1407 */ 1408 static void 1409 stge_stats_update(struct stge_softc *sc) 1410 { 1411 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1412 bus_space_tag_t st = sc->sc_st; 1413 bus_space_handle_t sh = sc->sc_sh; 1414 1415 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1416 1417 ifp->if_ipackets += 1418 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1419 1420 ifp->if_ierrors += 1421 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1422 1423 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1424 1425 ifp->if_opackets += 1426 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1427 1428 ifp->if_collisions += 1429 bus_space_read_4(st, sh, STGE_LateCollisions) + 1430 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1431 bus_space_read_4(st, sh, STGE_SingleColFrames); 1432 1433 ifp->if_oerrors += 1434 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1435 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1436 } 1437 1438 /* 1439 * stge_reset: 1440 * 1441 * Perform a soft reset on the TC9021. 1442 */ 1443 static void 1444 stge_reset(struct stge_softc *sc) 1445 { 1446 uint32_t ac; 1447 int i; 1448 1449 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1450 1451 /* 1452 * Only assert RstOut if we're fiber. We need GMII clocks 1453 * to be present in order for the reset to complete on fiber 1454 * cards. 1455 */ 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1457 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1458 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1459 (sc->sc_usefiber ? AC_RstOut : 0)); 1460 1461 delay(50000); 1462 1463 for (i = 0; i < STGE_TIMEOUT; i++) { 1464 delay(5000); 1465 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1466 AC_ResetBusy) == 0) 1467 break; 1468 } 1469 1470 if (i == STGE_TIMEOUT) 1471 printf("%s: reset failed to complete\n", 1472 device_xname(sc->sc_dev)); 1473 1474 delay(1000); 1475 } 1476 1477 /* 1478 * stge_init: [ ifnet interface function ] 1479 * 1480 * Initialize the interface. Must be called at splnet(). 1481 */ 1482 static int 1483 stge_init(struct ifnet *ifp) 1484 { 1485 struct stge_softc *sc = ifp->if_softc; 1486 bus_space_tag_t st = sc->sc_st; 1487 bus_space_handle_t sh = sc->sc_sh; 1488 struct stge_descsoft *ds; 1489 int i, error = 0; 1490 1491 /* 1492 * Cancel any pending I/O. 1493 */ 1494 stge_stop(ifp, 0); 1495 1496 /* 1497 * Reset the chip to a known state. 1498 */ 1499 stge_reset(sc); 1500 1501 /* 1502 * Initialize the transmit descriptor ring. 1503 */ 1504 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1505 for (i = 0; i < STGE_NTXDESC; i++) { 1506 sc->sc_txdescs[i].tfd_next = htole64( 1507 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1508 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1509 } 1510 sc->sc_txpending = 0; 1511 sc->sc_txdirty = 0; 1512 sc->sc_txlast = STGE_NTXDESC - 1; 1513 1514 /* 1515 * Initialize the receive descriptor and receive job 1516 * descriptor rings. 1517 */ 1518 for (i = 0; i < STGE_NRXDESC; i++) { 1519 ds = &sc->sc_rxsoft[i]; 1520 if (ds->ds_mbuf == NULL) { 1521 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1522 printf("%s: unable to allocate or map rx " 1523 "buffer %d, error = %d\n", 1524 device_xname(sc->sc_dev), i, error); 1525 /* 1526 * XXX Should attempt to run with fewer receive 1527 * XXX buffers instead of just failing. 1528 */ 1529 stge_rxdrain(sc); 1530 goto out; 1531 } 1532 } else 1533 STGE_INIT_RXDESC(sc, i); 1534 } 1535 sc->sc_rxptr = 0; 1536 sc->sc_rxdiscard = 0; 1537 STGE_RXCHAIN_RESET(sc); 1538 1539 /* Set the station address. */ 1540 for (i = 0; i < 6; i++) 1541 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1542 CLLADDR(ifp->if_sadl)[i]); 1543 1544 /* 1545 * Set the statistics masks. Disable all the RMON stats, 1546 * and disable selected stats in the non-RMON stats registers. 1547 */ 1548 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1549 bus_space_write_4(st, sh, STGE_StatisticsMask, 1550 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1551 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1552 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1553 (1U << 21)); 1554 1555 /* Set up the receive filter. */ 1556 stge_set_filter(sc); 1557 1558 /* 1559 * Give the transmit and receive ring to the chip. 1560 */ 1561 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1562 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1563 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1564 1565 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1566 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1567 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1568 1569 /* 1570 * Initialize the Tx auto-poll period. It's OK to make this number 1571 * large (255 is the max, but we use 127) -- we explicitly kick the 1572 * transmit engine when there's actually a packet. 1573 */ 1574 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1575 1576 /* ..and the Rx auto-poll period. */ 1577 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1578 1579 /* Initialize the Tx start threshold. */ 1580 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1581 1582 /* RX DMA thresholds, from linux */ 1583 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1584 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1585 1586 /* 1587 * Initialize the Rx DMA interrupt control register. We 1588 * request an interrupt after every incoming packet, but 1589 * defer it for 32us (64 * 512 ns). When the number of 1590 * interrupts pending reaches 8, we stop deferring the 1591 * interrupt, and signal it immediately. 1592 */ 1593 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1594 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1595 1596 /* 1597 * Initialize the interrupt mask. 1598 */ 1599 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1600 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1601 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1602 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1603 1604 /* 1605 * Configure the DMA engine. 1606 * XXX Should auto-tune TxBurstLimit. 1607 */ 1608 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1609 DMAC_TxBurstLimit(3)); 1610 1611 /* 1612 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1613 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1614 * empty again. 1615 */ 1616 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1617 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1618 1619 /* 1620 * Set the maximum frame size. 1621 */ 1622 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1623 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1624 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1625 ETHER_VLAN_ENCAP_LEN : 0)); 1626 1627 /* 1628 * Initialize MacCtrl -- do it before setting the media, 1629 * as setting the media will actually program the register. 1630 * 1631 * Note: We have to poke the IFS value before poking 1632 * anything else. 1633 */ 1634 sc->sc_MACCtrl = MC_IFSSelect(0); 1635 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1636 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1637 #ifdef STGE_VLAN_UNTAG 1638 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1639 #endif 1640 1641 if (sc->sc_rev >= 6) { /* >= B.2 */ 1642 /* Multi-frag frame bug work-around. */ 1643 bus_space_write_2(st, sh, STGE_DebugCtrl, 1644 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1645 1646 /* Tx Poll Now bug work-around. */ 1647 bus_space_write_2(st, sh, STGE_DebugCtrl, 1648 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1649 /* XXX ? from linux */ 1650 bus_space_write_2(st, sh, STGE_DebugCtrl, 1651 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1652 } 1653 1654 /* 1655 * Set the current media. 1656 */ 1657 if ((error = ether_mediachange(ifp)) != 0) 1658 goto out; 1659 1660 /* 1661 * Start the one second MII clock. 1662 */ 1663 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1664 1665 /* 1666 * ...all done! 1667 */ 1668 ifp->if_flags |= IFF_RUNNING; 1669 ifp->if_flags &= ~IFF_OACTIVE; 1670 1671 out: 1672 if (error) 1673 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1674 return (error); 1675 } 1676 1677 /* 1678 * stge_drain: 1679 * 1680 * Drain the receive queue. 1681 */ 1682 static void 1683 stge_rxdrain(struct stge_softc *sc) 1684 { 1685 struct stge_descsoft *ds; 1686 int i; 1687 1688 for (i = 0; i < STGE_NRXDESC; i++) { 1689 ds = &sc->sc_rxsoft[i]; 1690 if (ds->ds_mbuf != NULL) { 1691 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1692 ds->ds_mbuf->m_next = NULL; 1693 m_freem(ds->ds_mbuf); 1694 ds->ds_mbuf = NULL; 1695 } 1696 } 1697 } 1698 1699 /* 1700 * stge_stop: [ ifnet interface function ] 1701 * 1702 * Stop transmission on the interface. 1703 */ 1704 static void 1705 stge_stop(struct ifnet *ifp, int disable) 1706 { 1707 struct stge_softc *sc = ifp->if_softc; 1708 struct stge_descsoft *ds; 1709 int i; 1710 1711 /* 1712 * Stop the one second clock. 1713 */ 1714 callout_stop(&sc->sc_tick_ch); 1715 1716 /* Down the MII. */ 1717 mii_down(&sc->sc_mii); 1718 1719 /* 1720 * Disable interrupts. 1721 */ 1722 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1723 1724 /* 1725 * Stop receiver, transmitter, and stats update. 1726 */ 1727 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1728 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1729 1730 /* 1731 * Stop the transmit and receive DMA. 1732 */ 1733 stge_dma_wait(sc); 1734 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1735 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1736 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1737 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1738 1739 /* 1740 * Release any queued transmit buffers. 1741 */ 1742 for (i = 0; i < STGE_NTXDESC; i++) { 1743 ds = &sc->sc_txsoft[i]; 1744 if (ds->ds_mbuf != NULL) { 1745 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1746 m_freem(ds->ds_mbuf); 1747 ds->ds_mbuf = NULL; 1748 } 1749 } 1750 1751 /* 1752 * Mark the interface down and cancel the watchdog timer. 1753 */ 1754 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1755 ifp->if_timer = 0; 1756 1757 if (disable) 1758 stge_rxdrain(sc); 1759 } 1760 1761 static int 1762 stge_eeprom_wait(struct stge_softc *sc) 1763 { 1764 int i; 1765 1766 for (i = 0; i < STGE_TIMEOUT; i++) { 1767 delay(1000); 1768 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1769 EC_EepromBusy) == 0) 1770 return (0); 1771 } 1772 return (1); 1773 } 1774 1775 /* 1776 * stge_read_eeprom: 1777 * 1778 * Read data from the serial EEPROM. 1779 */ 1780 static void 1781 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1782 { 1783 1784 if (stge_eeprom_wait(sc)) 1785 printf("%s: EEPROM failed to come ready\n", 1786 device_xname(sc->sc_dev)); 1787 1788 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1789 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1790 if (stge_eeprom_wait(sc)) 1791 printf("%s: EEPROM read timed out\n", 1792 device_xname(sc->sc_dev)); 1793 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1794 } 1795 1796 /* 1797 * stge_add_rxbuf: 1798 * 1799 * Add a receive buffer to the indicated descriptor. 1800 */ 1801 static int 1802 stge_add_rxbuf(struct stge_softc *sc, int idx) 1803 { 1804 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1805 struct mbuf *m; 1806 int error; 1807 1808 MGETHDR(m, M_DONTWAIT, MT_DATA); 1809 if (m == NULL) 1810 return (ENOBUFS); 1811 1812 MCLGET(m, M_DONTWAIT); 1813 if ((m->m_flags & M_EXT) == 0) { 1814 m_freem(m); 1815 return (ENOBUFS); 1816 } 1817 1818 m->m_data = m->m_ext.ext_buf + 2; 1819 m->m_len = MCLBYTES - 2; 1820 1821 if (ds->ds_mbuf != NULL) 1822 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1823 1824 ds->ds_mbuf = m; 1825 1826 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1827 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1828 if (error) { 1829 printf("%s: can't load rx DMA map %d, error = %d\n", 1830 device_xname(sc->sc_dev), idx, error); 1831 panic("stge_add_rxbuf"); /* XXX */ 1832 } 1833 1834 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1835 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1836 1837 STGE_INIT_RXDESC(sc, idx); 1838 1839 return (0); 1840 } 1841 1842 /* 1843 * stge_set_filter: 1844 * 1845 * Set up the receive filter. 1846 */ 1847 static void 1848 stge_set_filter(struct stge_softc *sc) 1849 { 1850 struct ethercom *ec = &sc->sc_ethercom; 1851 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1852 struct ether_multi *enm; 1853 struct ether_multistep step; 1854 uint32_t crc; 1855 uint32_t mchash[2]; 1856 1857 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1858 if (ifp->if_flags & IFF_BROADCAST) 1859 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1860 1861 /* XXX: ST1023 only works in promiscuous mode */ 1862 if (sc->sc_stge1023) 1863 ifp->if_flags |= IFF_PROMISC; 1864 1865 if (ifp->if_flags & IFF_PROMISC) { 1866 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1867 goto allmulti; 1868 } 1869 1870 /* 1871 * Set up the multicast address filter by passing all multicast 1872 * addresses through a CRC generator, and then using the low-order 1873 * 6 bits as an index into the 64 bit multicast hash table. The 1874 * high order bits select the register, while the rest of the bits 1875 * select the bit within the register. 1876 */ 1877 1878 memset(mchash, 0, sizeof(mchash)); 1879 1880 ETHER_FIRST_MULTI(step, ec, enm); 1881 if (enm == NULL) 1882 goto done; 1883 1884 while (enm != NULL) { 1885 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1886 /* 1887 * We must listen to a range of multicast addresses. 1888 * For now, just accept all multicasts, rather than 1889 * trying to set only those filter bits needed to match 1890 * the range. (At this time, the only use of address 1891 * ranges is for IP multicast routing, for which the 1892 * range is big enough to require all bits set.) 1893 */ 1894 goto allmulti; 1895 } 1896 1897 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1898 1899 /* Just want the 6 least significant bits. */ 1900 crc &= 0x3f; 1901 1902 /* Set the corresponding bit in the hash table. */ 1903 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1904 1905 ETHER_NEXT_MULTI(step, enm); 1906 } 1907 1908 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1909 1910 ifp->if_flags &= ~IFF_ALLMULTI; 1911 goto done; 1912 1913 allmulti: 1914 ifp->if_flags |= IFF_ALLMULTI; 1915 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1916 1917 done: 1918 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1919 /* 1920 * Program the multicast hash table. 1921 */ 1922 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1923 mchash[0]); 1924 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1925 mchash[1]); 1926 } 1927 1928 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1929 sc->sc_ReceiveMode); 1930 } 1931 1932 /* 1933 * stge_mii_readreg: [mii interface function] 1934 * 1935 * Read a PHY register on the MII of the TC9021. 1936 */ 1937 static int 1938 stge_mii_readreg(device_t self, int phy, int reg) 1939 { 1940 1941 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1942 } 1943 1944 /* 1945 * stge_mii_writereg: [mii interface function] 1946 * 1947 * Write a PHY register on the MII of the TC9021. 1948 */ 1949 static void 1950 stge_mii_writereg(device_t self, int phy, int reg, int val) 1951 { 1952 1953 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1954 } 1955 1956 /* 1957 * stge_mii_statchg: [mii interface function] 1958 * 1959 * Callback from MII layer when media changes. 1960 */ 1961 static void 1962 stge_mii_statchg(struct ifnet *ifp) 1963 { 1964 struct stge_softc *sc = ifp->if_softc; 1965 1966 if (sc->sc_mii.mii_media_active & IFM_FDX) 1967 sc->sc_MACCtrl |= MC_DuplexSelect; 1968 else 1969 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1970 1971 /* XXX 802.1x flow-control? */ 1972 1973 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1974 } 1975 1976 /* 1977 * sste_mii_bitbang_read: [mii bit-bang interface function] 1978 * 1979 * Read the MII serial port for the MII bit-bang module. 1980 */ 1981 static uint32_t 1982 stge_mii_bitbang_read(device_t self) 1983 { 1984 struct stge_softc *sc = device_private(self); 1985 1986 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1987 } 1988 1989 /* 1990 * stge_mii_bitbang_write: [mii big-bang interface function] 1991 * 1992 * Write the MII serial port for the MII bit-bang module. 1993 */ 1994 static void 1995 stge_mii_bitbang_write(device_t self, uint32_t val) 1996 { 1997 struct stge_softc *sc = device_private(self); 1998 1999 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2000 val | sc->sc_PhyCtrl); 2001 } 2002