1 /* $NetBSD: if_stge.c,v 1.64 2017/09/28 16:23:57 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.64 2017/09/28 16:23:57 christos Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int); 282 static void stge_mii_writereg(device_t, int, int, int); 283 static void stge_mii_statchg(struct ifnet *); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 pci_intr_handle_t ih; 380 const char *intrstr = NULL; 381 bus_space_tag_t iot, memt; 382 bus_space_handle_t ioh, memh; 383 bus_dma_segment_t seg; 384 prop_data_t data; 385 int ioh_valid, memh_valid; 386 int i, rseg, error; 387 const struct stge_product *sp; 388 uint8_t enaddr[ETHER_ADDR_LEN]; 389 char intrbuf[PCI_INTRSTR_LEN]; 390 391 callout_init(&sc->sc_tick_ch, 0); 392 393 sp = stge_lookup(pa); 394 if (sp == NULL) { 395 printf("\n"); 396 panic("ste_attach: impossible"); 397 } 398 399 sc->sc_rev = PCI_REVISION(pa->pa_class); 400 401 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 402 403 /* 404 * Map the device. 405 */ 406 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 407 PCI_MAPREG_TYPE_IO, 0, 408 &iot, &ioh, NULL, NULL) == 0); 409 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 410 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 411 &memt, &memh, NULL, NULL) == 0); 412 413 if (memh_valid) { 414 sc->sc_st = memt; 415 sc->sc_sh = memh; 416 } else if (ioh_valid) { 417 sc->sc_st = iot; 418 sc->sc_sh = ioh; 419 } else { 420 aprint_error_dev(self, "unable to map device registers\n"); 421 return; 422 } 423 424 sc->sc_dmat = pa->pa_dmat; 425 426 /* Enable bus mastering. */ 427 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 428 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 429 PCI_COMMAND_MASTER_ENABLE); 430 431 /* power up chip */ 432 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 433 error != EOPNOTSUPP) { 434 aprint_error_dev(self, "cannot activate %d\n", error); 435 return; 436 } 437 /* 438 * Map and establish our interrupt. 439 */ 440 if (pci_intr_map(pa, &ih)) { 441 aprint_error_dev(self, "unable to map interrupt\n"); 442 return; 443 } 444 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 445 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 446 if (sc->sc_ih == NULL) { 447 aprint_error_dev(self, "unable to establish interrupt"); 448 if (intrstr != NULL) 449 aprint_error(" at %s", intrstr); 450 aprint_error("\n"); 451 return; 452 } 453 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 454 455 /* 456 * Allocate the control data structures, and create and load the 457 * DMA map for it. 458 */ 459 if ((error = bus_dmamem_alloc(sc->sc_dmat, 460 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 461 0)) != 0) { 462 aprint_error_dev(self, 463 "unable to allocate control data, error = %d\n", error); 464 goto fail_0; 465 } 466 467 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 468 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 469 BUS_DMA_COHERENT)) != 0) { 470 aprint_error_dev(self, 471 "unable to map control data, error = %d\n", error); 472 goto fail_1; 473 } 474 475 if ((error = bus_dmamap_create(sc->sc_dmat, 476 sizeof(struct stge_control_data), 1, 477 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 478 aprint_error_dev(self, 479 "unable to create control data DMA map, error = %d\n", 480 error); 481 goto fail_2; 482 } 483 484 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 485 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 486 0)) != 0) { 487 aprint_error_dev(self, 488 "unable to load control data DMA map, error = %d\n", 489 error); 490 goto fail_3; 491 } 492 493 /* 494 * Create the transmit buffer DMA maps. Note that rev B.3 495 * and earlier seem to have a bug regarding multi-fragment 496 * packets. We need to limit the number of Tx segments on 497 * such chips to 1. 498 */ 499 for (i = 0; i < STGE_NTXDESC; i++) { 500 if ((error = bus_dmamap_create(sc->sc_dmat, 501 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 502 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 503 aprint_error_dev(self, 504 "unable to create tx DMA map %d, error = %d\n", 505 i, error); 506 goto fail_4; 507 } 508 } 509 510 /* 511 * Create the receive buffer DMA maps. 512 */ 513 for (i = 0; i < STGE_NRXDESC; i++) { 514 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 515 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 516 aprint_error_dev(self, 517 "unable to create rx DMA map %d, error = %d\n", 518 i, error); 519 goto fail_5; 520 } 521 sc->sc_rxsoft[i].ds_mbuf = NULL; 522 } 523 524 /* 525 * Determine if we're copper or fiber. It affects how we 526 * reset the card. 527 */ 528 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 529 AC_PhyMedia) 530 sc->sc_usefiber = 1; 531 else 532 sc->sc_usefiber = 0; 533 534 /* 535 * Reset the chip to a known state. 536 */ 537 stge_reset(sc); 538 539 /* 540 * Reading the station address from the EEPROM doesn't seem 541 * to work, at least on my sample boards. Instead, since 542 * the reset sequence does AutoInit, read it from the station 543 * address registers. For Sundance 1023 you can only read it 544 * from EEPROM. 545 */ 546 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 547 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 548 STGE_StationAddress0) & 0xff; 549 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 550 STGE_StationAddress0) >> 8; 551 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress1) & 0xff; 553 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress1) >> 8; 555 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress2) & 0xff; 557 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress2) >> 8; 559 sc->sc_stge1023 = 0; 560 } else { 561 data = prop_dictionary_get(device_properties(self), 562 "mac-address"); 563 if (data != NULL) { 564 /* 565 * Try to get the station address from device 566 * properties first, in case the EEPROM is missing. 567 */ 568 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 569 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 570 (void)memcpy(enaddr, prop_data_data_nocopy(data), 571 ETHER_ADDR_LEN); 572 } else { 573 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 574 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 575 stge_read_eeprom(sc, 576 STGE_EEPROM_StationAddress0 + i, 577 &myaddr[i]); 578 myaddr[i] = le16toh(myaddr[i]); 579 } 580 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 581 } 582 sc->sc_stge1023 = 1; 583 } 584 585 aprint_normal_dev(self, "Ethernet address %s\n", 586 ether_sprintf(enaddr)); 587 588 /* 589 * Read some important bits from the PhyCtrl register. 590 */ 591 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 592 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 593 594 /* 595 * Initialize our media structures and probe the MII. 596 */ 597 sc->sc_mii.mii_ifp = ifp; 598 sc->sc_mii.mii_readreg = stge_mii_readreg; 599 sc->sc_mii.mii_writereg = stge_mii_writereg; 600 sc->sc_mii.mii_statchg = stge_mii_statchg; 601 sc->sc_ethercom.ec_mii = &sc->sc_mii; 602 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 603 ether_mediastatus); 604 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 605 MII_OFFSET_ANY, MIIF_DOPAUSE); 606 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 607 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 608 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 609 } else 610 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 611 612 ifp = &sc->sc_ethercom.ec_if; 613 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 614 ifp->if_softc = sc; 615 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 616 ifp->if_ioctl = stge_ioctl; 617 ifp->if_start = stge_start; 618 ifp->if_watchdog = stge_watchdog; 619 ifp->if_init = stge_init; 620 ifp->if_stop = stge_stop; 621 IFQ_SET_READY(&ifp->if_snd); 622 623 /* 624 * The manual recommends disabling early transmit, so we 625 * do. It's disabled anyway, if using IP checksumming, 626 * since the entire packet must be in the FIFO in order 627 * for the chip to perform the checksum. 628 */ 629 sc->sc_txthresh = 0x0fff; 630 631 /* 632 * Disable MWI if the PCI layer tells us to. 633 */ 634 sc->sc_DMACtrl = 0; 635 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 636 sc->sc_DMACtrl |= DMAC_MWIDisable; 637 638 /* 639 * We can support 802.1Q VLAN-sized frames and jumbo 640 * Ethernet frames. 641 * 642 * XXX Figure out how to do hw-assisted VLAN tagging in 643 * XXX a reasonable way on this chip. 644 */ 645 sc->sc_ethercom.ec_capabilities |= 646 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 647 ETHERCAP_VLAN_HWTAGGING; 648 649 /* 650 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 651 */ 652 sc->sc_ethercom.ec_if.if_capabilities |= 653 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 654 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 655 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 656 657 /* 658 * Attach the interface. 659 */ 660 if_attach(ifp); 661 if_deferred_start_init(ifp, NULL); 662 ether_ifattach(ifp, enaddr); 663 664 #ifdef STGE_EVENT_COUNTERS 665 /* 666 * Attach event counters. 667 */ 668 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 669 NULL, device_xname(self), "txstall"); 670 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 671 NULL, device_xname(self), "txdmaintr"); 672 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 673 NULL, device_xname(self), "txindintr"); 674 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 675 NULL, device_xname(self), "rxintr"); 676 677 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 678 NULL, device_xname(self), "txseg1"); 679 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "txseg2"); 681 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "txseg3"); 683 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "txseg4"); 685 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "txseg5"); 687 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "txsegmore"); 689 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "txcopy"); 691 692 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 693 NULL, device_xname(self), "rxipsum"); 694 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 695 NULL, device_xname(self), "rxtcpsum"); 696 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 697 NULL, device_xname(self), "rxudpsum"); 698 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 699 NULL, device_xname(self), "txipsum"); 700 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 701 NULL, device_xname(self), "txtcpsum"); 702 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 703 NULL, device_xname(self), "txudpsum"); 704 #endif /* STGE_EVENT_COUNTERS */ 705 706 /* 707 * Make sure the interface is shutdown during reboot. 708 */ 709 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 710 pmf_class_network_register(self, ifp); 711 else 712 aprint_error_dev(self, "couldn't establish power handler\n"); 713 714 return; 715 716 /* 717 * Free any resources we've allocated during the failed attach 718 * attempt. Do this in reverse order and fall through. 719 */ 720 fail_5: 721 for (i = 0; i < STGE_NRXDESC; i++) { 722 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 723 bus_dmamap_destroy(sc->sc_dmat, 724 sc->sc_rxsoft[i].ds_dmamap); 725 } 726 fail_4: 727 for (i = 0; i < STGE_NTXDESC; i++) { 728 if (sc->sc_txsoft[i].ds_dmamap != NULL) 729 bus_dmamap_destroy(sc->sc_dmat, 730 sc->sc_txsoft[i].ds_dmamap); 731 } 732 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 733 fail_3: 734 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 735 fail_2: 736 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 737 sizeof(struct stge_control_data)); 738 fail_1: 739 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 740 fail_0: 741 return; 742 } 743 744 /* 745 * stge_shutdown: 746 * 747 * Make sure the interface is stopped at reboot time. 748 */ 749 static bool 750 stge_shutdown(device_t self, int howto) 751 { 752 struct stge_softc *sc = device_private(self); 753 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 754 755 stge_stop(ifp, 1); 756 stge_reset(sc); 757 return true; 758 } 759 760 static void 761 stge_dma_wait(struct stge_softc *sc) 762 { 763 int i; 764 765 for (i = 0; i < STGE_TIMEOUT; i++) { 766 delay(2); 767 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 768 DMAC_TxDMAInProg) == 0) 769 break; 770 } 771 772 if (i == STGE_TIMEOUT) 773 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 774 } 775 776 /* 777 * stge_start: [ifnet interface function] 778 * 779 * Start packet transmission on the interface. 780 */ 781 static void 782 stge_start(struct ifnet *ifp) 783 { 784 struct stge_softc *sc = ifp->if_softc; 785 struct mbuf *m0; 786 struct stge_descsoft *ds; 787 struct stge_tfd *tfd; 788 bus_dmamap_t dmamap; 789 int error, firsttx, nexttx, opending, seg, totlen; 790 uint64_t csum_flags; 791 792 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 793 return; 794 795 /* 796 * Remember the previous number of pending transmissions 797 * and the first descriptor we will use. 798 */ 799 opending = sc->sc_txpending; 800 firsttx = STGE_NEXTTX(sc->sc_txlast); 801 802 /* 803 * Loop through the send queue, setting up transmit descriptors 804 * until we drain the queue, or use up all available transmit 805 * descriptors. 806 */ 807 for (;;) { 808 uint64_t tfc; 809 bool have_vtag; 810 uint16_t vtag; 811 812 /* 813 * Grab a packet off the queue. 814 */ 815 IFQ_POLL(&ifp->if_snd, m0); 816 if (m0 == NULL) 817 break; 818 819 /* 820 * Leave one unused descriptor at the end of the 821 * list to prevent wrapping completely around. 822 */ 823 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 824 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 825 break; 826 } 827 828 /* 829 * See if we have any VLAN stuff. 830 */ 831 have_vtag = vlan_has_tag(m0); 832 if (have_vtag) 833 vtag = vlan_get_tag(m0); 834 835 /* 836 * Get the last and next available transmit descriptor. 837 */ 838 nexttx = STGE_NEXTTX(sc->sc_txlast); 839 tfd = &sc->sc_txdescs[nexttx]; 840 ds = &sc->sc_txsoft[nexttx]; 841 842 dmamap = ds->ds_dmamap; 843 844 /* 845 * Load the DMA map. If this fails, the packet either 846 * didn't fit in the alloted number of segments, or we 847 * were short on resources. For the too-many-segments 848 * case, we simply report an error and drop the packet, 849 * since we can't sanely copy a jumbo packet to a single 850 * buffer. 851 */ 852 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 853 BUS_DMA_NOWAIT); 854 if (error) { 855 if (error == EFBIG) { 856 printf("%s: Tx packet consumes too many " 857 "DMA segments, dropping...\n", 858 device_xname(sc->sc_dev)); 859 IFQ_DEQUEUE(&ifp->if_snd, m0); 860 m_freem(m0); 861 continue; 862 } 863 /* 864 * Short on resources, just stop for now. 865 */ 866 break; 867 } 868 869 IFQ_DEQUEUE(&ifp->if_snd, m0); 870 871 /* 872 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 873 */ 874 875 /* Sync the DMA map. */ 876 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 877 BUS_DMASYNC_PREWRITE); 878 879 /* Initialize the fragment list. */ 880 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 881 tfd->tfd_frags[seg].frag_word0 = 882 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 883 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 884 totlen += dmamap->dm_segs[seg].ds_len; 885 } 886 887 #ifdef STGE_EVENT_COUNTERS 888 switch (dmamap->dm_nsegs) { 889 case 1: 890 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 891 break; 892 case 2: 893 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 894 break; 895 case 3: 896 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 897 break; 898 case 4: 899 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 900 break; 901 case 5: 902 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 903 break; 904 default: 905 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 906 break; 907 } 908 #endif /* STGE_EVENT_COUNTERS */ 909 910 /* 911 * Initialize checksumming flags in the descriptor. 912 * Byte-swap constants so the compiler can optimize. 913 */ 914 csum_flags = 0; 915 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 916 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 917 csum_flags |= TFD_IPChecksumEnable; 918 } 919 920 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 921 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 922 csum_flags |= TFD_TCPChecksumEnable; 923 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 924 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 925 csum_flags |= TFD_UDPChecksumEnable; 926 } 927 928 /* 929 * Initialize the descriptor and give it to the chip. 930 * Check to see if we have a VLAN tag to insert. 931 */ 932 933 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 934 TFD_FragCount(seg) | csum_flags | 935 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 936 TFD_TxDMAIndicate : 0); 937 if (have_vtag) { 938 #if 0 939 struct ether_header *eh = 940 mtod(m0, struct ether_header *); 941 u_int16_t etype = ntohs(eh->ether_type); 942 printf("%s: xmit (tag %d) etype %x\n", 943 ifp->if_xname, *mtod(n, int *), etype); 944 #endif 945 tfc |= TFD_VLANTagInsert | 946 #ifdef STGE_VLAN_CFI 947 TFD_CFI | 948 #endif 949 TFD_VID(vtag); 950 } 951 tfd->tfd_control = htole64(tfc); 952 953 /* Sync the descriptor. */ 954 STGE_CDTXSYNC(sc, nexttx, 955 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 956 957 /* 958 * Kick the transmit DMA logic. 959 */ 960 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 961 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 962 963 /* 964 * Store a pointer to the packet so we can free it later. 965 */ 966 ds->ds_mbuf = m0; 967 968 /* Advance the tx pointer. */ 969 sc->sc_txpending++; 970 sc->sc_txlast = nexttx; 971 972 /* 973 * Pass the packet to any BPF listeners. 974 */ 975 bpf_mtap(ifp, m0); 976 } 977 978 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 979 /* No more slots left; notify upper layer. */ 980 ifp->if_flags |= IFF_OACTIVE; 981 } 982 983 if (sc->sc_txpending != opending) { 984 /* 985 * We enqueued packets. If the transmitter was idle, 986 * reset the txdirty pointer. 987 */ 988 if (opending == 0) 989 sc->sc_txdirty = firsttx; 990 991 /* Set a watchdog timer in case the chip flakes out. */ 992 ifp->if_timer = 5; 993 } 994 } 995 996 /* 997 * stge_watchdog: [ifnet interface function] 998 * 999 * Watchdog timer handler. 1000 */ 1001 static void 1002 stge_watchdog(struct ifnet *ifp) 1003 { 1004 struct stge_softc *sc = ifp->if_softc; 1005 1006 /* 1007 * Sweep up first, since we don't interrupt every frame. 1008 */ 1009 stge_txintr(sc); 1010 if (sc->sc_txpending != 0) { 1011 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1012 ifp->if_oerrors++; 1013 1014 (void) stge_init(ifp); 1015 1016 /* Try to get more packets going. */ 1017 stge_start(ifp); 1018 } 1019 } 1020 1021 /* 1022 * stge_ioctl: [ifnet interface function] 1023 * 1024 * Handle control requests from the operator. 1025 */ 1026 static int 1027 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1028 { 1029 struct stge_softc *sc = ifp->if_softc; 1030 int s, error; 1031 1032 s = splnet(); 1033 1034 error = ether_ioctl(ifp, cmd, data); 1035 if (error == ENETRESET) { 1036 error = 0; 1037 1038 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1039 ; 1040 else if (ifp->if_flags & IFF_RUNNING) { 1041 /* 1042 * Multicast list has changed; set the hardware filter 1043 * accordingly. 1044 */ 1045 stge_set_filter(sc); 1046 } 1047 } 1048 1049 /* Try to get more packets going. */ 1050 stge_start(ifp); 1051 1052 splx(s); 1053 return (error); 1054 } 1055 1056 /* 1057 * stge_intr: 1058 * 1059 * Interrupt service routine. 1060 */ 1061 static int 1062 stge_intr(void *arg) 1063 { 1064 struct stge_softc *sc = arg; 1065 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1066 uint32_t txstat; 1067 int wantinit; 1068 uint16_t isr; 1069 1070 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1071 IS_InterruptStatus) == 0) 1072 return (0); 1073 1074 for (wantinit = 0; wantinit == 0;) { 1075 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1076 if ((isr & sc->sc_IntEnable) == 0) 1077 break; 1078 1079 /* Host interface errors. */ 1080 if (isr & IS_HostError) { 1081 printf("%s: Host interface error\n", 1082 device_xname(sc->sc_dev)); 1083 wantinit = 1; 1084 continue; 1085 } 1086 1087 /* Receive interrupts. */ 1088 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1089 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1090 stge_rxintr(sc); 1091 if (isr & IS_RFDListEnd) { 1092 printf("%s: receive ring overflow\n", 1093 device_xname(sc->sc_dev)); 1094 /* 1095 * XXX Should try to recover from this 1096 * XXX more gracefully. 1097 */ 1098 wantinit = 1; 1099 } 1100 } 1101 1102 /* Transmit interrupts. */ 1103 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1104 #ifdef STGE_EVENT_COUNTERS 1105 if (isr & IS_TxDMAComplete) 1106 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1107 #endif 1108 stge_txintr(sc); 1109 } 1110 1111 /* Statistics overflow. */ 1112 if (isr & IS_UpdateStats) 1113 stge_stats_update(sc); 1114 1115 /* Transmission errors. */ 1116 if (isr & IS_TxComplete) { 1117 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1118 for (;;) { 1119 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1120 STGE_TxStatus); 1121 if ((txstat & TS_TxComplete) == 0) 1122 break; 1123 if (txstat & TS_TxUnderrun) { 1124 sc->sc_txthresh++; 1125 if (sc->sc_txthresh > 0x0fff) 1126 sc->sc_txthresh = 0x0fff; 1127 printf("%s: transmit underrun, new " 1128 "threshold: %d bytes\n", 1129 device_xname(sc->sc_dev), 1130 sc->sc_txthresh << 5); 1131 } 1132 if (txstat & TS_MaxCollisions) 1133 printf("%s: excessive collisions\n", 1134 device_xname(sc->sc_dev)); 1135 } 1136 wantinit = 1; 1137 } 1138 1139 } 1140 1141 if (wantinit) 1142 stge_init(ifp); 1143 1144 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1145 sc->sc_IntEnable); 1146 1147 /* Try to get more packets going. */ 1148 if_schedule_deferred_start(ifp); 1149 1150 return (1); 1151 } 1152 1153 /* 1154 * stge_txintr: 1155 * 1156 * Helper; handle transmit interrupts. 1157 */ 1158 static void 1159 stge_txintr(struct stge_softc *sc) 1160 { 1161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162 struct stge_descsoft *ds; 1163 uint64_t control; 1164 int i; 1165 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 1168 /* 1169 * Go through our Tx list and free mbufs for those 1170 * frames which have been transmitted. 1171 */ 1172 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1173 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1174 ds = &sc->sc_txsoft[i]; 1175 1176 STGE_CDTXSYNC(sc, i, 1177 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1178 1179 control = le64toh(sc->sc_txdescs[i].tfd_control); 1180 if ((control & TFD_TFDDone) == 0) 1181 break; 1182 1183 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1184 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1185 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1186 m_freem(ds->ds_mbuf); 1187 ds->ds_mbuf = NULL; 1188 } 1189 1190 /* Update the dirty transmit buffer pointer. */ 1191 sc->sc_txdirty = i; 1192 1193 /* 1194 * If there are no more pending transmissions, cancel the watchdog 1195 * timer. 1196 */ 1197 if (sc->sc_txpending == 0) 1198 ifp->if_timer = 0; 1199 } 1200 1201 /* 1202 * stge_rxintr: 1203 * 1204 * Helper; handle receive interrupts. 1205 */ 1206 static void 1207 stge_rxintr(struct stge_softc *sc) 1208 { 1209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1210 struct stge_descsoft *ds; 1211 struct mbuf *m, *tailm; 1212 uint64_t status; 1213 int i, len; 1214 1215 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1216 ds = &sc->sc_rxsoft[i]; 1217 1218 STGE_CDRXSYNC(sc, i, 1219 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1220 1221 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1222 1223 if ((status & RFD_RFDDone) == 0) 1224 break; 1225 1226 if (__predict_false(sc->sc_rxdiscard)) { 1227 STGE_INIT_RXDESC(sc, i); 1228 if (status & RFD_FrameEnd) { 1229 /* Reset our state. */ 1230 sc->sc_rxdiscard = 0; 1231 } 1232 continue; 1233 } 1234 1235 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1236 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1237 1238 m = ds->ds_mbuf; 1239 1240 /* 1241 * Add a new receive buffer to the ring. 1242 */ 1243 if (stge_add_rxbuf(sc, i) != 0) { 1244 /* 1245 * Failed, throw away what we've done so 1246 * far, and discard the rest of the packet. 1247 */ 1248 ifp->if_ierrors++; 1249 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1250 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1251 STGE_INIT_RXDESC(sc, i); 1252 if ((status & RFD_FrameEnd) == 0) 1253 sc->sc_rxdiscard = 1; 1254 if (sc->sc_rxhead != NULL) 1255 m_freem(sc->sc_rxhead); 1256 STGE_RXCHAIN_RESET(sc); 1257 continue; 1258 } 1259 1260 #ifdef DIAGNOSTIC 1261 if (status & RFD_FrameStart) { 1262 KASSERT(sc->sc_rxhead == NULL); 1263 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1264 } 1265 #endif 1266 1267 STGE_RXCHAIN_LINK(sc, m); 1268 1269 /* 1270 * If this is not the end of the packet, keep 1271 * looking. 1272 */ 1273 if ((status & RFD_FrameEnd) == 0) { 1274 sc->sc_rxlen += m->m_len; 1275 continue; 1276 } 1277 1278 /* 1279 * Okay, we have the entire packet now... 1280 */ 1281 *sc->sc_rxtailp = NULL; 1282 m = sc->sc_rxhead; 1283 tailm = sc->sc_rxtail; 1284 1285 STGE_RXCHAIN_RESET(sc); 1286 1287 /* 1288 * If the packet had an error, drop it. Note we 1289 * count the error later in the periodic stats update. 1290 */ 1291 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1292 RFD_RxAlignmentError | RFD_RxFCSError | 1293 RFD_RxLengthError)) { 1294 m_freem(m); 1295 continue; 1296 } 1297 1298 /* 1299 * No errors. 1300 * 1301 * Note we have configured the chip to not include 1302 * the CRC at the end of the packet. 1303 */ 1304 len = RFD_RxDMAFrameLen(status); 1305 tailm->m_len = len - sc->sc_rxlen; 1306 1307 /* 1308 * If the packet is small enough to fit in a 1309 * single header mbuf, allocate one and copy 1310 * the data into it. This greatly reduces 1311 * memory consumption when we receive lots 1312 * of small packets. 1313 */ 1314 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1315 struct mbuf *nm; 1316 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1317 if (nm == NULL) { 1318 ifp->if_ierrors++; 1319 m_freem(m); 1320 continue; 1321 } 1322 nm->m_data += 2; 1323 nm->m_pkthdr.len = nm->m_len = len; 1324 m_copydata(m, 0, len, mtod(nm, void *)); 1325 m_freem(m); 1326 m = nm; 1327 } 1328 1329 /* 1330 * Set the incoming checksum information for the packet. 1331 */ 1332 if (status & RFD_IPDetected) { 1333 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1334 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1335 if (status & RFD_IPError) 1336 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1337 if (status & RFD_TCPDetected) { 1338 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1339 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1340 if (status & RFD_TCPError) 1341 m->m_pkthdr.csum_flags |= 1342 M_CSUM_TCP_UDP_BAD; 1343 } else if (status & RFD_UDPDetected) { 1344 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1345 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1346 if (status & RFD_UDPError) 1347 m->m_pkthdr.csum_flags |= 1348 M_CSUM_TCP_UDP_BAD; 1349 } 1350 } 1351 1352 m_set_rcvif(m, ifp); 1353 m->m_pkthdr.len = len; 1354 1355 /* 1356 * Pass this up to any BPF listeners, but only 1357 * pass if up the stack if it's for us. 1358 */ 1359 #ifdef STGE_VLAN_UNTAG 1360 /* 1361 * Check for VLAN tagged packets 1362 */ 1363 if (status & RFD_VLANDetected) 1364 vlan_set_tag(m, RFD_TCI(status)); 1365 1366 #endif 1367 #if 0 1368 if (status & RFD_VLANDetected) { 1369 struct ether_header *eh; 1370 u_int16_t etype; 1371 1372 eh = mtod(m, struct ether_header *); 1373 etype = ntohs(eh->ether_type); 1374 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1375 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1376 etype); 1377 } 1378 #endif 1379 /* Pass it on. */ 1380 if_percpuq_enqueue(ifp->if_percpuq, m); 1381 } 1382 1383 /* Update the receive pointer. */ 1384 sc->sc_rxptr = i; 1385 } 1386 1387 /* 1388 * stge_tick: 1389 * 1390 * One second timer, used to tick the MII. 1391 */ 1392 static void 1393 stge_tick(void *arg) 1394 { 1395 struct stge_softc *sc = arg; 1396 int s; 1397 1398 s = splnet(); 1399 mii_tick(&sc->sc_mii); 1400 stge_stats_update(sc); 1401 splx(s); 1402 1403 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1404 } 1405 1406 /* 1407 * stge_stats_update: 1408 * 1409 * Read the TC9021 statistics counters. 1410 */ 1411 static void 1412 stge_stats_update(struct stge_softc *sc) 1413 { 1414 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1415 bus_space_tag_t st = sc->sc_st; 1416 bus_space_handle_t sh = sc->sc_sh; 1417 1418 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1419 1420 ifp->if_ipackets += 1421 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1422 1423 ifp->if_ierrors += 1424 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1425 1426 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1427 1428 ifp->if_opackets += 1429 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1430 1431 ifp->if_collisions += 1432 bus_space_read_4(st, sh, STGE_LateCollisions) + 1433 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1434 bus_space_read_4(st, sh, STGE_SingleColFrames); 1435 1436 ifp->if_oerrors += 1437 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1438 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1439 } 1440 1441 /* 1442 * stge_reset: 1443 * 1444 * Perform a soft reset on the TC9021. 1445 */ 1446 static void 1447 stge_reset(struct stge_softc *sc) 1448 { 1449 uint32_t ac; 1450 int i; 1451 1452 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1453 1454 /* 1455 * Only assert RstOut if we're fiber. We need GMII clocks 1456 * to be present in order for the reset to complete on fiber 1457 * cards. 1458 */ 1459 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1460 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1461 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1462 (sc->sc_usefiber ? AC_RstOut : 0)); 1463 1464 delay(50000); 1465 1466 for (i = 0; i < STGE_TIMEOUT; i++) { 1467 delay(5000); 1468 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1469 AC_ResetBusy) == 0) 1470 break; 1471 } 1472 1473 if (i == STGE_TIMEOUT) 1474 printf("%s: reset failed to complete\n", 1475 device_xname(sc->sc_dev)); 1476 1477 delay(1000); 1478 } 1479 1480 /* 1481 * stge_init: [ ifnet interface function ] 1482 * 1483 * Initialize the interface. Must be called at splnet(). 1484 */ 1485 static int 1486 stge_init(struct ifnet *ifp) 1487 { 1488 struct stge_softc *sc = ifp->if_softc; 1489 bus_space_tag_t st = sc->sc_st; 1490 bus_space_handle_t sh = sc->sc_sh; 1491 struct stge_descsoft *ds; 1492 int i, error = 0; 1493 1494 /* 1495 * Cancel any pending I/O. 1496 */ 1497 stge_stop(ifp, 0); 1498 1499 /* 1500 * Reset the chip to a known state. 1501 */ 1502 stge_reset(sc); 1503 1504 /* 1505 * Initialize the transmit descriptor ring. 1506 */ 1507 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1508 for (i = 0; i < STGE_NTXDESC; i++) { 1509 sc->sc_txdescs[i].tfd_next = htole64( 1510 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1511 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1512 } 1513 sc->sc_txpending = 0; 1514 sc->sc_txdirty = 0; 1515 sc->sc_txlast = STGE_NTXDESC - 1; 1516 1517 /* 1518 * Initialize the receive descriptor and receive job 1519 * descriptor rings. 1520 */ 1521 for (i = 0; i < STGE_NRXDESC; i++) { 1522 ds = &sc->sc_rxsoft[i]; 1523 if (ds->ds_mbuf == NULL) { 1524 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1525 printf("%s: unable to allocate or map rx " 1526 "buffer %d, error = %d\n", 1527 device_xname(sc->sc_dev), i, error); 1528 /* 1529 * XXX Should attempt to run with fewer receive 1530 * XXX buffers instead of just failing. 1531 */ 1532 stge_rxdrain(sc); 1533 goto out; 1534 } 1535 } else 1536 STGE_INIT_RXDESC(sc, i); 1537 } 1538 sc->sc_rxptr = 0; 1539 sc->sc_rxdiscard = 0; 1540 STGE_RXCHAIN_RESET(sc); 1541 1542 /* Set the station address. */ 1543 for (i = 0; i < 6; i++) 1544 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1545 CLLADDR(ifp->if_sadl)[i]); 1546 1547 /* 1548 * Set the statistics masks. Disable all the RMON stats, 1549 * and disable selected stats in the non-RMON stats registers. 1550 */ 1551 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1552 bus_space_write_4(st, sh, STGE_StatisticsMask, 1553 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1554 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1555 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1556 (1U << 21)); 1557 1558 /* Set up the receive filter. */ 1559 stge_set_filter(sc); 1560 1561 /* 1562 * Give the transmit and receive ring to the chip. 1563 */ 1564 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1565 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1566 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1567 1568 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1569 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1570 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1571 1572 /* 1573 * Initialize the Tx auto-poll period. It's OK to make this number 1574 * large (255 is the max, but we use 127) -- we explicitly kick the 1575 * transmit engine when there's actually a packet. 1576 */ 1577 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1578 1579 /* ..and the Rx auto-poll period. */ 1580 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1581 1582 /* Initialize the Tx start threshold. */ 1583 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1584 1585 /* RX DMA thresholds, from linux */ 1586 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1587 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1588 1589 /* 1590 * Initialize the Rx DMA interrupt control register. We 1591 * request an interrupt after every incoming packet, but 1592 * defer it for 32us (64 * 512 ns). When the number of 1593 * interrupts pending reaches 8, we stop deferring the 1594 * interrupt, and signal it immediately. 1595 */ 1596 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1597 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1598 1599 /* 1600 * Initialize the interrupt mask. 1601 */ 1602 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1603 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1604 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1605 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1606 1607 /* 1608 * Configure the DMA engine. 1609 * XXX Should auto-tune TxBurstLimit. 1610 */ 1611 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1612 DMAC_TxBurstLimit(3)); 1613 1614 /* 1615 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1616 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1617 * empty again. 1618 */ 1619 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1620 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1621 1622 /* 1623 * Set the maximum frame size. 1624 */ 1625 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1626 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1627 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1628 ETHER_VLAN_ENCAP_LEN : 0)); 1629 1630 /* 1631 * Initialize MacCtrl -- do it before setting the media, 1632 * as setting the media will actually program the register. 1633 * 1634 * Note: We have to poke the IFS value before poking 1635 * anything else. 1636 */ 1637 sc->sc_MACCtrl = MC_IFSSelect(0); 1638 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1639 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1640 #ifdef STGE_VLAN_UNTAG 1641 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1642 #endif 1643 1644 if (sc->sc_rev >= 6) { /* >= B.2 */ 1645 /* Multi-frag frame bug work-around. */ 1646 bus_space_write_2(st, sh, STGE_DebugCtrl, 1647 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1648 1649 /* Tx Poll Now bug work-around. */ 1650 bus_space_write_2(st, sh, STGE_DebugCtrl, 1651 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1652 /* XXX ? from linux */ 1653 bus_space_write_2(st, sh, STGE_DebugCtrl, 1654 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1655 } 1656 1657 /* 1658 * Set the current media. 1659 */ 1660 if ((error = ether_mediachange(ifp)) != 0) 1661 goto out; 1662 1663 /* 1664 * Start the one second MII clock. 1665 */ 1666 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1667 1668 /* 1669 * ...all done! 1670 */ 1671 ifp->if_flags |= IFF_RUNNING; 1672 ifp->if_flags &= ~IFF_OACTIVE; 1673 1674 out: 1675 if (error) 1676 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1677 return (error); 1678 } 1679 1680 /* 1681 * stge_drain: 1682 * 1683 * Drain the receive queue. 1684 */ 1685 static void 1686 stge_rxdrain(struct stge_softc *sc) 1687 { 1688 struct stge_descsoft *ds; 1689 int i; 1690 1691 for (i = 0; i < STGE_NRXDESC; i++) { 1692 ds = &sc->sc_rxsoft[i]; 1693 if (ds->ds_mbuf != NULL) { 1694 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1695 ds->ds_mbuf->m_next = NULL; 1696 m_freem(ds->ds_mbuf); 1697 ds->ds_mbuf = NULL; 1698 } 1699 } 1700 } 1701 1702 /* 1703 * stge_stop: [ ifnet interface function ] 1704 * 1705 * Stop transmission on the interface. 1706 */ 1707 static void 1708 stge_stop(struct ifnet *ifp, int disable) 1709 { 1710 struct stge_softc *sc = ifp->if_softc; 1711 struct stge_descsoft *ds; 1712 int i; 1713 1714 /* 1715 * Stop the one second clock. 1716 */ 1717 callout_stop(&sc->sc_tick_ch); 1718 1719 /* Down the MII. */ 1720 mii_down(&sc->sc_mii); 1721 1722 /* 1723 * Disable interrupts. 1724 */ 1725 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1726 1727 /* 1728 * Stop receiver, transmitter, and stats update. 1729 */ 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1731 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1732 1733 /* 1734 * Stop the transmit and receive DMA. 1735 */ 1736 stge_dma_wait(sc); 1737 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1738 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1739 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1740 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1741 1742 /* 1743 * Release any queued transmit buffers. 1744 */ 1745 for (i = 0; i < STGE_NTXDESC; i++) { 1746 ds = &sc->sc_txsoft[i]; 1747 if (ds->ds_mbuf != NULL) { 1748 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1749 m_freem(ds->ds_mbuf); 1750 ds->ds_mbuf = NULL; 1751 } 1752 } 1753 1754 /* 1755 * Mark the interface down and cancel the watchdog timer. 1756 */ 1757 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1758 ifp->if_timer = 0; 1759 1760 if (disable) 1761 stge_rxdrain(sc); 1762 } 1763 1764 static int 1765 stge_eeprom_wait(struct stge_softc *sc) 1766 { 1767 int i; 1768 1769 for (i = 0; i < STGE_TIMEOUT; i++) { 1770 delay(1000); 1771 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1772 EC_EepromBusy) == 0) 1773 return (0); 1774 } 1775 return (1); 1776 } 1777 1778 /* 1779 * stge_read_eeprom: 1780 * 1781 * Read data from the serial EEPROM. 1782 */ 1783 static void 1784 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1785 { 1786 1787 if (stge_eeprom_wait(sc)) 1788 printf("%s: EEPROM failed to come ready\n", 1789 device_xname(sc->sc_dev)); 1790 1791 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1792 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1793 if (stge_eeprom_wait(sc)) 1794 printf("%s: EEPROM read timed out\n", 1795 device_xname(sc->sc_dev)); 1796 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1797 } 1798 1799 /* 1800 * stge_add_rxbuf: 1801 * 1802 * Add a receive buffer to the indicated descriptor. 1803 */ 1804 static int 1805 stge_add_rxbuf(struct stge_softc *sc, int idx) 1806 { 1807 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1808 struct mbuf *m; 1809 int error; 1810 1811 MGETHDR(m, M_DONTWAIT, MT_DATA); 1812 if (m == NULL) 1813 return (ENOBUFS); 1814 1815 MCLGET(m, M_DONTWAIT); 1816 if ((m->m_flags & M_EXT) == 0) { 1817 m_freem(m); 1818 return (ENOBUFS); 1819 } 1820 1821 m->m_data = m->m_ext.ext_buf + 2; 1822 m->m_len = MCLBYTES - 2; 1823 1824 if (ds->ds_mbuf != NULL) 1825 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1826 1827 ds->ds_mbuf = m; 1828 1829 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1830 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1831 if (error) { 1832 printf("%s: can't load rx DMA map %d, error = %d\n", 1833 device_xname(sc->sc_dev), idx, error); 1834 panic("stge_add_rxbuf"); /* XXX */ 1835 } 1836 1837 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1838 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1839 1840 STGE_INIT_RXDESC(sc, idx); 1841 1842 return (0); 1843 } 1844 1845 /* 1846 * stge_set_filter: 1847 * 1848 * Set up the receive filter. 1849 */ 1850 static void 1851 stge_set_filter(struct stge_softc *sc) 1852 { 1853 struct ethercom *ec = &sc->sc_ethercom; 1854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1855 struct ether_multi *enm; 1856 struct ether_multistep step; 1857 uint32_t crc; 1858 uint32_t mchash[2]; 1859 1860 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1861 if (ifp->if_flags & IFF_BROADCAST) 1862 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1863 1864 /* XXX: ST1023 only works in promiscuous mode */ 1865 if (sc->sc_stge1023) 1866 ifp->if_flags |= IFF_PROMISC; 1867 1868 if (ifp->if_flags & IFF_PROMISC) { 1869 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1870 goto allmulti; 1871 } 1872 1873 /* 1874 * Set up the multicast address filter by passing all multicast 1875 * addresses through a CRC generator, and then using the low-order 1876 * 6 bits as an index into the 64 bit multicast hash table. The 1877 * high order bits select the register, while the rest of the bits 1878 * select the bit within the register. 1879 */ 1880 1881 memset(mchash, 0, sizeof(mchash)); 1882 1883 ETHER_FIRST_MULTI(step, ec, enm); 1884 if (enm == NULL) 1885 goto done; 1886 1887 while (enm != NULL) { 1888 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1889 /* 1890 * We must listen to a range of multicast addresses. 1891 * For now, just accept all multicasts, rather than 1892 * trying to set only those filter bits needed to match 1893 * the range. (At this time, the only use of address 1894 * ranges is for IP multicast routing, for which the 1895 * range is big enough to require all bits set.) 1896 */ 1897 goto allmulti; 1898 } 1899 1900 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1901 1902 /* Just want the 6 least significant bits. */ 1903 crc &= 0x3f; 1904 1905 /* Set the corresponding bit in the hash table. */ 1906 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1907 1908 ETHER_NEXT_MULTI(step, enm); 1909 } 1910 1911 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1912 1913 ifp->if_flags &= ~IFF_ALLMULTI; 1914 goto done; 1915 1916 allmulti: 1917 ifp->if_flags |= IFF_ALLMULTI; 1918 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1919 1920 done: 1921 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1922 /* 1923 * Program the multicast hash table. 1924 */ 1925 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1926 mchash[0]); 1927 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1928 mchash[1]); 1929 } 1930 1931 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1932 sc->sc_ReceiveMode); 1933 } 1934 1935 /* 1936 * stge_mii_readreg: [mii interface function] 1937 * 1938 * Read a PHY register on the MII of the TC9021. 1939 */ 1940 static int 1941 stge_mii_readreg(device_t self, int phy, int reg) 1942 { 1943 1944 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1945 } 1946 1947 /* 1948 * stge_mii_writereg: [mii interface function] 1949 * 1950 * Write a PHY register on the MII of the TC9021. 1951 */ 1952 static void 1953 stge_mii_writereg(device_t self, int phy, int reg, int val) 1954 { 1955 1956 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1957 } 1958 1959 /* 1960 * stge_mii_statchg: [mii interface function] 1961 * 1962 * Callback from MII layer when media changes. 1963 */ 1964 static void 1965 stge_mii_statchg(struct ifnet *ifp) 1966 { 1967 struct stge_softc *sc = ifp->if_softc; 1968 1969 if (sc->sc_mii.mii_media_active & IFM_FDX) 1970 sc->sc_MACCtrl |= MC_DuplexSelect; 1971 else 1972 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1973 1974 /* XXX 802.1x flow-control? */ 1975 1976 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1977 } 1978 1979 /* 1980 * sste_mii_bitbang_read: [mii bit-bang interface function] 1981 * 1982 * Read the MII serial port for the MII bit-bang module. 1983 */ 1984 static uint32_t 1985 stge_mii_bitbang_read(device_t self) 1986 { 1987 struct stge_softc *sc = device_private(self); 1988 1989 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1990 } 1991 1992 /* 1993 * stge_mii_bitbang_write: [mii big-bang interface function] 1994 * 1995 * Write the MII serial port for the MII bit-bang module. 1996 */ 1997 static void 1998 stge_mii_bitbang_write(device_t self, uint32_t val) 1999 { 2000 struct stge_softc *sc = device_private(self); 2001 2002 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2003 val | sc->sc_PhyCtrl); 2004 } 2005