1 /* $NetBSD: if_stge.c,v 1.28 2005/06/25 21:43:38 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.28 2005/06/25 21:43:38 bouyer Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* #define STGE_CU_BUG 1 */ 86 #define STGE_VLAN_UNTAG 1 87 /* #define STGE_VLAN_CFI 1 */ 88 89 /* 90 * Transmit descriptor list size. 91 */ 92 #define STGE_NTXDESC 256 93 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 94 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 95 96 /* 97 * Receive descriptor list size. 98 */ 99 #define STGE_NRXDESC 256 100 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 101 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 102 103 /* 104 * Only interrupt every N frames. Must be a power-of-two. 105 */ 106 #define STGE_TXINTR_SPACING 16 107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 108 109 /* 110 * Control structures are DMA'd to the TC9021 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct stge_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 124 }; 125 126 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit and receive jobs. 132 */ 133 struct stge_descsoft { 134 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t ds_dmamap; /* our DMA map */ 136 }; 137 138 /* 139 * Software state per device. 140 */ 141 struct stge_softc { 142 struct device sc_dev; /* generic device information */ 143 bus_space_tag_t sc_st; /* bus space tag */ 144 bus_space_handle_t sc_sh; /* bus space handle */ 145 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 146 struct ethercom sc_ethercom; /* ethernet common data */ 147 void *sc_sdhook; /* shutdown hook */ 148 int sc_rev; /* silicon revision */ 149 150 void *sc_ih; /* interrupt cookie */ 151 152 struct mii_data sc_mii; /* MII/media information */ 153 154 struct callout sc_tick_ch; /* tick callout */ 155 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 163 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct stge_control_data *sc_control_data; 169 #define sc_txdescs sc_control_data->scd_txdescs 170 #define sc_rxdescs sc_control_data->scd_rxdescs 171 172 #ifdef STGE_EVENT_COUNTERS 173 /* 174 * Event counters. 175 */ 176 struct evcnt sc_ev_txstall; /* Tx stalled */ 177 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 178 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 179 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 180 181 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 182 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 183 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 184 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 185 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 186 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 187 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 188 189 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 190 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 191 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 192 193 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 194 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 195 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 196 #endif /* STGE_EVENT_COUNTERS */ 197 198 int sc_txpending; /* number of Tx requests pending */ 199 int sc_txdirty; /* first dirty Tx descriptor */ 200 int sc_txlast; /* last used Tx descriptor */ 201 202 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 203 int sc_rxdiscard; 204 int sc_rxlen; 205 struct mbuf *sc_rxhead; 206 struct mbuf *sc_rxtail; 207 struct mbuf **sc_rxtailp; 208 209 int sc_txthresh; /* Tx threshold */ 210 int sc_usefiber; /* if we're fiber */ 211 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 212 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 213 uint16_t sc_IntEnable; /* prototype IntEnable register */ 214 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 215 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 216 }; 217 218 #define STGE_RXCHAIN_RESET(sc) \ 219 do { \ 220 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 221 *(sc)->sc_rxtailp = NULL; \ 222 (sc)->sc_rxlen = 0; \ 223 } while (/*CONSTCOND*/0) 224 225 #define STGE_RXCHAIN_LINK(sc, m) \ 226 do { \ 227 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 228 (sc)->sc_rxtailp = &(m)->m_next; \ 229 } while (/*CONSTCOND*/0) 230 231 #ifdef STGE_EVENT_COUNTERS 232 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 233 #else 234 #define STGE_EVCNT_INCR(ev) /* nothing */ 235 #endif 236 237 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 238 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 239 240 #define STGE_CDTXSYNC(sc, x, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 242 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 243 244 #define STGE_CDRXSYNC(sc, x, ops) \ 245 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 247 248 #define STGE_INIT_RXDESC(sc, x) \ 249 do { \ 250 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 251 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 252 \ 253 /* \ 254 * Note: We scoot the packet forward 2 bytes in the buffer \ 255 * so that the payload after the Ethernet header is aligned \ 256 * to a 4-byte boundary. \ 257 */ \ 258 __rfd->rfd_frag.frag_word0 = \ 259 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 260 FRAG_LEN(MCLBYTES - 2)); \ 261 __rfd->rfd_next = \ 262 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 263 __rfd->rfd_status = 0; \ 264 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 265 } while (/*CONSTCOND*/0) 266 267 #define STGE_TIMEOUT 1000 268 269 static void stge_start(struct ifnet *); 270 static void stge_watchdog(struct ifnet *); 271 static int stge_ioctl(struct ifnet *, u_long, caddr_t); 272 static int stge_init(struct ifnet *); 273 static void stge_stop(struct ifnet *, int); 274 275 static void stge_shutdown(void *); 276 277 static void stge_reset(struct stge_softc *); 278 static void stge_rxdrain(struct stge_softc *); 279 static int stge_add_rxbuf(struct stge_softc *, int); 280 #if 0 281 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 282 #endif 283 static void stge_tick(void *); 284 285 static void stge_stats_update(struct stge_softc *); 286 287 static void stge_set_filter(struct stge_softc *); 288 289 static int stge_intr(void *); 290 static void stge_txintr(struct stge_softc *); 291 static void stge_rxintr(struct stge_softc *); 292 293 static int stge_mii_readreg(struct device *, int, int); 294 static void stge_mii_writereg(struct device *, int, int, int); 295 static void stge_mii_statchg(struct device *); 296 297 static int stge_mediachange(struct ifnet *); 298 static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 299 300 static int stge_match(struct device *, struct cfdata *, void *); 301 static void stge_attach(struct device *, struct device *, void *); 302 303 int stge_copy_small = 0; 304 305 CFATTACH_DECL(stge, sizeof(struct stge_softc), 306 stge_match, stge_attach, NULL, NULL); 307 308 static uint32_t stge_mii_bitbang_read(struct device *); 309 static void stge_mii_bitbang_write(struct device *, uint32_t); 310 311 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 312 stge_mii_bitbang_read, 313 stge_mii_bitbang_write, 314 { 315 PC_MgmtData, /* MII_BIT_MDO */ 316 PC_MgmtData, /* MII_BIT_MDI */ 317 PC_MgmtClk, /* MII_BIT_MDC */ 318 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 319 0, /* MII_BIT_DIR_PHY_HOST */ 320 } 321 }; 322 323 /* 324 * Devices supported by this driver. 325 */ 326 static const struct stge_product { 327 pci_vendor_id_t stge_vendor; 328 pci_product_id_t stge_product; 329 const char *stge_name; 330 } stge_products[] = { 331 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 332 "Sundance ST-2021 Gigabit Ethernet" }, 333 334 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 335 "Tamarack TC9021 Gigabit Ethernet" }, 336 337 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 338 "Tamarack TC9021 Gigabit Ethernet" }, 339 340 /* 341 * The Sundance sample boards use the Sundance vendor ID, 342 * but the Tamarack product ID. 343 */ 344 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 345 "Sundance TC9021 Gigabit Ethernet" }, 346 347 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 348 "Sundance TC9021 Gigabit Ethernet" }, 349 350 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 351 "D-Link DL-4000 Gigabit Ethernet" }, 352 353 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 354 "Antares Gigabit Ethernet" }, 355 356 { 0, 0, 357 NULL }, 358 }; 359 360 static const struct stge_product * 361 stge_lookup(const struct pci_attach_args *pa) 362 { 363 const struct stge_product *sp; 364 365 for (sp = stge_products; sp->stge_name != NULL; sp++) { 366 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 367 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 368 return (sp); 369 } 370 return (NULL); 371 } 372 373 static int 374 stge_match(struct device *parent, struct cfdata *cf, void *aux) 375 { 376 struct pci_attach_args *pa = aux; 377 378 if (stge_lookup(pa) != NULL) 379 return (1); 380 381 return (0); 382 } 383 384 static void 385 stge_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct stge_softc *sc = (struct stge_softc *) self; 388 struct pci_attach_args *pa = aux; 389 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pci_intr_handle_t ih; 392 const char *intrstr = NULL; 393 bus_space_tag_t iot, memt; 394 bus_space_handle_t ioh, memh; 395 bus_dma_segment_t seg; 396 int ioh_valid, memh_valid; 397 int i, rseg, error; 398 const struct stge_product *sp; 399 pcireg_t pmode; 400 uint8_t enaddr[ETHER_ADDR_LEN]; 401 int pmreg; 402 403 callout_init(&sc->sc_tick_ch); 404 405 sp = stge_lookup(pa); 406 if (sp == NULL) { 407 printf("\n"); 408 panic("ste_attach: impossible"); 409 } 410 411 sc->sc_rev = PCI_REVISION(pa->pa_class); 412 413 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 414 415 /* 416 * Map the device. 417 */ 418 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 419 PCI_MAPREG_TYPE_IO, 0, 420 &iot, &ioh, NULL, NULL) == 0); 421 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 422 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 423 &memt, &memh, NULL, NULL) == 0); 424 425 if (memh_valid) { 426 sc->sc_st = memt; 427 sc->sc_sh = memh; 428 } else if (ioh_valid) { 429 sc->sc_st = iot; 430 sc->sc_sh = ioh; 431 } else { 432 printf("%s: unable to map device registers\n", 433 sc->sc_dev.dv_xname); 434 return; 435 } 436 437 sc->sc_dmat = pa->pa_dmat; 438 439 /* Enable bus mastering. */ 440 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 441 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 442 PCI_COMMAND_MASTER_ENABLE); 443 444 /* Get it out of power save mode if needed. */ 445 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 446 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 447 PCI_PMCSR_STATE_MASK; 448 if (pmode == PCI_PMCSR_STATE_D3) { 449 /* 450 * The card has lost all configuration data in 451 * this state, so punt. 452 */ 453 printf("%s: unable to wake up from power state D3\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 if (pmode != 0) { 458 printf("%s: waking up from power state D%d\n", 459 sc->sc_dev.dv_xname, pmode); 460 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 461 PCI_PMCSR_STATE_D0); 462 } 463 } 464 465 /* 466 * Map and establish our interrupt. 467 */ 468 if (pci_intr_map(pa, &ih)) { 469 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 470 return; 471 } 472 intrstr = pci_intr_string(pc, ih); 473 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 474 if (sc->sc_ih == NULL) { 475 printf("%s: unable to establish interrupt", 476 sc->sc_dev.dv_xname); 477 if (intrstr != NULL) 478 printf(" at %s", intrstr); 479 printf("\n"); 480 return; 481 } 482 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 483 484 /* 485 * Allocate the control data structures, and create and load the 486 * DMA map for it. 487 */ 488 if ((error = bus_dmamem_alloc(sc->sc_dmat, 489 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 490 0)) != 0) { 491 printf("%s: unable to allocate control data, error = %d\n", 492 sc->sc_dev.dv_xname, error); 493 goto fail_0; 494 } 495 496 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 497 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 498 BUS_DMA_COHERENT)) != 0) { 499 printf("%s: unable to map control data, error = %d\n", 500 sc->sc_dev.dv_xname, error); 501 goto fail_1; 502 } 503 504 if ((error = bus_dmamap_create(sc->sc_dmat, 505 sizeof(struct stge_control_data), 1, 506 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 507 printf("%s: unable to create control data DMA map, " 508 "error = %d\n", sc->sc_dev.dv_xname, error); 509 goto fail_2; 510 } 511 512 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 513 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 514 0)) != 0) { 515 printf("%s: unable to load control data DMA map, error = %d\n", 516 sc->sc_dev.dv_xname, error); 517 goto fail_3; 518 } 519 520 /* 521 * Create the transmit buffer DMA maps. Note that rev B.3 522 * and earlier seem to have a bug regarding multi-fragment 523 * packets. We need to limit the number of Tx segments on 524 * such chips to 1. 525 */ 526 for (i = 0; i < STGE_NTXDESC; i++) { 527 if ((error = bus_dmamap_create(sc->sc_dmat, 528 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 529 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 530 printf("%s: unable to create tx DMA map %d, " 531 "error = %d\n", sc->sc_dev.dv_xname, i, error); 532 goto fail_4; 533 } 534 } 535 536 /* 537 * Create the receive buffer DMA maps. 538 */ 539 for (i = 0; i < STGE_NRXDESC; i++) { 540 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 541 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 542 printf("%s: unable to create rx DMA map %d, " 543 "error = %d\n", sc->sc_dev.dv_xname, i, error); 544 goto fail_5; 545 } 546 sc->sc_rxsoft[i].ds_mbuf = NULL; 547 } 548 549 /* 550 * Determine if we're copper or fiber. It affects how we 551 * reset the card. 552 */ 553 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 554 AC_PhyMedia) 555 sc->sc_usefiber = 1; 556 else 557 sc->sc_usefiber = 0; 558 559 /* 560 * Reset the chip to a known state. 561 */ 562 stge_reset(sc); 563 564 /* 565 * Reading the station address from the EEPROM doesn't seem 566 * to work, at least on my sample boards. Instead, since 567 * the reset sequence does AutoInit, read it from the station 568 * address registers. 569 */ 570 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 571 STGE_StationAddress0) & 0xff; 572 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 573 STGE_StationAddress0) >> 8; 574 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 575 STGE_StationAddress1) & 0xff; 576 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 577 STGE_StationAddress1) >> 8; 578 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 579 STGE_StationAddress2) & 0xff; 580 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 581 STGE_StationAddress2) >> 8; 582 583 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 584 ether_sprintf(enaddr)); 585 586 /* 587 * Read some important bits from the PhyCtrl register. 588 */ 589 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 590 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 591 592 /* 593 * Initialize our media structures and probe the MII. 594 */ 595 sc->sc_mii.mii_ifp = ifp; 596 sc->sc_mii.mii_readreg = stge_mii_readreg; 597 sc->sc_mii.mii_writereg = stge_mii_writereg; 598 sc->sc_mii.mii_statchg = stge_mii_statchg; 599 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, stge_mediachange, 600 stge_mediastatus); 601 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 602 MII_OFFSET_ANY, MIIF_DOPAUSE); 603 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 604 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 605 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 606 } else 607 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 608 609 ifp = &sc->sc_ethercom.ec_if; 610 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 611 ifp->if_softc = sc; 612 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 613 ifp->if_ioctl = stge_ioctl; 614 ifp->if_start = stge_start; 615 ifp->if_watchdog = stge_watchdog; 616 ifp->if_init = stge_init; 617 ifp->if_stop = stge_stop; 618 IFQ_SET_READY(&ifp->if_snd); 619 620 /* 621 * The manual recommends disabling early transmit, so we 622 * do. It's disabled anyway, if using IP checksumming, 623 * since the entire packet must be in the FIFO in order 624 * for the chip to perform the checksum. 625 */ 626 sc->sc_txthresh = 0x0fff; 627 628 /* 629 * Disable MWI if the PCI layer tells us to. 630 */ 631 sc->sc_DMACtrl = 0; 632 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 633 sc->sc_DMACtrl |= DMAC_MWIDisable; 634 635 /* 636 * We can support 802.1Q VLAN-sized frames and jumbo 637 * Ethernet frames. 638 * 639 * XXX Figure out how to do hw-assisted VLAN tagging in 640 * XXX a reasonable way on this chip. 641 */ 642 sc->sc_ethercom.ec_capabilities |= 643 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 644 ETHERCAP_VLAN_HWTAGGING; 645 646 /* 647 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 648 */ 649 sc->sc_ethercom.ec_if.if_capabilities |= 650 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 651 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 652 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 653 654 /* 655 * Attach the interface. 656 */ 657 if_attach(ifp); 658 ether_ifattach(ifp, enaddr); 659 660 #ifdef STGE_EVENT_COUNTERS 661 /* 662 * Attach event counters. 663 */ 664 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 665 NULL, sc->sc_dev.dv_xname, "txstall"); 666 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 667 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 668 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 669 NULL, sc->sc_dev.dv_xname, "txindintr"); 670 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 671 NULL, sc->sc_dev.dv_xname, "rxintr"); 672 673 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 674 NULL, sc->sc_dev.dv_xname, "txseg1"); 675 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 676 NULL, sc->sc_dev.dv_xname, "txseg2"); 677 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 678 NULL, sc->sc_dev.dv_xname, "txseg3"); 679 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 680 NULL, sc->sc_dev.dv_xname, "txseg4"); 681 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 682 NULL, sc->sc_dev.dv_xname, "txseg5"); 683 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 684 NULL, sc->sc_dev.dv_xname, "txsegmore"); 685 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 686 NULL, sc->sc_dev.dv_xname, "txcopy"); 687 688 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 689 NULL, sc->sc_dev.dv_xname, "rxipsum"); 690 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 691 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 692 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 693 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 694 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 695 NULL, sc->sc_dev.dv_xname, "txipsum"); 696 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 697 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 698 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 699 NULL, sc->sc_dev.dv_xname, "txudpsum"); 700 #endif /* STGE_EVENT_COUNTERS */ 701 702 /* 703 * Make sure the interface is shutdown during reboot. 704 */ 705 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 706 if (sc->sc_sdhook == NULL) 707 printf("%s: WARNING: unable to establish shutdown hook\n", 708 sc->sc_dev.dv_xname); 709 return; 710 711 /* 712 * Free any resources we've allocated during the failed attach 713 * attempt. Do this in reverse order and fall through. 714 */ 715 fail_5: 716 for (i = 0; i < STGE_NRXDESC; i++) { 717 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 718 bus_dmamap_destroy(sc->sc_dmat, 719 sc->sc_rxsoft[i].ds_dmamap); 720 } 721 fail_4: 722 for (i = 0; i < STGE_NTXDESC; i++) { 723 if (sc->sc_txsoft[i].ds_dmamap != NULL) 724 bus_dmamap_destroy(sc->sc_dmat, 725 sc->sc_txsoft[i].ds_dmamap); 726 } 727 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 728 fail_3: 729 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 730 fail_2: 731 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 732 sizeof(struct stge_control_data)); 733 fail_1: 734 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 735 fail_0: 736 return; 737 } 738 739 /* 740 * stge_shutdown: 741 * 742 * Make sure the interface is stopped at reboot time. 743 */ 744 static void 745 stge_shutdown(void *arg) 746 { 747 struct stge_softc *sc = arg; 748 749 stge_stop(&sc->sc_ethercom.ec_if, 1); 750 } 751 752 static void 753 stge_dma_wait(struct stge_softc *sc) 754 { 755 int i; 756 757 for (i = 0; i < STGE_TIMEOUT; i++) { 758 delay(2); 759 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 760 DMAC_TxDMAInProg) == 0) 761 break; 762 } 763 764 if (i == STGE_TIMEOUT) 765 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 766 } 767 768 /* 769 * stge_start: [ifnet interface function] 770 * 771 * Start packet transmission on the interface. 772 */ 773 static void 774 stge_start(struct ifnet *ifp) 775 { 776 struct stge_softc *sc = ifp->if_softc; 777 struct mbuf *m0; 778 struct stge_descsoft *ds; 779 struct stge_tfd *tfd; 780 bus_dmamap_t dmamap; 781 int error, firsttx, nexttx, opending, seg, totlen; 782 uint64_t csum_flags; 783 784 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 785 return; 786 787 /* 788 * Remember the previous number of pending transmissions 789 * and the first descriptor we will use. 790 */ 791 opending = sc->sc_txpending; 792 firsttx = STGE_NEXTTX(sc->sc_txlast); 793 794 /* 795 * Loop through the send queue, setting up transmit descriptors 796 * until we drain the queue, or use up all available transmit 797 * descriptors. 798 */ 799 for (;;) { 800 struct m_tag *mtag; 801 uint64_t tfc; 802 803 /* 804 * Grab a packet off the queue. 805 */ 806 IFQ_POLL(&ifp->if_snd, m0); 807 if (m0 == NULL) 808 break; 809 810 /* 811 * Leave one unused descriptor at the end of the 812 * list to prevent wrapping completely around. 813 */ 814 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 815 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 816 break; 817 } 818 819 /* 820 * See if we have any VLAN stuff. 821 */ 822 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 823 824 /* 825 * Get the last and next available transmit descriptor. 826 */ 827 nexttx = STGE_NEXTTX(sc->sc_txlast); 828 tfd = &sc->sc_txdescs[nexttx]; 829 ds = &sc->sc_txsoft[nexttx]; 830 831 dmamap = ds->ds_dmamap; 832 833 /* 834 * Load the DMA map. If this fails, the packet either 835 * didn't fit in the alloted number of segments, or we 836 * were short on resources. For the too-many-segments 837 * case, we simply report an error and drop the packet, 838 * since we can't sanely copy a jumbo packet to a single 839 * buffer. 840 */ 841 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 842 BUS_DMA_NOWAIT); 843 if (error) { 844 if (error == EFBIG) { 845 printf("%s: Tx packet consumes too many " 846 "DMA segments, dropping...\n", 847 sc->sc_dev.dv_xname); 848 IFQ_DEQUEUE(&ifp->if_snd, m0); 849 m_freem(m0); 850 continue; 851 } 852 /* 853 * Short on resources, just stop for now. 854 */ 855 break; 856 } 857 858 IFQ_DEQUEUE(&ifp->if_snd, m0); 859 860 /* 861 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 862 */ 863 864 /* Sync the DMA map. */ 865 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 866 BUS_DMASYNC_PREWRITE); 867 868 /* Initialize the fragment list. */ 869 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 870 tfd->tfd_frags[seg].frag_word0 = 871 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 872 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 873 totlen += dmamap->dm_segs[seg].ds_len; 874 } 875 876 #ifdef STGE_EVENT_COUNTERS 877 switch (dmamap->dm_nsegs) { 878 case 1: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 880 break; 881 case 2: 882 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 883 break; 884 case 3: 885 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 886 break; 887 case 4: 888 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 889 break; 890 case 5: 891 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 892 break; 893 default: 894 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 895 break; 896 } 897 #endif /* STGE_EVENT_COUNTERS */ 898 899 /* 900 * Initialize checksumming flags in the descriptor. 901 * Byte-swap constants so the compiler can optimize. 902 */ 903 csum_flags = 0; 904 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 905 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 906 csum_flags |= TFD_IPChecksumEnable; 907 } 908 909 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 910 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 911 csum_flags |= TFD_TCPChecksumEnable; 912 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 913 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 914 csum_flags |= TFD_UDPChecksumEnable; 915 } 916 917 /* 918 * Initialize the descriptor and give it to the chip. 919 * Check to see if we have a VLAN tag to insert. 920 */ 921 922 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 923 TFD_FragCount(seg) | csum_flags | 924 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 925 TFD_TxDMAIndicate : 0); 926 if (mtag) { 927 #if 0 928 struct ether_header *eh = 929 mtod(m0, struct ether_header *); 930 u_int16_t etype = ntohs(eh->ether_type); 931 printf("%s: xmit (tag %d) etype %x\n", 932 ifp->if_xname, *mtod(n, int *), etype); 933 #endif 934 tfc |= TFD_VLANTagInsert | 935 #ifdef STGE_VLAN_CFI 936 TFD_CFI | 937 #endif 938 TFD_VID(VLAN_TAG_VALUE(mtag)); 939 } 940 tfd->tfd_control = htole64(tfc); 941 942 /* Sync the descriptor. */ 943 STGE_CDTXSYNC(sc, nexttx, 944 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 945 946 /* 947 * Kick the transmit DMA logic. 948 */ 949 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 950 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 951 952 /* 953 * Store a pointer to the packet so we can free it later. 954 */ 955 ds->ds_mbuf = m0; 956 957 /* Advance the tx pointer. */ 958 sc->sc_txpending++; 959 sc->sc_txlast = nexttx; 960 961 #if NBPFILTER > 0 962 /* 963 * Pass the packet to any BPF listeners. 964 */ 965 if (ifp->if_bpf) 966 bpf_mtap(ifp->if_bpf, m0); 967 #endif /* NBPFILTER > 0 */ 968 } 969 970 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 971 /* No more slots left; notify upper layer. */ 972 ifp->if_flags |= IFF_OACTIVE; 973 } 974 975 if (sc->sc_txpending != opending) { 976 /* 977 * We enqueued packets. If the transmitter was idle, 978 * reset the txdirty pointer. 979 */ 980 if (opending == 0) 981 sc->sc_txdirty = firsttx; 982 983 /* Set a watchdog timer in case the chip flakes out. */ 984 ifp->if_timer = 5; 985 } 986 } 987 988 /* 989 * stge_watchdog: [ifnet interface function] 990 * 991 * Watchdog timer handler. 992 */ 993 static void 994 stge_watchdog(struct ifnet *ifp) 995 { 996 struct stge_softc *sc = ifp->if_softc; 997 998 /* 999 * Sweep up first, since we don't interrupt every frame. 1000 */ 1001 stge_txintr(sc); 1002 if (sc->sc_txpending != 0) { 1003 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1004 ifp->if_oerrors++; 1005 1006 (void) stge_init(ifp); 1007 1008 /* Try to get more packets going. */ 1009 stge_start(ifp); 1010 } 1011 } 1012 1013 /* 1014 * stge_ioctl: [ifnet interface function] 1015 * 1016 * Handle control requests from the operator. 1017 */ 1018 static int 1019 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1020 { 1021 struct stge_softc *sc = ifp->if_softc; 1022 struct ifreq *ifr = (struct ifreq *)data; 1023 int s, error; 1024 1025 s = splnet(); 1026 1027 switch (cmd) { 1028 case SIOCSIFMEDIA: 1029 case SIOCGIFMEDIA: 1030 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1031 break; 1032 1033 default: 1034 error = ether_ioctl(ifp, cmd, data); 1035 if (error == ENETRESET) { 1036 /* 1037 * Multicast list has changed; set the hardware filter 1038 * accordingly. 1039 */ 1040 if (ifp->if_flags & IFF_RUNNING) 1041 stge_set_filter(sc); 1042 error = 0; 1043 } 1044 break; 1045 } 1046 1047 /* Try to get more packets going. */ 1048 stge_start(ifp); 1049 1050 splx(s); 1051 return (error); 1052 } 1053 1054 /* 1055 * stge_intr: 1056 * 1057 * Interrupt service routine. 1058 */ 1059 static int 1060 stge_intr(void *arg) 1061 { 1062 struct stge_softc *sc = arg; 1063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1064 uint32_t txstat; 1065 int wantinit; 1066 uint16_t isr; 1067 1068 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1069 IS_InterruptStatus) == 0) 1070 return (0); 1071 1072 for (wantinit = 0; wantinit == 0;) { 1073 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1074 if ((isr & sc->sc_IntEnable) == 0) 1075 break; 1076 1077 /* Host interface errors. */ 1078 if (isr & IS_HostError) { 1079 printf("%s: Host interface error\n", 1080 sc->sc_dev.dv_xname); 1081 wantinit = 1; 1082 continue; 1083 } 1084 1085 /* Receive interrupts. */ 1086 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1087 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1088 stge_rxintr(sc); 1089 if (isr & IS_RFDListEnd) { 1090 printf("%s: receive ring overflow\n", 1091 sc->sc_dev.dv_xname); 1092 /* 1093 * XXX Should try to recover from this 1094 * XXX more gracefully. 1095 */ 1096 wantinit = 1; 1097 } 1098 } 1099 1100 /* Transmit interrupts. */ 1101 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1102 #ifdef STGE_EVENT_COUNTERS 1103 if (isr & IS_TxDMAComplete) 1104 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1105 #endif 1106 stge_txintr(sc); 1107 } 1108 1109 /* Statistics overflow. */ 1110 if (isr & IS_UpdateStats) 1111 stge_stats_update(sc); 1112 1113 /* Transmission errors. */ 1114 if (isr & IS_TxComplete) { 1115 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1116 for (;;) { 1117 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1118 STGE_TxStatus); 1119 if ((txstat & TS_TxComplete) == 0) 1120 break; 1121 if (txstat & TS_TxUnderrun) { 1122 sc->sc_txthresh++; 1123 if (sc->sc_txthresh > 0x0fff) 1124 sc->sc_txthresh = 0x0fff; 1125 printf("%s: transmit underrun, new " 1126 "threshold: %d bytes\n", 1127 sc->sc_dev.dv_xname, 1128 sc->sc_txthresh << 5); 1129 } 1130 if (txstat & TS_MaxCollisions) 1131 printf("%s: excessive collisions\n", 1132 sc->sc_dev.dv_xname); 1133 } 1134 wantinit = 1; 1135 } 1136 1137 } 1138 1139 if (wantinit) 1140 stge_init(ifp); 1141 1142 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1143 sc->sc_IntEnable); 1144 1145 /* Try to get more packets going. */ 1146 stge_start(ifp); 1147 1148 return (1); 1149 } 1150 1151 /* 1152 * stge_txintr: 1153 * 1154 * Helper; handle transmit interrupts. 1155 */ 1156 static void 1157 stge_txintr(struct stge_softc *sc) 1158 { 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 struct stge_descsoft *ds; 1161 uint64_t control; 1162 int i; 1163 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 1166 /* 1167 * Go through our Tx list and free mbufs for those 1168 * frames which have been transmitted. 1169 */ 1170 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1171 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1172 ds = &sc->sc_txsoft[i]; 1173 1174 STGE_CDTXSYNC(sc, i, 1175 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1176 1177 control = le64toh(sc->sc_txdescs[i].tfd_control); 1178 if ((control & TFD_TFDDone) == 0) 1179 break; 1180 1181 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1182 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1184 m_freem(ds->ds_mbuf); 1185 ds->ds_mbuf = NULL; 1186 } 1187 1188 /* Update the dirty transmit buffer pointer. */ 1189 sc->sc_txdirty = i; 1190 1191 /* 1192 * If there are no more pending transmissions, cancel the watchdog 1193 * timer. 1194 */ 1195 if (sc->sc_txpending == 0) 1196 ifp->if_timer = 0; 1197 } 1198 1199 /* 1200 * stge_rxintr: 1201 * 1202 * Helper; handle receive interrupts. 1203 */ 1204 static void 1205 stge_rxintr(struct stge_softc *sc) 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 struct stge_descsoft *ds; 1209 struct mbuf *m, *tailm; 1210 uint64_t status; 1211 int i, len; 1212 1213 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1214 ds = &sc->sc_rxsoft[i]; 1215 1216 STGE_CDRXSYNC(sc, i, 1217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1218 1219 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1220 1221 if ((status & RFD_RFDDone) == 0) 1222 break; 1223 1224 if (__predict_false(sc->sc_rxdiscard)) { 1225 STGE_INIT_RXDESC(sc, i); 1226 if (status & RFD_FrameEnd) { 1227 /* Reset our state. */ 1228 sc->sc_rxdiscard = 0; 1229 } 1230 continue; 1231 } 1232 1233 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1234 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1235 1236 m = ds->ds_mbuf; 1237 1238 /* 1239 * Add a new receive buffer to the ring. 1240 */ 1241 if (stge_add_rxbuf(sc, i) != 0) { 1242 /* 1243 * Failed, throw away what we've done so 1244 * far, and discard the rest of the packet. 1245 */ 1246 ifp->if_ierrors++; 1247 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1248 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1249 STGE_INIT_RXDESC(sc, i); 1250 if ((status & RFD_FrameEnd) == 0) 1251 sc->sc_rxdiscard = 1; 1252 if (sc->sc_rxhead != NULL) 1253 m_freem(sc->sc_rxhead); 1254 STGE_RXCHAIN_RESET(sc); 1255 continue; 1256 } 1257 1258 #ifdef DIAGNOSTIC 1259 if (status & RFD_FrameStart) { 1260 KASSERT(sc->sc_rxhead == NULL); 1261 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1262 } 1263 #endif 1264 1265 STGE_RXCHAIN_LINK(sc, m); 1266 1267 /* 1268 * If this is not the end of the packet, keep 1269 * looking. 1270 */ 1271 if ((status & RFD_FrameEnd) == 0) { 1272 sc->sc_rxlen += m->m_len; 1273 continue; 1274 } 1275 1276 /* 1277 * Okay, we have the entire packet now... 1278 */ 1279 *sc->sc_rxtailp = NULL; 1280 m = sc->sc_rxhead; 1281 tailm = sc->sc_rxtail; 1282 1283 STGE_RXCHAIN_RESET(sc); 1284 1285 /* 1286 * If the packet had an error, drop it. Note we 1287 * count the error later in the periodic stats update. 1288 */ 1289 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1290 RFD_RxAlignmentError | RFD_RxFCSError | 1291 RFD_RxLengthError)) { 1292 m_freem(m); 1293 continue; 1294 } 1295 1296 /* 1297 * No errors. 1298 * 1299 * Note we have configured the chip to not include 1300 * the CRC at the end of the packet. 1301 */ 1302 len = RFD_RxDMAFrameLen(status); 1303 tailm->m_len = len - sc->sc_rxlen; 1304 1305 /* 1306 * If the packet is small enough to fit in a 1307 * single header mbuf, allocate one and copy 1308 * the data into it. This greatly reduces 1309 * memory consumption when we receive lots 1310 * of small packets. 1311 */ 1312 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1313 struct mbuf *nm; 1314 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1315 if (nm == NULL) { 1316 ifp->if_ierrors++; 1317 m_freem(m); 1318 continue; 1319 } 1320 nm->m_data += 2; 1321 nm->m_pkthdr.len = nm->m_len = len; 1322 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1323 m_freem(m); 1324 m = nm; 1325 } 1326 1327 /* 1328 * Set the incoming checksum information for the packet. 1329 */ 1330 if (status & RFD_IPDetected) { 1331 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1332 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1333 if (status & RFD_IPError) 1334 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1335 if (status & RFD_TCPDetected) { 1336 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1337 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1338 if (status & RFD_TCPError) 1339 m->m_pkthdr.csum_flags |= 1340 M_CSUM_TCP_UDP_BAD; 1341 } else if (status & RFD_UDPDetected) { 1342 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1343 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1344 if (status & RFD_UDPError) 1345 m->m_pkthdr.csum_flags |= 1346 M_CSUM_TCP_UDP_BAD; 1347 } 1348 } 1349 1350 m->m_pkthdr.rcvif = ifp; 1351 m->m_pkthdr.len = len; 1352 1353 #if NBPFILTER > 0 1354 /* 1355 * Pass this up to any BPF listeners, but only 1356 * pass if up the stack if it's for us. 1357 */ 1358 if (ifp->if_bpf) 1359 bpf_mtap(ifp->if_bpf, m); 1360 #endif /* NBPFILTER > 0 */ 1361 #ifdef STGE_VLAN_UNTAG 1362 /* 1363 * Check for VLAN tagged packets 1364 */ 1365 if (status & RFD_VLANDetected) 1366 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1367 1368 #endif 1369 #if 0 1370 if (status & RFD_VLANDetected) { 1371 struct ether_header *eh; 1372 u_int16_t etype; 1373 1374 eh = mtod(m, struct ether_header *); 1375 etype = ntohs(eh->ether_type); 1376 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1377 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1378 etype); 1379 } 1380 #endif 1381 /* Pass it on. */ 1382 (*ifp->if_input)(ifp, m); 1383 } 1384 1385 /* Update the receive pointer. */ 1386 sc->sc_rxptr = i; 1387 } 1388 1389 /* 1390 * stge_tick: 1391 * 1392 * One second timer, used to tick the MII. 1393 */ 1394 static void 1395 stge_tick(void *arg) 1396 { 1397 struct stge_softc *sc = arg; 1398 int s; 1399 1400 s = splnet(); 1401 mii_tick(&sc->sc_mii); 1402 stge_stats_update(sc); 1403 splx(s); 1404 1405 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1406 } 1407 1408 /* 1409 * stge_stats_update: 1410 * 1411 * Read the TC9021 statistics counters. 1412 */ 1413 static void 1414 stge_stats_update(struct stge_softc *sc) 1415 { 1416 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1417 bus_space_tag_t st = sc->sc_st; 1418 bus_space_handle_t sh = sc->sc_sh; 1419 1420 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1421 1422 ifp->if_ipackets += 1423 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1424 1425 ifp->if_ierrors += 1426 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1427 1428 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1429 1430 ifp->if_opackets += 1431 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1432 1433 ifp->if_collisions += 1434 bus_space_read_4(st, sh, STGE_LateCollisions) + 1435 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1436 bus_space_read_4(st, sh, STGE_SingleColFrames); 1437 1438 ifp->if_oerrors += 1439 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1440 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1441 } 1442 1443 /* 1444 * stge_reset: 1445 * 1446 * Perform a soft reset on the TC9021. 1447 */ 1448 static void 1449 stge_reset(struct stge_softc *sc) 1450 { 1451 uint32_t ac; 1452 int i; 1453 1454 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1455 1456 /* 1457 * Only assert RstOut if we're fiber. We need GMII clocks 1458 * to be present in order for the reset to complete on fiber 1459 * cards. 1460 */ 1461 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1462 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1463 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1464 (sc->sc_usefiber ? AC_RstOut : 0)); 1465 1466 delay(50000); 1467 1468 for (i = 0; i < STGE_TIMEOUT; i++) { 1469 delay(5000); 1470 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1471 AC_ResetBusy) == 0) 1472 break; 1473 } 1474 1475 if (i == STGE_TIMEOUT) 1476 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1477 1478 delay(1000); 1479 } 1480 1481 /* 1482 * stge_init: [ ifnet interface function ] 1483 * 1484 * Initialize the interface. Must be called at splnet(). 1485 */ 1486 static int 1487 stge_init(struct ifnet *ifp) 1488 { 1489 struct stge_softc *sc = ifp->if_softc; 1490 bus_space_tag_t st = sc->sc_st; 1491 bus_space_handle_t sh = sc->sc_sh; 1492 struct stge_descsoft *ds; 1493 int i, error = 0; 1494 1495 /* 1496 * Cancel any pending I/O. 1497 */ 1498 stge_stop(ifp, 0); 1499 1500 /* 1501 * Reset the chip to a known state. 1502 */ 1503 stge_reset(sc); 1504 1505 /* 1506 * Initialize the transmit descriptor ring. 1507 */ 1508 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1509 for (i = 0; i < STGE_NTXDESC; i++) { 1510 sc->sc_txdescs[i].tfd_next = htole64( 1511 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1512 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1513 } 1514 sc->sc_txpending = 0; 1515 sc->sc_txdirty = 0; 1516 sc->sc_txlast = STGE_NTXDESC - 1; 1517 1518 /* 1519 * Initialize the receive descriptor and receive job 1520 * descriptor rings. 1521 */ 1522 for (i = 0; i < STGE_NRXDESC; i++) { 1523 ds = &sc->sc_rxsoft[i]; 1524 if (ds->ds_mbuf == NULL) { 1525 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1526 printf("%s: unable to allocate or map rx " 1527 "buffer %d, error = %d\n", 1528 sc->sc_dev.dv_xname, i, error); 1529 /* 1530 * XXX Should attempt to run with fewer receive 1531 * XXX buffers instead of just failing. 1532 */ 1533 stge_rxdrain(sc); 1534 goto out; 1535 } 1536 } else 1537 STGE_INIT_RXDESC(sc, i); 1538 } 1539 sc->sc_rxptr = 0; 1540 sc->sc_rxdiscard = 0; 1541 STGE_RXCHAIN_RESET(sc); 1542 1543 /* Set the station address. */ 1544 for (i = 0; i < 6; i++) 1545 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1546 LLADDR(ifp->if_sadl)[i]); 1547 1548 /* 1549 * Set the statistics masks. Disable all the RMON stats, 1550 * and disable selected stats in the non-RMON stats registers. 1551 */ 1552 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1553 bus_space_write_4(st, sh, STGE_StatisticsMask, 1554 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1555 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1556 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1557 (1U << 21)); 1558 1559 /* Set up the receive filter. */ 1560 stge_set_filter(sc); 1561 1562 /* 1563 * Give the transmit and receive ring to the chip. 1564 */ 1565 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1566 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1567 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1568 1569 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1570 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1571 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1572 1573 /* 1574 * Initialize the Tx auto-poll period. It's OK to make this number 1575 * large (255 is the max, but we use 127) -- we explicitly kick the 1576 * transmit engine when there's actually a packet. 1577 */ 1578 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1579 1580 /* ..and the Rx auto-poll period. */ 1581 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1582 1583 /* Initialize the Tx start threshold. */ 1584 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1585 1586 /* RX DMA thresholds, from linux */ 1587 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1588 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1589 1590 /* 1591 * Initialize the Rx DMA interrupt control register. We 1592 * request an interrupt after every incoming packet, but 1593 * defer it for 32us (64 * 512 ns). When the number of 1594 * interrupts pending reaches 8, we stop deferring the 1595 * interrupt, and signal it immediately. 1596 */ 1597 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1598 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1599 1600 /* 1601 * Initialize the interrupt mask. 1602 */ 1603 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1604 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1605 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1606 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1607 1608 /* 1609 * Configure the DMA engine. 1610 * XXX Should auto-tune TxBurstLimit. 1611 */ 1612 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1613 DMAC_TxBurstLimit(3)); 1614 1615 /* 1616 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1617 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1618 * empty again. 1619 */ 1620 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1621 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1622 1623 /* 1624 * Set the maximum frame size. 1625 */ 1626 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1627 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1628 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1629 ETHER_VLAN_ENCAP_LEN : 0)); 1630 1631 /* 1632 * Initialize MacCtrl -- do it before setting the media, 1633 * as setting the media will actually program the register. 1634 * 1635 * Note: We have to poke the IFS value before poking 1636 * anything else. 1637 */ 1638 sc->sc_MACCtrl = MC_IFSSelect(0); 1639 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1640 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1641 #ifdef STGE_VLAN_UNTAG 1642 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1643 #endif 1644 1645 if (sc->sc_rev >= 6) { /* >= B.2 */ 1646 /* Multi-frag frame bug work-around. */ 1647 bus_space_write_2(st, sh, STGE_DebugCtrl, 1648 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1649 1650 /* Tx Poll Now bug work-around. */ 1651 bus_space_write_2(st, sh, STGE_DebugCtrl, 1652 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1653 /* XXX ? from linux */ 1654 bus_space_write_2(st, sh, STGE_DebugCtrl, 1655 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1656 } 1657 1658 /* 1659 * Set the current media. 1660 */ 1661 mii_mediachg(&sc->sc_mii); 1662 1663 /* 1664 * Start the one second MII clock. 1665 */ 1666 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1667 1668 /* 1669 * ...all done! 1670 */ 1671 ifp->if_flags |= IFF_RUNNING; 1672 ifp->if_flags &= ~IFF_OACTIVE; 1673 1674 out: 1675 if (error) 1676 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1677 return (error); 1678 } 1679 1680 /* 1681 * stge_drain: 1682 * 1683 * Drain the receive queue. 1684 */ 1685 static void 1686 stge_rxdrain(struct stge_softc *sc) 1687 { 1688 struct stge_descsoft *ds; 1689 int i; 1690 1691 for (i = 0; i < STGE_NRXDESC; i++) { 1692 ds = &sc->sc_rxsoft[i]; 1693 if (ds->ds_mbuf != NULL) { 1694 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1695 ds->ds_mbuf->m_next = NULL; 1696 m_freem(ds->ds_mbuf); 1697 ds->ds_mbuf = NULL; 1698 } 1699 } 1700 } 1701 1702 /* 1703 * stge_stop: [ ifnet interface function ] 1704 * 1705 * Stop transmission on the interface. 1706 */ 1707 static void 1708 stge_stop(struct ifnet *ifp, int disable) 1709 { 1710 struct stge_softc *sc = ifp->if_softc; 1711 struct stge_descsoft *ds; 1712 int i; 1713 1714 /* 1715 * Stop the one second clock. 1716 */ 1717 callout_stop(&sc->sc_tick_ch); 1718 1719 /* Down the MII. */ 1720 mii_down(&sc->sc_mii); 1721 1722 /* 1723 * Disable interrupts. 1724 */ 1725 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1726 1727 /* 1728 * Stop receiver, transmitter, and stats update. 1729 */ 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1731 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1732 1733 /* 1734 * Stop the transmit and receive DMA. 1735 */ 1736 stge_dma_wait(sc); 1737 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1738 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1739 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1740 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1741 1742 /* 1743 * Release any queued transmit buffers. 1744 */ 1745 for (i = 0; i < STGE_NTXDESC; i++) { 1746 ds = &sc->sc_txsoft[i]; 1747 if (ds->ds_mbuf != NULL) { 1748 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1749 m_freem(ds->ds_mbuf); 1750 ds->ds_mbuf = NULL; 1751 } 1752 } 1753 1754 if (disable) 1755 stge_rxdrain(sc); 1756 1757 /* 1758 * Mark the interface down and cancel the watchdog timer. 1759 */ 1760 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1761 ifp->if_timer = 0; 1762 } 1763 1764 #if 0 1765 static int 1766 stge_eeprom_wait(struct stge_softc *sc) 1767 { 1768 int i; 1769 1770 for (i = 0; i < STGE_TIMEOUT; i++) { 1771 delay(1000); 1772 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1773 EC_EepromBusy) == 0) 1774 return (0); 1775 } 1776 return (1); 1777 } 1778 1779 /* 1780 * stge_read_eeprom: 1781 * 1782 * Read data from the serial EEPROM. 1783 */ 1784 static void 1785 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1786 { 1787 1788 if (stge_eeprom_wait(sc)) 1789 printf("%s: EEPROM failed to come ready\n", 1790 sc->sc_dev.dv_xname); 1791 1792 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1793 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1794 if (stge_eeprom_wait(sc)) 1795 printf("%s: EEPROM read timed out\n", 1796 sc->sc_dev.dv_xname); 1797 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1798 } 1799 #endif /* 0 */ 1800 1801 /* 1802 * stge_add_rxbuf: 1803 * 1804 * Add a receive buffer to the indicated descriptor. 1805 */ 1806 static int 1807 stge_add_rxbuf(struct stge_softc *sc, int idx) 1808 { 1809 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1810 struct mbuf *m; 1811 int error; 1812 1813 MGETHDR(m, M_DONTWAIT, MT_DATA); 1814 if (m == NULL) 1815 return (ENOBUFS); 1816 1817 MCLGET(m, M_DONTWAIT); 1818 if ((m->m_flags & M_EXT) == 0) { 1819 m_freem(m); 1820 return (ENOBUFS); 1821 } 1822 1823 m->m_data = m->m_ext.ext_buf + 2; 1824 m->m_len = MCLBYTES - 2; 1825 1826 if (ds->ds_mbuf != NULL) 1827 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1828 1829 ds->ds_mbuf = m; 1830 1831 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1832 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1833 if (error) { 1834 printf("%s: can't load rx DMA map %d, error = %d\n", 1835 sc->sc_dev.dv_xname, idx, error); 1836 panic("stge_add_rxbuf"); /* XXX */ 1837 } 1838 1839 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1840 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1841 1842 STGE_INIT_RXDESC(sc, idx); 1843 1844 return (0); 1845 } 1846 1847 /* 1848 * stge_set_filter: 1849 * 1850 * Set up the receive filter. 1851 */ 1852 static void 1853 stge_set_filter(struct stge_softc *sc) 1854 { 1855 struct ethercom *ec = &sc->sc_ethercom; 1856 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1857 struct ether_multi *enm; 1858 struct ether_multistep step; 1859 uint32_t crc; 1860 uint32_t mchash[2]; 1861 1862 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1863 if (ifp->if_flags & IFF_BROADCAST) 1864 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1865 1866 if (ifp->if_flags & IFF_PROMISC) { 1867 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1868 goto allmulti; 1869 } 1870 1871 /* 1872 * Set up the multicast address filter by passing all multicast 1873 * addresses through a CRC generator, and then using the low-order 1874 * 6 bits as an index into the 64 bit multicast hash table. The 1875 * high order bits select the register, while the rest of the bits 1876 * select the bit within the register. 1877 */ 1878 1879 memset(mchash, 0, sizeof(mchash)); 1880 1881 ETHER_FIRST_MULTI(step, ec, enm); 1882 if (enm == NULL) 1883 goto done; 1884 1885 while (enm != NULL) { 1886 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1887 /* 1888 * We must listen to a range of multicast addresses. 1889 * For now, just accept all multicasts, rather than 1890 * trying to set only those filter bits needed to match 1891 * the range. (At this time, the only use of address 1892 * ranges is for IP multicast routing, for which the 1893 * range is big enough to require all bits set.) 1894 */ 1895 goto allmulti; 1896 } 1897 1898 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1899 1900 /* Just want the 6 least significant bits. */ 1901 crc &= 0x3f; 1902 1903 /* Set the corresponding bit in the hash table. */ 1904 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1905 1906 ETHER_NEXT_MULTI(step, enm); 1907 } 1908 1909 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1910 1911 ifp->if_flags &= ~IFF_ALLMULTI; 1912 goto done; 1913 1914 allmulti: 1915 ifp->if_flags |= IFF_ALLMULTI; 1916 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1917 1918 done: 1919 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1920 /* 1921 * Program the multicast hash table. 1922 */ 1923 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1924 mchash[0]); 1925 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1926 mchash[1]); 1927 } 1928 1929 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1930 sc->sc_ReceiveMode); 1931 } 1932 1933 /* 1934 * stge_mii_readreg: [mii interface function] 1935 * 1936 * Read a PHY register on the MII of the TC9021. 1937 */ 1938 static int 1939 stge_mii_readreg(struct device *self, int phy, int reg) 1940 { 1941 1942 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1943 } 1944 1945 /* 1946 * stge_mii_writereg: [mii interface function] 1947 * 1948 * Write a PHY register on the MII of the TC9021. 1949 */ 1950 static void 1951 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1952 { 1953 1954 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1955 } 1956 1957 /* 1958 * stge_mii_statchg: [mii interface function] 1959 * 1960 * Callback from MII layer when media changes. 1961 */ 1962 static void 1963 stge_mii_statchg(struct device *self) 1964 { 1965 struct stge_softc *sc = (struct stge_softc *) self; 1966 1967 if (sc->sc_mii.mii_media_active & IFM_FDX) 1968 sc->sc_MACCtrl |= MC_DuplexSelect; 1969 else 1970 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1971 1972 /* XXX 802.1x flow-control? */ 1973 1974 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1975 } 1976 1977 /* 1978 * sste_mii_bitbang_read: [mii bit-bang interface function] 1979 * 1980 * Read the MII serial port for the MII bit-bang module. 1981 */ 1982 static uint32_t 1983 stge_mii_bitbang_read(struct device *self) 1984 { 1985 struct stge_softc *sc = (void *) self; 1986 1987 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1988 } 1989 1990 /* 1991 * stge_mii_bitbang_write: [mii big-bang interface function] 1992 * 1993 * Write the MII serial port for the MII bit-bang module. 1994 */ 1995 static void 1996 stge_mii_bitbang_write(struct device *self, uint32_t val) 1997 { 1998 struct stge_softc *sc = (void *) self; 1999 2000 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2001 val | sc->sc_PhyCtrl); 2002 } 2003 2004 /* 2005 * stge_mediastatus: [ifmedia interface function] 2006 * 2007 * Get the current interface media status. 2008 */ 2009 static void 2010 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2011 { 2012 struct stge_softc *sc = ifp->if_softc; 2013 2014 mii_pollstat(&sc->sc_mii); 2015 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2016 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2017 } 2018 2019 /* 2020 * stge_mediachange: [ifmedia interface function] 2021 * 2022 * Set hardware to newly-selected media. 2023 */ 2024 static int 2025 stge_mediachange(struct ifnet *ifp) 2026 { 2027 struct stge_softc *sc = ifp->if_softc; 2028 2029 if (ifp->if_flags & IFF_UP) 2030 mii_mediachg(&sc->sc_mii); 2031 return (0); 2032 } 2033