1 /* $NetBSD: if_stge.c,v 1.50 2010/04/05 07:20:27 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.50 2010/04/05 07:20:27 joerg Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/mii/mii_bitbang.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_stgereg.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int); 282 static void stge_mii_writereg(device_t, int, int, int); 283 static void stge_mii_statchg(device_t); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 pci_intr_handle_t ih; 380 const char *intrstr = NULL; 381 bus_space_tag_t iot, memt; 382 bus_space_handle_t ioh, memh; 383 bus_dma_segment_t seg; 384 int ioh_valid, memh_valid; 385 int i, rseg, error; 386 const struct stge_product *sp; 387 uint8_t enaddr[ETHER_ADDR_LEN]; 388 389 callout_init(&sc->sc_tick_ch, 0); 390 391 sp = stge_lookup(pa); 392 if (sp == NULL) { 393 printf("\n"); 394 panic("ste_attach: impossible"); 395 } 396 397 sc->sc_rev = PCI_REVISION(pa->pa_class); 398 399 aprint_normal(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 400 401 /* 402 * Map the device. 403 */ 404 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 405 PCI_MAPREG_TYPE_IO, 0, 406 &iot, &ioh, NULL, NULL) == 0); 407 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 408 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 409 &memt, &memh, NULL, NULL) == 0); 410 411 if (memh_valid) { 412 sc->sc_st = memt; 413 sc->sc_sh = memh; 414 } else if (ioh_valid) { 415 sc->sc_st = iot; 416 sc->sc_sh = ioh; 417 } else { 418 aprint_error_dev(self, "unable to map device registers\n"); 419 return; 420 } 421 422 sc->sc_dmat = pa->pa_dmat; 423 424 /* Enable bus mastering. */ 425 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 427 PCI_COMMAND_MASTER_ENABLE); 428 429 /* power up chip */ 430 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 431 error != EOPNOTSUPP) { 432 aprint_error_dev(self, "cannot activate %d\n", 433 error); 434 return; 435 } 436 /* 437 * Map and establish our interrupt. 438 */ 439 if (pci_intr_map(pa, &ih)) { 440 aprint_error_dev(self, "unable to map interrupt\n"); 441 return; 442 } 443 intrstr = pci_intr_string(pc, ih); 444 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 445 if (sc->sc_ih == NULL) { 446 aprint_error_dev(self, "unable to establish interrupt"); 447 if (intrstr != NULL) 448 aprint_error(" at %s", intrstr); 449 aprint_error("\n"); 450 return; 451 } 452 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 453 454 /* 455 * Allocate the control data structures, and create and load the 456 * DMA map for it. 457 */ 458 if ((error = bus_dmamem_alloc(sc->sc_dmat, 459 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 460 0)) != 0) { 461 aprint_error_dev(self, 462 "unable to allocate control data, error = %d\n", 463 error); 464 goto fail_0; 465 } 466 467 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 468 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 469 BUS_DMA_COHERENT)) != 0) { 470 aprint_error_dev(self, 471 "unable to map control data, error = %d\n", 472 error); 473 goto fail_1; 474 } 475 476 if ((error = bus_dmamap_create(sc->sc_dmat, 477 sizeof(struct stge_control_data), 1, 478 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 479 aprint_error_dev(self, 480 "unable to create control data DMA map, error = %d\n", 481 error); 482 goto fail_2; 483 } 484 485 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 486 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 487 0)) != 0) { 488 aprint_error_dev(self, 489 "unable to load control data DMA map, error = %d\n", 490 error); 491 goto fail_3; 492 } 493 494 /* 495 * Create the transmit buffer DMA maps. Note that rev B.3 496 * and earlier seem to have a bug regarding multi-fragment 497 * packets. We need to limit the number of Tx segments on 498 * such chips to 1. 499 */ 500 for (i = 0; i < STGE_NTXDESC; i++) { 501 if ((error = bus_dmamap_create(sc->sc_dmat, 502 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 503 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 504 aprint_error_dev(self, 505 "unable to create tx DMA map %d, error = %d\n", 506 i, error); 507 goto fail_4; 508 } 509 } 510 511 /* 512 * Create the receive buffer DMA maps. 513 */ 514 for (i = 0; i < STGE_NRXDESC; i++) { 515 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 516 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 517 aprint_error_dev(self, 518 "unable to create rx DMA map %d, error = %d\n", 519 i, error); 520 goto fail_5; 521 } 522 sc->sc_rxsoft[i].ds_mbuf = NULL; 523 } 524 525 /* 526 * Determine if we're copper or fiber. It affects how we 527 * reset the card. 528 */ 529 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 530 AC_PhyMedia) 531 sc->sc_usefiber = 1; 532 else 533 sc->sc_usefiber = 0; 534 535 /* 536 * Reset the chip to a known state. 537 */ 538 stge_reset(sc); 539 540 /* 541 * Reading the station address from the EEPROM doesn't seem 542 * to work, at least on my sample boards. Instead, since 543 * the reset sequence does AutoInit, read it from the station 544 * address registers. For Sundance 1023 you can only read it 545 * from EEPROM. 546 */ 547 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 548 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 549 STGE_StationAddress0) & 0xff; 550 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 551 STGE_StationAddress0) >> 8; 552 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 553 STGE_StationAddress1) & 0xff; 554 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 555 STGE_StationAddress1) >> 8; 556 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 557 STGE_StationAddress2) & 0xff; 558 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 559 STGE_StationAddress2) >> 8; 560 sc->sc_stge1023 = 0; 561 } else { 562 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 563 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 564 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 565 &myaddr[i]); 566 myaddr[i] = le16toh(myaddr[i]); 567 } 568 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 569 sc->sc_stge1023 = 1; 570 } 571 572 aprint_normal_dev(self, "Ethernet address %s\n", 573 ether_sprintf(enaddr)); 574 575 /* 576 * Read some important bits from the PhyCtrl register. 577 */ 578 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 579 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 580 581 /* 582 * Initialize our media structures and probe the MII. 583 */ 584 sc->sc_mii.mii_ifp = ifp; 585 sc->sc_mii.mii_readreg = stge_mii_readreg; 586 sc->sc_mii.mii_writereg = stge_mii_writereg; 587 sc->sc_mii.mii_statchg = stge_mii_statchg; 588 sc->sc_ethercom.ec_mii = &sc->sc_mii; 589 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 590 ether_mediastatus); 591 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 592 MII_OFFSET_ANY, MIIF_DOPAUSE); 593 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 594 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 595 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 596 } else 597 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 598 599 ifp = &sc->sc_ethercom.ec_if; 600 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 601 ifp->if_softc = sc; 602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 603 ifp->if_ioctl = stge_ioctl; 604 ifp->if_start = stge_start; 605 ifp->if_watchdog = stge_watchdog; 606 ifp->if_init = stge_init; 607 ifp->if_stop = stge_stop; 608 IFQ_SET_READY(&ifp->if_snd); 609 610 /* 611 * The manual recommends disabling early transmit, so we 612 * do. It's disabled anyway, if using IP checksumming, 613 * since the entire packet must be in the FIFO in order 614 * for the chip to perform the checksum. 615 */ 616 sc->sc_txthresh = 0x0fff; 617 618 /* 619 * Disable MWI if the PCI layer tells us to. 620 */ 621 sc->sc_DMACtrl = 0; 622 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 623 sc->sc_DMACtrl |= DMAC_MWIDisable; 624 625 /* 626 * We can support 802.1Q VLAN-sized frames and jumbo 627 * Ethernet frames. 628 * 629 * XXX Figure out how to do hw-assisted VLAN tagging in 630 * XXX a reasonable way on this chip. 631 */ 632 sc->sc_ethercom.ec_capabilities |= 633 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 634 ETHERCAP_VLAN_HWTAGGING; 635 636 /* 637 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 638 */ 639 sc->sc_ethercom.ec_if.if_capabilities |= 640 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 641 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 642 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 643 644 /* 645 * Attach the interface. 646 */ 647 if_attach(ifp); 648 ether_ifattach(ifp, enaddr); 649 650 #ifdef STGE_EVENT_COUNTERS 651 /* 652 * Attach event counters. 653 */ 654 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 655 NULL, device_xname(self), "txstall"); 656 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 657 NULL, device_xname(self), "txdmaintr"); 658 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 659 NULL, device_xname(self), "txindintr"); 660 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 661 NULL, device_xname(self), "rxintr"); 662 663 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 664 NULL, device_xname(self), "txseg1"); 665 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 666 NULL, device_xname(self), "txseg2"); 667 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 668 NULL, device_xname(self), "txseg3"); 669 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "txseg4"); 671 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "txseg5"); 673 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 674 NULL, device_xname(self), "txsegmore"); 675 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 676 NULL, device_xname(self), "txcopy"); 677 678 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 679 NULL, device_xname(self), "rxipsum"); 680 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 681 NULL, device_xname(self), "rxtcpsum"); 682 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "rxudpsum"); 684 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "txipsum"); 686 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "txtcpsum"); 688 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "txudpsum"); 690 #endif /* STGE_EVENT_COUNTERS */ 691 692 /* 693 * Make sure the interface is shutdown during reboot. 694 */ 695 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 696 pmf_class_network_register(self, ifp); 697 else 698 aprint_error_dev(self, "couldn't establish power handler\n"); 699 700 return; 701 702 /* 703 * Free any resources we've allocated during the failed attach 704 * attempt. Do this in reverse order and fall through. 705 */ 706 fail_5: 707 for (i = 0; i < STGE_NRXDESC; i++) { 708 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 709 bus_dmamap_destroy(sc->sc_dmat, 710 sc->sc_rxsoft[i].ds_dmamap); 711 } 712 fail_4: 713 for (i = 0; i < STGE_NTXDESC; i++) { 714 if (sc->sc_txsoft[i].ds_dmamap != NULL) 715 bus_dmamap_destroy(sc->sc_dmat, 716 sc->sc_txsoft[i].ds_dmamap); 717 } 718 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 719 fail_3: 720 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 721 fail_2: 722 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 723 sizeof(struct stge_control_data)); 724 fail_1: 725 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 726 fail_0: 727 return; 728 } 729 730 /* 731 * stge_shutdown: 732 * 733 * Make sure the interface is stopped at reboot time. 734 */ 735 static bool 736 stge_shutdown(device_t self, int howto) 737 { 738 struct stge_softc *sc = device_private(self); 739 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 740 741 stge_stop(ifp, 1); 742 743 return true; 744 } 745 746 static void 747 stge_dma_wait(struct stge_softc *sc) 748 { 749 int i; 750 751 for (i = 0; i < STGE_TIMEOUT; i++) { 752 delay(2); 753 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 754 DMAC_TxDMAInProg) == 0) 755 break; 756 } 757 758 if (i == STGE_TIMEOUT) 759 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 760 } 761 762 /* 763 * stge_start: [ifnet interface function] 764 * 765 * Start packet transmission on the interface. 766 */ 767 static void 768 stge_start(struct ifnet *ifp) 769 { 770 struct stge_softc *sc = ifp->if_softc; 771 struct mbuf *m0; 772 struct stge_descsoft *ds; 773 struct stge_tfd *tfd; 774 bus_dmamap_t dmamap; 775 int error, firsttx, nexttx, opending, seg, totlen; 776 uint64_t csum_flags; 777 778 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 779 return; 780 781 /* 782 * Remember the previous number of pending transmissions 783 * and the first descriptor we will use. 784 */ 785 opending = sc->sc_txpending; 786 firsttx = STGE_NEXTTX(sc->sc_txlast); 787 788 /* 789 * Loop through the send queue, setting up transmit descriptors 790 * until we drain the queue, or use up all available transmit 791 * descriptors. 792 */ 793 for (;;) { 794 struct m_tag *mtag; 795 uint64_t tfc; 796 797 /* 798 * Grab a packet off the queue. 799 */ 800 IFQ_POLL(&ifp->if_snd, m0); 801 if (m0 == NULL) 802 break; 803 804 /* 805 * Leave one unused descriptor at the end of the 806 * list to prevent wrapping completely around. 807 */ 808 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 809 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 810 break; 811 } 812 813 /* 814 * See if we have any VLAN stuff. 815 */ 816 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 817 818 /* 819 * Get the last and next available transmit descriptor. 820 */ 821 nexttx = STGE_NEXTTX(sc->sc_txlast); 822 tfd = &sc->sc_txdescs[nexttx]; 823 ds = &sc->sc_txsoft[nexttx]; 824 825 dmamap = ds->ds_dmamap; 826 827 /* 828 * Load the DMA map. If this fails, the packet either 829 * didn't fit in the alloted number of segments, or we 830 * were short on resources. For the too-many-segments 831 * case, we simply report an error and drop the packet, 832 * since we can't sanely copy a jumbo packet to a single 833 * buffer. 834 */ 835 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 836 BUS_DMA_NOWAIT); 837 if (error) { 838 if (error == EFBIG) { 839 printf("%s: Tx packet consumes too many " 840 "DMA segments, dropping...\n", 841 device_xname(sc->sc_dev)); 842 IFQ_DEQUEUE(&ifp->if_snd, m0); 843 m_freem(m0); 844 continue; 845 } 846 /* 847 * Short on resources, just stop for now. 848 */ 849 break; 850 } 851 852 IFQ_DEQUEUE(&ifp->if_snd, m0); 853 854 /* 855 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 856 */ 857 858 /* Sync the DMA map. */ 859 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 860 BUS_DMASYNC_PREWRITE); 861 862 /* Initialize the fragment list. */ 863 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 864 tfd->tfd_frags[seg].frag_word0 = 865 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 866 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 867 totlen += dmamap->dm_segs[seg].ds_len; 868 } 869 870 #ifdef STGE_EVENT_COUNTERS 871 switch (dmamap->dm_nsegs) { 872 case 1: 873 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 874 break; 875 case 2: 876 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 877 break; 878 case 3: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 880 break; 881 case 4: 882 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 883 break; 884 case 5: 885 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 886 break; 887 default: 888 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 889 break; 890 } 891 #endif /* STGE_EVENT_COUNTERS */ 892 893 /* 894 * Initialize checksumming flags in the descriptor. 895 * Byte-swap constants so the compiler can optimize. 896 */ 897 csum_flags = 0; 898 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 899 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 900 csum_flags |= TFD_IPChecksumEnable; 901 } 902 903 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 904 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 905 csum_flags |= TFD_TCPChecksumEnable; 906 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 907 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 908 csum_flags |= TFD_UDPChecksumEnable; 909 } 910 911 /* 912 * Initialize the descriptor and give it to the chip. 913 * Check to see if we have a VLAN tag to insert. 914 */ 915 916 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 917 TFD_FragCount(seg) | csum_flags | 918 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 919 TFD_TxDMAIndicate : 0); 920 if (mtag) { 921 #if 0 922 struct ether_header *eh = 923 mtod(m0, struct ether_header *); 924 u_int16_t etype = ntohs(eh->ether_type); 925 printf("%s: xmit (tag %d) etype %x\n", 926 ifp->if_xname, *mtod(n, int *), etype); 927 #endif 928 tfc |= TFD_VLANTagInsert | 929 #ifdef STGE_VLAN_CFI 930 TFD_CFI | 931 #endif 932 TFD_VID(VLAN_TAG_VALUE(mtag)); 933 } 934 tfd->tfd_control = htole64(tfc); 935 936 /* Sync the descriptor. */ 937 STGE_CDTXSYNC(sc, nexttx, 938 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 939 940 /* 941 * Kick the transmit DMA logic. 942 */ 943 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 944 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 945 946 /* 947 * Store a pointer to the packet so we can free it later. 948 */ 949 ds->ds_mbuf = m0; 950 951 /* Advance the tx pointer. */ 952 sc->sc_txpending++; 953 sc->sc_txlast = nexttx; 954 955 /* 956 * Pass the packet to any BPF listeners. 957 */ 958 bpf_mtap(ifp, m0); 959 } 960 961 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 962 /* No more slots left; notify upper layer. */ 963 ifp->if_flags |= IFF_OACTIVE; 964 } 965 966 if (sc->sc_txpending != opending) { 967 /* 968 * We enqueued packets. If the transmitter was idle, 969 * reset the txdirty pointer. 970 */ 971 if (opending == 0) 972 sc->sc_txdirty = firsttx; 973 974 /* Set a watchdog timer in case the chip flakes out. */ 975 ifp->if_timer = 5; 976 } 977 } 978 979 /* 980 * stge_watchdog: [ifnet interface function] 981 * 982 * Watchdog timer handler. 983 */ 984 static void 985 stge_watchdog(struct ifnet *ifp) 986 { 987 struct stge_softc *sc = ifp->if_softc; 988 989 /* 990 * Sweep up first, since we don't interrupt every frame. 991 */ 992 stge_txintr(sc); 993 if (sc->sc_txpending != 0) { 994 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 995 ifp->if_oerrors++; 996 997 (void) stge_init(ifp); 998 999 /* Try to get more packets going. */ 1000 stge_start(ifp); 1001 } 1002 } 1003 1004 /* 1005 * stge_ioctl: [ifnet interface function] 1006 * 1007 * Handle control requests from the operator. 1008 */ 1009 static int 1010 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1011 { 1012 struct stge_softc *sc = ifp->if_softc; 1013 int s, error; 1014 1015 s = splnet(); 1016 1017 error = ether_ioctl(ifp, cmd, data); 1018 if (error == ENETRESET) { 1019 error = 0; 1020 1021 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1022 ; 1023 else if (ifp->if_flags & IFF_RUNNING) { 1024 /* 1025 * Multicast list has changed; set the hardware filter 1026 * accordingly. 1027 */ 1028 stge_set_filter(sc); 1029 } 1030 } 1031 1032 /* Try to get more packets going. */ 1033 stge_start(ifp); 1034 1035 splx(s); 1036 return (error); 1037 } 1038 1039 /* 1040 * stge_intr: 1041 * 1042 * Interrupt service routine. 1043 */ 1044 static int 1045 stge_intr(void *arg) 1046 { 1047 struct stge_softc *sc = arg; 1048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1049 uint32_t txstat; 1050 int wantinit; 1051 uint16_t isr; 1052 1053 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1054 IS_InterruptStatus) == 0) 1055 return (0); 1056 1057 for (wantinit = 0; wantinit == 0;) { 1058 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1059 if ((isr & sc->sc_IntEnable) == 0) 1060 break; 1061 1062 /* Host interface errors. */ 1063 if (isr & IS_HostError) { 1064 printf("%s: Host interface error\n", 1065 device_xname(sc->sc_dev)); 1066 wantinit = 1; 1067 continue; 1068 } 1069 1070 /* Receive interrupts. */ 1071 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1072 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1073 stge_rxintr(sc); 1074 if (isr & IS_RFDListEnd) { 1075 printf("%s: receive ring overflow\n", 1076 device_xname(sc->sc_dev)); 1077 /* 1078 * XXX Should try to recover from this 1079 * XXX more gracefully. 1080 */ 1081 wantinit = 1; 1082 } 1083 } 1084 1085 /* Transmit interrupts. */ 1086 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1087 #ifdef STGE_EVENT_COUNTERS 1088 if (isr & IS_TxDMAComplete) 1089 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1090 #endif 1091 stge_txintr(sc); 1092 } 1093 1094 /* Statistics overflow. */ 1095 if (isr & IS_UpdateStats) 1096 stge_stats_update(sc); 1097 1098 /* Transmission errors. */ 1099 if (isr & IS_TxComplete) { 1100 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1101 for (;;) { 1102 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1103 STGE_TxStatus); 1104 if ((txstat & TS_TxComplete) == 0) 1105 break; 1106 if (txstat & TS_TxUnderrun) { 1107 sc->sc_txthresh++; 1108 if (sc->sc_txthresh > 0x0fff) 1109 sc->sc_txthresh = 0x0fff; 1110 printf("%s: transmit underrun, new " 1111 "threshold: %d bytes\n", 1112 device_xname(sc->sc_dev), 1113 sc->sc_txthresh << 5); 1114 } 1115 if (txstat & TS_MaxCollisions) 1116 printf("%s: excessive collisions\n", 1117 device_xname(sc->sc_dev)); 1118 } 1119 wantinit = 1; 1120 } 1121 1122 } 1123 1124 if (wantinit) 1125 stge_init(ifp); 1126 1127 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1128 sc->sc_IntEnable); 1129 1130 /* Try to get more packets going. */ 1131 stge_start(ifp); 1132 1133 return (1); 1134 } 1135 1136 /* 1137 * stge_txintr: 1138 * 1139 * Helper; handle transmit interrupts. 1140 */ 1141 static void 1142 stge_txintr(struct stge_softc *sc) 1143 { 1144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1145 struct stge_descsoft *ds; 1146 uint64_t control; 1147 int i; 1148 1149 ifp->if_flags &= ~IFF_OACTIVE; 1150 1151 /* 1152 * Go through our Tx list and free mbufs for those 1153 * frames which have been transmitted. 1154 */ 1155 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1156 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1157 ds = &sc->sc_txsoft[i]; 1158 1159 STGE_CDTXSYNC(sc, i, 1160 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1161 1162 control = le64toh(sc->sc_txdescs[i].tfd_control); 1163 if ((control & TFD_TFDDone) == 0) 1164 break; 1165 1166 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1167 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1168 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1169 m_freem(ds->ds_mbuf); 1170 ds->ds_mbuf = NULL; 1171 } 1172 1173 /* Update the dirty transmit buffer pointer. */ 1174 sc->sc_txdirty = i; 1175 1176 /* 1177 * If there are no more pending transmissions, cancel the watchdog 1178 * timer. 1179 */ 1180 if (sc->sc_txpending == 0) 1181 ifp->if_timer = 0; 1182 } 1183 1184 /* 1185 * stge_rxintr: 1186 * 1187 * Helper; handle receive interrupts. 1188 */ 1189 static void 1190 stge_rxintr(struct stge_softc *sc) 1191 { 1192 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1193 struct stge_descsoft *ds; 1194 struct mbuf *m, *tailm; 1195 uint64_t status; 1196 int i, len; 1197 1198 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1199 ds = &sc->sc_rxsoft[i]; 1200 1201 STGE_CDRXSYNC(sc, i, 1202 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1203 1204 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1205 1206 if ((status & RFD_RFDDone) == 0) 1207 break; 1208 1209 if (__predict_false(sc->sc_rxdiscard)) { 1210 STGE_INIT_RXDESC(sc, i); 1211 if (status & RFD_FrameEnd) { 1212 /* Reset our state. */ 1213 sc->sc_rxdiscard = 0; 1214 } 1215 continue; 1216 } 1217 1218 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1219 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1220 1221 m = ds->ds_mbuf; 1222 1223 /* 1224 * Add a new receive buffer to the ring. 1225 */ 1226 if (stge_add_rxbuf(sc, i) != 0) { 1227 /* 1228 * Failed, throw away what we've done so 1229 * far, and discard the rest of the packet. 1230 */ 1231 ifp->if_ierrors++; 1232 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1233 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1234 STGE_INIT_RXDESC(sc, i); 1235 if ((status & RFD_FrameEnd) == 0) 1236 sc->sc_rxdiscard = 1; 1237 if (sc->sc_rxhead != NULL) 1238 m_freem(sc->sc_rxhead); 1239 STGE_RXCHAIN_RESET(sc); 1240 continue; 1241 } 1242 1243 #ifdef DIAGNOSTIC 1244 if (status & RFD_FrameStart) { 1245 KASSERT(sc->sc_rxhead == NULL); 1246 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1247 } 1248 #endif 1249 1250 STGE_RXCHAIN_LINK(sc, m); 1251 1252 /* 1253 * If this is not the end of the packet, keep 1254 * looking. 1255 */ 1256 if ((status & RFD_FrameEnd) == 0) { 1257 sc->sc_rxlen += m->m_len; 1258 continue; 1259 } 1260 1261 /* 1262 * Okay, we have the entire packet now... 1263 */ 1264 *sc->sc_rxtailp = NULL; 1265 m = sc->sc_rxhead; 1266 tailm = sc->sc_rxtail; 1267 1268 STGE_RXCHAIN_RESET(sc); 1269 1270 /* 1271 * If the packet had an error, drop it. Note we 1272 * count the error later in the periodic stats update. 1273 */ 1274 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1275 RFD_RxAlignmentError | RFD_RxFCSError | 1276 RFD_RxLengthError)) { 1277 m_freem(m); 1278 continue; 1279 } 1280 1281 /* 1282 * No errors. 1283 * 1284 * Note we have configured the chip to not include 1285 * the CRC at the end of the packet. 1286 */ 1287 len = RFD_RxDMAFrameLen(status); 1288 tailm->m_len = len - sc->sc_rxlen; 1289 1290 /* 1291 * If the packet is small enough to fit in a 1292 * single header mbuf, allocate one and copy 1293 * the data into it. This greatly reduces 1294 * memory consumption when we receive lots 1295 * of small packets. 1296 */ 1297 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1298 struct mbuf *nm; 1299 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1300 if (nm == NULL) { 1301 ifp->if_ierrors++; 1302 m_freem(m); 1303 continue; 1304 } 1305 nm->m_data += 2; 1306 nm->m_pkthdr.len = nm->m_len = len; 1307 m_copydata(m, 0, len, mtod(nm, void *)); 1308 m_freem(m); 1309 m = nm; 1310 } 1311 1312 /* 1313 * Set the incoming checksum information for the packet. 1314 */ 1315 if (status & RFD_IPDetected) { 1316 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1317 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1318 if (status & RFD_IPError) 1319 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1320 if (status & RFD_TCPDetected) { 1321 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1322 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1323 if (status & RFD_TCPError) 1324 m->m_pkthdr.csum_flags |= 1325 M_CSUM_TCP_UDP_BAD; 1326 } else if (status & RFD_UDPDetected) { 1327 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1328 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1329 if (status & RFD_UDPError) 1330 m->m_pkthdr.csum_flags |= 1331 M_CSUM_TCP_UDP_BAD; 1332 } 1333 } 1334 1335 m->m_pkthdr.rcvif = ifp; 1336 m->m_pkthdr.len = len; 1337 1338 /* 1339 * Pass this up to any BPF listeners, but only 1340 * pass if up the stack if it's for us. 1341 */ 1342 bpf_mtap(ifp, m); 1343 #ifdef STGE_VLAN_UNTAG 1344 /* 1345 * Check for VLAN tagged packets 1346 */ 1347 if (status & RFD_VLANDetected) 1348 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1349 1350 #endif 1351 #if 0 1352 if (status & RFD_VLANDetected) { 1353 struct ether_header *eh; 1354 u_int16_t etype; 1355 1356 eh = mtod(m, struct ether_header *); 1357 etype = ntohs(eh->ether_type); 1358 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1359 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1360 etype); 1361 } 1362 #endif 1363 /* Pass it on. */ 1364 (*ifp->if_input)(ifp, m); 1365 } 1366 1367 /* Update the receive pointer. */ 1368 sc->sc_rxptr = i; 1369 } 1370 1371 /* 1372 * stge_tick: 1373 * 1374 * One second timer, used to tick the MII. 1375 */ 1376 static void 1377 stge_tick(void *arg) 1378 { 1379 struct stge_softc *sc = arg; 1380 int s; 1381 1382 s = splnet(); 1383 mii_tick(&sc->sc_mii); 1384 stge_stats_update(sc); 1385 splx(s); 1386 1387 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1388 } 1389 1390 /* 1391 * stge_stats_update: 1392 * 1393 * Read the TC9021 statistics counters. 1394 */ 1395 static void 1396 stge_stats_update(struct stge_softc *sc) 1397 { 1398 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1399 bus_space_tag_t st = sc->sc_st; 1400 bus_space_handle_t sh = sc->sc_sh; 1401 1402 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1403 1404 ifp->if_ipackets += 1405 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1406 1407 ifp->if_ierrors += 1408 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1409 1410 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1411 1412 ifp->if_opackets += 1413 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1414 1415 ifp->if_collisions += 1416 bus_space_read_4(st, sh, STGE_LateCollisions) + 1417 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1418 bus_space_read_4(st, sh, STGE_SingleColFrames); 1419 1420 ifp->if_oerrors += 1421 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1422 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1423 } 1424 1425 /* 1426 * stge_reset: 1427 * 1428 * Perform a soft reset on the TC9021. 1429 */ 1430 static void 1431 stge_reset(struct stge_softc *sc) 1432 { 1433 uint32_t ac; 1434 int i; 1435 1436 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1437 1438 /* 1439 * Only assert RstOut if we're fiber. We need GMII clocks 1440 * to be present in order for the reset to complete on fiber 1441 * cards. 1442 */ 1443 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1444 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1445 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1446 (sc->sc_usefiber ? AC_RstOut : 0)); 1447 1448 delay(50000); 1449 1450 for (i = 0; i < STGE_TIMEOUT; i++) { 1451 delay(5000); 1452 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1453 AC_ResetBusy) == 0) 1454 break; 1455 } 1456 1457 if (i == STGE_TIMEOUT) 1458 printf("%s: reset failed to complete\n", 1459 device_xname(sc->sc_dev)); 1460 1461 delay(1000); 1462 } 1463 1464 /* 1465 * stge_init: [ ifnet interface function ] 1466 * 1467 * Initialize the interface. Must be called at splnet(). 1468 */ 1469 static int 1470 stge_init(struct ifnet *ifp) 1471 { 1472 struct stge_softc *sc = ifp->if_softc; 1473 bus_space_tag_t st = sc->sc_st; 1474 bus_space_handle_t sh = sc->sc_sh; 1475 struct stge_descsoft *ds; 1476 int i, error = 0; 1477 1478 /* 1479 * Cancel any pending I/O. 1480 */ 1481 stge_stop(ifp, 0); 1482 1483 /* 1484 * Reset the chip to a known state. 1485 */ 1486 stge_reset(sc); 1487 1488 /* 1489 * Initialize the transmit descriptor ring. 1490 */ 1491 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1492 for (i = 0; i < STGE_NTXDESC; i++) { 1493 sc->sc_txdescs[i].tfd_next = htole64( 1494 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1495 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1496 } 1497 sc->sc_txpending = 0; 1498 sc->sc_txdirty = 0; 1499 sc->sc_txlast = STGE_NTXDESC - 1; 1500 1501 /* 1502 * Initialize the receive descriptor and receive job 1503 * descriptor rings. 1504 */ 1505 for (i = 0; i < STGE_NRXDESC; i++) { 1506 ds = &sc->sc_rxsoft[i]; 1507 if (ds->ds_mbuf == NULL) { 1508 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1509 printf("%s: unable to allocate or map rx " 1510 "buffer %d, error = %d\n", 1511 device_xname(sc->sc_dev), i, error); 1512 /* 1513 * XXX Should attempt to run with fewer receive 1514 * XXX buffers instead of just failing. 1515 */ 1516 stge_rxdrain(sc); 1517 goto out; 1518 } 1519 } else 1520 STGE_INIT_RXDESC(sc, i); 1521 } 1522 sc->sc_rxptr = 0; 1523 sc->sc_rxdiscard = 0; 1524 STGE_RXCHAIN_RESET(sc); 1525 1526 /* Set the station address. */ 1527 for (i = 0; i < 6; i++) 1528 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1529 CLLADDR(ifp->if_sadl)[i]); 1530 1531 /* 1532 * Set the statistics masks. Disable all the RMON stats, 1533 * and disable selected stats in the non-RMON stats registers. 1534 */ 1535 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1536 bus_space_write_4(st, sh, STGE_StatisticsMask, 1537 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1538 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1539 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1540 (1U << 21)); 1541 1542 /* Set up the receive filter. */ 1543 stge_set_filter(sc); 1544 1545 /* 1546 * Give the transmit and receive ring to the chip. 1547 */ 1548 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1549 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1550 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1551 1552 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1553 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1554 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1555 1556 /* 1557 * Initialize the Tx auto-poll period. It's OK to make this number 1558 * large (255 is the max, but we use 127) -- we explicitly kick the 1559 * transmit engine when there's actually a packet. 1560 */ 1561 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1562 1563 /* ..and the Rx auto-poll period. */ 1564 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1565 1566 /* Initialize the Tx start threshold. */ 1567 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1568 1569 /* RX DMA thresholds, from linux */ 1570 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1571 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1572 1573 /* 1574 * Initialize the Rx DMA interrupt control register. We 1575 * request an interrupt after every incoming packet, but 1576 * defer it for 32us (64 * 512 ns). When the number of 1577 * interrupts pending reaches 8, we stop deferring the 1578 * interrupt, and signal it immediately. 1579 */ 1580 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1581 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1582 1583 /* 1584 * Initialize the interrupt mask. 1585 */ 1586 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1587 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1588 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1589 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1590 1591 /* 1592 * Configure the DMA engine. 1593 * XXX Should auto-tune TxBurstLimit. 1594 */ 1595 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1596 DMAC_TxBurstLimit(3)); 1597 1598 /* 1599 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1600 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1601 * empty again. 1602 */ 1603 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1604 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1605 1606 /* 1607 * Set the maximum frame size. 1608 */ 1609 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1610 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1611 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1612 ETHER_VLAN_ENCAP_LEN : 0)); 1613 1614 /* 1615 * Initialize MacCtrl -- do it before setting the media, 1616 * as setting the media will actually program the register. 1617 * 1618 * Note: We have to poke the IFS value before poking 1619 * anything else. 1620 */ 1621 sc->sc_MACCtrl = MC_IFSSelect(0); 1622 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1623 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1624 #ifdef STGE_VLAN_UNTAG 1625 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1626 #endif 1627 1628 if (sc->sc_rev >= 6) { /* >= B.2 */ 1629 /* Multi-frag frame bug work-around. */ 1630 bus_space_write_2(st, sh, STGE_DebugCtrl, 1631 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1632 1633 /* Tx Poll Now bug work-around. */ 1634 bus_space_write_2(st, sh, STGE_DebugCtrl, 1635 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1636 /* XXX ? from linux */ 1637 bus_space_write_2(st, sh, STGE_DebugCtrl, 1638 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1639 } 1640 1641 /* 1642 * Set the current media. 1643 */ 1644 if ((error = ether_mediachange(ifp)) != 0) 1645 goto out; 1646 1647 /* 1648 * Start the one second MII clock. 1649 */ 1650 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1651 1652 /* 1653 * ...all done! 1654 */ 1655 ifp->if_flags |= IFF_RUNNING; 1656 ifp->if_flags &= ~IFF_OACTIVE; 1657 1658 out: 1659 if (error) 1660 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1661 return (error); 1662 } 1663 1664 /* 1665 * stge_drain: 1666 * 1667 * Drain the receive queue. 1668 */ 1669 static void 1670 stge_rxdrain(struct stge_softc *sc) 1671 { 1672 struct stge_descsoft *ds; 1673 int i; 1674 1675 for (i = 0; i < STGE_NRXDESC; i++) { 1676 ds = &sc->sc_rxsoft[i]; 1677 if (ds->ds_mbuf != NULL) { 1678 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1679 ds->ds_mbuf->m_next = NULL; 1680 m_freem(ds->ds_mbuf); 1681 ds->ds_mbuf = NULL; 1682 } 1683 } 1684 } 1685 1686 /* 1687 * stge_stop: [ ifnet interface function ] 1688 * 1689 * Stop transmission on the interface. 1690 */ 1691 static void 1692 stge_stop(struct ifnet *ifp, int disable) 1693 { 1694 struct stge_softc *sc = ifp->if_softc; 1695 struct stge_descsoft *ds; 1696 int i; 1697 1698 /* 1699 * Stop the one second clock. 1700 */ 1701 callout_stop(&sc->sc_tick_ch); 1702 1703 /* Down the MII. */ 1704 mii_down(&sc->sc_mii); 1705 1706 /* 1707 * Disable interrupts. 1708 */ 1709 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1710 1711 /* 1712 * Stop receiver, transmitter, and stats update. 1713 */ 1714 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1715 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1716 1717 /* 1718 * Stop the transmit and receive DMA. 1719 */ 1720 stge_dma_wait(sc); 1721 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1722 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1723 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1724 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1725 1726 /* 1727 * Release any queued transmit buffers. 1728 */ 1729 for (i = 0; i < STGE_NTXDESC; i++) { 1730 ds = &sc->sc_txsoft[i]; 1731 if (ds->ds_mbuf != NULL) { 1732 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1733 m_freem(ds->ds_mbuf); 1734 ds->ds_mbuf = NULL; 1735 } 1736 } 1737 1738 /* 1739 * Mark the interface down and cancel the watchdog timer. 1740 */ 1741 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1742 ifp->if_timer = 0; 1743 1744 if (disable) 1745 stge_rxdrain(sc); 1746 } 1747 1748 static int 1749 stge_eeprom_wait(struct stge_softc *sc) 1750 { 1751 int i; 1752 1753 for (i = 0; i < STGE_TIMEOUT; i++) { 1754 delay(1000); 1755 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1756 EC_EepromBusy) == 0) 1757 return (0); 1758 } 1759 return (1); 1760 } 1761 1762 /* 1763 * stge_read_eeprom: 1764 * 1765 * Read data from the serial EEPROM. 1766 */ 1767 static void 1768 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1769 { 1770 1771 if (stge_eeprom_wait(sc)) 1772 printf("%s: EEPROM failed to come ready\n", 1773 device_xname(sc->sc_dev)); 1774 1775 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1776 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1777 if (stge_eeprom_wait(sc)) 1778 printf("%s: EEPROM read timed out\n", 1779 device_xname(sc->sc_dev)); 1780 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1781 } 1782 1783 /* 1784 * stge_add_rxbuf: 1785 * 1786 * Add a receive buffer to the indicated descriptor. 1787 */ 1788 static int 1789 stge_add_rxbuf(struct stge_softc *sc, int idx) 1790 { 1791 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1792 struct mbuf *m; 1793 int error; 1794 1795 MGETHDR(m, M_DONTWAIT, MT_DATA); 1796 if (m == NULL) 1797 return (ENOBUFS); 1798 1799 MCLGET(m, M_DONTWAIT); 1800 if ((m->m_flags & M_EXT) == 0) { 1801 m_freem(m); 1802 return (ENOBUFS); 1803 } 1804 1805 m->m_data = m->m_ext.ext_buf + 2; 1806 m->m_len = MCLBYTES - 2; 1807 1808 if (ds->ds_mbuf != NULL) 1809 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1810 1811 ds->ds_mbuf = m; 1812 1813 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1814 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1815 if (error) { 1816 printf("%s: can't load rx DMA map %d, error = %d\n", 1817 device_xname(sc->sc_dev), idx, error); 1818 panic("stge_add_rxbuf"); /* XXX */ 1819 } 1820 1821 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1822 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1823 1824 STGE_INIT_RXDESC(sc, idx); 1825 1826 return (0); 1827 } 1828 1829 /* 1830 * stge_set_filter: 1831 * 1832 * Set up the receive filter. 1833 */ 1834 static void 1835 stge_set_filter(struct stge_softc *sc) 1836 { 1837 struct ethercom *ec = &sc->sc_ethercom; 1838 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1839 struct ether_multi *enm; 1840 struct ether_multistep step; 1841 uint32_t crc; 1842 uint32_t mchash[2]; 1843 1844 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1845 if (ifp->if_flags & IFF_BROADCAST) 1846 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1847 1848 /* XXX: ST1023 only works in promiscuous mode */ 1849 if (sc->sc_stge1023) 1850 ifp->if_flags |= IFF_PROMISC; 1851 1852 if (ifp->if_flags & IFF_PROMISC) { 1853 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1854 goto allmulti; 1855 } 1856 1857 /* 1858 * Set up the multicast address filter by passing all multicast 1859 * addresses through a CRC generator, and then using the low-order 1860 * 6 bits as an index into the 64 bit multicast hash table. The 1861 * high order bits select the register, while the rest of the bits 1862 * select the bit within the register. 1863 */ 1864 1865 memset(mchash, 0, sizeof(mchash)); 1866 1867 ETHER_FIRST_MULTI(step, ec, enm); 1868 if (enm == NULL) 1869 goto done; 1870 1871 while (enm != NULL) { 1872 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1873 /* 1874 * We must listen to a range of multicast addresses. 1875 * For now, just accept all multicasts, rather than 1876 * trying to set only those filter bits needed to match 1877 * the range. (At this time, the only use of address 1878 * ranges is for IP multicast routing, for which the 1879 * range is big enough to require all bits set.) 1880 */ 1881 goto allmulti; 1882 } 1883 1884 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1885 1886 /* Just want the 6 least significant bits. */ 1887 crc &= 0x3f; 1888 1889 /* Set the corresponding bit in the hash table. */ 1890 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1891 1892 ETHER_NEXT_MULTI(step, enm); 1893 } 1894 1895 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1896 1897 ifp->if_flags &= ~IFF_ALLMULTI; 1898 goto done; 1899 1900 allmulti: 1901 ifp->if_flags |= IFF_ALLMULTI; 1902 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1903 1904 done: 1905 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1906 /* 1907 * Program the multicast hash table. 1908 */ 1909 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1910 mchash[0]); 1911 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1912 mchash[1]); 1913 } 1914 1915 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1916 sc->sc_ReceiveMode); 1917 } 1918 1919 /* 1920 * stge_mii_readreg: [mii interface function] 1921 * 1922 * Read a PHY register on the MII of the TC9021. 1923 */ 1924 static int 1925 stge_mii_readreg(device_t self, int phy, int reg) 1926 { 1927 1928 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1929 } 1930 1931 /* 1932 * stge_mii_writereg: [mii interface function] 1933 * 1934 * Write a PHY register on the MII of the TC9021. 1935 */ 1936 static void 1937 stge_mii_writereg(device_t self, int phy, int reg, int val) 1938 { 1939 1940 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1941 } 1942 1943 /* 1944 * stge_mii_statchg: [mii interface function] 1945 * 1946 * Callback from MII layer when media changes. 1947 */ 1948 static void 1949 stge_mii_statchg(device_t self) 1950 { 1951 struct stge_softc *sc = device_private(self); 1952 1953 if (sc->sc_mii.mii_media_active & IFM_FDX) 1954 sc->sc_MACCtrl |= MC_DuplexSelect; 1955 else 1956 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1957 1958 /* XXX 802.1x flow-control? */ 1959 1960 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1961 } 1962 1963 /* 1964 * sste_mii_bitbang_read: [mii bit-bang interface function] 1965 * 1966 * Read the MII serial port for the MII bit-bang module. 1967 */ 1968 static uint32_t 1969 stge_mii_bitbang_read(device_t self) 1970 { 1971 struct stge_softc *sc = device_private(self); 1972 1973 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1974 } 1975 1976 /* 1977 * stge_mii_bitbang_write: [mii big-bang interface function] 1978 * 1979 * Write the MII serial port for the MII bit-bang module. 1980 */ 1981 static void 1982 stge_mii_bitbang_write(device_t self, uint32_t val) 1983 { 1984 struct stge_softc *sc = device_private(self); 1985 1986 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1987 val | sc->sc_PhyCtrl); 1988 } 1989