1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* #define STGE_CU_BUG 1 */ 86 #define STGE_VLAN_UNTAG 1 87 /* #define STGE_VLAN_CFI 1 */ 88 89 /* 90 * Transmit descriptor list size. 91 */ 92 #define STGE_NTXDESC 256 93 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 94 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 95 96 /* 97 * Receive descriptor list size. 98 */ 99 #define STGE_NRXDESC 256 100 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 101 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 102 103 /* 104 * Only interrupt every N frames. Must be a power-of-two. 105 */ 106 #define STGE_TXINTR_SPACING 16 107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 108 109 /* 110 * Control structures are DMA'd to the TC9021 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct stge_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 124 }; 125 126 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit and receive jobs. 132 */ 133 struct stge_descsoft { 134 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t ds_dmamap; /* our DMA map */ 136 }; 137 138 /* 139 * Software state per device. 140 */ 141 struct stge_softc { 142 struct device sc_dev; /* generic device information */ 143 bus_space_tag_t sc_st; /* bus space tag */ 144 bus_space_handle_t sc_sh; /* bus space handle */ 145 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 146 struct ethercom sc_ethercom; /* ethernet common data */ 147 void *sc_sdhook; /* shutdown hook */ 148 int sc_rev; /* silicon revision */ 149 150 void *sc_ih; /* interrupt cookie */ 151 152 struct mii_data sc_mii; /* MII/media information */ 153 154 struct callout sc_tick_ch; /* tick callout */ 155 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 163 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct stge_control_data *sc_control_data; 169 #define sc_txdescs sc_control_data->scd_txdescs 170 #define sc_rxdescs sc_control_data->scd_rxdescs 171 172 #ifdef STGE_EVENT_COUNTERS 173 /* 174 * Event counters. 175 */ 176 struct evcnt sc_ev_txstall; /* Tx stalled */ 177 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 178 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 179 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 180 181 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 182 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 183 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 184 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 185 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 186 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 187 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 188 189 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 190 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 191 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 192 193 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 194 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 195 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 196 #endif /* STGE_EVENT_COUNTERS */ 197 198 int sc_txpending; /* number of Tx requests pending */ 199 int sc_txdirty; /* first dirty Tx descriptor */ 200 int sc_txlast; /* last used Tx descriptor */ 201 202 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 203 int sc_rxdiscard; 204 int sc_rxlen; 205 struct mbuf *sc_rxhead; 206 struct mbuf *sc_rxtail; 207 struct mbuf **sc_rxtailp; 208 209 int sc_txthresh; /* Tx threshold */ 210 uint32_t sc_usefiber:1; /* if we're fiber */ 211 uint32_t sc_stge1023:1; /* are we a 1023 */ 212 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 213 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 214 uint16_t sc_IntEnable; /* prototype IntEnable register */ 215 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 216 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 217 }; 218 219 #define STGE_RXCHAIN_RESET(sc) \ 220 do { \ 221 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 222 *(sc)->sc_rxtailp = NULL; \ 223 (sc)->sc_rxlen = 0; \ 224 } while (/*CONSTCOND*/0) 225 226 #define STGE_RXCHAIN_LINK(sc, m) \ 227 do { \ 228 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 229 (sc)->sc_rxtailp = &(m)->m_next; \ 230 } while (/*CONSTCOND*/0) 231 232 #ifdef STGE_EVENT_COUNTERS 233 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 234 #else 235 #define STGE_EVCNT_INCR(ev) /* nothing */ 236 #endif 237 238 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 239 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 240 241 #define STGE_CDTXSYNC(sc, x, ops) \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 243 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 244 245 #define STGE_CDRXSYNC(sc, x, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 248 249 #define STGE_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 252 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 253 \ 254 /* \ 255 * Note: We scoot the packet forward 2 bytes in the buffer \ 256 * so that the payload after the Ethernet header is aligned \ 257 * to a 4-byte boundary. \ 258 */ \ 259 __rfd->rfd_frag.frag_word0 = \ 260 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 261 FRAG_LEN(MCLBYTES - 2)); \ 262 __rfd->rfd_next = \ 263 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 264 __rfd->rfd_status = 0; \ 265 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 266 } while (/*CONSTCOND*/0) 267 268 #define STGE_TIMEOUT 1000 269 270 static void stge_start(struct ifnet *); 271 static void stge_watchdog(struct ifnet *); 272 static int stge_ioctl(struct ifnet *, u_long, caddr_t); 273 static int stge_init(struct ifnet *); 274 static void stge_stop(struct ifnet *, int); 275 276 static void stge_shutdown(void *); 277 278 static void stge_reset(struct stge_softc *); 279 static void stge_rxdrain(struct stge_softc *); 280 static int stge_add_rxbuf(struct stge_softc *, int); 281 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 282 static void stge_tick(void *); 283 284 static void stge_stats_update(struct stge_softc *); 285 286 static void stge_set_filter(struct stge_softc *); 287 288 static int stge_intr(void *); 289 static void stge_txintr(struct stge_softc *); 290 static void stge_rxintr(struct stge_softc *); 291 292 static int stge_mii_readreg(struct device *, int, int); 293 static void stge_mii_writereg(struct device *, int, int, int); 294 static void stge_mii_statchg(struct device *); 295 296 static int stge_mediachange(struct ifnet *); 297 static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 298 299 static int stge_match(struct device *, struct cfdata *, void *); 300 static void stge_attach(struct device *, struct device *, void *); 301 302 int stge_copy_small = 0; 303 304 CFATTACH_DECL(stge, sizeof(struct stge_softc), 305 stge_match, stge_attach, NULL, NULL); 306 307 static uint32_t stge_mii_bitbang_read(struct device *); 308 static void stge_mii_bitbang_write(struct device *, uint32_t); 309 310 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 311 stge_mii_bitbang_read, 312 stge_mii_bitbang_write, 313 { 314 PC_MgmtData, /* MII_BIT_MDO */ 315 PC_MgmtData, /* MII_BIT_MDI */ 316 PC_MgmtClk, /* MII_BIT_MDC */ 317 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 318 0, /* MII_BIT_DIR_PHY_HOST */ 319 } 320 }; 321 322 /* 323 * Devices supported by this driver. 324 */ 325 static const struct stge_product { 326 pci_vendor_id_t stge_vendor; 327 pci_product_id_t stge_product; 328 const char *stge_name; 329 } stge_products[] = { 330 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 331 "Sundance ST-1023 Gigabit Ethernet" }, 332 333 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 334 "Sundance ST-2021 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 337 "Tamarack TC9021 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 340 "Tamarack TC9021 Gigabit Ethernet" }, 341 342 /* 343 * The Sundance sample boards use the Sundance vendor ID, 344 * but the Tamarack product ID. 345 */ 346 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 347 "Sundance TC9021 Gigabit Ethernet" }, 348 349 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 350 "Sundance TC9021 Gigabit Ethernet" }, 351 352 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 353 "D-Link DL-4000 Gigabit Ethernet" }, 354 355 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 356 "Antares Gigabit Ethernet" }, 357 358 { 0, 0, 359 NULL }, 360 }; 361 362 static const struct stge_product * 363 stge_lookup(const struct pci_attach_args *pa) 364 { 365 const struct stge_product *sp; 366 367 for (sp = stge_products; sp->stge_name != NULL; sp++) { 368 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 369 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 370 return (sp); 371 } 372 return (NULL); 373 } 374 375 static int 376 stge_match(struct device *parent, struct cfdata *cf, void *aux) 377 { 378 struct pci_attach_args *pa = aux; 379 380 if (stge_lookup(pa) != NULL) 381 return (1); 382 383 return (0); 384 } 385 386 static void 387 stge_attach(struct device *parent, struct device *self, void *aux) 388 { 389 struct stge_softc *sc = (struct stge_softc *) self; 390 struct pci_attach_args *pa = aux; 391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 392 pci_chipset_tag_t pc = pa->pa_pc; 393 pci_intr_handle_t ih; 394 const char *intrstr = NULL; 395 bus_space_tag_t iot, memt; 396 bus_space_handle_t ioh, memh; 397 bus_dma_segment_t seg; 398 int ioh_valid, memh_valid; 399 int i, rseg, error; 400 const struct stge_product *sp; 401 pcireg_t pmode; 402 uint8_t enaddr[ETHER_ADDR_LEN]; 403 int pmreg; 404 405 callout_init(&sc->sc_tick_ch); 406 407 sp = stge_lookup(pa); 408 if (sp == NULL) { 409 printf("\n"); 410 panic("ste_attach: impossible"); 411 } 412 413 sc->sc_rev = PCI_REVISION(pa->pa_class); 414 415 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 416 417 /* 418 * Map the device. 419 */ 420 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 421 PCI_MAPREG_TYPE_IO, 0, 422 &iot, &ioh, NULL, NULL) == 0); 423 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 424 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 425 &memt, &memh, NULL, NULL) == 0); 426 427 if (memh_valid) { 428 sc->sc_st = memt; 429 sc->sc_sh = memh; 430 } else if (ioh_valid) { 431 sc->sc_st = iot; 432 sc->sc_sh = ioh; 433 } else { 434 printf("%s: unable to map device registers\n", 435 sc->sc_dev.dv_xname); 436 return; 437 } 438 439 sc->sc_dmat = pa->pa_dmat; 440 441 /* Enable bus mastering. */ 442 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 443 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 444 PCI_COMMAND_MASTER_ENABLE); 445 446 /* Get it out of power save mode if needed. */ 447 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 448 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 449 PCI_PMCSR_STATE_MASK; 450 if (pmode == PCI_PMCSR_STATE_D3) { 451 /* 452 * The card has lost all configuration data in 453 * this state, so punt. 454 */ 455 printf("%s: unable to wake up from power state D3\n", 456 sc->sc_dev.dv_xname); 457 return; 458 } 459 if (pmode != 0) { 460 printf("%s: waking up from power state D%d\n", 461 sc->sc_dev.dv_xname, pmode); 462 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 463 PCI_PMCSR_STATE_D0); 464 } 465 } 466 467 /* 468 * Map and establish our interrupt. 469 */ 470 if (pci_intr_map(pa, &ih)) { 471 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 472 return; 473 } 474 intrstr = pci_intr_string(pc, ih); 475 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 476 if (sc->sc_ih == NULL) { 477 printf("%s: unable to establish interrupt", 478 sc->sc_dev.dv_xname); 479 if (intrstr != NULL) 480 printf(" at %s", intrstr); 481 printf("\n"); 482 return; 483 } 484 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 485 486 /* 487 * Allocate the control data structures, and create and load the 488 * DMA map for it. 489 */ 490 if ((error = bus_dmamem_alloc(sc->sc_dmat, 491 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 492 0)) != 0) { 493 printf("%s: unable to allocate control data, error = %d\n", 494 sc->sc_dev.dv_xname, error); 495 goto fail_0; 496 } 497 498 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 499 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 500 BUS_DMA_COHERENT)) != 0) { 501 printf("%s: unable to map control data, error = %d\n", 502 sc->sc_dev.dv_xname, error); 503 goto fail_1; 504 } 505 506 if ((error = bus_dmamap_create(sc->sc_dmat, 507 sizeof(struct stge_control_data), 1, 508 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 509 printf("%s: unable to create control data DMA map, " 510 "error = %d\n", sc->sc_dev.dv_xname, error); 511 goto fail_2; 512 } 513 514 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 515 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 516 0)) != 0) { 517 printf("%s: unable to load control data DMA map, error = %d\n", 518 sc->sc_dev.dv_xname, error); 519 goto fail_3; 520 } 521 522 /* 523 * Create the transmit buffer DMA maps. Note that rev B.3 524 * and earlier seem to have a bug regarding multi-fragment 525 * packets. We need to limit the number of Tx segments on 526 * such chips to 1. 527 */ 528 for (i = 0; i < STGE_NTXDESC; i++) { 529 if ((error = bus_dmamap_create(sc->sc_dmat, 530 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 531 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 532 printf("%s: unable to create tx DMA map %d, " 533 "error = %d\n", sc->sc_dev.dv_xname, i, error); 534 goto fail_4; 535 } 536 } 537 538 /* 539 * Create the receive buffer DMA maps. 540 */ 541 for (i = 0; i < STGE_NRXDESC; i++) { 542 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 543 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 544 printf("%s: unable to create rx DMA map %d, " 545 "error = %d\n", sc->sc_dev.dv_xname, i, error); 546 goto fail_5; 547 } 548 sc->sc_rxsoft[i].ds_mbuf = NULL; 549 } 550 551 /* 552 * Determine if we're copper or fiber. It affects how we 553 * reset the card. 554 */ 555 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 556 AC_PhyMedia) 557 sc->sc_usefiber = 1; 558 else 559 sc->sc_usefiber = 0; 560 561 /* 562 * Reset the chip to a known state. 563 */ 564 stge_reset(sc); 565 566 /* 567 * Reading the station address from the EEPROM doesn't seem 568 * to work, at least on my sample boards. Instead, since 569 * the reset sequence does AutoInit, read it from the station 570 * address registers. For Sundance 1023 you can only read it 571 * from EEPROM. 572 */ 573 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 574 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 575 STGE_StationAddress0) & 0xff; 576 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 577 STGE_StationAddress0) >> 8; 578 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 579 STGE_StationAddress1) & 0xff; 580 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 581 STGE_StationAddress1) >> 8; 582 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 583 STGE_StationAddress2) & 0xff; 584 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 585 STGE_StationAddress2) >> 8; 586 sc->sc_stge1023 = 0; 587 } else { 588 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 589 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 590 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 591 &myaddr[i]); 592 myaddr[i] = le16toh(myaddr[i]); 593 } 594 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 595 sc->sc_stge1023 = 1; 596 } 597 598 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 599 ether_sprintf(enaddr)); 600 601 /* 602 * Read some important bits from the PhyCtrl register. 603 */ 604 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 605 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 606 607 /* 608 * Initialize our media structures and probe the MII. 609 */ 610 sc->sc_mii.mii_ifp = ifp; 611 sc->sc_mii.mii_readreg = stge_mii_readreg; 612 sc->sc_mii.mii_writereg = stge_mii_writereg; 613 sc->sc_mii.mii_statchg = stge_mii_statchg; 614 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, stge_mediachange, 615 stge_mediastatus); 616 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 617 MII_OFFSET_ANY, MIIF_DOPAUSE); 618 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 619 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 620 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 621 } else 622 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 623 624 ifp = &sc->sc_ethercom.ec_if; 625 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 626 ifp->if_softc = sc; 627 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 628 ifp->if_ioctl = stge_ioctl; 629 ifp->if_start = stge_start; 630 ifp->if_watchdog = stge_watchdog; 631 ifp->if_init = stge_init; 632 ifp->if_stop = stge_stop; 633 IFQ_SET_READY(&ifp->if_snd); 634 635 /* 636 * The manual recommends disabling early transmit, so we 637 * do. It's disabled anyway, if using IP checksumming, 638 * since the entire packet must be in the FIFO in order 639 * for the chip to perform the checksum. 640 */ 641 sc->sc_txthresh = 0x0fff; 642 643 /* 644 * Disable MWI if the PCI layer tells us to. 645 */ 646 sc->sc_DMACtrl = 0; 647 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 648 sc->sc_DMACtrl |= DMAC_MWIDisable; 649 650 /* 651 * We can support 802.1Q VLAN-sized frames and jumbo 652 * Ethernet frames. 653 * 654 * XXX Figure out how to do hw-assisted VLAN tagging in 655 * XXX a reasonable way on this chip. 656 */ 657 sc->sc_ethercom.ec_capabilities |= 658 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 659 ETHERCAP_VLAN_HWTAGGING; 660 661 /* 662 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 663 */ 664 sc->sc_ethercom.ec_if.if_capabilities |= 665 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 666 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 667 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 668 669 /* 670 * Attach the interface. 671 */ 672 if_attach(ifp); 673 ether_ifattach(ifp, enaddr); 674 675 #ifdef STGE_EVENT_COUNTERS 676 /* 677 * Attach event counters. 678 */ 679 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 680 NULL, sc->sc_dev.dv_xname, "txstall"); 681 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 682 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 683 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 684 NULL, sc->sc_dev.dv_xname, "txindintr"); 685 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 686 NULL, sc->sc_dev.dv_xname, "rxintr"); 687 688 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 689 NULL, sc->sc_dev.dv_xname, "txseg1"); 690 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 691 NULL, sc->sc_dev.dv_xname, "txseg2"); 692 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 693 NULL, sc->sc_dev.dv_xname, "txseg3"); 694 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 695 NULL, sc->sc_dev.dv_xname, "txseg4"); 696 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 697 NULL, sc->sc_dev.dv_xname, "txseg5"); 698 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 699 NULL, sc->sc_dev.dv_xname, "txsegmore"); 700 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 701 NULL, sc->sc_dev.dv_xname, "txcopy"); 702 703 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 704 NULL, sc->sc_dev.dv_xname, "rxipsum"); 705 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 706 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 707 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 708 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 709 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 710 NULL, sc->sc_dev.dv_xname, "txipsum"); 711 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 712 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 713 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 714 NULL, sc->sc_dev.dv_xname, "txudpsum"); 715 #endif /* STGE_EVENT_COUNTERS */ 716 717 /* 718 * Make sure the interface is shutdown during reboot. 719 */ 720 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 721 if (sc->sc_sdhook == NULL) 722 printf("%s: WARNING: unable to establish shutdown hook\n", 723 sc->sc_dev.dv_xname); 724 return; 725 726 /* 727 * Free any resources we've allocated during the failed attach 728 * attempt. Do this in reverse order and fall through. 729 */ 730 fail_5: 731 for (i = 0; i < STGE_NRXDESC; i++) { 732 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 733 bus_dmamap_destroy(sc->sc_dmat, 734 sc->sc_rxsoft[i].ds_dmamap); 735 } 736 fail_4: 737 for (i = 0; i < STGE_NTXDESC; i++) { 738 if (sc->sc_txsoft[i].ds_dmamap != NULL) 739 bus_dmamap_destroy(sc->sc_dmat, 740 sc->sc_txsoft[i].ds_dmamap); 741 } 742 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 743 fail_3: 744 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 745 fail_2: 746 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 747 sizeof(struct stge_control_data)); 748 fail_1: 749 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 750 fail_0: 751 return; 752 } 753 754 /* 755 * stge_shutdown: 756 * 757 * Make sure the interface is stopped at reboot time. 758 */ 759 static void 760 stge_shutdown(void *arg) 761 { 762 struct stge_softc *sc = arg; 763 764 stge_stop(&sc->sc_ethercom.ec_if, 1); 765 } 766 767 static void 768 stge_dma_wait(struct stge_softc *sc) 769 { 770 int i; 771 772 for (i = 0; i < STGE_TIMEOUT; i++) { 773 delay(2); 774 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 775 DMAC_TxDMAInProg) == 0) 776 break; 777 } 778 779 if (i == STGE_TIMEOUT) 780 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 781 } 782 783 /* 784 * stge_start: [ifnet interface function] 785 * 786 * Start packet transmission on the interface. 787 */ 788 static void 789 stge_start(struct ifnet *ifp) 790 { 791 struct stge_softc *sc = ifp->if_softc; 792 struct mbuf *m0; 793 struct stge_descsoft *ds; 794 struct stge_tfd *tfd; 795 bus_dmamap_t dmamap; 796 int error, firsttx, nexttx, opending, seg, totlen; 797 uint64_t csum_flags; 798 799 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 800 return; 801 802 /* 803 * Remember the previous number of pending transmissions 804 * and the first descriptor we will use. 805 */ 806 opending = sc->sc_txpending; 807 firsttx = STGE_NEXTTX(sc->sc_txlast); 808 809 /* 810 * Loop through the send queue, setting up transmit descriptors 811 * until we drain the queue, or use up all available transmit 812 * descriptors. 813 */ 814 for (;;) { 815 struct m_tag *mtag; 816 uint64_t tfc; 817 818 /* 819 * Grab a packet off the queue. 820 */ 821 IFQ_POLL(&ifp->if_snd, m0); 822 if (m0 == NULL) 823 break; 824 825 /* 826 * Leave one unused descriptor at the end of the 827 * list to prevent wrapping completely around. 828 */ 829 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 830 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 831 break; 832 } 833 834 /* 835 * See if we have any VLAN stuff. 836 */ 837 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 838 839 /* 840 * Get the last and next available transmit descriptor. 841 */ 842 nexttx = STGE_NEXTTX(sc->sc_txlast); 843 tfd = &sc->sc_txdescs[nexttx]; 844 ds = &sc->sc_txsoft[nexttx]; 845 846 dmamap = ds->ds_dmamap; 847 848 /* 849 * Load the DMA map. If this fails, the packet either 850 * didn't fit in the alloted number of segments, or we 851 * were short on resources. For the too-many-segments 852 * case, we simply report an error and drop the packet, 853 * since we can't sanely copy a jumbo packet to a single 854 * buffer. 855 */ 856 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 857 BUS_DMA_NOWAIT); 858 if (error) { 859 if (error == EFBIG) { 860 printf("%s: Tx packet consumes too many " 861 "DMA segments, dropping...\n", 862 sc->sc_dev.dv_xname); 863 IFQ_DEQUEUE(&ifp->if_snd, m0); 864 m_freem(m0); 865 continue; 866 } 867 /* 868 * Short on resources, just stop for now. 869 */ 870 break; 871 } 872 873 IFQ_DEQUEUE(&ifp->if_snd, m0); 874 875 /* 876 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 877 */ 878 879 /* Sync the DMA map. */ 880 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 881 BUS_DMASYNC_PREWRITE); 882 883 /* Initialize the fragment list. */ 884 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 885 tfd->tfd_frags[seg].frag_word0 = 886 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 887 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 888 totlen += dmamap->dm_segs[seg].ds_len; 889 } 890 891 #ifdef STGE_EVENT_COUNTERS 892 switch (dmamap->dm_nsegs) { 893 case 1: 894 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 895 break; 896 case 2: 897 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 898 break; 899 case 3: 900 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 901 break; 902 case 4: 903 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 904 break; 905 case 5: 906 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 907 break; 908 default: 909 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 910 break; 911 } 912 #endif /* STGE_EVENT_COUNTERS */ 913 914 /* 915 * Initialize checksumming flags in the descriptor. 916 * Byte-swap constants so the compiler can optimize. 917 */ 918 csum_flags = 0; 919 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 920 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 921 csum_flags |= TFD_IPChecksumEnable; 922 } 923 924 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 925 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 926 csum_flags |= TFD_TCPChecksumEnable; 927 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 928 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 929 csum_flags |= TFD_UDPChecksumEnable; 930 } 931 932 /* 933 * Initialize the descriptor and give it to the chip. 934 * Check to see if we have a VLAN tag to insert. 935 */ 936 937 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 938 TFD_FragCount(seg) | csum_flags | 939 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 940 TFD_TxDMAIndicate : 0); 941 if (mtag) { 942 #if 0 943 struct ether_header *eh = 944 mtod(m0, struct ether_header *); 945 u_int16_t etype = ntohs(eh->ether_type); 946 printf("%s: xmit (tag %d) etype %x\n", 947 ifp->if_xname, *mtod(n, int *), etype); 948 #endif 949 tfc |= TFD_VLANTagInsert | 950 #ifdef STGE_VLAN_CFI 951 TFD_CFI | 952 #endif 953 TFD_VID(VLAN_TAG_VALUE(mtag)); 954 } 955 tfd->tfd_control = htole64(tfc); 956 957 /* Sync the descriptor. */ 958 STGE_CDTXSYNC(sc, nexttx, 959 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 960 961 /* 962 * Kick the transmit DMA logic. 963 */ 964 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 965 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 966 967 /* 968 * Store a pointer to the packet so we can free it later. 969 */ 970 ds->ds_mbuf = m0; 971 972 /* Advance the tx pointer. */ 973 sc->sc_txpending++; 974 sc->sc_txlast = nexttx; 975 976 #if NBPFILTER > 0 977 /* 978 * Pass the packet to any BPF listeners. 979 */ 980 if (ifp->if_bpf) 981 bpf_mtap(ifp->if_bpf, m0); 982 #endif /* NBPFILTER > 0 */ 983 } 984 985 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 986 /* No more slots left; notify upper layer. */ 987 ifp->if_flags |= IFF_OACTIVE; 988 } 989 990 if (sc->sc_txpending != opending) { 991 /* 992 * We enqueued packets. If the transmitter was idle, 993 * reset the txdirty pointer. 994 */ 995 if (opending == 0) 996 sc->sc_txdirty = firsttx; 997 998 /* Set a watchdog timer in case the chip flakes out. */ 999 ifp->if_timer = 5; 1000 } 1001 } 1002 1003 /* 1004 * stge_watchdog: [ifnet interface function] 1005 * 1006 * Watchdog timer handler. 1007 */ 1008 static void 1009 stge_watchdog(struct ifnet *ifp) 1010 { 1011 struct stge_softc *sc = ifp->if_softc; 1012 1013 /* 1014 * Sweep up first, since we don't interrupt every frame. 1015 */ 1016 stge_txintr(sc); 1017 if (sc->sc_txpending != 0) { 1018 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1019 ifp->if_oerrors++; 1020 1021 (void) stge_init(ifp); 1022 1023 /* Try to get more packets going. */ 1024 stge_start(ifp); 1025 } 1026 } 1027 1028 /* 1029 * stge_ioctl: [ifnet interface function] 1030 * 1031 * Handle control requests from the operator. 1032 */ 1033 static int 1034 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1035 { 1036 struct stge_softc *sc = ifp->if_softc; 1037 struct ifreq *ifr = (struct ifreq *)data; 1038 int s, error; 1039 1040 s = splnet(); 1041 1042 switch (cmd) { 1043 case SIOCSIFMEDIA: 1044 case SIOCGIFMEDIA: 1045 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1046 break; 1047 1048 default: 1049 error = ether_ioctl(ifp, cmd, data); 1050 if (error == ENETRESET) { 1051 /* 1052 * Multicast list has changed; set the hardware filter 1053 * accordingly. 1054 */ 1055 if (ifp->if_flags & IFF_RUNNING) 1056 stge_set_filter(sc); 1057 error = 0; 1058 } 1059 break; 1060 } 1061 1062 /* Try to get more packets going. */ 1063 stge_start(ifp); 1064 1065 splx(s); 1066 return (error); 1067 } 1068 1069 /* 1070 * stge_intr: 1071 * 1072 * Interrupt service routine. 1073 */ 1074 static int 1075 stge_intr(void *arg) 1076 { 1077 struct stge_softc *sc = arg; 1078 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1079 uint32_t txstat; 1080 int wantinit; 1081 uint16_t isr; 1082 1083 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1084 IS_InterruptStatus) == 0) 1085 return (0); 1086 1087 for (wantinit = 0; wantinit == 0;) { 1088 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1089 if ((isr & sc->sc_IntEnable) == 0) 1090 break; 1091 1092 /* Host interface errors. */ 1093 if (isr & IS_HostError) { 1094 printf("%s: Host interface error\n", 1095 sc->sc_dev.dv_xname); 1096 wantinit = 1; 1097 continue; 1098 } 1099 1100 /* Receive interrupts. */ 1101 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1102 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1103 stge_rxintr(sc); 1104 if (isr & IS_RFDListEnd) { 1105 printf("%s: receive ring overflow\n", 1106 sc->sc_dev.dv_xname); 1107 /* 1108 * XXX Should try to recover from this 1109 * XXX more gracefully. 1110 */ 1111 wantinit = 1; 1112 } 1113 } 1114 1115 /* Transmit interrupts. */ 1116 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1117 #ifdef STGE_EVENT_COUNTERS 1118 if (isr & IS_TxDMAComplete) 1119 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1120 #endif 1121 stge_txintr(sc); 1122 } 1123 1124 /* Statistics overflow. */ 1125 if (isr & IS_UpdateStats) 1126 stge_stats_update(sc); 1127 1128 /* Transmission errors. */ 1129 if (isr & IS_TxComplete) { 1130 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1131 for (;;) { 1132 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1133 STGE_TxStatus); 1134 if ((txstat & TS_TxComplete) == 0) 1135 break; 1136 if (txstat & TS_TxUnderrun) { 1137 sc->sc_txthresh++; 1138 if (sc->sc_txthresh > 0x0fff) 1139 sc->sc_txthresh = 0x0fff; 1140 printf("%s: transmit underrun, new " 1141 "threshold: %d bytes\n", 1142 sc->sc_dev.dv_xname, 1143 sc->sc_txthresh << 5); 1144 } 1145 if (txstat & TS_MaxCollisions) 1146 printf("%s: excessive collisions\n", 1147 sc->sc_dev.dv_xname); 1148 } 1149 wantinit = 1; 1150 } 1151 1152 } 1153 1154 if (wantinit) 1155 stge_init(ifp); 1156 1157 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1158 sc->sc_IntEnable); 1159 1160 /* Try to get more packets going. */ 1161 stge_start(ifp); 1162 1163 return (1); 1164 } 1165 1166 /* 1167 * stge_txintr: 1168 * 1169 * Helper; handle transmit interrupts. 1170 */ 1171 static void 1172 stge_txintr(struct stge_softc *sc) 1173 { 1174 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1175 struct stge_descsoft *ds; 1176 uint64_t control; 1177 int i; 1178 1179 ifp->if_flags &= ~IFF_OACTIVE; 1180 1181 /* 1182 * Go through our Tx list and free mbufs for those 1183 * frames which have been transmitted. 1184 */ 1185 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1186 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1187 ds = &sc->sc_txsoft[i]; 1188 1189 STGE_CDTXSYNC(sc, i, 1190 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1191 1192 control = le64toh(sc->sc_txdescs[i].tfd_control); 1193 if ((control & TFD_TFDDone) == 0) 1194 break; 1195 1196 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1197 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1198 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1199 m_freem(ds->ds_mbuf); 1200 ds->ds_mbuf = NULL; 1201 } 1202 1203 /* Update the dirty transmit buffer pointer. */ 1204 sc->sc_txdirty = i; 1205 1206 /* 1207 * If there are no more pending transmissions, cancel the watchdog 1208 * timer. 1209 */ 1210 if (sc->sc_txpending == 0) 1211 ifp->if_timer = 0; 1212 } 1213 1214 /* 1215 * stge_rxintr: 1216 * 1217 * Helper; handle receive interrupts. 1218 */ 1219 static void 1220 stge_rxintr(struct stge_softc *sc) 1221 { 1222 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1223 struct stge_descsoft *ds; 1224 struct mbuf *m, *tailm; 1225 uint64_t status; 1226 int i, len; 1227 1228 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1229 ds = &sc->sc_rxsoft[i]; 1230 1231 STGE_CDRXSYNC(sc, i, 1232 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1233 1234 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1235 1236 if ((status & RFD_RFDDone) == 0) 1237 break; 1238 1239 if (__predict_false(sc->sc_rxdiscard)) { 1240 STGE_INIT_RXDESC(sc, i); 1241 if (status & RFD_FrameEnd) { 1242 /* Reset our state. */ 1243 sc->sc_rxdiscard = 0; 1244 } 1245 continue; 1246 } 1247 1248 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1249 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1250 1251 m = ds->ds_mbuf; 1252 1253 /* 1254 * Add a new receive buffer to the ring. 1255 */ 1256 if (stge_add_rxbuf(sc, i) != 0) { 1257 /* 1258 * Failed, throw away what we've done so 1259 * far, and discard the rest of the packet. 1260 */ 1261 ifp->if_ierrors++; 1262 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1263 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1264 STGE_INIT_RXDESC(sc, i); 1265 if ((status & RFD_FrameEnd) == 0) 1266 sc->sc_rxdiscard = 1; 1267 if (sc->sc_rxhead != NULL) 1268 m_freem(sc->sc_rxhead); 1269 STGE_RXCHAIN_RESET(sc); 1270 continue; 1271 } 1272 1273 #ifdef DIAGNOSTIC 1274 if (status & RFD_FrameStart) { 1275 KASSERT(sc->sc_rxhead == NULL); 1276 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1277 } 1278 #endif 1279 1280 STGE_RXCHAIN_LINK(sc, m); 1281 1282 /* 1283 * If this is not the end of the packet, keep 1284 * looking. 1285 */ 1286 if ((status & RFD_FrameEnd) == 0) { 1287 sc->sc_rxlen += m->m_len; 1288 continue; 1289 } 1290 1291 /* 1292 * Okay, we have the entire packet now... 1293 */ 1294 *sc->sc_rxtailp = NULL; 1295 m = sc->sc_rxhead; 1296 tailm = sc->sc_rxtail; 1297 1298 STGE_RXCHAIN_RESET(sc); 1299 1300 /* 1301 * If the packet had an error, drop it. Note we 1302 * count the error later in the periodic stats update. 1303 */ 1304 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1305 RFD_RxAlignmentError | RFD_RxFCSError | 1306 RFD_RxLengthError)) { 1307 m_freem(m); 1308 continue; 1309 } 1310 1311 /* 1312 * No errors. 1313 * 1314 * Note we have configured the chip to not include 1315 * the CRC at the end of the packet. 1316 */ 1317 len = RFD_RxDMAFrameLen(status); 1318 tailm->m_len = len - sc->sc_rxlen; 1319 1320 /* 1321 * If the packet is small enough to fit in a 1322 * single header mbuf, allocate one and copy 1323 * the data into it. This greatly reduces 1324 * memory consumption when we receive lots 1325 * of small packets. 1326 */ 1327 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1328 struct mbuf *nm; 1329 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1330 if (nm == NULL) { 1331 ifp->if_ierrors++; 1332 m_freem(m); 1333 continue; 1334 } 1335 nm->m_data += 2; 1336 nm->m_pkthdr.len = nm->m_len = len; 1337 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1338 m_freem(m); 1339 m = nm; 1340 } 1341 1342 /* 1343 * Set the incoming checksum information for the packet. 1344 */ 1345 if (status & RFD_IPDetected) { 1346 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1347 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1348 if (status & RFD_IPError) 1349 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1350 if (status & RFD_TCPDetected) { 1351 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1352 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1353 if (status & RFD_TCPError) 1354 m->m_pkthdr.csum_flags |= 1355 M_CSUM_TCP_UDP_BAD; 1356 } else if (status & RFD_UDPDetected) { 1357 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1358 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1359 if (status & RFD_UDPError) 1360 m->m_pkthdr.csum_flags |= 1361 M_CSUM_TCP_UDP_BAD; 1362 } 1363 } 1364 1365 m->m_pkthdr.rcvif = ifp; 1366 m->m_pkthdr.len = len; 1367 1368 #if NBPFILTER > 0 1369 /* 1370 * Pass this up to any BPF listeners, but only 1371 * pass if up the stack if it's for us. 1372 */ 1373 if (ifp->if_bpf) 1374 bpf_mtap(ifp->if_bpf, m); 1375 #endif /* NBPFILTER > 0 */ 1376 #ifdef STGE_VLAN_UNTAG 1377 /* 1378 * Check for VLAN tagged packets 1379 */ 1380 if (status & RFD_VLANDetected) 1381 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1382 1383 #endif 1384 #if 0 1385 if (status & RFD_VLANDetected) { 1386 struct ether_header *eh; 1387 u_int16_t etype; 1388 1389 eh = mtod(m, struct ether_header *); 1390 etype = ntohs(eh->ether_type); 1391 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1392 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1393 etype); 1394 } 1395 #endif 1396 /* Pass it on. */ 1397 (*ifp->if_input)(ifp, m); 1398 } 1399 1400 /* Update the receive pointer. */ 1401 sc->sc_rxptr = i; 1402 } 1403 1404 /* 1405 * stge_tick: 1406 * 1407 * One second timer, used to tick the MII. 1408 */ 1409 static void 1410 stge_tick(void *arg) 1411 { 1412 struct stge_softc *sc = arg; 1413 int s; 1414 1415 s = splnet(); 1416 mii_tick(&sc->sc_mii); 1417 stge_stats_update(sc); 1418 splx(s); 1419 1420 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1421 } 1422 1423 /* 1424 * stge_stats_update: 1425 * 1426 * Read the TC9021 statistics counters. 1427 */ 1428 static void 1429 stge_stats_update(struct stge_softc *sc) 1430 { 1431 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1432 bus_space_tag_t st = sc->sc_st; 1433 bus_space_handle_t sh = sc->sc_sh; 1434 1435 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1436 1437 ifp->if_ipackets += 1438 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1439 1440 ifp->if_ierrors += 1441 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1442 1443 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1444 1445 ifp->if_opackets += 1446 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1447 1448 ifp->if_collisions += 1449 bus_space_read_4(st, sh, STGE_LateCollisions) + 1450 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1451 bus_space_read_4(st, sh, STGE_SingleColFrames); 1452 1453 ifp->if_oerrors += 1454 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1455 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1456 } 1457 1458 /* 1459 * stge_reset: 1460 * 1461 * Perform a soft reset on the TC9021. 1462 */ 1463 static void 1464 stge_reset(struct stge_softc *sc) 1465 { 1466 uint32_t ac; 1467 int i; 1468 1469 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1470 1471 /* 1472 * Only assert RstOut if we're fiber. We need GMII clocks 1473 * to be present in order for the reset to complete on fiber 1474 * cards. 1475 */ 1476 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1477 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1478 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1479 (sc->sc_usefiber ? AC_RstOut : 0)); 1480 1481 delay(50000); 1482 1483 for (i = 0; i < STGE_TIMEOUT; i++) { 1484 delay(5000); 1485 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1486 AC_ResetBusy) == 0) 1487 break; 1488 } 1489 1490 if (i == STGE_TIMEOUT) 1491 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1492 1493 delay(1000); 1494 } 1495 1496 /* 1497 * stge_init: [ ifnet interface function ] 1498 * 1499 * Initialize the interface. Must be called at splnet(). 1500 */ 1501 static int 1502 stge_init(struct ifnet *ifp) 1503 { 1504 struct stge_softc *sc = ifp->if_softc; 1505 bus_space_tag_t st = sc->sc_st; 1506 bus_space_handle_t sh = sc->sc_sh; 1507 struct stge_descsoft *ds; 1508 int i, error = 0; 1509 1510 /* 1511 * Cancel any pending I/O. 1512 */ 1513 stge_stop(ifp, 0); 1514 1515 /* 1516 * Reset the chip to a known state. 1517 */ 1518 stge_reset(sc); 1519 1520 /* 1521 * Initialize the transmit descriptor ring. 1522 */ 1523 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1524 for (i = 0; i < STGE_NTXDESC; i++) { 1525 sc->sc_txdescs[i].tfd_next = htole64( 1526 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1527 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1528 } 1529 sc->sc_txpending = 0; 1530 sc->sc_txdirty = 0; 1531 sc->sc_txlast = STGE_NTXDESC - 1; 1532 1533 /* 1534 * Initialize the receive descriptor and receive job 1535 * descriptor rings. 1536 */ 1537 for (i = 0; i < STGE_NRXDESC; i++) { 1538 ds = &sc->sc_rxsoft[i]; 1539 if (ds->ds_mbuf == NULL) { 1540 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1541 printf("%s: unable to allocate or map rx " 1542 "buffer %d, error = %d\n", 1543 sc->sc_dev.dv_xname, i, error); 1544 /* 1545 * XXX Should attempt to run with fewer receive 1546 * XXX buffers instead of just failing. 1547 */ 1548 stge_rxdrain(sc); 1549 goto out; 1550 } 1551 } else 1552 STGE_INIT_RXDESC(sc, i); 1553 } 1554 sc->sc_rxptr = 0; 1555 sc->sc_rxdiscard = 0; 1556 STGE_RXCHAIN_RESET(sc); 1557 1558 /* Set the station address. */ 1559 for (i = 0; i < 6; i++) 1560 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1561 LLADDR(ifp->if_sadl)[i]); 1562 1563 /* 1564 * Set the statistics masks. Disable all the RMON stats, 1565 * and disable selected stats in the non-RMON stats registers. 1566 */ 1567 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1568 bus_space_write_4(st, sh, STGE_StatisticsMask, 1569 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1570 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1571 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1572 (1U << 21)); 1573 1574 /* Set up the receive filter. */ 1575 stge_set_filter(sc); 1576 1577 /* 1578 * Give the transmit and receive ring to the chip. 1579 */ 1580 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1581 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1582 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1583 1584 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1585 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1586 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1587 1588 /* 1589 * Initialize the Tx auto-poll period. It's OK to make this number 1590 * large (255 is the max, but we use 127) -- we explicitly kick the 1591 * transmit engine when there's actually a packet. 1592 */ 1593 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1594 1595 /* ..and the Rx auto-poll period. */ 1596 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1597 1598 /* Initialize the Tx start threshold. */ 1599 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1600 1601 /* RX DMA thresholds, from linux */ 1602 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1603 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1604 1605 /* 1606 * Initialize the Rx DMA interrupt control register. We 1607 * request an interrupt after every incoming packet, but 1608 * defer it for 32us (64 * 512 ns). When the number of 1609 * interrupts pending reaches 8, we stop deferring the 1610 * interrupt, and signal it immediately. 1611 */ 1612 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1613 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1614 1615 /* 1616 * Initialize the interrupt mask. 1617 */ 1618 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1619 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1620 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1621 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1622 1623 /* 1624 * Configure the DMA engine. 1625 * XXX Should auto-tune TxBurstLimit. 1626 */ 1627 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1628 DMAC_TxBurstLimit(3)); 1629 1630 /* 1631 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1632 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1633 * empty again. 1634 */ 1635 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1636 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1637 1638 /* 1639 * Set the maximum frame size. 1640 */ 1641 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1642 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1643 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1644 ETHER_VLAN_ENCAP_LEN : 0)); 1645 1646 /* 1647 * Initialize MacCtrl -- do it before setting the media, 1648 * as setting the media will actually program the register. 1649 * 1650 * Note: We have to poke the IFS value before poking 1651 * anything else. 1652 */ 1653 sc->sc_MACCtrl = MC_IFSSelect(0); 1654 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1655 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1656 #ifdef STGE_VLAN_UNTAG 1657 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1658 #endif 1659 1660 if (sc->sc_rev >= 6) { /* >= B.2 */ 1661 /* Multi-frag frame bug work-around. */ 1662 bus_space_write_2(st, sh, STGE_DebugCtrl, 1663 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1664 1665 /* Tx Poll Now bug work-around. */ 1666 bus_space_write_2(st, sh, STGE_DebugCtrl, 1667 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1668 /* XXX ? from linux */ 1669 bus_space_write_2(st, sh, STGE_DebugCtrl, 1670 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1671 } 1672 1673 /* 1674 * Set the current media. 1675 */ 1676 mii_mediachg(&sc->sc_mii); 1677 1678 /* 1679 * Start the one second MII clock. 1680 */ 1681 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1682 1683 /* 1684 * ...all done! 1685 */ 1686 ifp->if_flags |= IFF_RUNNING; 1687 ifp->if_flags &= ~IFF_OACTIVE; 1688 1689 out: 1690 if (error) 1691 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1692 return (error); 1693 } 1694 1695 /* 1696 * stge_drain: 1697 * 1698 * Drain the receive queue. 1699 */ 1700 static void 1701 stge_rxdrain(struct stge_softc *sc) 1702 { 1703 struct stge_descsoft *ds; 1704 int i; 1705 1706 for (i = 0; i < STGE_NRXDESC; i++) { 1707 ds = &sc->sc_rxsoft[i]; 1708 if (ds->ds_mbuf != NULL) { 1709 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1710 ds->ds_mbuf->m_next = NULL; 1711 m_freem(ds->ds_mbuf); 1712 ds->ds_mbuf = NULL; 1713 } 1714 } 1715 } 1716 1717 /* 1718 * stge_stop: [ ifnet interface function ] 1719 * 1720 * Stop transmission on the interface. 1721 */ 1722 static void 1723 stge_stop(struct ifnet *ifp, int disable) 1724 { 1725 struct stge_softc *sc = ifp->if_softc; 1726 struct stge_descsoft *ds; 1727 int i; 1728 1729 /* 1730 * Stop the one second clock. 1731 */ 1732 callout_stop(&sc->sc_tick_ch); 1733 1734 /* Down the MII. */ 1735 mii_down(&sc->sc_mii); 1736 1737 /* 1738 * Disable interrupts. 1739 */ 1740 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1741 1742 /* 1743 * Stop receiver, transmitter, and stats update. 1744 */ 1745 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1746 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1747 1748 /* 1749 * Stop the transmit and receive DMA. 1750 */ 1751 stge_dma_wait(sc); 1752 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1753 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1754 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1755 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1756 1757 /* 1758 * Release any queued transmit buffers. 1759 */ 1760 for (i = 0; i < STGE_NTXDESC; i++) { 1761 ds = &sc->sc_txsoft[i]; 1762 if (ds->ds_mbuf != NULL) { 1763 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1764 m_freem(ds->ds_mbuf); 1765 ds->ds_mbuf = NULL; 1766 } 1767 } 1768 1769 if (disable) 1770 stge_rxdrain(sc); 1771 1772 /* 1773 * Mark the interface down and cancel the watchdog timer. 1774 */ 1775 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1776 ifp->if_timer = 0; 1777 } 1778 1779 static int 1780 stge_eeprom_wait(struct stge_softc *sc) 1781 { 1782 int i; 1783 1784 for (i = 0; i < STGE_TIMEOUT; i++) { 1785 delay(1000); 1786 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1787 EC_EepromBusy) == 0) 1788 return (0); 1789 } 1790 return (1); 1791 } 1792 1793 /* 1794 * stge_read_eeprom: 1795 * 1796 * Read data from the serial EEPROM. 1797 */ 1798 static void 1799 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1800 { 1801 1802 if (stge_eeprom_wait(sc)) 1803 printf("%s: EEPROM failed to come ready\n", 1804 sc->sc_dev.dv_xname); 1805 1806 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1807 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1808 if (stge_eeprom_wait(sc)) 1809 printf("%s: EEPROM read timed out\n", 1810 sc->sc_dev.dv_xname); 1811 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1812 } 1813 1814 /* 1815 * stge_add_rxbuf: 1816 * 1817 * Add a receive buffer to the indicated descriptor. 1818 */ 1819 static int 1820 stge_add_rxbuf(struct stge_softc *sc, int idx) 1821 { 1822 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1823 struct mbuf *m; 1824 int error; 1825 1826 MGETHDR(m, M_DONTWAIT, MT_DATA); 1827 if (m == NULL) 1828 return (ENOBUFS); 1829 1830 MCLGET(m, M_DONTWAIT); 1831 if ((m->m_flags & M_EXT) == 0) { 1832 m_freem(m); 1833 return (ENOBUFS); 1834 } 1835 1836 m->m_data = m->m_ext.ext_buf + 2; 1837 m->m_len = MCLBYTES - 2; 1838 1839 if (ds->ds_mbuf != NULL) 1840 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1841 1842 ds->ds_mbuf = m; 1843 1844 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1845 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1846 if (error) { 1847 printf("%s: can't load rx DMA map %d, error = %d\n", 1848 sc->sc_dev.dv_xname, idx, error); 1849 panic("stge_add_rxbuf"); /* XXX */ 1850 } 1851 1852 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1853 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1854 1855 STGE_INIT_RXDESC(sc, idx); 1856 1857 return (0); 1858 } 1859 1860 /* 1861 * stge_set_filter: 1862 * 1863 * Set up the receive filter. 1864 */ 1865 static void 1866 stge_set_filter(struct stge_softc *sc) 1867 { 1868 struct ethercom *ec = &sc->sc_ethercom; 1869 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1870 struct ether_multi *enm; 1871 struct ether_multistep step; 1872 uint32_t crc; 1873 uint32_t mchash[2]; 1874 1875 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1876 if (ifp->if_flags & IFF_BROADCAST) 1877 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1878 1879 /* XXX: ST1023 only works in promiscuous mode */ 1880 if (sc->sc_stge1023) 1881 ifp->if_flags |= IFF_PROMISC; 1882 1883 if (ifp->if_flags & IFF_PROMISC) { 1884 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1885 goto allmulti; 1886 } 1887 1888 /* 1889 * Set up the multicast address filter by passing all multicast 1890 * addresses through a CRC generator, and then using the low-order 1891 * 6 bits as an index into the 64 bit multicast hash table. The 1892 * high order bits select the register, while the rest of the bits 1893 * select the bit within the register. 1894 */ 1895 1896 memset(mchash, 0, sizeof(mchash)); 1897 1898 ETHER_FIRST_MULTI(step, ec, enm); 1899 if (enm == NULL) 1900 goto done; 1901 1902 while (enm != NULL) { 1903 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1904 /* 1905 * We must listen to a range of multicast addresses. 1906 * For now, just accept all multicasts, rather than 1907 * trying to set only those filter bits needed to match 1908 * the range. (At this time, the only use of address 1909 * ranges is for IP multicast routing, for which the 1910 * range is big enough to require all bits set.) 1911 */ 1912 goto allmulti; 1913 } 1914 1915 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1916 1917 /* Just want the 6 least significant bits. */ 1918 crc &= 0x3f; 1919 1920 /* Set the corresponding bit in the hash table. */ 1921 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1922 1923 ETHER_NEXT_MULTI(step, enm); 1924 } 1925 1926 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1927 1928 ifp->if_flags &= ~IFF_ALLMULTI; 1929 goto done; 1930 1931 allmulti: 1932 ifp->if_flags |= IFF_ALLMULTI; 1933 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1934 1935 done: 1936 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1937 /* 1938 * Program the multicast hash table. 1939 */ 1940 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1941 mchash[0]); 1942 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1943 mchash[1]); 1944 } 1945 1946 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1947 sc->sc_ReceiveMode); 1948 } 1949 1950 /* 1951 * stge_mii_readreg: [mii interface function] 1952 * 1953 * Read a PHY register on the MII of the TC9021. 1954 */ 1955 static int 1956 stge_mii_readreg(struct device *self, int phy, int reg) 1957 { 1958 1959 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1960 } 1961 1962 /* 1963 * stge_mii_writereg: [mii interface function] 1964 * 1965 * Write a PHY register on the MII of the TC9021. 1966 */ 1967 static void 1968 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1969 { 1970 1971 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1972 } 1973 1974 /* 1975 * stge_mii_statchg: [mii interface function] 1976 * 1977 * Callback from MII layer when media changes. 1978 */ 1979 static void 1980 stge_mii_statchg(struct device *self) 1981 { 1982 struct stge_softc *sc = (struct stge_softc *) self; 1983 1984 if (sc->sc_mii.mii_media_active & IFM_FDX) 1985 sc->sc_MACCtrl |= MC_DuplexSelect; 1986 else 1987 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1988 1989 /* XXX 802.1x flow-control? */ 1990 1991 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1992 } 1993 1994 /* 1995 * sste_mii_bitbang_read: [mii bit-bang interface function] 1996 * 1997 * Read the MII serial port for the MII bit-bang module. 1998 */ 1999 static uint32_t 2000 stge_mii_bitbang_read(struct device *self) 2001 { 2002 struct stge_softc *sc = (void *) self; 2003 2004 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 2005 } 2006 2007 /* 2008 * stge_mii_bitbang_write: [mii big-bang interface function] 2009 * 2010 * Write the MII serial port for the MII bit-bang module. 2011 */ 2012 static void 2013 stge_mii_bitbang_write(struct device *self, uint32_t val) 2014 { 2015 struct stge_softc *sc = (void *) self; 2016 2017 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2018 val | sc->sc_PhyCtrl); 2019 } 2020 2021 /* 2022 * stge_mediastatus: [ifmedia interface function] 2023 * 2024 * Get the current interface media status. 2025 */ 2026 static void 2027 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2028 { 2029 struct stge_softc *sc = ifp->if_softc; 2030 2031 mii_pollstat(&sc->sc_mii); 2032 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2033 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2034 } 2035 2036 /* 2037 * stge_mediachange: [ifmedia interface function] 2038 * 2039 * Set hardware to newly-selected media. 2040 */ 2041 static int 2042 stge_mediachange(struct ifnet *ifp) 2043 { 2044 struct stge_softc *sc = ifp->if_softc; 2045 2046 if (ifp->if_flags & IFF_UP) 2047 mii_mediachg(&sc->sc_mii); 2048 return (0); 2049 } 2050