1 /* $NetBSD: if_stge.c,v 1.44 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.44 2008/04/10 19:13:37 cegger Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <sys/bus.h> 73 #include <sys/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* #define STGE_CU_BUG 1 */ 86 #define STGE_VLAN_UNTAG 1 87 /* #define STGE_VLAN_CFI 1 */ 88 89 /* 90 * Transmit descriptor list size. 91 */ 92 #define STGE_NTXDESC 256 93 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 94 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 95 96 /* 97 * Receive descriptor list size. 98 */ 99 #define STGE_NRXDESC 256 100 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 101 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 102 103 /* 104 * Only interrupt every N frames. Must be a power-of-two. 105 */ 106 #define STGE_TXINTR_SPACING 16 107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 108 109 /* 110 * Control structures are DMA'd to the TC9021 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct stge_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 124 }; 125 126 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit and receive jobs. 132 */ 133 struct stge_descsoft { 134 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t ds_dmamap; /* our DMA map */ 136 }; 137 138 /* 139 * Software state per device. 140 */ 141 struct stge_softc { 142 struct device sc_dev; /* generic device information */ 143 bus_space_tag_t sc_st; /* bus space tag */ 144 bus_space_handle_t sc_sh; /* bus space handle */ 145 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 146 struct ethercom sc_ethercom; /* ethernet common data */ 147 void *sc_sdhook; /* shutdown hook */ 148 int sc_rev; /* silicon revision */ 149 150 void *sc_ih; /* interrupt cookie */ 151 152 struct mii_data sc_mii; /* MII/media information */ 153 154 callout_t sc_tick_ch; /* tick callout */ 155 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 163 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct stge_control_data *sc_control_data; 169 #define sc_txdescs sc_control_data->scd_txdescs 170 #define sc_rxdescs sc_control_data->scd_rxdescs 171 172 #ifdef STGE_EVENT_COUNTERS 173 /* 174 * Event counters. 175 */ 176 struct evcnt sc_ev_txstall; /* Tx stalled */ 177 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 178 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 179 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 180 181 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 182 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 183 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 184 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 185 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 186 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 187 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 188 189 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 190 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 191 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 192 193 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 194 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 195 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 196 #endif /* STGE_EVENT_COUNTERS */ 197 198 int sc_txpending; /* number of Tx requests pending */ 199 int sc_txdirty; /* first dirty Tx descriptor */ 200 int sc_txlast; /* last used Tx descriptor */ 201 202 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 203 int sc_rxdiscard; 204 int sc_rxlen; 205 struct mbuf *sc_rxhead; 206 struct mbuf *sc_rxtail; 207 struct mbuf **sc_rxtailp; 208 209 int sc_txthresh; /* Tx threshold */ 210 uint32_t sc_usefiber:1; /* if we're fiber */ 211 uint32_t sc_stge1023:1; /* are we a 1023 */ 212 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 213 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 214 uint16_t sc_IntEnable; /* prototype IntEnable register */ 215 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 216 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 217 }; 218 219 #define STGE_RXCHAIN_RESET(sc) \ 220 do { \ 221 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 222 *(sc)->sc_rxtailp = NULL; \ 223 (sc)->sc_rxlen = 0; \ 224 } while (/*CONSTCOND*/0) 225 226 #define STGE_RXCHAIN_LINK(sc, m) \ 227 do { \ 228 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 229 (sc)->sc_rxtailp = &(m)->m_next; \ 230 } while (/*CONSTCOND*/0) 231 232 #ifdef STGE_EVENT_COUNTERS 233 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 234 #else 235 #define STGE_EVCNT_INCR(ev) /* nothing */ 236 #endif 237 238 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 239 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 240 241 #define STGE_CDTXSYNC(sc, x, ops) \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 243 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 244 245 #define STGE_CDRXSYNC(sc, x, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 248 249 #define STGE_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 252 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 253 \ 254 /* \ 255 * Note: We scoot the packet forward 2 bytes in the buffer \ 256 * so that the payload after the Ethernet header is aligned \ 257 * to a 4-byte boundary. \ 258 */ \ 259 __rfd->rfd_frag.frag_word0 = \ 260 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 261 FRAG_LEN(MCLBYTES - 2)); \ 262 __rfd->rfd_next = \ 263 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 264 __rfd->rfd_status = 0; \ 265 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 266 } while (/*CONSTCOND*/0) 267 268 #define STGE_TIMEOUT 1000 269 270 static void stge_start(struct ifnet *); 271 static void stge_watchdog(struct ifnet *); 272 static int stge_ioctl(struct ifnet *, u_long, void *); 273 static int stge_init(struct ifnet *); 274 static void stge_stop(struct ifnet *, int); 275 276 static void stge_shutdown(void *); 277 278 static void stge_reset(struct stge_softc *); 279 static void stge_rxdrain(struct stge_softc *); 280 static int stge_add_rxbuf(struct stge_softc *, int); 281 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 282 static void stge_tick(void *); 283 284 static void stge_stats_update(struct stge_softc *); 285 286 static void stge_set_filter(struct stge_softc *); 287 288 static int stge_intr(void *); 289 static void stge_txintr(struct stge_softc *); 290 static void stge_rxintr(struct stge_softc *); 291 292 static int stge_mii_readreg(device_t, int, int); 293 static void stge_mii_writereg(device_t, int, int, int); 294 static void stge_mii_statchg(device_t); 295 296 static int stge_match(device_t, struct cfdata *, void *); 297 static void stge_attach(device_t, device_t, void *); 298 299 int stge_copy_small = 0; 300 301 CFATTACH_DECL(stge, sizeof(struct stge_softc), 302 stge_match, stge_attach, NULL, NULL); 303 304 static uint32_t stge_mii_bitbang_read(device_t); 305 static void stge_mii_bitbang_write(device_t, uint32_t); 306 307 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 308 stge_mii_bitbang_read, 309 stge_mii_bitbang_write, 310 { 311 PC_MgmtData, /* MII_BIT_MDO */ 312 PC_MgmtData, /* MII_BIT_MDI */ 313 PC_MgmtClk, /* MII_BIT_MDC */ 314 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 315 0, /* MII_BIT_DIR_PHY_HOST */ 316 } 317 }; 318 319 /* 320 * Devices supported by this driver. 321 */ 322 static const struct stge_product { 323 pci_vendor_id_t stge_vendor; 324 pci_product_id_t stge_product; 325 const char *stge_name; 326 } stge_products[] = { 327 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 328 "Sundance ST-1023 Gigabit Ethernet" }, 329 330 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 331 "Sundance ST-2021 Gigabit Ethernet" }, 332 333 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 334 "Tamarack TC9021 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 337 "Tamarack TC9021 Gigabit Ethernet" }, 338 339 /* 340 * The Sundance sample boards use the Sundance vendor ID, 341 * but the Tamarack product ID. 342 */ 343 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 344 "Sundance TC9021 Gigabit Ethernet" }, 345 346 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 347 "Sundance TC9021 Gigabit Ethernet" }, 348 349 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 350 "D-Link DL-4000 Gigabit Ethernet" }, 351 352 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 353 "Antares Gigabit Ethernet" }, 354 355 { 0, 0, 356 NULL }, 357 }; 358 359 static const struct stge_product * 360 stge_lookup(const struct pci_attach_args *pa) 361 { 362 const struct stge_product *sp; 363 364 for (sp = stge_products; sp->stge_name != NULL; sp++) { 365 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 366 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 367 return (sp); 368 } 369 return (NULL); 370 } 371 372 static int 373 stge_match(device_t parent, struct cfdata *cf, void *aux) 374 { 375 struct pci_attach_args *pa = aux; 376 377 if (stge_lookup(pa) != NULL) 378 return (1); 379 380 return (0); 381 } 382 383 static void 384 stge_attach(device_t parent, device_t self, void *aux) 385 { 386 struct stge_softc *sc = device_private(self); 387 struct pci_attach_args *pa = aux; 388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 389 pci_chipset_tag_t pc = pa->pa_pc; 390 pci_intr_handle_t ih; 391 const char *intrstr = NULL; 392 bus_space_tag_t iot, memt; 393 bus_space_handle_t ioh, memh; 394 bus_dma_segment_t seg; 395 int ioh_valid, memh_valid; 396 int i, rseg, error; 397 const struct stge_product *sp; 398 uint8_t enaddr[ETHER_ADDR_LEN]; 399 400 callout_init(&sc->sc_tick_ch, 0); 401 402 sp = stge_lookup(pa); 403 if (sp == NULL) { 404 printf("\n"); 405 panic("ste_attach: impossible"); 406 } 407 408 sc->sc_rev = PCI_REVISION(pa->pa_class); 409 410 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 411 412 /* 413 * Map the device. 414 */ 415 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 416 PCI_MAPREG_TYPE_IO, 0, 417 &iot, &ioh, NULL, NULL) == 0); 418 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 419 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 420 &memt, &memh, NULL, NULL) == 0); 421 422 if (memh_valid) { 423 sc->sc_st = memt; 424 sc->sc_sh = memh; 425 } else if (ioh_valid) { 426 sc->sc_st = iot; 427 sc->sc_sh = ioh; 428 } else { 429 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 430 return; 431 } 432 433 sc->sc_dmat = pa->pa_dmat; 434 435 /* Enable bus mastering. */ 436 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 437 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 438 PCI_COMMAND_MASTER_ENABLE); 439 440 /* power up chip */ 441 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 442 error != EOPNOTSUPP) { 443 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 444 error); 445 return; 446 } 447 /* 448 * Map and establish our interrupt. 449 */ 450 if (pci_intr_map(pa, &ih)) { 451 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 452 return; 453 } 454 intrstr = pci_intr_string(pc, ih); 455 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 456 if (sc->sc_ih == NULL) { 457 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 458 if (intrstr != NULL) 459 printf(" at %s", intrstr); 460 printf("\n"); 461 return; 462 } 463 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 464 465 /* 466 * Allocate the control data structures, and create and load the 467 * DMA map for it. 468 */ 469 if ((error = bus_dmamem_alloc(sc->sc_dmat, 470 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 471 0)) != 0) { 472 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 473 error); 474 goto fail_0; 475 } 476 477 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 478 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 479 BUS_DMA_COHERENT)) != 0) { 480 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 481 error); 482 goto fail_1; 483 } 484 485 if ((error = bus_dmamap_create(sc->sc_dmat, 486 sizeof(struct stge_control_data), 1, 487 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 488 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 489 "error = %d\n", error); 490 goto fail_2; 491 } 492 493 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 494 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 495 0)) != 0) { 496 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 497 error); 498 goto fail_3; 499 } 500 501 /* 502 * Create the transmit buffer DMA maps. Note that rev B.3 503 * and earlier seem to have a bug regarding multi-fragment 504 * packets. We need to limit the number of Tx segments on 505 * such chips to 1. 506 */ 507 for (i = 0; i < STGE_NTXDESC; i++) { 508 if ((error = bus_dmamap_create(sc->sc_dmat, 509 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 510 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 511 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 512 "error = %d\n", i, error); 513 goto fail_4; 514 } 515 } 516 517 /* 518 * Create the receive buffer DMA maps. 519 */ 520 for (i = 0; i < STGE_NRXDESC; i++) { 521 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 522 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 523 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 524 "error = %d\n", i, error); 525 goto fail_5; 526 } 527 sc->sc_rxsoft[i].ds_mbuf = NULL; 528 } 529 530 /* 531 * Determine if we're copper or fiber. It affects how we 532 * reset the card. 533 */ 534 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 535 AC_PhyMedia) 536 sc->sc_usefiber = 1; 537 else 538 sc->sc_usefiber = 0; 539 540 /* 541 * Reset the chip to a known state. 542 */ 543 stge_reset(sc); 544 545 /* 546 * Reading the station address from the EEPROM doesn't seem 547 * to work, at least on my sample boards. Instead, since 548 * the reset sequence does AutoInit, read it from the station 549 * address registers. For Sundance 1023 you can only read it 550 * from EEPROM. 551 */ 552 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 553 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress0) & 0xff; 555 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress0) >> 8; 557 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress1) & 0xff; 559 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress1) >> 8; 561 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 562 STGE_StationAddress2) & 0xff; 563 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 564 STGE_StationAddress2) >> 8; 565 sc->sc_stge1023 = 0; 566 } else { 567 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 568 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 569 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 570 &myaddr[i]); 571 myaddr[i] = le16toh(myaddr[i]); 572 } 573 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 574 sc->sc_stge1023 = 1; 575 } 576 577 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 578 ether_sprintf(enaddr)); 579 580 /* 581 * Read some important bits from the PhyCtrl register. 582 */ 583 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 584 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 585 586 /* 587 * Initialize our media structures and probe the MII. 588 */ 589 sc->sc_mii.mii_ifp = ifp; 590 sc->sc_mii.mii_readreg = stge_mii_readreg; 591 sc->sc_mii.mii_writereg = stge_mii_writereg; 592 sc->sc_mii.mii_statchg = stge_mii_statchg; 593 sc->sc_ethercom.ec_mii = &sc->sc_mii; 594 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 595 ether_mediastatus); 596 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 597 MII_OFFSET_ANY, MIIF_DOPAUSE); 598 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 599 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 600 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 601 } else 602 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 603 604 ifp = &sc->sc_ethercom.ec_if; 605 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 606 ifp->if_softc = sc; 607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 608 ifp->if_ioctl = stge_ioctl; 609 ifp->if_start = stge_start; 610 ifp->if_watchdog = stge_watchdog; 611 ifp->if_init = stge_init; 612 ifp->if_stop = stge_stop; 613 IFQ_SET_READY(&ifp->if_snd); 614 615 /* 616 * The manual recommends disabling early transmit, so we 617 * do. It's disabled anyway, if using IP checksumming, 618 * since the entire packet must be in the FIFO in order 619 * for the chip to perform the checksum. 620 */ 621 sc->sc_txthresh = 0x0fff; 622 623 /* 624 * Disable MWI if the PCI layer tells us to. 625 */ 626 sc->sc_DMACtrl = 0; 627 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 628 sc->sc_DMACtrl |= DMAC_MWIDisable; 629 630 /* 631 * We can support 802.1Q VLAN-sized frames and jumbo 632 * Ethernet frames. 633 * 634 * XXX Figure out how to do hw-assisted VLAN tagging in 635 * XXX a reasonable way on this chip. 636 */ 637 sc->sc_ethercom.ec_capabilities |= 638 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 639 ETHERCAP_VLAN_HWTAGGING; 640 641 /* 642 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 643 */ 644 sc->sc_ethercom.ec_if.if_capabilities |= 645 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 646 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 647 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 648 649 /* 650 * Attach the interface. 651 */ 652 if_attach(ifp); 653 ether_ifattach(ifp, enaddr); 654 655 #ifdef STGE_EVENT_COUNTERS 656 /* 657 * Attach event counters. 658 */ 659 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 660 NULL, device_xname(&sc->sc_dev), "txstall"); 661 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 662 NULL, device_xname(&sc->sc_dev), "txdmaintr"); 663 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 664 NULL, device_xname(&sc->sc_dev), "txindintr"); 665 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 666 NULL, device_xname(&sc->sc_dev), "rxintr"); 667 668 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 669 NULL, device_xname(&sc->sc_dev), "txseg1"); 670 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 671 NULL, device_xname(&sc->sc_dev), "txseg2"); 672 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 673 NULL, device_xname(&sc->sc_dev), "txseg3"); 674 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 675 NULL, device_xname(&sc->sc_dev), "txseg4"); 676 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 677 NULL, device_xname(&sc->sc_dev), "txseg5"); 678 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 679 NULL, device_xname(&sc->sc_dev), "txsegmore"); 680 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 681 NULL, device_xname(&sc->sc_dev), "txcopy"); 682 683 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 684 NULL, device_xname(&sc->sc_dev), "rxipsum"); 685 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 686 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 687 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 688 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 689 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 690 NULL, device_xname(&sc->sc_dev), "txipsum"); 691 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 692 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 693 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 694 NULL, device_xname(&sc->sc_dev), "txudpsum"); 695 #endif /* STGE_EVENT_COUNTERS */ 696 697 /* 698 * Make sure the interface is shutdown during reboot. 699 */ 700 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 701 if (sc->sc_sdhook == NULL) 702 printf("%s: WARNING: unable to establish shutdown hook\n", 703 device_xname(&sc->sc_dev)); 704 return; 705 706 /* 707 * Free any resources we've allocated during the failed attach 708 * attempt. Do this in reverse order and fall through. 709 */ 710 fail_5: 711 for (i = 0; i < STGE_NRXDESC; i++) { 712 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 713 bus_dmamap_destroy(sc->sc_dmat, 714 sc->sc_rxsoft[i].ds_dmamap); 715 } 716 fail_4: 717 for (i = 0; i < STGE_NTXDESC; i++) { 718 if (sc->sc_txsoft[i].ds_dmamap != NULL) 719 bus_dmamap_destroy(sc->sc_dmat, 720 sc->sc_txsoft[i].ds_dmamap); 721 } 722 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 723 fail_3: 724 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 725 fail_2: 726 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 727 sizeof(struct stge_control_data)); 728 fail_1: 729 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 730 fail_0: 731 return; 732 } 733 734 /* 735 * stge_shutdown: 736 * 737 * Make sure the interface is stopped at reboot time. 738 */ 739 static void 740 stge_shutdown(void *arg) 741 { 742 struct stge_softc *sc = arg; 743 744 stge_stop(&sc->sc_ethercom.ec_if, 1); 745 } 746 747 static void 748 stge_dma_wait(struct stge_softc *sc) 749 { 750 int i; 751 752 for (i = 0; i < STGE_TIMEOUT; i++) { 753 delay(2); 754 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 755 DMAC_TxDMAInProg) == 0) 756 break; 757 } 758 759 if (i == STGE_TIMEOUT) 760 printf("%s: DMA wait timed out\n", device_xname(&sc->sc_dev)); 761 } 762 763 /* 764 * stge_start: [ifnet interface function] 765 * 766 * Start packet transmission on the interface. 767 */ 768 static void 769 stge_start(struct ifnet *ifp) 770 { 771 struct stge_softc *sc = ifp->if_softc; 772 struct mbuf *m0; 773 struct stge_descsoft *ds; 774 struct stge_tfd *tfd; 775 bus_dmamap_t dmamap; 776 int error, firsttx, nexttx, opending, seg, totlen; 777 uint64_t csum_flags; 778 779 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 780 return; 781 782 /* 783 * Remember the previous number of pending transmissions 784 * and the first descriptor we will use. 785 */ 786 opending = sc->sc_txpending; 787 firsttx = STGE_NEXTTX(sc->sc_txlast); 788 789 /* 790 * Loop through the send queue, setting up transmit descriptors 791 * until we drain the queue, or use up all available transmit 792 * descriptors. 793 */ 794 for (;;) { 795 struct m_tag *mtag; 796 uint64_t tfc; 797 798 /* 799 * Grab a packet off the queue. 800 */ 801 IFQ_POLL(&ifp->if_snd, m0); 802 if (m0 == NULL) 803 break; 804 805 /* 806 * Leave one unused descriptor at the end of the 807 * list to prevent wrapping completely around. 808 */ 809 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 810 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 811 break; 812 } 813 814 /* 815 * See if we have any VLAN stuff. 816 */ 817 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 818 819 /* 820 * Get the last and next available transmit descriptor. 821 */ 822 nexttx = STGE_NEXTTX(sc->sc_txlast); 823 tfd = &sc->sc_txdescs[nexttx]; 824 ds = &sc->sc_txsoft[nexttx]; 825 826 dmamap = ds->ds_dmamap; 827 828 /* 829 * Load the DMA map. If this fails, the packet either 830 * didn't fit in the alloted number of segments, or we 831 * were short on resources. For the too-many-segments 832 * case, we simply report an error and drop the packet, 833 * since we can't sanely copy a jumbo packet to a single 834 * buffer. 835 */ 836 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 837 BUS_DMA_NOWAIT); 838 if (error) { 839 if (error == EFBIG) { 840 printf("%s: Tx packet consumes too many " 841 "DMA segments, dropping...\n", 842 device_xname(&sc->sc_dev)); 843 IFQ_DEQUEUE(&ifp->if_snd, m0); 844 m_freem(m0); 845 continue; 846 } 847 /* 848 * Short on resources, just stop for now. 849 */ 850 break; 851 } 852 853 IFQ_DEQUEUE(&ifp->if_snd, m0); 854 855 /* 856 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 857 */ 858 859 /* Sync the DMA map. */ 860 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 861 BUS_DMASYNC_PREWRITE); 862 863 /* Initialize the fragment list. */ 864 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 865 tfd->tfd_frags[seg].frag_word0 = 866 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 867 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 868 totlen += dmamap->dm_segs[seg].ds_len; 869 } 870 871 #ifdef STGE_EVENT_COUNTERS 872 switch (dmamap->dm_nsegs) { 873 case 1: 874 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 875 break; 876 case 2: 877 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 878 break; 879 case 3: 880 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 881 break; 882 case 4: 883 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 884 break; 885 case 5: 886 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 887 break; 888 default: 889 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 890 break; 891 } 892 #endif /* STGE_EVENT_COUNTERS */ 893 894 /* 895 * Initialize checksumming flags in the descriptor. 896 * Byte-swap constants so the compiler can optimize. 897 */ 898 csum_flags = 0; 899 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 900 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 901 csum_flags |= TFD_IPChecksumEnable; 902 } 903 904 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 905 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 906 csum_flags |= TFD_TCPChecksumEnable; 907 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 908 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 909 csum_flags |= TFD_UDPChecksumEnable; 910 } 911 912 /* 913 * Initialize the descriptor and give it to the chip. 914 * Check to see if we have a VLAN tag to insert. 915 */ 916 917 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 918 TFD_FragCount(seg) | csum_flags | 919 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 920 TFD_TxDMAIndicate : 0); 921 if (mtag) { 922 #if 0 923 struct ether_header *eh = 924 mtod(m0, struct ether_header *); 925 u_int16_t etype = ntohs(eh->ether_type); 926 printf("%s: xmit (tag %d) etype %x\n", 927 ifp->if_xname, *mtod(n, int *), etype); 928 #endif 929 tfc |= TFD_VLANTagInsert | 930 #ifdef STGE_VLAN_CFI 931 TFD_CFI | 932 #endif 933 TFD_VID(VLAN_TAG_VALUE(mtag)); 934 } 935 tfd->tfd_control = htole64(tfc); 936 937 /* Sync the descriptor. */ 938 STGE_CDTXSYNC(sc, nexttx, 939 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 940 941 /* 942 * Kick the transmit DMA logic. 943 */ 944 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 945 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 946 947 /* 948 * Store a pointer to the packet so we can free it later. 949 */ 950 ds->ds_mbuf = m0; 951 952 /* Advance the tx pointer. */ 953 sc->sc_txpending++; 954 sc->sc_txlast = nexttx; 955 956 #if NBPFILTER > 0 957 /* 958 * Pass the packet to any BPF listeners. 959 */ 960 if (ifp->if_bpf) 961 bpf_mtap(ifp->if_bpf, m0); 962 #endif /* NBPFILTER > 0 */ 963 } 964 965 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 966 /* No more slots left; notify upper layer. */ 967 ifp->if_flags |= IFF_OACTIVE; 968 } 969 970 if (sc->sc_txpending != opending) { 971 /* 972 * We enqueued packets. If the transmitter was idle, 973 * reset the txdirty pointer. 974 */ 975 if (opending == 0) 976 sc->sc_txdirty = firsttx; 977 978 /* Set a watchdog timer in case the chip flakes out. */ 979 ifp->if_timer = 5; 980 } 981 } 982 983 /* 984 * stge_watchdog: [ifnet interface function] 985 * 986 * Watchdog timer handler. 987 */ 988 static void 989 stge_watchdog(struct ifnet *ifp) 990 { 991 struct stge_softc *sc = ifp->if_softc; 992 993 /* 994 * Sweep up first, since we don't interrupt every frame. 995 */ 996 stge_txintr(sc); 997 if (sc->sc_txpending != 0) { 998 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 999 ifp->if_oerrors++; 1000 1001 (void) stge_init(ifp); 1002 1003 /* Try to get more packets going. */ 1004 stge_start(ifp); 1005 } 1006 } 1007 1008 /* 1009 * stge_ioctl: [ifnet interface function] 1010 * 1011 * Handle control requests from the operator. 1012 */ 1013 static int 1014 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1015 { 1016 struct stge_softc *sc = ifp->if_softc; 1017 int s, error; 1018 1019 s = splnet(); 1020 1021 error = ether_ioctl(ifp, cmd, data); 1022 if (error == ENETRESET) { 1023 error = 0; 1024 1025 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1026 ; 1027 else if (ifp->if_flags & IFF_RUNNING) { 1028 /* 1029 * Multicast list has changed; set the hardware filter 1030 * accordingly. 1031 */ 1032 stge_set_filter(sc); 1033 } 1034 } 1035 1036 /* Try to get more packets going. */ 1037 stge_start(ifp); 1038 1039 splx(s); 1040 return (error); 1041 } 1042 1043 /* 1044 * stge_intr: 1045 * 1046 * Interrupt service routine. 1047 */ 1048 static int 1049 stge_intr(void *arg) 1050 { 1051 struct stge_softc *sc = arg; 1052 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1053 uint32_t txstat; 1054 int wantinit; 1055 uint16_t isr; 1056 1057 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1058 IS_InterruptStatus) == 0) 1059 return (0); 1060 1061 for (wantinit = 0; wantinit == 0;) { 1062 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1063 if ((isr & sc->sc_IntEnable) == 0) 1064 break; 1065 1066 /* Host interface errors. */ 1067 if (isr & IS_HostError) { 1068 printf("%s: Host interface error\n", 1069 device_xname(&sc->sc_dev)); 1070 wantinit = 1; 1071 continue; 1072 } 1073 1074 /* Receive interrupts. */ 1075 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1076 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1077 stge_rxintr(sc); 1078 if (isr & IS_RFDListEnd) { 1079 printf("%s: receive ring overflow\n", 1080 device_xname(&sc->sc_dev)); 1081 /* 1082 * XXX Should try to recover from this 1083 * XXX more gracefully. 1084 */ 1085 wantinit = 1; 1086 } 1087 } 1088 1089 /* Transmit interrupts. */ 1090 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1091 #ifdef STGE_EVENT_COUNTERS 1092 if (isr & IS_TxDMAComplete) 1093 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1094 #endif 1095 stge_txintr(sc); 1096 } 1097 1098 /* Statistics overflow. */ 1099 if (isr & IS_UpdateStats) 1100 stge_stats_update(sc); 1101 1102 /* Transmission errors. */ 1103 if (isr & IS_TxComplete) { 1104 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1105 for (;;) { 1106 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1107 STGE_TxStatus); 1108 if ((txstat & TS_TxComplete) == 0) 1109 break; 1110 if (txstat & TS_TxUnderrun) { 1111 sc->sc_txthresh++; 1112 if (sc->sc_txthresh > 0x0fff) 1113 sc->sc_txthresh = 0x0fff; 1114 printf("%s: transmit underrun, new " 1115 "threshold: %d bytes\n", 1116 device_xname(&sc->sc_dev), 1117 sc->sc_txthresh << 5); 1118 } 1119 if (txstat & TS_MaxCollisions) 1120 printf("%s: excessive collisions\n", 1121 device_xname(&sc->sc_dev)); 1122 } 1123 wantinit = 1; 1124 } 1125 1126 } 1127 1128 if (wantinit) 1129 stge_init(ifp); 1130 1131 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1132 sc->sc_IntEnable); 1133 1134 /* Try to get more packets going. */ 1135 stge_start(ifp); 1136 1137 return (1); 1138 } 1139 1140 /* 1141 * stge_txintr: 1142 * 1143 * Helper; handle transmit interrupts. 1144 */ 1145 static void 1146 stge_txintr(struct stge_softc *sc) 1147 { 1148 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1149 struct stge_descsoft *ds; 1150 uint64_t control; 1151 int i; 1152 1153 ifp->if_flags &= ~IFF_OACTIVE; 1154 1155 /* 1156 * Go through our Tx list and free mbufs for those 1157 * frames which have been transmitted. 1158 */ 1159 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1160 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1161 ds = &sc->sc_txsoft[i]; 1162 1163 STGE_CDTXSYNC(sc, i, 1164 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1165 1166 control = le64toh(sc->sc_txdescs[i].tfd_control); 1167 if ((control & TFD_TFDDone) == 0) 1168 break; 1169 1170 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1171 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1172 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1173 m_freem(ds->ds_mbuf); 1174 ds->ds_mbuf = NULL; 1175 } 1176 1177 /* Update the dirty transmit buffer pointer. */ 1178 sc->sc_txdirty = i; 1179 1180 /* 1181 * If there are no more pending transmissions, cancel the watchdog 1182 * timer. 1183 */ 1184 if (sc->sc_txpending == 0) 1185 ifp->if_timer = 0; 1186 } 1187 1188 /* 1189 * stge_rxintr: 1190 * 1191 * Helper; handle receive interrupts. 1192 */ 1193 static void 1194 stge_rxintr(struct stge_softc *sc) 1195 { 1196 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1197 struct stge_descsoft *ds; 1198 struct mbuf *m, *tailm; 1199 uint64_t status; 1200 int i, len; 1201 1202 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1203 ds = &sc->sc_rxsoft[i]; 1204 1205 STGE_CDRXSYNC(sc, i, 1206 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1207 1208 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1209 1210 if ((status & RFD_RFDDone) == 0) 1211 break; 1212 1213 if (__predict_false(sc->sc_rxdiscard)) { 1214 STGE_INIT_RXDESC(sc, i); 1215 if (status & RFD_FrameEnd) { 1216 /* Reset our state. */ 1217 sc->sc_rxdiscard = 0; 1218 } 1219 continue; 1220 } 1221 1222 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1223 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1224 1225 m = ds->ds_mbuf; 1226 1227 /* 1228 * Add a new receive buffer to the ring. 1229 */ 1230 if (stge_add_rxbuf(sc, i) != 0) { 1231 /* 1232 * Failed, throw away what we've done so 1233 * far, and discard the rest of the packet. 1234 */ 1235 ifp->if_ierrors++; 1236 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1237 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1238 STGE_INIT_RXDESC(sc, i); 1239 if ((status & RFD_FrameEnd) == 0) 1240 sc->sc_rxdiscard = 1; 1241 if (sc->sc_rxhead != NULL) 1242 m_freem(sc->sc_rxhead); 1243 STGE_RXCHAIN_RESET(sc); 1244 continue; 1245 } 1246 1247 #ifdef DIAGNOSTIC 1248 if (status & RFD_FrameStart) { 1249 KASSERT(sc->sc_rxhead == NULL); 1250 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1251 } 1252 #endif 1253 1254 STGE_RXCHAIN_LINK(sc, m); 1255 1256 /* 1257 * If this is not the end of the packet, keep 1258 * looking. 1259 */ 1260 if ((status & RFD_FrameEnd) == 0) { 1261 sc->sc_rxlen += m->m_len; 1262 continue; 1263 } 1264 1265 /* 1266 * Okay, we have the entire packet now... 1267 */ 1268 *sc->sc_rxtailp = NULL; 1269 m = sc->sc_rxhead; 1270 tailm = sc->sc_rxtail; 1271 1272 STGE_RXCHAIN_RESET(sc); 1273 1274 /* 1275 * If the packet had an error, drop it. Note we 1276 * count the error later in the periodic stats update. 1277 */ 1278 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1279 RFD_RxAlignmentError | RFD_RxFCSError | 1280 RFD_RxLengthError)) { 1281 m_freem(m); 1282 continue; 1283 } 1284 1285 /* 1286 * No errors. 1287 * 1288 * Note we have configured the chip to not include 1289 * the CRC at the end of the packet. 1290 */ 1291 len = RFD_RxDMAFrameLen(status); 1292 tailm->m_len = len - sc->sc_rxlen; 1293 1294 /* 1295 * If the packet is small enough to fit in a 1296 * single header mbuf, allocate one and copy 1297 * the data into it. This greatly reduces 1298 * memory consumption when we receive lots 1299 * of small packets. 1300 */ 1301 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1302 struct mbuf *nm; 1303 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1304 if (nm == NULL) { 1305 ifp->if_ierrors++; 1306 m_freem(m); 1307 continue; 1308 } 1309 nm->m_data += 2; 1310 nm->m_pkthdr.len = nm->m_len = len; 1311 m_copydata(m, 0, len, mtod(nm, void *)); 1312 m_freem(m); 1313 m = nm; 1314 } 1315 1316 /* 1317 * Set the incoming checksum information for the packet. 1318 */ 1319 if (status & RFD_IPDetected) { 1320 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1321 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1322 if (status & RFD_IPError) 1323 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1324 if (status & RFD_TCPDetected) { 1325 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1326 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1327 if (status & RFD_TCPError) 1328 m->m_pkthdr.csum_flags |= 1329 M_CSUM_TCP_UDP_BAD; 1330 } else if (status & RFD_UDPDetected) { 1331 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1332 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1333 if (status & RFD_UDPError) 1334 m->m_pkthdr.csum_flags |= 1335 M_CSUM_TCP_UDP_BAD; 1336 } 1337 } 1338 1339 m->m_pkthdr.rcvif = ifp; 1340 m->m_pkthdr.len = len; 1341 1342 #if NBPFILTER > 0 1343 /* 1344 * Pass this up to any BPF listeners, but only 1345 * pass if up the stack if it's for us. 1346 */ 1347 if (ifp->if_bpf) 1348 bpf_mtap(ifp->if_bpf, m); 1349 #endif /* NBPFILTER > 0 */ 1350 #ifdef STGE_VLAN_UNTAG 1351 /* 1352 * Check for VLAN tagged packets 1353 */ 1354 if (status & RFD_VLANDetected) 1355 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1356 1357 #endif 1358 #if 0 1359 if (status & RFD_VLANDetected) { 1360 struct ether_header *eh; 1361 u_int16_t etype; 1362 1363 eh = mtod(m, struct ether_header *); 1364 etype = ntohs(eh->ether_type); 1365 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1366 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1367 etype); 1368 } 1369 #endif 1370 /* Pass it on. */ 1371 (*ifp->if_input)(ifp, m); 1372 } 1373 1374 /* Update the receive pointer. */ 1375 sc->sc_rxptr = i; 1376 } 1377 1378 /* 1379 * stge_tick: 1380 * 1381 * One second timer, used to tick the MII. 1382 */ 1383 static void 1384 stge_tick(void *arg) 1385 { 1386 struct stge_softc *sc = arg; 1387 int s; 1388 1389 s = splnet(); 1390 mii_tick(&sc->sc_mii); 1391 stge_stats_update(sc); 1392 splx(s); 1393 1394 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1395 } 1396 1397 /* 1398 * stge_stats_update: 1399 * 1400 * Read the TC9021 statistics counters. 1401 */ 1402 static void 1403 stge_stats_update(struct stge_softc *sc) 1404 { 1405 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1406 bus_space_tag_t st = sc->sc_st; 1407 bus_space_handle_t sh = sc->sc_sh; 1408 1409 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1410 1411 ifp->if_ipackets += 1412 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1413 1414 ifp->if_ierrors += 1415 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1416 1417 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1418 1419 ifp->if_opackets += 1420 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1421 1422 ifp->if_collisions += 1423 bus_space_read_4(st, sh, STGE_LateCollisions) + 1424 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1425 bus_space_read_4(st, sh, STGE_SingleColFrames); 1426 1427 ifp->if_oerrors += 1428 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1429 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1430 } 1431 1432 /* 1433 * stge_reset: 1434 * 1435 * Perform a soft reset on the TC9021. 1436 */ 1437 static void 1438 stge_reset(struct stge_softc *sc) 1439 { 1440 uint32_t ac; 1441 int i; 1442 1443 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1444 1445 /* 1446 * Only assert RstOut if we're fiber. We need GMII clocks 1447 * to be present in order for the reset to complete on fiber 1448 * cards. 1449 */ 1450 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1451 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1452 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1453 (sc->sc_usefiber ? AC_RstOut : 0)); 1454 1455 delay(50000); 1456 1457 for (i = 0; i < STGE_TIMEOUT; i++) { 1458 delay(5000); 1459 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1460 AC_ResetBusy) == 0) 1461 break; 1462 } 1463 1464 if (i == STGE_TIMEOUT) 1465 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1466 1467 delay(1000); 1468 } 1469 1470 /* 1471 * stge_init: [ ifnet interface function ] 1472 * 1473 * Initialize the interface. Must be called at splnet(). 1474 */ 1475 static int 1476 stge_init(struct ifnet *ifp) 1477 { 1478 struct stge_softc *sc = ifp->if_softc; 1479 bus_space_tag_t st = sc->sc_st; 1480 bus_space_handle_t sh = sc->sc_sh; 1481 struct stge_descsoft *ds; 1482 int i, error = 0; 1483 1484 /* 1485 * Cancel any pending I/O. 1486 */ 1487 stge_stop(ifp, 0); 1488 1489 /* 1490 * Reset the chip to a known state. 1491 */ 1492 stge_reset(sc); 1493 1494 /* 1495 * Initialize the transmit descriptor ring. 1496 */ 1497 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1498 for (i = 0; i < STGE_NTXDESC; i++) { 1499 sc->sc_txdescs[i].tfd_next = htole64( 1500 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1501 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1502 } 1503 sc->sc_txpending = 0; 1504 sc->sc_txdirty = 0; 1505 sc->sc_txlast = STGE_NTXDESC - 1; 1506 1507 /* 1508 * Initialize the receive descriptor and receive job 1509 * descriptor rings. 1510 */ 1511 for (i = 0; i < STGE_NRXDESC; i++) { 1512 ds = &sc->sc_rxsoft[i]; 1513 if (ds->ds_mbuf == NULL) { 1514 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1515 printf("%s: unable to allocate or map rx " 1516 "buffer %d, error = %d\n", 1517 device_xname(&sc->sc_dev), i, error); 1518 /* 1519 * XXX Should attempt to run with fewer receive 1520 * XXX buffers instead of just failing. 1521 */ 1522 stge_rxdrain(sc); 1523 goto out; 1524 } 1525 } else 1526 STGE_INIT_RXDESC(sc, i); 1527 } 1528 sc->sc_rxptr = 0; 1529 sc->sc_rxdiscard = 0; 1530 STGE_RXCHAIN_RESET(sc); 1531 1532 /* Set the station address. */ 1533 for (i = 0; i < 6; i++) 1534 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1535 CLLADDR(ifp->if_sadl)[i]); 1536 1537 /* 1538 * Set the statistics masks. Disable all the RMON stats, 1539 * and disable selected stats in the non-RMON stats registers. 1540 */ 1541 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1542 bus_space_write_4(st, sh, STGE_StatisticsMask, 1543 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1544 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1545 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1546 (1U << 21)); 1547 1548 /* Set up the receive filter. */ 1549 stge_set_filter(sc); 1550 1551 /* 1552 * Give the transmit and receive ring to the chip. 1553 */ 1554 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1555 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1556 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1557 1558 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1559 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1560 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1561 1562 /* 1563 * Initialize the Tx auto-poll period. It's OK to make this number 1564 * large (255 is the max, but we use 127) -- we explicitly kick the 1565 * transmit engine when there's actually a packet. 1566 */ 1567 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1568 1569 /* ..and the Rx auto-poll period. */ 1570 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1571 1572 /* Initialize the Tx start threshold. */ 1573 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1574 1575 /* RX DMA thresholds, from linux */ 1576 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1577 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1578 1579 /* 1580 * Initialize the Rx DMA interrupt control register. We 1581 * request an interrupt after every incoming packet, but 1582 * defer it for 32us (64 * 512 ns). When the number of 1583 * interrupts pending reaches 8, we stop deferring the 1584 * interrupt, and signal it immediately. 1585 */ 1586 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1587 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1588 1589 /* 1590 * Initialize the interrupt mask. 1591 */ 1592 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1593 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1594 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1595 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1596 1597 /* 1598 * Configure the DMA engine. 1599 * XXX Should auto-tune TxBurstLimit. 1600 */ 1601 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1602 DMAC_TxBurstLimit(3)); 1603 1604 /* 1605 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1606 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1607 * empty again. 1608 */ 1609 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1610 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1611 1612 /* 1613 * Set the maximum frame size. 1614 */ 1615 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1616 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1617 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1618 ETHER_VLAN_ENCAP_LEN : 0)); 1619 1620 /* 1621 * Initialize MacCtrl -- do it before setting the media, 1622 * as setting the media will actually program the register. 1623 * 1624 * Note: We have to poke the IFS value before poking 1625 * anything else. 1626 */ 1627 sc->sc_MACCtrl = MC_IFSSelect(0); 1628 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1629 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1630 #ifdef STGE_VLAN_UNTAG 1631 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1632 #endif 1633 1634 if (sc->sc_rev >= 6) { /* >= B.2 */ 1635 /* Multi-frag frame bug work-around. */ 1636 bus_space_write_2(st, sh, STGE_DebugCtrl, 1637 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1638 1639 /* Tx Poll Now bug work-around. */ 1640 bus_space_write_2(st, sh, STGE_DebugCtrl, 1641 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1642 /* XXX ? from linux */ 1643 bus_space_write_2(st, sh, STGE_DebugCtrl, 1644 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1645 } 1646 1647 /* 1648 * Set the current media. 1649 */ 1650 if ((error = ether_mediachange(ifp)) != 0) 1651 goto out; 1652 1653 /* 1654 * Start the one second MII clock. 1655 */ 1656 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1657 1658 /* 1659 * ...all done! 1660 */ 1661 ifp->if_flags |= IFF_RUNNING; 1662 ifp->if_flags &= ~IFF_OACTIVE; 1663 1664 out: 1665 if (error) 1666 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1667 return (error); 1668 } 1669 1670 /* 1671 * stge_drain: 1672 * 1673 * Drain the receive queue. 1674 */ 1675 static void 1676 stge_rxdrain(struct stge_softc *sc) 1677 { 1678 struct stge_descsoft *ds; 1679 int i; 1680 1681 for (i = 0; i < STGE_NRXDESC; i++) { 1682 ds = &sc->sc_rxsoft[i]; 1683 if (ds->ds_mbuf != NULL) { 1684 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1685 ds->ds_mbuf->m_next = NULL; 1686 m_freem(ds->ds_mbuf); 1687 ds->ds_mbuf = NULL; 1688 } 1689 } 1690 } 1691 1692 /* 1693 * stge_stop: [ ifnet interface function ] 1694 * 1695 * Stop transmission on the interface. 1696 */ 1697 static void 1698 stge_stop(struct ifnet *ifp, int disable) 1699 { 1700 struct stge_softc *sc = ifp->if_softc; 1701 struct stge_descsoft *ds; 1702 int i; 1703 1704 /* 1705 * Stop the one second clock. 1706 */ 1707 callout_stop(&sc->sc_tick_ch); 1708 1709 /* Down the MII. */ 1710 mii_down(&sc->sc_mii); 1711 1712 /* 1713 * Disable interrupts. 1714 */ 1715 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1716 1717 /* 1718 * Stop receiver, transmitter, and stats update. 1719 */ 1720 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1721 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1722 1723 /* 1724 * Stop the transmit and receive DMA. 1725 */ 1726 stge_dma_wait(sc); 1727 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1728 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1729 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1731 1732 /* 1733 * Release any queued transmit buffers. 1734 */ 1735 for (i = 0; i < STGE_NTXDESC; i++) { 1736 ds = &sc->sc_txsoft[i]; 1737 if (ds->ds_mbuf != NULL) { 1738 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1739 m_freem(ds->ds_mbuf); 1740 ds->ds_mbuf = NULL; 1741 } 1742 } 1743 1744 /* 1745 * Mark the interface down and cancel the watchdog timer. 1746 */ 1747 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1748 ifp->if_timer = 0; 1749 1750 if (disable) 1751 stge_rxdrain(sc); 1752 } 1753 1754 static int 1755 stge_eeprom_wait(struct stge_softc *sc) 1756 { 1757 int i; 1758 1759 for (i = 0; i < STGE_TIMEOUT; i++) { 1760 delay(1000); 1761 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1762 EC_EepromBusy) == 0) 1763 return (0); 1764 } 1765 return (1); 1766 } 1767 1768 /* 1769 * stge_read_eeprom: 1770 * 1771 * Read data from the serial EEPROM. 1772 */ 1773 static void 1774 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1775 { 1776 1777 if (stge_eeprom_wait(sc)) 1778 printf("%s: EEPROM failed to come ready\n", 1779 device_xname(&sc->sc_dev)); 1780 1781 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1782 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1783 if (stge_eeprom_wait(sc)) 1784 printf("%s: EEPROM read timed out\n", 1785 device_xname(&sc->sc_dev)); 1786 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1787 } 1788 1789 /* 1790 * stge_add_rxbuf: 1791 * 1792 * Add a receive buffer to the indicated descriptor. 1793 */ 1794 static int 1795 stge_add_rxbuf(struct stge_softc *sc, int idx) 1796 { 1797 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1798 struct mbuf *m; 1799 int error; 1800 1801 MGETHDR(m, M_DONTWAIT, MT_DATA); 1802 if (m == NULL) 1803 return (ENOBUFS); 1804 1805 MCLGET(m, M_DONTWAIT); 1806 if ((m->m_flags & M_EXT) == 0) { 1807 m_freem(m); 1808 return (ENOBUFS); 1809 } 1810 1811 m->m_data = m->m_ext.ext_buf + 2; 1812 m->m_len = MCLBYTES - 2; 1813 1814 if (ds->ds_mbuf != NULL) 1815 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1816 1817 ds->ds_mbuf = m; 1818 1819 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1820 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1821 if (error) { 1822 printf("%s: can't load rx DMA map %d, error = %d\n", 1823 device_xname(&sc->sc_dev), idx, error); 1824 panic("stge_add_rxbuf"); /* XXX */ 1825 } 1826 1827 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1828 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1829 1830 STGE_INIT_RXDESC(sc, idx); 1831 1832 return (0); 1833 } 1834 1835 /* 1836 * stge_set_filter: 1837 * 1838 * Set up the receive filter. 1839 */ 1840 static void 1841 stge_set_filter(struct stge_softc *sc) 1842 { 1843 struct ethercom *ec = &sc->sc_ethercom; 1844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1845 struct ether_multi *enm; 1846 struct ether_multistep step; 1847 uint32_t crc; 1848 uint32_t mchash[2]; 1849 1850 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1851 if (ifp->if_flags & IFF_BROADCAST) 1852 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1853 1854 /* XXX: ST1023 only works in promiscuous mode */ 1855 if (sc->sc_stge1023) 1856 ifp->if_flags |= IFF_PROMISC; 1857 1858 if (ifp->if_flags & IFF_PROMISC) { 1859 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1860 goto allmulti; 1861 } 1862 1863 /* 1864 * Set up the multicast address filter by passing all multicast 1865 * addresses through a CRC generator, and then using the low-order 1866 * 6 bits as an index into the 64 bit multicast hash table. The 1867 * high order bits select the register, while the rest of the bits 1868 * select the bit within the register. 1869 */ 1870 1871 memset(mchash, 0, sizeof(mchash)); 1872 1873 ETHER_FIRST_MULTI(step, ec, enm); 1874 if (enm == NULL) 1875 goto done; 1876 1877 while (enm != NULL) { 1878 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1879 /* 1880 * We must listen to a range of multicast addresses. 1881 * For now, just accept all multicasts, rather than 1882 * trying to set only those filter bits needed to match 1883 * the range. (At this time, the only use of address 1884 * ranges is for IP multicast routing, for which the 1885 * range is big enough to require all bits set.) 1886 */ 1887 goto allmulti; 1888 } 1889 1890 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1891 1892 /* Just want the 6 least significant bits. */ 1893 crc &= 0x3f; 1894 1895 /* Set the corresponding bit in the hash table. */ 1896 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1897 1898 ETHER_NEXT_MULTI(step, enm); 1899 } 1900 1901 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1902 1903 ifp->if_flags &= ~IFF_ALLMULTI; 1904 goto done; 1905 1906 allmulti: 1907 ifp->if_flags |= IFF_ALLMULTI; 1908 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1909 1910 done: 1911 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1912 /* 1913 * Program the multicast hash table. 1914 */ 1915 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1916 mchash[0]); 1917 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1918 mchash[1]); 1919 } 1920 1921 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1922 sc->sc_ReceiveMode); 1923 } 1924 1925 /* 1926 * stge_mii_readreg: [mii interface function] 1927 * 1928 * Read a PHY register on the MII of the TC9021. 1929 */ 1930 static int 1931 stge_mii_readreg(device_t self, int phy, int reg) 1932 { 1933 1934 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1935 } 1936 1937 /* 1938 * stge_mii_writereg: [mii interface function] 1939 * 1940 * Write a PHY register on the MII of the TC9021. 1941 */ 1942 static void 1943 stge_mii_writereg(device_t self, int phy, int reg, int val) 1944 { 1945 1946 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1947 } 1948 1949 /* 1950 * stge_mii_statchg: [mii interface function] 1951 * 1952 * Callback from MII layer when media changes. 1953 */ 1954 static void 1955 stge_mii_statchg(device_t self) 1956 { 1957 struct stge_softc *sc = device_private(self); 1958 1959 if (sc->sc_mii.mii_media_active & IFM_FDX) 1960 sc->sc_MACCtrl |= MC_DuplexSelect; 1961 else 1962 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1963 1964 /* XXX 802.1x flow-control? */ 1965 1966 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1967 } 1968 1969 /* 1970 * sste_mii_bitbang_read: [mii bit-bang interface function] 1971 * 1972 * Read the MII serial port for the MII bit-bang module. 1973 */ 1974 static uint32_t 1975 stge_mii_bitbang_read(device_t self) 1976 { 1977 struct stge_softc *sc = device_private(self); 1978 1979 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1980 } 1981 1982 /* 1983 * stge_mii_bitbang_write: [mii big-bang interface function] 1984 * 1985 * Write the MII serial port for the MII bit-bang module. 1986 */ 1987 static void 1988 stge_mii_bitbang_write(device_t self, uint32_t val) 1989 { 1990 struct stge_softc *sc = device_private(self); 1991 1992 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1993 val | sc->sc_PhyCtrl); 1994 } 1995