1 /* $NetBSD: if_stge.c,v 1.56 2013/03/30 03:21:07 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.56 2013/03/30 03:21:07 christos Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int); 282 static void stge_mii_writereg(device_t, int, int, int); 283 static void stge_mii_statchg(struct ifnet *); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 pci_intr_handle_t ih; 380 const char *intrstr = NULL; 381 bus_space_tag_t iot, memt; 382 bus_space_handle_t ioh, memh; 383 bus_dma_segment_t seg; 384 prop_data_t data; 385 int ioh_valid, memh_valid; 386 int i, rseg, error; 387 const struct stge_product *sp; 388 uint8_t enaddr[ETHER_ADDR_LEN]; 389 390 callout_init(&sc->sc_tick_ch, 0); 391 392 sp = stge_lookup(pa); 393 if (sp == NULL) { 394 printf("\n"); 395 panic("ste_attach: impossible"); 396 } 397 398 sc->sc_rev = PCI_REVISION(pa->pa_class); 399 400 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 401 402 /* 403 * Map the device. 404 */ 405 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 406 PCI_MAPREG_TYPE_IO, 0, 407 &iot, &ioh, NULL, NULL) == 0); 408 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 409 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 410 &memt, &memh, NULL, NULL) == 0); 411 412 if (memh_valid) { 413 sc->sc_st = memt; 414 sc->sc_sh = memh; 415 } else if (ioh_valid) { 416 sc->sc_st = iot; 417 sc->sc_sh = ioh; 418 } else { 419 aprint_error_dev(self, "unable to map device registers\n"); 420 return; 421 } 422 423 sc->sc_dmat = pa->pa_dmat; 424 425 /* Enable bus mastering. */ 426 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 427 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 428 PCI_COMMAND_MASTER_ENABLE); 429 430 /* power up chip */ 431 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 432 error != EOPNOTSUPP) { 433 aprint_error_dev(self, "cannot activate %d\n", 434 error); 435 return; 436 } 437 /* 438 * Map and establish our interrupt. 439 */ 440 if (pci_intr_map(pa, &ih)) { 441 aprint_error_dev(self, "unable to map interrupt\n"); 442 return; 443 } 444 intrstr = pci_intr_string(pc, ih); 445 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 446 if (sc->sc_ih == NULL) { 447 aprint_error_dev(self, "unable to establish interrupt"); 448 if (intrstr != NULL) 449 aprint_error(" at %s", intrstr); 450 aprint_error("\n"); 451 return; 452 } 453 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 454 455 /* 456 * Allocate the control data structures, and create and load the 457 * DMA map for it. 458 */ 459 if ((error = bus_dmamem_alloc(sc->sc_dmat, 460 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 461 0)) != 0) { 462 aprint_error_dev(self, 463 "unable to allocate control data, error = %d\n", 464 error); 465 goto fail_0; 466 } 467 468 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 469 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 470 BUS_DMA_COHERENT)) != 0) { 471 aprint_error_dev(self, 472 "unable to map control data, error = %d\n", 473 error); 474 goto fail_1; 475 } 476 477 if ((error = bus_dmamap_create(sc->sc_dmat, 478 sizeof(struct stge_control_data), 1, 479 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 480 aprint_error_dev(self, 481 "unable to create control data DMA map, error = %d\n", 482 error); 483 goto fail_2; 484 } 485 486 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 487 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 488 0)) != 0) { 489 aprint_error_dev(self, 490 "unable to load control data DMA map, error = %d\n", 491 error); 492 goto fail_3; 493 } 494 495 /* 496 * Create the transmit buffer DMA maps. Note that rev B.3 497 * and earlier seem to have a bug regarding multi-fragment 498 * packets. We need to limit the number of Tx segments on 499 * such chips to 1. 500 */ 501 for (i = 0; i < STGE_NTXDESC; i++) { 502 if ((error = bus_dmamap_create(sc->sc_dmat, 503 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 504 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 505 aprint_error_dev(self, 506 "unable to create tx DMA map %d, error = %d\n", 507 i, error); 508 goto fail_4; 509 } 510 } 511 512 /* 513 * Create the receive buffer DMA maps. 514 */ 515 for (i = 0; i < STGE_NRXDESC; i++) { 516 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 517 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 518 aprint_error_dev(self, 519 "unable to create rx DMA map %d, error = %d\n", 520 i, error); 521 goto fail_5; 522 } 523 sc->sc_rxsoft[i].ds_mbuf = NULL; 524 } 525 526 /* 527 * Determine if we're copper or fiber. It affects how we 528 * reset the card. 529 */ 530 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 531 AC_PhyMedia) 532 sc->sc_usefiber = 1; 533 else 534 sc->sc_usefiber = 0; 535 536 /* 537 * Reset the chip to a known state. 538 */ 539 stge_reset(sc); 540 541 /* 542 * Reading the station address from the EEPROM doesn't seem 543 * to work, at least on my sample boards. Instead, since 544 * the reset sequence does AutoInit, read it from the station 545 * address registers. For Sundance 1023 you can only read it 546 * from EEPROM. 547 */ 548 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 549 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 550 STGE_StationAddress0) & 0xff; 551 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress0) >> 8; 553 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress1) & 0xff; 555 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress1) >> 8; 557 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress2) & 0xff; 559 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress2) >> 8; 561 sc->sc_stge1023 = 0; 562 } else { 563 data = prop_dictionary_get(device_properties(self), 564 "mac-address"); 565 if (data != NULL) { 566 /* 567 * Try to get the station address from device 568 * properties first, in case the EEPROM is missing. 569 */ 570 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 571 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 572 (void)memcpy(enaddr, prop_data_data_nocopy(data), 573 ETHER_ADDR_LEN); 574 } else { 575 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 576 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 577 stge_read_eeprom(sc, 578 STGE_EEPROM_StationAddress0 + i, 579 &myaddr[i]); 580 myaddr[i] = le16toh(myaddr[i]); 581 } 582 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 583 } 584 sc->sc_stge1023 = 1; 585 } 586 587 aprint_normal_dev(self, "Ethernet address %s\n", 588 ether_sprintf(enaddr)); 589 590 /* 591 * Read some important bits from the PhyCtrl register. 592 */ 593 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 594 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595 596 /* 597 * Initialize our media structures and probe the MII. 598 */ 599 sc->sc_mii.mii_ifp = ifp; 600 sc->sc_mii.mii_readreg = stge_mii_readreg; 601 sc->sc_mii.mii_writereg = stge_mii_writereg; 602 sc->sc_mii.mii_statchg = stge_mii_statchg; 603 sc->sc_ethercom.ec_mii = &sc->sc_mii; 604 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 605 ether_mediastatus); 606 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 607 MII_OFFSET_ANY, MIIF_DOPAUSE); 608 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 609 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 610 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 611 } else 612 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 613 614 ifp = &sc->sc_ethercom.ec_if; 615 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 616 ifp->if_softc = sc; 617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 618 ifp->if_ioctl = stge_ioctl; 619 ifp->if_start = stge_start; 620 ifp->if_watchdog = stge_watchdog; 621 ifp->if_init = stge_init; 622 ifp->if_stop = stge_stop; 623 IFQ_SET_READY(&ifp->if_snd); 624 625 /* 626 * The manual recommends disabling early transmit, so we 627 * do. It's disabled anyway, if using IP checksumming, 628 * since the entire packet must be in the FIFO in order 629 * for the chip to perform the checksum. 630 */ 631 sc->sc_txthresh = 0x0fff; 632 633 /* 634 * Disable MWI if the PCI layer tells us to. 635 */ 636 sc->sc_DMACtrl = 0; 637 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 638 sc->sc_DMACtrl |= DMAC_MWIDisable; 639 640 /* 641 * We can support 802.1Q VLAN-sized frames and jumbo 642 * Ethernet frames. 643 * 644 * XXX Figure out how to do hw-assisted VLAN tagging in 645 * XXX a reasonable way on this chip. 646 */ 647 sc->sc_ethercom.ec_capabilities |= 648 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 649 ETHERCAP_VLAN_HWTAGGING; 650 651 /* 652 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 653 */ 654 sc->sc_ethercom.ec_if.if_capabilities |= 655 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 656 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 657 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 658 659 /* 660 * Attach the interface. 661 */ 662 if_attach(ifp); 663 ether_ifattach(ifp, enaddr); 664 665 #ifdef STGE_EVENT_COUNTERS 666 /* 667 * Attach event counters. 668 */ 669 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "txstall"); 671 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 672 NULL, device_xname(self), "txdmaintr"); 673 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 674 NULL, device_xname(self), "txindintr"); 675 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 676 NULL, device_xname(self), "rxintr"); 677 678 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 679 NULL, device_xname(self), "txseg1"); 680 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 681 NULL, device_xname(self), "txseg2"); 682 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "txseg3"); 684 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "txseg4"); 686 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "txseg5"); 688 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "txsegmore"); 690 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 691 NULL, device_xname(self), "txcopy"); 692 693 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 694 NULL, device_xname(self), "rxipsum"); 695 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 696 NULL, device_xname(self), "rxtcpsum"); 697 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 698 NULL, device_xname(self), "rxudpsum"); 699 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 700 NULL, device_xname(self), "txipsum"); 701 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 702 NULL, device_xname(self), "txtcpsum"); 703 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 704 NULL, device_xname(self), "txudpsum"); 705 #endif /* STGE_EVENT_COUNTERS */ 706 707 /* 708 * Make sure the interface is shutdown during reboot. 709 */ 710 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 711 pmf_class_network_register(self, ifp); 712 else 713 aprint_error_dev(self, "couldn't establish power handler\n"); 714 715 return; 716 717 /* 718 * Free any resources we've allocated during the failed attach 719 * attempt. Do this in reverse order and fall through. 720 */ 721 fail_5: 722 for (i = 0; i < STGE_NRXDESC; i++) { 723 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 724 bus_dmamap_destroy(sc->sc_dmat, 725 sc->sc_rxsoft[i].ds_dmamap); 726 } 727 fail_4: 728 for (i = 0; i < STGE_NTXDESC; i++) { 729 if (sc->sc_txsoft[i].ds_dmamap != NULL) 730 bus_dmamap_destroy(sc->sc_dmat, 731 sc->sc_txsoft[i].ds_dmamap); 732 } 733 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 734 fail_3: 735 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 736 fail_2: 737 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 738 sizeof(struct stge_control_data)); 739 fail_1: 740 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 741 fail_0: 742 return; 743 } 744 745 /* 746 * stge_shutdown: 747 * 748 * Make sure the interface is stopped at reboot time. 749 */ 750 static bool 751 stge_shutdown(device_t self, int howto) 752 { 753 struct stge_softc *sc = device_private(self); 754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 755 756 stge_stop(ifp, 1); 757 stge_reset(sc); 758 return true; 759 } 760 761 static void 762 stge_dma_wait(struct stge_softc *sc) 763 { 764 int i; 765 766 for (i = 0; i < STGE_TIMEOUT; i++) { 767 delay(2); 768 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 769 DMAC_TxDMAInProg) == 0) 770 break; 771 } 772 773 if (i == STGE_TIMEOUT) 774 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 775 } 776 777 /* 778 * stge_start: [ifnet interface function] 779 * 780 * Start packet transmission on the interface. 781 */ 782 static void 783 stge_start(struct ifnet *ifp) 784 { 785 struct stge_softc *sc = ifp->if_softc; 786 struct mbuf *m0; 787 struct stge_descsoft *ds; 788 struct stge_tfd *tfd; 789 bus_dmamap_t dmamap; 790 int error, firsttx, nexttx, opending, seg, totlen; 791 uint64_t csum_flags; 792 793 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 794 return; 795 796 /* 797 * Remember the previous number of pending transmissions 798 * and the first descriptor we will use. 799 */ 800 opending = sc->sc_txpending; 801 firsttx = STGE_NEXTTX(sc->sc_txlast); 802 803 /* 804 * Loop through the send queue, setting up transmit descriptors 805 * until we drain the queue, or use up all available transmit 806 * descriptors. 807 */ 808 for (;;) { 809 struct m_tag *mtag; 810 uint64_t tfc; 811 812 /* 813 * Grab a packet off the queue. 814 */ 815 IFQ_POLL(&ifp->if_snd, m0); 816 if (m0 == NULL) 817 break; 818 819 /* 820 * Leave one unused descriptor at the end of the 821 * list to prevent wrapping completely around. 822 */ 823 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 824 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 825 break; 826 } 827 828 /* 829 * See if we have any VLAN stuff. 830 */ 831 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 832 833 /* 834 * Get the last and next available transmit descriptor. 835 */ 836 nexttx = STGE_NEXTTX(sc->sc_txlast); 837 tfd = &sc->sc_txdescs[nexttx]; 838 ds = &sc->sc_txsoft[nexttx]; 839 840 dmamap = ds->ds_dmamap; 841 842 /* 843 * Load the DMA map. If this fails, the packet either 844 * didn't fit in the alloted number of segments, or we 845 * were short on resources. For the too-many-segments 846 * case, we simply report an error and drop the packet, 847 * since we can't sanely copy a jumbo packet to a single 848 * buffer. 849 */ 850 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 851 BUS_DMA_NOWAIT); 852 if (error) { 853 if (error == EFBIG) { 854 printf("%s: Tx packet consumes too many " 855 "DMA segments, dropping...\n", 856 device_xname(sc->sc_dev)); 857 IFQ_DEQUEUE(&ifp->if_snd, m0); 858 m_freem(m0); 859 continue; 860 } 861 /* 862 * Short on resources, just stop for now. 863 */ 864 break; 865 } 866 867 IFQ_DEQUEUE(&ifp->if_snd, m0); 868 869 /* 870 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 871 */ 872 873 /* Sync the DMA map. */ 874 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 875 BUS_DMASYNC_PREWRITE); 876 877 /* Initialize the fragment list. */ 878 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 879 tfd->tfd_frags[seg].frag_word0 = 880 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 881 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 882 totlen += dmamap->dm_segs[seg].ds_len; 883 } 884 885 #ifdef STGE_EVENT_COUNTERS 886 switch (dmamap->dm_nsegs) { 887 case 1: 888 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 889 break; 890 case 2: 891 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 892 break; 893 case 3: 894 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 895 break; 896 case 4: 897 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 898 break; 899 case 5: 900 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 901 break; 902 default: 903 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 904 break; 905 } 906 #endif /* STGE_EVENT_COUNTERS */ 907 908 /* 909 * Initialize checksumming flags in the descriptor. 910 * Byte-swap constants so the compiler can optimize. 911 */ 912 csum_flags = 0; 913 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 914 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 915 csum_flags |= TFD_IPChecksumEnable; 916 } 917 918 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 919 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 920 csum_flags |= TFD_TCPChecksumEnable; 921 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 922 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 923 csum_flags |= TFD_UDPChecksumEnable; 924 } 925 926 /* 927 * Initialize the descriptor and give it to the chip. 928 * Check to see if we have a VLAN tag to insert. 929 */ 930 931 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 932 TFD_FragCount(seg) | csum_flags | 933 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 934 TFD_TxDMAIndicate : 0); 935 if (mtag) { 936 #if 0 937 struct ether_header *eh = 938 mtod(m0, struct ether_header *); 939 u_int16_t etype = ntohs(eh->ether_type); 940 printf("%s: xmit (tag %d) etype %x\n", 941 ifp->if_xname, *mtod(n, int *), etype); 942 #endif 943 tfc |= TFD_VLANTagInsert | 944 #ifdef STGE_VLAN_CFI 945 TFD_CFI | 946 #endif 947 TFD_VID(VLAN_TAG_VALUE(mtag)); 948 } 949 tfd->tfd_control = htole64(tfc); 950 951 /* Sync the descriptor. */ 952 STGE_CDTXSYNC(sc, nexttx, 953 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 954 955 /* 956 * Kick the transmit DMA logic. 957 */ 958 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 959 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 960 961 /* 962 * Store a pointer to the packet so we can free it later. 963 */ 964 ds->ds_mbuf = m0; 965 966 /* Advance the tx pointer. */ 967 sc->sc_txpending++; 968 sc->sc_txlast = nexttx; 969 970 /* 971 * Pass the packet to any BPF listeners. 972 */ 973 bpf_mtap(ifp, m0); 974 } 975 976 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 977 /* No more slots left; notify upper layer. */ 978 ifp->if_flags |= IFF_OACTIVE; 979 } 980 981 if (sc->sc_txpending != opending) { 982 /* 983 * We enqueued packets. If the transmitter was idle, 984 * reset the txdirty pointer. 985 */ 986 if (opending == 0) 987 sc->sc_txdirty = firsttx; 988 989 /* Set a watchdog timer in case the chip flakes out. */ 990 ifp->if_timer = 5; 991 } 992 } 993 994 /* 995 * stge_watchdog: [ifnet interface function] 996 * 997 * Watchdog timer handler. 998 */ 999 static void 1000 stge_watchdog(struct ifnet *ifp) 1001 { 1002 struct stge_softc *sc = ifp->if_softc; 1003 1004 /* 1005 * Sweep up first, since we don't interrupt every frame. 1006 */ 1007 stge_txintr(sc); 1008 if (sc->sc_txpending != 0) { 1009 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1010 ifp->if_oerrors++; 1011 1012 (void) stge_init(ifp); 1013 1014 /* Try to get more packets going. */ 1015 stge_start(ifp); 1016 } 1017 } 1018 1019 /* 1020 * stge_ioctl: [ifnet interface function] 1021 * 1022 * Handle control requests from the operator. 1023 */ 1024 static int 1025 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1026 { 1027 struct stge_softc *sc = ifp->if_softc; 1028 int s, error; 1029 1030 s = splnet(); 1031 1032 error = ether_ioctl(ifp, cmd, data); 1033 if (error == ENETRESET) { 1034 error = 0; 1035 1036 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1037 ; 1038 else if (ifp->if_flags & IFF_RUNNING) { 1039 /* 1040 * Multicast list has changed; set the hardware filter 1041 * accordingly. 1042 */ 1043 stge_set_filter(sc); 1044 } 1045 } 1046 1047 /* Try to get more packets going. */ 1048 stge_start(ifp); 1049 1050 splx(s); 1051 return (error); 1052 } 1053 1054 /* 1055 * stge_intr: 1056 * 1057 * Interrupt service routine. 1058 */ 1059 static int 1060 stge_intr(void *arg) 1061 { 1062 struct stge_softc *sc = arg; 1063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1064 uint32_t txstat; 1065 int wantinit; 1066 uint16_t isr; 1067 1068 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1069 IS_InterruptStatus) == 0) 1070 return (0); 1071 1072 for (wantinit = 0; wantinit == 0;) { 1073 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1074 if ((isr & sc->sc_IntEnable) == 0) 1075 break; 1076 1077 /* Host interface errors. */ 1078 if (isr & IS_HostError) { 1079 printf("%s: Host interface error\n", 1080 device_xname(sc->sc_dev)); 1081 wantinit = 1; 1082 continue; 1083 } 1084 1085 /* Receive interrupts. */ 1086 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1087 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1088 stge_rxintr(sc); 1089 if (isr & IS_RFDListEnd) { 1090 printf("%s: receive ring overflow\n", 1091 device_xname(sc->sc_dev)); 1092 /* 1093 * XXX Should try to recover from this 1094 * XXX more gracefully. 1095 */ 1096 wantinit = 1; 1097 } 1098 } 1099 1100 /* Transmit interrupts. */ 1101 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1102 #ifdef STGE_EVENT_COUNTERS 1103 if (isr & IS_TxDMAComplete) 1104 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1105 #endif 1106 stge_txintr(sc); 1107 } 1108 1109 /* Statistics overflow. */ 1110 if (isr & IS_UpdateStats) 1111 stge_stats_update(sc); 1112 1113 /* Transmission errors. */ 1114 if (isr & IS_TxComplete) { 1115 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1116 for (;;) { 1117 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1118 STGE_TxStatus); 1119 if ((txstat & TS_TxComplete) == 0) 1120 break; 1121 if (txstat & TS_TxUnderrun) { 1122 sc->sc_txthresh++; 1123 if (sc->sc_txthresh > 0x0fff) 1124 sc->sc_txthresh = 0x0fff; 1125 printf("%s: transmit underrun, new " 1126 "threshold: %d bytes\n", 1127 device_xname(sc->sc_dev), 1128 sc->sc_txthresh << 5); 1129 } 1130 if (txstat & TS_MaxCollisions) 1131 printf("%s: excessive collisions\n", 1132 device_xname(sc->sc_dev)); 1133 } 1134 wantinit = 1; 1135 } 1136 1137 } 1138 1139 if (wantinit) 1140 stge_init(ifp); 1141 1142 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1143 sc->sc_IntEnable); 1144 1145 /* Try to get more packets going. */ 1146 stge_start(ifp); 1147 1148 return (1); 1149 } 1150 1151 /* 1152 * stge_txintr: 1153 * 1154 * Helper; handle transmit interrupts. 1155 */ 1156 static void 1157 stge_txintr(struct stge_softc *sc) 1158 { 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 struct stge_descsoft *ds; 1161 uint64_t control; 1162 int i; 1163 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 1166 /* 1167 * Go through our Tx list and free mbufs for those 1168 * frames which have been transmitted. 1169 */ 1170 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1171 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1172 ds = &sc->sc_txsoft[i]; 1173 1174 STGE_CDTXSYNC(sc, i, 1175 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1176 1177 control = le64toh(sc->sc_txdescs[i].tfd_control); 1178 if ((control & TFD_TFDDone) == 0) 1179 break; 1180 1181 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1182 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1184 m_freem(ds->ds_mbuf); 1185 ds->ds_mbuf = NULL; 1186 } 1187 1188 /* Update the dirty transmit buffer pointer. */ 1189 sc->sc_txdirty = i; 1190 1191 /* 1192 * If there are no more pending transmissions, cancel the watchdog 1193 * timer. 1194 */ 1195 if (sc->sc_txpending == 0) 1196 ifp->if_timer = 0; 1197 } 1198 1199 /* 1200 * stge_rxintr: 1201 * 1202 * Helper; handle receive interrupts. 1203 */ 1204 static void 1205 stge_rxintr(struct stge_softc *sc) 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 struct stge_descsoft *ds; 1209 struct mbuf *m, *tailm; 1210 uint64_t status; 1211 int i, len; 1212 1213 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1214 ds = &sc->sc_rxsoft[i]; 1215 1216 STGE_CDRXSYNC(sc, i, 1217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1218 1219 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1220 1221 if ((status & RFD_RFDDone) == 0) 1222 break; 1223 1224 if (__predict_false(sc->sc_rxdiscard)) { 1225 STGE_INIT_RXDESC(sc, i); 1226 if (status & RFD_FrameEnd) { 1227 /* Reset our state. */ 1228 sc->sc_rxdiscard = 0; 1229 } 1230 continue; 1231 } 1232 1233 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1234 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1235 1236 m = ds->ds_mbuf; 1237 1238 /* 1239 * Add a new receive buffer to the ring. 1240 */ 1241 if (stge_add_rxbuf(sc, i) != 0) { 1242 /* 1243 * Failed, throw away what we've done so 1244 * far, and discard the rest of the packet. 1245 */ 1246 ifp->if_ierrors++; 1247 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1248 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1249 STGE_INIT_RXDESC(sc, i); 1250 if ((status & RFD_FrameEnd) == 0) 1251 sc->sc_rxdiscard = 1; 1252 if (sc->sc_rxhead != NULL) 1253 m_freem(sc->sc_rxhead); 1254 STGE_RXCHAIN_RESET(sc); 1255 continue; 1256 } 1257 1258 #ifdef DIAGNOSTIC 1259 if (status & RFD_FrameStart) { 1260 KASSERT(sc->sc_rxhead == NULL); 1261 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1262 } 1263 #endif 1264 1265 STGE_RXCHAIN_LINK(sc, m); 1266 1267 /* 1268 * If this is not the end of the packet, keep 1269 * looking. 1270 */ 1271 if ((status & RFD_FrameEnd) == 0) { 1272 sc->sc_rxlen += m->m_len; 1273 continue; 1274 } 1275 1276 /* 1277 * Okay, we have the entire packet now... 1278 */ 1279 *sc->sc_rxtailp = NULL; 1280 m = sc->sc_rxhead; 1281 tailm = sc->sc_rxtail; 1282 1283 STGE_RXCHAIN_RESET(sc); 1284 1285 /* 1286 * If the packet had an error, drop it. Note we 1287 * count the error later in the periodic stats update. 1288 */ 1289 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1290 RFD_RxAlignmentError | RFD_RxFCSError | 1291 RFD_RxLengthError)) { 1292 m_freem(m); 1293 continue; 1294 } 1295 1296 /* 1297 * No errors. 1298 * 1299 * Note we have configured the chip to not include 1300 * the CRC at the end of the packet. 1301 */ 1302 len = RFD_RxDMAFrameLen(status); 1303 tailm->m_len = len - sc->sc_rxlen; 1304 1305 /* 1306 * If the packet is small enough to fit in a 1307 * single header mbuf, allocate one and copy 1308 * the data into it. This greatly reduces 1309 * memory consumption when we receive lots 1310 * of small packets. 1311 */ 1312 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1313 struct mbuf *nm; 1314 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1315 if (nm == NULL) { 1316 ifp->if_ierrors++; 1317 m_freem(m); 1318 continue; 1319 } 1320 nm->m_data += 2; 1321 nm->m_pkthdr.len = nm->m_len = len; 1322 m_copydata(m, 0, len, mtod(nm, void *)); 1323 m_freem(m); 1324 m = nm; 1325 } 1326 1327 /* 1328 * Set the incoming checksum information for the packet. 1329 */ 1330 if (status & RFD_IPDetected) { 1331 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1332 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1333 if (status & RFD_IPError) 1334 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1335 if (status & RFD_TCPDetected) { 1336 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1337 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1338 if (status & RFD_TCPError) 1339 m->m_pkthdr.csum_flags |= 1340 M_CSUM_TCP_UDP_BAD; 1341 } else if (status & RFD_UDPDetected) { 1342 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1343 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1344 if (status & RFD_UDPError) 1345 m->m_pkthdr.csum_flags |= 1346 M_CSUM_TCP_UDP_BAD; 1347 } 1348 } 1349 1350 m->m_pkthdr.rcvif = ifp; 1351 m->m_pkthdr.len = len; 1352 1353 /* 1354 * Pass this up to any BPF listeners, but only 1355 * pass if up the stack if it's for us. 1356 */ 1357 bpf_mtap(ifp, m); 1358 #ifdef STGE_VLAN_UNTAG 1359 /* 1360 * Check for VLAN tagged packets 1361 */ 1362 if (status & RFD_VLANDetected) 1363 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1364 1365 #endif 1366 #if 0 1367 if (status & RFD_VLANDetected) { 1368 struct ether_header *eh; 1369 u_int16_t etype; 1370 1371 eh = mtod(m, struct ether_header *); 1372 etype = ntohs(eh->ether_type); 1373 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1374 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1375 etype); 1376 } 1377 #endif 1378 /* Pass it on. */ 1379 (*ifp->if_input)(ifp, m); 1380 } 1381 1382 /* Update the receive pointer. */ 1383 sc->sc_rxptr = i; 1384 } 1385 1386 /* 1387 * stge_tick: 1388 * 1389 * One second timer, used to tick the MII. 1390 */ 1391 static void 1392 stge_tick(void *arg) 1393 { 1394 struct stge_softc *sc = arg; 1395 int s; 1396 1397 s = splnet(); 1398 mii_tick(&sc->sc_mii); 1399 stge_stats_update(sc); 1400 splx(s); 1401 1402 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1403 } 1404 1405 /* 1406 * stge_stats_update: 1407 * 1408 * Read the TC9021 statistics counters. 1409 */ 1410 static void 1411 stge_stats_update(struct stge_softc *sc) 1412 { 1413 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1414 bus_space_tag_t st = sc->sc_st; 1415 bus_space_handle_t sh = sc->sc_sh; 1416 1417 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1418 1419 ifp->if_ipackets += 1420 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1421 1422 ifp->if_ierrors += 1423 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1424 1425 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1426 1427 ifp->if_opackets += 1428 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1429 1430 ifp->if_collisions += 1431 bus_space_read_4(st, sh, STGE_LateCollisions) + 1432 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1433 bus_space_read_4(st, sh, STGE_SingleColFrames); 1434 1435 ifp->if_oerrors += 1436 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1437 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1438 } 1439 1440 /* 1441 * stge_reset: 1442 * 1443 * Perform a soft reset on the TC9021. 1444 */ 1445 static void 1446 stge_reset(struct stge_softc *sc) 1447 { 1448 uint32_t ac; 1449 int i; 1450 1451 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1452 1453 /* 1454 * Only assert RstOut if we're fiber. We need GMII clocks 1455 * to be present in order for the reset to complete on fiber 1456 * cards. 1457 */ 1458 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1459 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1460 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1461 (sc->sc_usefiber ? AC_RstOut : 0)); 1462 1463 delay(50000); 1464 1465 for (i = 0; i < STGE_TIMEOUT; i++) { 1466 delay(5000); 1467 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1468 AC_ResetBusy) == 0) 1469 break; 1470 } 1471 1472 if (i == STGE_TIMEOUT) 1473 printf("%s: reset failed to complete\n", 1474 device_xname(sc->sc_dev)); 1475 1476 delay(1000); 1477 } 1478 1479 /* 1480 * stge_init: [ ifnet interface function ] 1481 * 1482 * Initialize the interface. Must be called at splnet(). 1483 */ 1484 static int 1485 stge_init(struct ifnet *ifp) 1486 { 1487 struct stge_softc *sc = ifp->if_softc; 1488 bus_space_tag_t st = sc->sc_st; 1489 bus_space_handle_t sh = sc->sc_sh; 1490 struct stge_descsoft *ds; 1491 int i, error = 0; 1492 1493 /* 1494 * Cancel any pending I/O. 1495 */ 1496 stge_stop(ifp, 0); 1497 1498 /* 1499 * Reset the chip to a known state. 1500 */ 1501 stge_reset(sc); 1502 1503 /* 1504 * Initialize the transmit descriptor ring. 1505 */ 1506 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1507 for (i = 0; i < STGE_NTXDESC; i++) { 1508 sc->sc_txdescs[i].tfd_next = htole64( 1509 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1510 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1511 } 1512 sc->sc_txpending = 0; 1513 sc->sc_txdirty = 0; 1514 sc->sc_txlast = STGE_NTXDESC - 1; 1515 1516 /* 1517 * Initialize the receive descriptor and receive job 1518 * descriptor rings. 1519 */ 1520 for (i = 0; i < STGE_NRXDESC; i++) { 1521 ds = &sc->sc_rxsoft[i]; 1522 if (ds->ds_mbuf == NULL) { 1523 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1524 printf("%s: unable to allocate or map rx " 1525 "buffer %d, error = %d\n", 1526 device_xname(sc->sc_dev), i, error); 1527 /* 1528 * XXX Should attempt to run with fewer receive 1529 * XXX buffers instead of just failing. 1530 */ 1531 stge_rxdrain(sc); 1532 goto out; 1533 } 1534 } else 1535 STGE_INIT_RXDESC(sc, i); 1536 } 1537 sc->sc_rxptr = 0; 1538 sc->sc_rxdiscard = 0; 1539 STGE_RXCHAIN_RESET(sc); 1540 1541 /* Set the station address. */ 1542 for (i = 0; i < 6; i++) 1543 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1544 CLLADDR(ifp->if_sadl)[i]); 1545 1546 /* 1547 * Set the statistics masks. Disable all the RMON stats, 1548 * and disable selected stats in the non-RMON stats registers. 1549 */ 1550 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1551 bus_space_write_4(st, sh, STGE_StatisticsMask, 1552 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1553 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1554 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1555 (1U << 21)); 1556 1557 /* Set up the receive filter. */ 1558 stge_set_filter(sc); 1559 1560 /* 1561 * Give the transmit and receive ring to the chip. 1562 */ 1563 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1564 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1565 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1566 1567 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1568 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1569 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1570 1571 /* 1572 * Initialize the Tx auto-poll period. It's OK to make this number 1573 * large (255 is the max, but we use 127) -- we explicitly kick the 1574 * transmit engine when there's actually a packet. 1575 */ 1576 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1577 1578 /* ..and the Rx auto-poll period. */ 1579 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1580 1581 /* Initialize the Tx start threshold. */ 1582 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1583 1584 /* RX DMA thresholds, from linux */ 1585 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1586 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1587 1588 /* 1589 * Initialize the Rx DMA interrupt control register. We 1590 * request an interrupt after every incoming packet, but 1591 * defer it for 32us (64 * 512 ns). When the number of 1592 * interrupts pending reaches 8, we stop deferring the 1593 * interrupt, and signal it immediately. 1594 */ 1595 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1596 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1597 1598 /* 1599 * Initialize the interrupt mask. 1600 */ 1601 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1602 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1603 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1604 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1605 1606 /* 1607 * Configure the DMA engine. 1608 * XXX Should auto-tune TxBurstLimit. 1609 */ 1610 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1611 DMAC_TxBurstLimit(3)); 1612 1613 /* 1614 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1615 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1616 * empty again. 1617 */ 1618 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1619 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1620 1621 /* 1622 * Set the maximum frame size. 1623 */ 1624 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1625 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1626 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1627 ETHER_VLAN_ENCAP_LEN : 0)); 1628 1629 /* 1630 * Initialize MacCtrl -- do it before setting the media, 1631 * as setting the media will actually program the register. 1632 * 1633 * Note: We have to poke the IFS value before poking 1634 * anything else. 1635 */ 1636 sc->sc_MACCtrl = MC_IFSSelect(0); 1637 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1638 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1639 #ifdef STGE_VLAN_UNTAG 1640 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1641 #endif 1642 1643 if (sc->sc_rev >= 6) { /* >= B.2 */ 1644 /* Multi-frag frame bug work-around. */ 1645 bus_space_write_2(st, sh, STGE_DebugCtrl, 1646 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1647 1648 /* Tx Poll Now bug work-around. */ 1649 bus_space_write_2(st, sh, STGE_DebugCtrl, 1650 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1651 /* XXX ? from linux */ 1652 bus_space_write_2(st, sh, STGE_DebugCtrl, 1653 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1654 } 1655 1656 /* 1657 * Set the current media. 1658 */ 1659 if ((error = ether_mediachange(ifp)) != 0) 1660 goto out; 1661 1662 /* 1663 * Start the one second MII clock. 1664 */ 1665 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1666 1667 /* 1668 * ...all done! 1669 */ 1670 ifp->if_flags |= IFF_RUNNING; 1671 ifp->if_flags &= ~IFF_OACTIVE; 1672 1673 out: 1674 if (error) 1675 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1676 return (error); 1677 } 1678 1679 /* 1680 * stge_drain: 1681 * 1682 * Drain the receive queue. 1683 */ 1684 static void 1685 stge_rxdrain(struct stge_softc *sc) 1686 { 1687 struct stge_descsoft *ds; 1688 int i; 1689 1690 for (i = 0; i < STGE_NRXDESC; i++) { 1691 ds = &sc->sc_rxsoft[i]; 1692 if (ds->ds_mbuf != NULL) { 1693 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1694 ds->ds_mbuf->m_next = NULL; 1695 m_freem(ds->ds_mbuf); 1696 ds->ds_mbuf = NULL; 1697 } 1698 } 1699 } 1700 1701 /* 1702 * stge_stop: [ ifnet interface function ] 1703 * 1704 * Stop transmission on the interface. 1705 */ 1706 static void 1707 stge_stop(struct ifnet *ifp, int disable) 1708 { 1709 struct stge_softc *sc = ifp->if_softc; 1710 struct stge_descsoft *ds; 1711 int i; 1712 1713 /* 1714 * Stop the one second clock. 1715 */ 1716 callout_stop(&sc->sc_tick_ch); 1717 1718 /* Down the MII. */ 1719 mii_down(&sc->sc_mii); 1720 1721 /* 1722 * Disable interrupts. 1723 */ 1724 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1725 1726 /* 1727 * Stop receiver, transmitter, and stats update. 1728 */ 1729 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1730 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1731 1732 /* 1733 * Stop the transmit and receive DMA. 1734 */ 1735 stge_dma_wait(sc); 1736 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1737 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1738 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1739 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1740 1741 /* 1742 * Release any queued transmit buffers. 1743 */ 1744 for (i = 0; i < STGE_NTXDESC; i++) { 1745 ds = &sc->sc_txsoft[i]; 1746 if (ds->ds_mbuf != NULL) { 1747 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1748 m_freem(ds->ds_mbuf); 1749 ds->ds_mbuf = NULL; 1750 } 1751 } 1752 1753 /* 1754 * Mark the interface down and cancel the watchdog timer. 1755 */ 1756 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1757 ifp->if_timer = 0; 1758 1759 if (disable) 1760 stge_rxdrain(sc); 1761 } 1762 1763 static int 1764 stge_eeprom_wait(struct stge_softc *sc) 1765 { 1766 int i; 1767 1768 for (i = 0; i < STGE_TIMEOUT; i++) { 1769 delay(1000); 1770 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1771 EC_EepromBusy) == 0) 1772 return (0); 1773 } 1774 return (1); 1775 } 1776 1777 /* 1778 * stge_read_eeprom: 1779 * 1780 * Read data from the serial EEPROM. 1781 */ 1782 static void 1783 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1784 { 1785 1786 if (stge_eeprom_wait(sc)) 1787 printf("%s: EEPROM failed to come ready\n", 1788 device_xname(sc->sc_dev)); 1789 1790 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1791 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1792 if (stge_eeprom_wait(sc)) 1793 printf("%s: EEPROM read timed out\n", 1794 device_xname(sc->sc_dev)); 1795 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1796 } 1797 1798 /* 1799 * stge_add_rxbuf: 1800 * 1801 * Add a receive buffer to the indicated descriptor. 1802 */ 1803 static int 1804 stge_add_rxbuf(struct stge_softc *sc, int idx) 1805 { 1806 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1807 struct mbuf *m; 1808 int error; 1809 1810 MGETHDR(m, M_DONTWAIT, MT_DATA); 1811 if (m == NULL) 1812 return (ENOBUFS); 1813 1814 MCLGET(m, M_DONTWAIT); 1815 if ((m->m_flags & M_EXT) == 0) { 1816 m_freem(m); 1817 return (ENOBUFS); 1818 } 1819 1820 m->m_data = m->m_ext.ext_buf + 2; 1821 m->m_len = MCLBYTES - 2; 1822 1823 if (ds->ds_mbuf != NULL) 1824 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1825 1826 ds->ds_mbuf = m; 1827 1828 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1829 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1830 if (error) { 1831 printf("%s: can't load rx DMA map %d, error = %d\n", 1832 device_xname(sc->sc_dev), idx, error); 1833 panic("stge_add_rxbuf"); /* XXX */ 1834 } 1835 1836 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1837 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1838 1839 STGE_INIT_RXDESC(sc, idx); 1840 1841 return (0); 1842 } 1843 1844 /* 1845 * stge_set_filter: 1846 * 1847 * Set up the receive filter. 1848 */ 1849 static void 1850 stge_set_filter(struct stge_softc *sc) 1851 { 1852 struct ethercom *ec = &sc->sc_ethercom; 1853 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1854 struct ether_multi *enm; 1855 struct ether_multistep step; 1856 uint32_t crc; 1857 uint32_t mchash[2]; 1858 1859 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1860 if (ifp->if_flags & IFF_BROADCAST) 1861 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1862 1863 /* XXX: ST1023 only works in promiscuous mode */ 1864 if (sc->sc_stge1023) 1865 ifp->if_flags |= IFF_PROMISC; 1866 1867 if (ifp->if_flags & IFF_PROMISC) { 1868 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1869 goto allmulti; 1870 } 1871 1872 /* 1873 * Set up the multicast address filter by passing all multicast 1874 * addresses through a CRC generator, and then using the low-order 1875 * 6 bits as an index into the 64 bit multicast hash table. The 1876 * high order bits select the register, while the rest of the bits 1877 * select the bit within the register. 1878 */ 1879 1880 memset(mchash, 0, sizeof(mchash)); 1881 1882 ETHER_FIRST_MULTI(step, ec, enm); 1883 if (enm == NULL) 1884 goto done; 1885 1886 while (enm != NULL) { 1887 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1888 /* 1889 * We must listen to a range of multicast addresses. 1890 * For now, just accept all multicasts, rather than 1891 * trying to set only those filter bits needed to match 1892 * the range. (At this time, the only use of address 1893 * ranges is for IP multicast routing, for which the 1894 * range is big enough to require all bits set.) 1895 */ 1896 goto allmulti; 1897 } 1898 1899 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1900 1901 /* Just want the 6 least significant bits. */ 1902 crc &= 0x3f; 1903 1904 /* Set the corresponding bit in the hash table. */ 1905 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1906 1907 ETHER_NEXT_MULTI(step, enm); 1908 } 1909 1910 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1911 1912 ifp->if_flags &= ~IFF_ALLMULTI; 1913 goto done; 1914 1915 allmulti: 1916 ifp->if_flags |= IFF_ALLMULTI; 1917 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1918 1919 done: 1920 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1921 /* 1922 * Program the multicast hash table. 1923 */ 1924 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1925 mchash[0]); 1926 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1927 mchash[1]); 1928 } 1929 1930 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1931 sc->sc_ReceiveMode); 1932 } 1933 1934 /* 1935 * stge_mii_readreg: [mii interface function] 1936 * 1937 * Read a PHY register on the MII of the TC9021. 1938 */ 1939 static int 1940 stge_mii_readreg(device_t self, int phy, int reg) 1941 { 1942 1943 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1944 } 1945 1946 /* 1947 * stge_mii_writereg: [mii interface function] 1948 * 1949 * Write a PHY register on the MII of the TC9021. 1950 */ 1951 static void 1952 stge_mii_writereg(device_t self, int phy, int reg, int val) 1953 { 1954 1955 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1956 } 1957 1958 /* 1959 * stge_mii_statchg: [mii interface function] 1960 * 1961 * Callback from MII layer when media changes. 1962 */ 1963 static void 1964 stge_mii_statchg(struct ifnet *ifp) 1965 { 1966 struct stge_softc *sc = ifp->if_softc; 1967 1968 if (sc->sc_mii.mii_media_active & IFM_FDX) 1969 sc->sc_MACCtrl |= MC_DuplexSelect; 1970 else 1971 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1972 1973 /* XXX 802.1x flow-control? */ 1974 1975 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1976 } 1977 1978 /* 1979 * sste_mii_bitbang_read: [mii bit-bang interface function] 1980 * 1981 * Read the MII serial port for the MII bit-bang module. 1982 */ 1983 static uint32_t 1984 stge_mii_bitbang_read(device_t self) 1985 { 1986 struct stge_softc *sc = device_private(self); 1987 1988 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1989 } 1990 1991 /* 1992 * stge_mii_bitbang_write: [mii big-bang interface function] 1993 * 1994 * Write the MII serial port for the MII bit-bang module. 1995 */ 1996 static void 1997 stge_mii_bitbang_write(device_t self, uint32_t val) 1998 { 1999 struct stge_softc *sc = device_private(self); 2000 2001 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2002 val | sc->sc_PhyCtrl); 2003 } 2004