1 /* $NetBSD: if_stge.c,v 1.45 2008/04/28 20:23:55 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.45 2008/04/28 20:23:55 martin Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/mii/mii_bitbang.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_stgereg.h> 77 78 /* #define STGE_CU_BUG 1 */ 79 #define STGE_VLAN_UNTAG 1 80 /* #define STGE_VLAN_CFI 1 */ 81 82 /* 83 * Transmit descriptor list size. 84 */ 85 #define STGE_NTXDESC 256 86 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 87 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 88 89 /* 90 * Receive descriptor list size. 91 */ 92 #define STGE_NRXDESC 256 93 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 94 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 95 96 /* 97 * Only interrupt every N frames. Must be a power-of-two. 98 */ 99 #define STGE_TXINTR_SPACING 16 100 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 101 102 /* 103 * Control structures are DMA'd to the TC9021 chip. We allocate them in 104 * a single clump that maps to a single DMA segment to make several things 105 * easier. 106 */ 107 struct stge_control_data { 108 /* 109 * The transmit descriptors. 110 */ 111 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 112 113 /* 114 * The receive descriptors. 115 */ 116 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 117 }; 118 119 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 120 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 121 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 122 123 /* 124 * Software state for transmit and receive jobs. 125 */ 126 struct stge_descsoft { 127 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 128 bus_dmamap_t ds_dmamap; /* our DMA map */ 129 }; 130 131 /* 132 * Software state per device. 133 */ 134 struct stge_softc { 135 struct device sc_dev; /* generic device information */ 136 bus_space_tag_t sc_st; /* bus space tag */ 137 bus_space_handle_t sc_sh; /* bus space handle */ 138 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 139 struct ethercom sc_ethercom; /* ethernet common data */ 140 void *sc_sdhook; /* shutdown hook */ 141 int sc_rev; /* silicon revision */ 142 143 void *sc_ih; /* interrupt cookie */ 144 145 struct mii_data sc_mii; /* MII/media information */ 146 147 callout_t sc_tick_ch; /* tick callout */ 148 149 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 150 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 151 152 /* 153 * Software state for transmit and receive descriptors. 154 */ 155 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 156 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 157 158 /* 159 * Control data structures. 160 */ 161 struct stge_control_data *sc_control_data; 162 #define sc_txdescs sc_control_data->scd_txdescs 163 #define sc_rxdescs sc_control_data->scd_rxdescs 164 165 #ifdef STGE_EVENT_COUNTERS 166 /* 167 * Event counters. 168 */ 169 struct evcnt sc_ev_txstall; /* Tx stalled */ 170 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 171 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 172 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 173 174 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 175 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 176 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 177 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 178 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 179 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 180 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 181 182 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 183 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 184 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 185 186 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 187 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 188 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 189 #endif /* STGE_EVENT_COUNTERS */ 190 191 int sc_txpending; /* number of Tx requests pending */ 192 int sc_txdirty; /* first dirty Tx descriptor */ 193 int sc_txlast; /* last used Tx descriptor */ 194 195 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 196 int sc_rxdiscard; 197 int sc_rxlen; 198 struct mbuf *sc_rxhead; 199 struct mbuf *sc_rxtail; 200 struct mbuf **sc_rxtailp; 201 202 int sc_txthresh; /* Tx threshold */ 203 uint32_t sc_usefiber:1; /* if we're fiber */ 204 uint32_t sc_stge1023:1; /* are we a 1023 */ 205 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 206 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 207 uint16_t sc_IntEnable; /* prototype IntEnable register */ 208 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 209 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 210 }; 211 212 #define STGE_RXCHAIN_RESET(sc) \ 213 do { \ 214 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 215 *(sc)->sc_rxtailp = NULL; \ 216 (sc)->sc_rxlen = 0; \ 217 } while (/*CONSTCOND*/0) 218 219 #define STGE_RXCHAIN_LINK(sc, m) \ 220 do { \ 221 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 222 (sc)->sc_rxtailp = &(m)->m_next; \ 223 } while (/*CONSTCOND*/0) 224 225 #ifdef STGE_EVENT_COUNTERS 226 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 227 #else 228 #define STGE_EVCNT_INCR(ev) /* nothing */ 229 #endif 230 231 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 232 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 233 234 #define STGE_CDTXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 237 238 #define STGE_CDRXSYNC(sc, x, ops) \ 239 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 240 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 241 242 #define STGE_INIT_RXDESC(sc, x) \ 243 do { \ 244 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 245 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 246 \ 247 /* \ 248 * Note: We scoot the packet forward 2 bytes in the buffer \ 249 * so that the payload after the Ethernet header is aligned \ 250 * to a 4-byte boundary. \ 251 */ \ 252 __rfd->rfd_frag.frag_word0 = \ 253 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 254 FRAG_LEN(MCLBYTES - 2)); \ 255 __rfd->rfd_next = \ 256 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 257 __rfd->rfd_status = 0; \ 258 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 259 } while (/*CONSTCOND*/0) 260 261 #define STGE_TIMEOUT 1000 262 263 static void stge_start(struct ifnet *); 264 static void stge_watchdog(struct ifnet *); 265 static int stge_ioctl(struct ifnet *, u_long, void *); 266 static int stge_init(struct ifnet *); 267 static void stge_stop(struct ifnet *, int); 268 269 static void stge_shutdown(void *); 270 271 static void stge_reset(struct stge_softc *); 272 static void stge_rxdrain(struct stge_softc *); 273 static int stge_add_rxbuf(struct stge_softc *, int); 274 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 275 static void stge_tick(void *); 276 277 static void stge_stats_update(struct stge_softc *); 278 279 static void stge_set_filter(struct stge_softc *); 280 281 static int stge_intr(void *); 282 static void stge_txintr(struct stge_softc *); 283 static void stge_rxintr(struct stge_softc *); 284 285 static int stge_mii_readreg(device_t, int, int); 286 static void stge_mii_writereg(device_t, int, int, int); 287 static void stge_mii_statchg(device_t); 288 289 static int stge_match(device_t, struct cfdata *, void *); 290 static void stge_attach(device_t, device_t, void *); 291 292 int stge_copy_small = 0; 293 294 CFATTACH_DECL(stge, sizeof(struct stge_softc), 295 stge_match, stge_attach, NULL, NULL); 296 297 static uint32_t stge_mii_bitbang_read(device_t); 298 static void stge_mii_bitbang_write(device_t, uint32_t); 299 300 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 301 stge_mii_bitbang_read, 302 stge_mii_bitbang_write, 303 { 304 PC_MgmtData, /* MII_BIT_MDO */ 305 PC_MgmtData, /* MII_BIT_MDI */ 306 PC_MgmtClk, /* MII_BIT_MDC */ 307 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 308 0, /* MII_BIT_DIR_PHY_HOST */ 309 } 310 }; 311 312 /* 313 * Devices supported by this driver. 314 */ 315 static const struct stge_product { 316 pci_vendor_id_t stge_vendor; 317 pci_product_id_t stge_product; 318 const char *stge_name; 319 } stge_products[] = { 320 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 321 "Sundance ST-1023 Gigabit Ethernet" }, 322 323 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 324 "Sundance ST-2021 Gigabit Ethernet" }, 325 326 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 327 "Tamarack TC9021 Gigabit Ethernet" }, 328 329 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 330 "Tamarack TC9021 Gigabit Ethernet" }, 331 332 /* 333 * The Sundance sample boards use the Sundance vendor ID, 334 * but the Tamarack product ID. 335 */ 336 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 337 "Sundance TC9021 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 340 "Sundance TC9021 Gigabit Ethernet" }, 341 342 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 343 "D-Link DL-4000 Gigabit Ethernet" }, 344 345 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 346 "Antares Gigabit Ethernet" }, 347 348 { 0, 0, 349 NULL }, 350 }; 351 352 static const struct stge_product * 353 stge_lookup(const struct pci_attach_args *pa) 354 { 355 const struct stge_product *sp; 356 357 for (sp = stge_products; sp->stge_name != NULL; sp++) { 358 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 359 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 360 return (sp); 361 } 362 return (NULL); 363 } 364 365 static int 366 stge_match(device_t parent, struct cfdata *cf, void *aux) 367 { 368 struct pci_attach_args *pa = aux; 369 370 if (stge_lookup(pa) != NULL) 371 return (1); 372 373 return (0); 374 } 375 376 static void 377 stge_attach(device_t parent, device_t self, void *aux) 378 { 379 struct stge_softc *sc = device_private(self); 380 struct pci_attach_args *pa = aux; 381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pci_intr_handle_t ih; 384 const char *intrstr = NULL; 385 bus_space_tag_t iot, memt; 386 bus_space_handle_t ioh, memh; 387 bus_dma_segment_t seg; 388 int ioh_valid, memh_valid; 389 int i, rseg, error; 390 const struct stge_product *sp; 391 uint8_t enaddr[ETHER_ADDR_LEN]; 392 393 callout_init(&sc->sc_tick_ch, 0); 394 395 sp = stge_lookup(pa); 396 if (sp == NULL) { 397 printf("\n"); 398 panic("ste_attach: impossible"); 399 } 400 401 sc->sc_rev = PCI_REVISION(pa->pa_class); 402 403 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 404 405 /* 406 * Map the device. 407 */ 408 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 409 PCI_MAPREG_TYPE_IO, 0, 410 &iot, &ioh, NULL, NULL) == 0); 411 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 412 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 413 &memt, &memh, NULL, NULL) == 0); 414 415 if (memh_valid) { 416 sc->sc_st = memt; 417 sc->sc_sh = memh; 418 } else if (ioh_valid) { 419 sc->sc_st = iot; 420 sc->sc_sh = ioh; 421 } else { 422 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 423 return; 424 } 425 426 sc->sc_dmat = pa->pa_dmat; 427 428 /* Enable bus mastering. */ 429 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 430 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 431 PCI_COMMAND_MASTER_ENABLE); 432 433 /* power up chip */ 434 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 435 error != EOPNOTSUPP) { 436 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 437 error); 438 return; 439 } 440 /* 441 * Map and establish our interrupt. 442 */ 443 if (pci_intr_map(pa, &ih)) { 444 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 445 return; 446 } 447 intrstr = pci_intr_string(pc, ih); 448 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 449 if (sc->sc_ih == NULL) { 450 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 451 if (intrstr != NULL) 452 printf(" at %s", intrstr); 453 printf("\n"); 454 return; 455 } 456 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 457 458 /* 459 * Allocate the control data structures, and create and load the 460 * DMA map for it. 461 */ 462 if ((error = bus_dmamem_alloc(sc->sc_dmat, 463 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 464 0)) != 0) { 465 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 466 error); 467 goto fail_0; 468 } 469 470 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 471 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 472 BUS_DMA_COHERENT)) != 0) { 473 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 474 error); 475 goto fail_1; 476 } 477 478 if ((error = bus_dmamap_create(sc->sc_dmat, 479 sizeof(struct stge_control_data), 1, 480 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 481 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 482 "error = %d\n", error); 483 goto fail_2; 484 } 485 486 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 487 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 488 0)) != 0) { 489 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 490 error); 491 goto fail_3; 492 } 493 494 /* 495 * Create the transmit buffer DMA maps. Note that rev B.3 496 * and earlier seem to have a bug regarding multi-fragment 497 * packets. We need to limit the number of Tx segments on 498 * such chips to 1. 499 */ 500 for (i = 0; i < STGE_NTXDESC; i++) { 501 if ((error = bus_dmamap_create(sc->sc_dmat, 502 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 503 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 504 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 505 "error = %d\n", i, error); 506 goto fail_4; 507 } 508 } 509 510 /* 511 * Create the receive buffer DMA maps. 512 */ 513 for (i = 0; i < STGE_NRXDESC; i++) { 514 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 515 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 516 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 517 "error = %d\n", i, error); 518 goto fail_5; 519 } 520 sc->sc_rxsoft[i].ds_mbuf = NULL; 521 } 522 523 /* 524 * Determine if we're copper or fiber. It affects how we 525 * reset the card. 526 */ 527 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 528 AC_PhyMedia) 529 sc->sc_usefiber = 1; 530 else 531 sc->sc_usefiber = 0; 532 533 /* 534 * Reset the chip to a known state. 535 */ 536 stge_reset(sc); 537 538 /* 539 * Reading the station address from the EEPROM doesn't seem 540 * to work, at least on my sample boards. Instead, since 541 * the reset sequence does AutoInit, read it from the station 542 * address registers. For Sundance 1023 you can only read it 543 * from EEPROM. 544 */ 545 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 546 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 547 STGE_StationAddress0) & 0xff; 548 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 549 STGE_StationAddress0) >> 8; 550 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 551 STGE_StationAddress1) & 0xff; 552 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 553 STGE_StationAddress1) >> 8; 554 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 555 STGE_StationAddress2) & 0xff; 556 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 557 STGE_StationAddress2) >> 8; 558 sc->sc_stge1023 = 0; 559 } else { 560 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 561 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 562 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 563 &myaddr[i]); 564 myaddr[i] = le16toh(myaddr[i]); 565 } 566 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 567 sc->sc_stge1023 = 1; 568 } 569 570 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 571 ether_sprintf(enaddr)); 572 573 /* 574 * Read some important bits from the PhyCtrl register. 575 */ 576 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 577 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 578 579 /* 580 * Initialize our media structures and probe the MII. 581 */ 582 sc->sc_mii.mii_ifp = ifp; 583 sc->sc_mii.mii_readreg = stge_mii_readreg; 584 sc->sc_mii.mii_writereg = stge_mii_writereg; 585 sc->sc_mii.mii_statchg = stge_mii_statchg; 586 sc->sc_ethercom.ec_mii = &sc->sc_mii; 587 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 588 ether_mediastatus); 589 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 590 MII_OFFSET_ANY, MIIF_DOPAUSE); 591 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 592 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 593 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 594 } else 595 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 596 597 ifp = &sc->sc_ethercom.ec_if; 598 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 599 ifp->if_softc = sc; 600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 601 ifp->if_ioctl = stge_ioctl; 602 ifp->if_start = stge_start; 603 ifp->if_watchdog = stge_watchdog; 604 ifp->if_init = stge_init; 605 ifp->if_stop = stge_stop; 606 IFQ_SET_READY(&ifp->if_snd); 607 608 /* 609 * The manual recommends disabling early transmit, so we 610 * do. It's disabled anyway, if using IP checksumming, 611 * since the entire packet must be in the FIFO in order 612 * for the chip to perform the checksum. 613 */ 614 sc->sc_txthresh = 0x0fff; 615 616 /* 617 * Disable MWI if the PCI layer tells us to. 618 */ 619 sc->sc_DMACtrl = 0; 620 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 621 sc->sc_DMACtrl |= DMAC_MWIDisable; 622 623 /* 624 * We can support 802.1Q VLAN-sized frames and jumbo 625 * Ethernet frames. 626 * 627 * XXX Figure out how to do hw-assisted VLAN tagging in 628 * XXX a reasonable way on this chip. 629 */ 630 sc->sc_ethercom.ec_capabilities |= 631 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 632 ETHERCAP_VLAN_HWTAGGING; 633 634 /* 635 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 636 */ 637 sc->sc_ethercom.ec_if.if_capabilities |= 638 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 639 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 640 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 641 642 /* 643 * Attach the interface. 644 */ 645 if_attach(ifp); 646 ether_ifattach(ifp, enaddr); 647 648 #ifdef STGE_EVENT_COUNTERS 649 /* 650 * Attach event counters. 651 */ 652 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 653 NULL, device_xname(&sc->sc_dev), "txstall"); 654 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 655 NULL, device_xname(&sc->sc_dev), "txdmaintr"); 656 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 657 NULL, device_xname(&sc->sc_dev), "txindintr"); 658 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 659 NULL, device_xname(&sc->sc_dev), "rxintr"); 660 661 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 662 NULL, device_xname(&sc->sc_dev), "txseg1"); 663 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 664 NULL, device_xname(&sc->sc_dev), "txseg2"); 665 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 666 NULL, device_xname(&sc->sc_dev), "txseg3"); 667 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 668 NULL, device_xname(&sc->sc_dev), "txseg4"); 669 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 670 NULL, device_xname(&sc->sc_dev), "txseg5"); 671 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 672 NULL, device_xname(&sc->sc_dev), "txsegmore"); 673 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 674 NULL, device_xname(&sc->sc_dev), "txcopy"); 675 676 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 677 NULL, device_xname(&sc->sc_dev), "rxipsum"); 678 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 679 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 680 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 681 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 682 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 683 NULL, device_xname(&sc->sc_dev), "txipsum"); 684 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 685 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 686 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 687 NULL, device_xname(&sc->sc_dev), "txudpsum"); 688 #endif /* STGE_EVENT_COUNTERS */ 689 690 /* 691 * Make sure the interface is shutdown during reboot. 692 */ 693 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 694 if (sc->sc_sdhook == NULL) 695 printf("%s: WARNING: unable to establish shutdown hook\n", 696 device_xname(&sc->sc_dev)); 697 return; 698 699 /* 700 * Free any resources we've allocated during the failed attach 701 * attempt. Do this in reverse order and fall through. 702 */ 703 fail_5: 704 for (i = 0; i < STGE_NRXDESC; i++) { 705 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 706 bus_dmamap_destroy(sc->sc_dmat, 707 sc->sc_rxsoft[i].ds_dmamap); 708 } 709 fail_4: 710 for (i = 0; i < STGE_NTXDESC; i++) { 711 if (sc->sc_txsoft[i].ds_dmamap != NULL) 712 bus_dmamap_destroy(sc->sc_dmat, 713 sc->sc_txsoft[i].ds_dmamap); 714 } 715 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 716 fail_3: 717 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 718 fail_2: 719 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 720 sizeof(struct stge_control_data)); 721 fail_1: 722 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 723 fail_0: 724 return; 725 } 726 727 /* 728 * stge_shutdown: 729 * 730 * Make sure the interface is stopped at reboot time. 731 */ 732 static void 733 stge_shutdown(void *arg) 734 { 735 struct stge_softc *sc = arg; 736 737 stge_stop(&sc->sc_ethercom.ec_if, 1); 738 } 739 740 static void 741 stge_dma_wait(struct stge_softc *sc) 742 { 743 int i; 744 745 for (i = 0; i < STGE_TIMEOUT; i++) { 746 delay(2); 747 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 748 DMAC_TxDMAInProg) == 0) 749 break; 750 } 751 752 if (i == STGE_TIMEOUT) 753 printf("%s: DMA wait timed out\n", device_xname(&sc->sc_dev)); 754 } 755 756 /* 757 * stge_start: [ifnet interface function] 758 * 759 * Start packet transmission on the interface. 760 */ 761 static void 762 stge_start(struct ifnet *ifp) 763 { 764 struct stge_softc *sc = ifp->if_softc; 765 struct mbuf *m0; 766 struct stge_descsoft *ds; 767 struct stge_tfd *tfd; 768 bus_dmamap_t dmamap; 769 int error, firsttx, nexttx, opending, seg, totlen; 770 uint64_t csum_flags; 771 772 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 773 return; 774 775 /* 776 * Remember the previous number of pending transmissions 777 * and the first descriptor we will use. 778 */ 779 opending = sc->sc_txpending; 780 firsttx = STGE_NEXTTX(sc->sc_txlast); 781 782 /* 783 * Loop through the send queue, setting up transmit descriptors 784 * until we drain the queue, or use up all available transmit 785 * descriptors. 786 */ 787 for (;;) { 788 struct m_tag *mtag; 789 uint64_t tfc; 790 791 /* 792 * Grab a packet off the queue. 793 */ 794 IFQ_POLL(&ifp->if_snd, m0); 795 if (m0 == NULL) 796 break; 797 798 /* 799 * Leave one unused descriptor at the end of the 800 * list to prevent wrapping completely around. 801 */ 802 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 803 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 804 break; 805 } 806 807 /* 808 * See if we have any VLAN stuff. 809 */ 810 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 811 812 /* 813 * Get the last and next available transmit descriptor. 814 */ 815 nexttx = STGE_NEXTTX(sc->sc_txlast); 816 tfd = &sc->sc_txdescs[nexttx]; 817 ds = &sc->sc_txsoft[nexttx]; 818 819 dmamap = ds->ds_dmamap; 820 821 /* 822 * Load the DMA map. If this fails, the packet either 823 * didn't fit in the alloted number of segments, or we 824 * were short on resources. For the too-many-segments 825 * case, we simply report an error and drop the packet, 826 * since we can't sanely copy a jumbo packet to a single 827 * buffer. 828 */ 829 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 830 BUS_DMA_NOWAIT); 831 if (error) { 832 if (error == EFBIG) { 833 printf("%s: Tx packet consumes too many " 834 "DMA segments, dropping...\n", 835 device_xname(&sc->sc_dev)); 836 IFQ_DEQUEUE(&ifp->if_snd, m0); 837 m_freem(m0); 838 continue; 839 } 840 /* 841 * Short on resources, just stop for now. 842 */ 843 break; 844 } 845 846 IFQ_DEQUEUE(&ifp->if_snd, m0); 847 848 /* 849 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 850 */ 851 852 /* Sync the DMA map. */ 853 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 854 BUS_DMASYNC_PREWRITE); 855 856 /* Initialize the fragment list. */ 857 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 858 tfd->tfd_frags[seg].frag_word0 = 859 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 860 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 861 totlen += dmamap->dm_segs[seg].ds_len; 862 } 863 864 #ifdef STGE_EVENT_COUNTERS 865 switch (dmamap->dm_nsegs) { 866 case 1: 867 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 868 break; 869 case 2: 870 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 871 break; 872 case 3: 873 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 874 break; 875 case 4: 876 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 877 break; 878 case 5: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 880 break; 881 default: 882 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 883 break; 884 } 885 #endif /* STGE_EVENT_COUNTERS */ 886 887 /* 888 * Initialize checksumming flags in the descriptor. 889 * Byte-swap constants so the compiler can optimize. 890 */ 891 csum_flags = 0; 892 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 893 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 894 csum_flags |= TFD_IPChecksumEnable; 895 } 896 897 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 898 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 899 csum_flags |= TFD_TCPChecksumEnable; 900 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 901 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 902 csum_flags |= TFD_UDPChecksumEnable; 903 } 904 905 /* 906 * Initialize the descriptor and give it to the chip. 907 * Check to see if we have a VLAN tag to insert. 908 */ 909 910 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 911 TFD_FragCount(seg) | csum_flags | 912 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 913 TFD_TxDMAIndicate : 0); 914 if (mtag) { 915 #if 0 916 struct ether_header *eh = 917 mtod(m0, struct ether_header *); 918 u_int16_t etype = ntohs(eh->ether_type); 919 printf("%s: xmit (tag %d) etype %x\n", 920 ifp->if_xname, *mtod(n, int *), etype); 921 #endif 922 tfc |= TFD_VLANTagInsert | 923 #ifdef STGE_VLAN_CFI 924 TFD_CFI | 925 #endif 926 TFD_VID(VLAN_TAG_VALUE(mtag)); 927 } 928 tfd->tfd_control = htole64(tfc); 929 930 /* Sync the descriptor. */ 931 STGE_CDTXSYNC(sc, nexttx, 932 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 933 934 /* 935 * Kick the transmit DMA logic. 936 */ 937 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 938 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 939 940 /* 941 * Store a pointer to the packet so we can free it later. 942 */ 943 ds->ds_mbuf = m0; 944 945 /* Advance the tx pointer. */ 946 sc->sc_txpending++; 947 sc->sc_txlast = nexttx; 948 949 #if NBPFILTER > 0 950 /* 951 * Pass the packet to any BPF listeners. 952 */ 953 if (ifp->if_bpf) 954 bpf_mtap(ifp->if_bpf, m0); 955 #endif /* NBPFILTER > 0 */ 956 } 957 958 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 959 /* No more slots left; notify upper layer. */ 960 ifp->if_flags |= IFF_OACTIVE; 961 } 962 963 if (sc->sc_txpending != opending) { 964 /* 965 * We enqueued packets. If the transmitter was idle, 966 * reset the txdirty pointer. 967 */ 968 if (opending == 0) 969 sc->sc_txdirty = firsttx; 970 971 /* Set a watchdog timer in case the chip flakes out. */ 972 ifp->if_timer = 5; 973 } 974 } 975 976 /* 977 * stge_watchdog: [ifnet interface function] 978 * 979 * Watchdog timer handler. 980 */ 981 static void 982 stge_watchdog(struct ifnet *ifp) 983 { 984 struct stge_softc *sc = ifp->if_softc; 985 986 /* 987 * Sweep up first, since we don't interrupt every frame. 988 */ 989 stge_txintr(sc); 990 if (sc->sc_txpending != 0) { 991 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 992 ifp->if_oerrors++; 993 994 (void) stge_init(ifp); 995 996 /* Try to get more packets going. */ 997 stge_start(ifp); 998 } 999 } 1000 1001 /* 1002 * stge_ioctl: [ifnet interface function] 1003 * 1004 * Handle control requests from the operator. 1005 */ 1006 static int 1007 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1008 { 1009 struct stge_softc *sc = ifp->if_softc; 1010 int s, error; 1011 1012 s = splnet(); 1013 1014 error = ether_ioctl(ifp, cmd, data); 1015 if (error == ENETRESET) { 1016 error = 0; 1017 1018 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1019 ; 1020 else if (ifp->if_flags & IFF_RUNNING) { 1021 /* 1022 * Multicast list has changed; set the hardware filter 1023 * accordingly. 1024 */ 1025 stge_set_filter(sc); 1026 } 1027 } 1028 1029 /* Try to get more packets going. */ 1030 stge_start(ifp); 1031 1032 splx(s); 1033 return (error); 1034 } 1035 1036 /* 1037 * stge_intr: 1038 * 1039 * Interrupt service routine. 1040 */ 1041 static int 1042 stge_intr(void *arg) 1043 { 1044 struct stge_softc *sc = arg; 1045 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1046 uint32_t txstat; 1047 int wantinit; 1048 uint16_t isr; 1049 1050 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1051 IS_InterruptStatus) == 0) 1052 return (0); 1053 1054 for (wantinit = 0; wantinit == 0;) { 1055 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1056 if ((isr & sc->sc_IntEnable) == 0) 1057 break; 1058 1059 /* Host interface errors. */ 1060 if (isr & IS_HostError) { 1061 printf("%s: Host interface error\n", 1062 device_xname(&sc->sc_dev)); 1063 wantinit = 1; 1064 continue; 1065 } 1066 1067 /* Receive interrupts. */ 1068 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1069 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1070 stge_rxintr(sc); 1071 if (isr & IS_RFDListEnd) { 1072 printf("%s: receive ring overflow\n", 1073 device_xname(&sc->sc_dev)); 1074 /* 1075 * XXX Should try to recover from this 1076 * XXX more gracefully. 1077 */ 1078 wantinit = 1; 1079 } 1080 } 1081 1082 /* Transmit interrupts. */ 1083 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1084 #ifdef STGE_EVENT_COUNTERS 1085 if (isr & IS_TxDMAComplete) 1086 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1087 #endif 1088 stge_txintr(sc); 1089 } 1090 1091 /* Statistics overflow. */ 1092 if (isr & IS_UpdateStats) 1093 stge_stats_update(sc); 1094 1095 /* Transmission errors. */ 1096 if (isr & IS_TxComplete) { 1097 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1098 for (;;) { 1099 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1100 STGE_TxStatus); 1101 if ((txstat & TS_TxComplete) == 0) 1102 break; 1103 if (txstat & TS_TxUnderrun) { 1104 sc->sc_txthresh++; 1105 if (sc->sc_txthresh > 0x0fff) 1106 sc->sc_txthresh = 0x0fff; 1107 printf("%s: transmit underrun, new " 1108 "threshold: %d bytes\n", 1109 device_xname(&sc->sc_dev), 1110 sc->sc_txthresh << 5); 1111 } 1112 if (txstat & TS_MaxCollisions) 1113 printf("%s: excessive collisions\n", 1114 device_xname(&sc->sc_dev)); 1115 } 1116 wantinit = 1; 1117 } 1118 1119 } 1120 1121 if (wantinit) 1122 stge_init(ifp); 1123 1124 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1125 sc->sc_IntEnable); 1126 1127 /* Try to get more packets going. */ 1128 stge_start(ifp); 1129 1130 return (1); 1131 } 1132 1133 /* 1134 * stge_txintr: 1135 * 1136 * Helper; handle transmit interrupts. 1137 */ 1138 static void 1139 stge_txintr(struct stge_softc *sc) 1140 { 1141 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1142 struct stge_descsoft *ds; 1143 uint64_t control; 1144 int i; 1145 1146 ifp->if_flags &= ~IFF_OACTIVE; 1147 1148 /* 1149 * Go through our Tx list and free mbufs for those 1150 * frames which have been transmitted. 1151 */ 1152 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1153 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1154 ds = &sc->sc_txsoft[i]; 1155 1156 STGE_CDTXSYNC(sc, i, 1157 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1158 1159 control = le64toh(sc->sc_txdescs[i].tfd_control); 1160 if ((control & TFD_TFDDone) == 0) 1161 break; 1162 1163 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1164 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1165 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1166 m_freem(ds->ds_mbuf); 1167 ds->ds_mbuf = NULL; 1168 } 1169 1170 /* Update the dirty transmit buffer pointer. */ 1171 sc->sc_txdirty = i; 1172 1173 /* 1174 * If there are no more pending transmissions, cancel the watchdog 1175 * timer. 1176 */ 1177 if (sc->sc_txpending == 0) 1178 ifp->if_timer = 0; 1179 } 1180 1181 /* 1182 * stge_rxintr: 1183 * 1184 * Helper; handle receive interrupts. 1185 */ 1186 static void 1187 stge_rxintr(struct stge_softc *sc) 1188 { 1189 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1190 struct stge_descsoft *ds; 1191 struct mbuf *m, *tailm; 1192 uint64_t status; 1193 int i, len; 1194 1195 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1196 ds = &sc->sc_rxsoft[i]; 1197 1198 STGE_CDRXSYNC(sc, i, 1199 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1200 1201 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1202 1203 if ((status & RFD_RFDDone) == 0) 1204 break; 1205 1206 if (__predict_false(sc->sc_rxdiscard)) { 1207 STGE_INIT_RXDESC(sc, i); 1208 if (status & RFD_FrameEnd) { 1209 /* Reset our state. */ 1210 sc->sc_rxdiscard = 0; 1211 } 1212 continue; 1213 } 1214 1215 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1216 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1217 1218 m = ds->ds_mbuf; 1219 1220 /* 1221 * Add a new receive buffer to the ring. 1222 */ 1223 if (stge_add_rxbuf(sc, i) != 0) { 1224 /* 1225 * Failed, throw away what we've done so 1226 * far, and discard the rest of the packet. 1227 */ 1228 ifp->if_ierrors++; 1229 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1230 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1231 STGE_INIT_RXDESC(sc, i); 1232 if ((status & RFD_FrameEnd) == 0) 1233 sc->sc_rxdiscard = 1; 1234 if (sc->sc_rxhead != NULL) 1235 m_freem(sc->sc_rxhead); 1236 STGE_RXCHAIN_RESET(sc); 1237 continue; 1238 } 1239 1240 #ifdef DIAGNOSTIC 1241 if (status & RFD_FrameStart) { 1242 KASSERT(sc->sc_rxhead == NULL); 1243 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1244 } 1245 #endif 1246 1247 STGE_RXCHAIN_LINK(sc, m); 1248 1249 /* 1250 * If this is not the end of the packet, keep 1251 * looking. 1252 */ 1253 if ((status & RFD_FrameEnd) == 0) { 1254 sc->sc_rxlen += m->m_len; 1255 continue; 1256 } 1257 1258 /* 1259 * Okay, we have the entire packet now... 1260 */ 1261 *sc->sc_rxtailp = NULL; 1262 m = sc->sc_rxhead; 1263 tailm = sc->sc_rxtail; 1264 1265 STGE_RXCHAIN_RESET(sc); 1266 1267 /* 1268 * If the packet had an error, drop it. Note we 1269 * count the error later in the periodic stats update. 1270 */ 1271 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1272 RFD_RxAlignmentError | RFD_RxFCSError | 1273 RFD_RxLengthError)) { 1274 m_freem(m); 1275 continue; 1276 } 1277 1278 /* 1279 * No errors. 1280 * 1281 * Note we have configured the chip to not include 1282 * the CRC at the end of the packet. 1283 */ 1284 len = RFD_RxDMAFrameLen(status); 1285 tailm->m_len = len - sc->sc_rxlen; 1286 1287 /* 1288 * If the packet is small enough to fit in a 1289 * single header mbuf, allocate one and copy 1290 * the data into it. This greatly reduces 1291 * memory consumption when we receive lots 1292 * of small packets. 1293 */ 1294 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1295 struct mbuf *nm; 1296 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1297 if (nm == NULL) { 1298 ifp->if_ierrors++; 1299 m_freem(m); 1300 continue; 1301 } 1302 nm->m_data += 2; 1303 nm->m_pkthdr.len = nm->m_len = len; 1304 m_copydata(m, 0, len, mtod(nm, void *)); 1305 m_freem(m); 1306 m = nm; 1307 } 1308 1309 /* 1310 * Set the incoming checksum information for the packet. 1311 */ 1312 if (status & RFD_IPDetected) { 1313 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1314 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1315 if (status & RFD_IPError) 1316 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1317 if (status & RFD_TCPDetected) { 1318 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1319 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1320 if (status & RFD_TCPError) 1321 m->m_pkthdr.csum_flags |= 1322 M_CSUM_TCP_UDP_BAD; 1323 } else if (status & RFD_UDPDetected) { 1324 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1325 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1326 if (status & RFD_UDPError) 1327 m->m_pkthdr.csum_flags |= 1328 M_CSUM_TCP_UDP_BAD; 1329 } 1330 } 1331 1332 m->m_pkthdr.rcvif = ifp; 1333 m->m_pkthdr.len = len; 1334 1335 #if NBPFILTER > 0 1336 /* 1337 * Pass this up to any BPF listeners, but only 1338 * pass if up the stack if it's for us. 1339 */ 1340 if (ifp->if_bpf) 1341 bpf_mtap(ifp->if_bpf, m); 1342 #endif /* NBPFILTER > 0 */ 1343 #ifdef STGE_VLAN_UNTAG 1344 /* 1345 * Check for VLAN tagged packets 1346 */ 1347 if (status & RFD_VLANDetected) 1348 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1349 1350 #endif 1351 #if 0 1352 if (status & RFD_VLANDetected) { 1353 struct ether_header *eh; 1354 u_int16_t etype; 1355 1356 eh = mtod(m, struct ether_header *); 1357 etype = ntohs(eh->ether_type); 1358 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1359 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1360 etype); 1361 } 1362 #endif 1363 /* Pass it on. */ 1364 (*ifp->if_input)(ifp, m); 1365 } 1366 1367 /* Update the receive pointer. */ 1368 sc->sc_rxptr = i; 1369 } 1370 1371 /* 1372 * stge_tick: 1373 * 1374 * One second timer, used to tick the MII. 1375 */ 1376 static void 1377 stge_tick(void *arg) 1378 { 1379 struct stge_softc *sc = arg; 1380 int s; 1381 1382 s = splnet(); 1383 mii_tick(&sc->sc_mii); 1384 stge_stats_update(sc); 1385 splx(s); 1386 1387 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1388 } 1389 1390 /* 1391 * stge_stats_update: 1392 * 1393 * Read the TC9021 statistics counters. 1394 */ 1395 static void 1396 stge_stats_update(struct stge_softc *sc) 1397 { 1398 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1399 bus_space_tag_t st = sc->sc_st; 1400 bus_space_handle_t sh = sc->sc_sh; 1401 1402 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1403 1404 ifp->if_ipackets += 1405 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1406 1407 ifp->if_ierrors += 1408 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1409 1410 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1411 1412 ifp->if_opackets += 1413 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1414 1415 ifp->if_collisions += 1416 bus_space_read_4(st, sh, STGE_LateCollisions) + 1417 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1418 bus_space_read_4(st, sh, STGE_SingleColFrames); 1419 1420 ifp->if_oerrors += 1421 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1422 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1423 } 1424 1425 /* 1426 * stge_reset: 1427 * 1428 * Perform a soft reset on the TC9021. 1429 */ 1430 static void 1431 stge_reset(struct stge_softc *sc) 1432 { 1433 uint32_t ac; 1434 int i; 1435 1436 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1437 1438 /* 1439 * Only assert RstOut if we're fiber. We need GMII clocks 1440 * to be present in order for the reset to complete on fiber 1441 * cards. 1442 */ 1443 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1444 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1445 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1446 (sc->sc_usefiber ? AC_RstOut : 0)); 1447 1448 delay(50000); 1449 1450 for (i = 0; i < STGE_TIMEOUT; i++) { 1451 delay(5000); 1452 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1453 AC_ResetBusy) == 0) 1454 break; 1455 } 1456 1457 if (i == STGE_TIMEOUT) 1458 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1459 1460 delay(1000); 1461 } 1462 1463 /* 1464 * stge_init: [ ifnet interface function ] 1465 * 1466 * Initialize the interface. Must be called at splnet(). 1467 */ 1468 static int 1469 stge_init(struct ifnet *ifp) 1470 { 1471 struct stge_softc *sc = ifp->if_softc; 1472 bus_space_tag_t st = sc->sc_st; 1473 bus_space_handle_t sh = sc->sc_sh; 1474 struct stge_descsoft *ds; 1475 int i, error = 0; 1476 1477 /* 1478 * Cancel any pending I/O. 1479 */ 1480 stge_stop(ifp, 0); 1481 1482 /* 1483 * Reset the chip to a known state. 1484 */ 1485 stge_reset(sc); 1486 1487 /* 1488 * Initialize the transmit descriptor ring. 1489 */ 1490 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1491 for (i = 0; i < STGE_NTXDESC; i++) { 1492 sc->sc_txdescs[i].tfd_next = htole64( 1493 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1494 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1495 } 1496 sc->sc_txpending = 0; 1497 sc->sc_txdirty = 0; 1498 sc->sc_txlast = STGE_NTXDESC - 1; 1499 1500 /* 1501 * Initialize the receive descriptor and receive job 1502 * descriptor rings. 1503 */ 1504 for (i = 0; i < STGE_NRXDESC; i++) { 1505 ds = &sc->sc_rxsoft[i]; 1506 if (ds->ds_mbuf == NULL) { 1507 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1508 printf("%s: unable to allocate or map rx " 1509 "buffer %d, error = %d\n", 1510 device_xname(&sc->sc_dev), i, error); 1511 /* 1512 * XXX Should attempt to run with fewer receive 1513 * XXX buffers instead of just failing. 1514 */ 1515 stge_rxdrain(sc); 1516 goto out; 1517 } 1518 } else 1519 STGE_INIT_RXDESC(sc, i); 1520 } 1521 sc->sc_rxptr = 0; 1522 sc->sc_rxdiscard = 0; 1523 STGE_RXCHAIN_RESET(sc); 1524 1525 /* Set the station address. */ 1526 for (i = 0; i < 6; i++) 1527 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1528 CLLADDR(ifp->if_sadl)[i]); 1529 1530 /* 1531 * Set the statistics masks. Disable all the RMON stats, 1532 * and disable selected stats in the non-RMON stats registers. 1533 */ 1534 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1535 bus_space_write_4(st, sh, STGE_StatisticsMask, 1536 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1537 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1538 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1539 (1U << 21)); 1540 1541 /* Set up the receive filter. */ 1542 stge_set_filter(sc); 1543 1544 /* 1545 * Give the transmit and receive ring to the chip. 1546 */ 1547 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1548 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1549 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1550 1551 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1552 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1553 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1554 1555 /* 1556 * Initialize the Tx auto-poll period. It's OK to make this number 1557 * large (255 is the max, but we use 127) -- we explicitly kick the 1558 * transmit engine when there's actually a packet. 1559 */ 1560 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1561 1562 /* ..and the Rx auto-poll period. */ 1563 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1564 1565 /* Initialize the Tx start threshold. */ 1566 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1567 1568 /* RX DMA thresholds, from linux */ 1569 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1570 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1571 1572 /* 1573 * Initialize the Rx DMA interrupt control register. We 1574 * request an interrupt after every incoming packet, but 1575 * defer it for 32us (64 * 512 ns). When the number of 1576 * interrupts pending reaches 8, we stop deferring the 1577 * interrupt, and signal it immediately. 1578 */ 1579 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1580 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1581 1582 /* 1583 * Initialize the interrupt mask. 1584 */ 1585 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1586 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1587 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1588 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1589 1590 /* 1591 * Configure the DMA engine. 1592 * XXX Should auto-tune TxBurstLimit. 1593 */ 1594 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1595 DMAC_TxBurstLimit(3)); 1596 1597 /* 1598 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1599 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1600 * empty again. 1601 */ 1602 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1603 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1604 1605 /* 1606 * Set the maximum frame size. 1607 */ 1608 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1609 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1610 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1611 ETHER_VLAN_ENCAP_LEN : 0)); 1612 1613 /* 1614 * Initialize MacCtrl -- do it before setting the media, 1615 * as setting the media will actually program the register. 1616 * 1617 * Note: We have to poke the IFS value before poking 1618 * anything else. 1619 */ 1620 sc->sc_MACCtrl = MC_IFSSelect(0); 1621 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1622 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1623 #ifdef STGE_VLAN_UNTAG 1624 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1625 #endif 1626 1627 if (sc->sc_rev >= 6) { /* >= B.2 */ 1628 /* Multi-frag frame bug work-around. */ 1629 bus_space_write_2(st, sh, STGE_DebugCtrl, 1630 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1631 1632 /* Tx Poll Now bug work-around. */ 1633 bus_space_write_2(st, sh, STGE_DebugCtrl, 1634 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1635 /* XXX ? from linux */ 1636 bus_space_write_2(st, sh, STGE_DebugCtrl, 1637 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1638 } 1639 1640 /* 1641 * Set the current media. 1642 */ 1643 if ((error = ether_mediachange(ifp)) != 0) 1644 goto out; 1645 1646 /* 1647 * Start the one second MII clock. 1648 */ 1649 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1650 1651 /* 1652 * ...all done! 1653 */ 1654 ifp->if_flags |= IFF_RUNNING; 1655 ifp->if_flags &= ~IFF_OACTIVE; 1656 1657 out: 1658 if (error) 1659 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1660 return (error); 1661 } 1662 1663 /* 1664 * stge_drain: 1665 * 1666 * Drain the receive queue. 1667 */ 1668 static void 1669 stge_rxdrain(struct stge_softc *sc) 1670 { 1671 struct stge_descsoft *ds; 1672 int i; 1673 1674 for (i = 0; i < STGE_NRXDESC; i++) { 1675 ds = &sc->sc_rxsoft[i]; 1676 if (ds->ds_mbuf != NULL) { 1677 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1678 ds->ds_mbuf->m_next = NULL; 1679 m_freem(ds->ds_mbuf); 1680 ds->ds_mbuf = NULL; 1681 } 1682 } 1683 } 1684 1685 /* 1686 * stge_stop: [ ifnet interface function ] 1687 * 1688 * Stop transmission on the interface. 1689 */ 1690 static void 1691 stge_stop(struct ifnet *ifp, int disable) 1692 { 1693 struct stge_softc *sc = ifp->if_softc; 1694 struct stge_descsoft *ds; 1695 int i; 1696 1697 /* 1698 * Stop the one second clock. 1699 */ 1700 callout_stop(&sc->sc_tick_ch); 1701 1702 /* Down the MII. */ 1703 mii_down(&sc->sc_mii); 1704 1705 /* 1706 * Disable interrupts. 1707 */ 1708 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1709 1710 /* 1711 * Stop receiver, transmitter, and stats update. 1712 */ 1713 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1714 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1715 1716 /* 1717 * Stop the transmit and receive DMA. 1718 */ 1719 stge_dma_wait(sc); 1720 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1721 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1722 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1723 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1724 1725 /* 1726 * Release any queued transmit buffers. 1727 */ 1728 for (i = 0; i < STGE_NTXDESC; i++) { 1729 ds = &sc->sc_txsoft[i]; 1730 if (ds->ds_mbuf != NULL) { 1731 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1732 m_freem(ds->ds_mbuf); 1733 ds->ds_mbuf = NULL; 1734 } 1735 } 1736 1737 /* 1738 * Mark the interface down and cancel the watchdog timer. 1739 */ 1740 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1741 ifp->if_timer = 0; 1742 1743 if (disable) 1744 stge_rxdrain(sc); 1745 } 1746 1747 static int 1748 stge_eeprom_wait(struct stge_softc *sc) 1749 { 1750 int i; 1751 1752 for (i = 0; i < STGE_TIMEOUT; i++) { 1753 delay(1000); 1754 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1755 EC_EepromBusy) == 0) 1756 return (0); 1757 } 1758 return (1); 1759 } 1760 1761 /* 1762 * stge_read_eeprom: 1763 * 1764 * Read data from the serial EEPROM. 1765 */ 1766 static void 1767 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1768 { 1769 1770 if (stge_eeprom_wait(sc)) 1771 printf("%s: EEPROM failed to come ready\n", 1772 device_xname(&sc->sc_dev)); 1773 1774 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1775 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1776 if (stge_eeprom_wait(sc)) 1777 printf("%s: EEPROM read timed out\n", 1778 device_xname(&sc->sc_dev)); 1779 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1780 } 1781 1782 /* 1783 * stge_add_rxbuf: 1784 * 1785 * Add a receive buffer to the indicated descriptor. 1786 */ 1787 static int 1788 stge_add_rxbuf(struct stge_softc *sc, int idx) 1789 { 1790 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1791 struct mbuf *m; 1792 int error; 1793 1794 MGETHDR(m, M_DONTWAIT, MT_DATA); 1795 if (m == NULL) 1796 return (ENOBUFS); 1797 1798 MCLGET(m, M_DONTWAIT); 1799 if ((m->m_flags & M_EXT) == 0) { 1800 m_freem(m); 1801 return (ENOBUFS); 1802 } 1803 1804 m->m_data = m->m_ext.ext_buf + 2; 1805 m->m_len = MCLBYTES - 2; 1806 1807 if (ds->ds_mbuf != NULL) 1808 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1809 1810 ds->ds_mbuf = m; 1811 1812 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1813 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1814 if (error) { 1815 printf("%s: can't load rx DMA map %d, error = %d\n", 1816 device_xname(&sc->sc_dev), idx, error); 1817 panic("stge_add_rxbuf"); /* XXX */ 1818 } 1819 1820 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1821 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1822 1823 STGE_INIT_RXDESC(sc, idx); 1824 1825 return (0); 1826 } 1827 1828 /* 1829 * stge_set_filter: 1830 * 1831 * Set up the receive filter. 1832 */ 1833 static void 1834 stge_set_filter(struct stge_softc *sc) 1835 { 1836 struct ethercom *ec = &sc->sc_ethercom; 1837 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1838 struct ether_multi *enm; 1839 struct ether_multistep step; 1840 uint32_t crc; 1841 uint32_t mchash[2]; 1842 1843 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1844 if (ifp->if_flags & IFF_BROADCAST) 1845 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1846 1847 /* XXX: ST1023 only works in promiscuous mode */ 1848 if (sc->sc_stge1023) 1849 ifp->if_flags |= IFF_PROMISC; 1850 1851 if (ifp->if_flags & IFF_PROMISC) { 1852 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1853 goto allmulti; 1854 } 1855 1856 /* 1857 * Set up the multicast address filter by passing all multicast 1858 * addresses through a CRC generator, and then using the low-order 1859 * 6 bits as an index into the 64 bit multicast hash table. The 1860 * high order bits select the register, while the rest of the bits 1861 * select the bit within the register. 1862 */ 1863 1864 memset(mchash, 0, sizeof(mchash)); 1865 1866 ETHER_FIRST_MULTI(step, ec, enm); 1867 if (enm == NULL) 1868 goto done; 1869 1870 while (enm != NULL) { 1871 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1872 /* 1873 * We must listen to a range of multicast addresses. 1874 * For now, just accept all multicasts, rather than 1875 * trying to set only those filter bits needed to match 1876 * the range. (At this time, the only use of address 1877 * ranges is for IP multicast routing, for which the 1878 * range is big enough to require all bits set.) 1879 */ 1880 goto allmulti; 1881 } 1882 1883 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1884 1885 /* Just want the 6 least significant bits. */ 1886 crc &= 0x3f; 1887 1888 /* Set the corresponding bit in the hash table. */ 1889 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1890 1891 ETHER_NEXT_MULTI(step, enm); 1892 } 1893 1894 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1895 1896 ifp->if_flags &= ~IFF_ALLMULTI; 1897 goto done; 1898 1899 allmulti: 1900 ifp->if_flags |= IFF_ALLMULTI; 1901 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1902 1903 done: 1904 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1905 /* 1906 * Program the multicast hash table. 1907 */ 1908 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1909 mchash[0]); 1910 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1911 mchash[1]); 1912 } 1913 1914 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1915 sc->sc_ReceiveMode); 1916 } 1917 1918 /* 1919 * stge_mii_readreg: [mii interface function] 1920 * 1921 * Read a PHY register on the MII of the TC9021. 1922 */ 1923 static int 1924 stge_mii_readreg(device_t self, int phy, int reg) 1925 { 1926 1927 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1928 } 1929 1930 /* 1931 * stge_mii_writereg: [mii interface function] 1932 * 1933 * Write a PHY register on the MII of the TC9021. 1934 */ 1935 static void 1936 stge_mii_writereg(device_t self, int phy, int reg, int val) 1937 { 1938 1939 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1940 } 1941 1942 /* 1943 * stge_mii_statchg: [mii interface function] 1944 * 1945 * Callback from MII layer when media changes. 1946 */ 1947 static void 1948 stge_mii_statchg(device_t self) 1949 { 1950 struct stge_softc *sc = device_private(self); 1951 1952 if (sc->sc_mii.mii_media_active & IFM_FDX) 1953 sc->sc_MACCtrl |= MC_DuplexSelect; 1954 else 1955 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1956 1957 /* XXX 802.1x flow-control? */ 1958 1959 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1960 } 1961 1962 /* 1963 * sste_mii_bitbang_read: [mii bit-bang interface function] 1964 * 1965 * Read the MII serial port for the MII bit-bang module. 1966 */ 1967 static uint32_t 1968 stge_mii_bitbang_read(device_t self) 1969 { 1970 struct stge_softc *sc = device_private(self); 1971 1972 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1973 } 1974 1975 /* 1976 * stge_mii_bitbang_write: [mii big-bang interface function] 1977 * 1978 * Write the MII serial port for the MII bit-bang module. 1979 */ 1980 static void 1981 stge_mii_bitbang_write(device_t self, uint32_t val) 1982 { 1983 struct stge_softc *sc = device_private(self); 1984 1985 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1986 val | sc->sc_PhyCtrl); 1987 } 1988