1 /* $NetBSD: if_stge.c,v 1.6 2001/07/30 20:12:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include "bpfilter.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/callout.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 #include <sys/queue.h> 57 58 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 59 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_ether.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <machine/bus.h> 70 #include <machine/intr.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/mii/mii_bitbang.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_stgereg.h> 81 82 /* 83 * Transmit descriptor list size. 84 */ 85 #define STGE_NTXDESC 256 86 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 87 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 88 89 /* 90 * Receive descriptor list size. 91 */ 92 #define STGE_NRXDESC 256 93 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 94 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 95 96 /* 97 * Only interrupt every N frames. Must be a power-of-two. 98 */ 99 #define STGE_TXINTR_SPACING 16 100 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 101 102 /* 103 * Control structures are DMA'd to the TC9021 chip. We allocate them in 104 * a single clump that maps to a single DMA segment to make several things 105 * easier. 106 */ 107 struct stge_control_data { 108 /* 109 * The transmit descriptors. 110 */ 111 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 112 113 /* 114 * The receive descriptors. 115 */ 116 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 117 }; 118 119 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 120 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 121 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 122 123 /* 124 * Software state for transmit and receive jobs. 125 */ 126 struct stge_descsoft { 127 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 128 bus_dmamap_t ds_dmamap; /* our DMA map */ 129 }; 130 131 /* 132 * Software state per device. 133 */ 134 struct stge_softc { 135 struct device sc_dev; /* generic device information */ 136 bus_space_tag_t sc_st; /* bus space tag */ 137 bus_space_handle_t sc_sh; /* bus space handle */ 138 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 139 struct ethercom sc_ethercom; /* ethernet common data */ 140 void *sc_sdhook; /* shutdown hook */ 141 int sc_rev; /* silicon revision */ 142 143 void *sc_ih; /* interrupt cookie */ 144 145 struct mii_data sc_mii; /* MII/media information */ 146 147 struct callout sc_tick_ch; /* tick callout */ 148 149 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 150 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 151 152 /* 153 * Software state for transmit and receive descriptors. 154 */ 155 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 156 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 157 158 /* 159 * Control data structures. 160 */ 161 struct stge_control_data *sc_control_data; 162 #define sc_txdescs sc_control_data->scd_txdescs 163 #define sc_rxdescs sc_control_data->scd_rxdescs 164 165 #ifdef STGE_EVENT_COUNTERS 166 /* 167 * Event counters. 168 */ 169 struct evcnt sc_ev_txstall; /* Tx stalled */ 170 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 171 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 172 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 173 174 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 175 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 176 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 177 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 178 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 179 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 180 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 181 182 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 183 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 184 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 185 186 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 187 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 188 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 189 #endif /* STGE_EVENT_COUNTERS */ 190 191 int sc_txpending; /* number of Tx requests pending */ 192 int sc_txdirty; /* first dirty Tx descriptor */ 193 int sc_txlast; /* last used Tx descriptor */ 194 195 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 196 int sc_rxdiscard; 197 int sc_rxlen; 198 struct mbuf *sc_rxhead; 199 struct mbuf *sc_rxtail; 200 struct mbuf **sc_rxtailp; 201 202 int sc_txthresh; /* Tx threshold */ 203 int sc_usefiber; /* if we're fiber */ 204 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 205 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 206 uint16_t sc_IntEnable; /* prototype IntEnable register */ 207 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 208 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 209 }; 210 211 #define STGE_RXCHAIN_RESET(sc) \ 212 do { \ 213 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 214 *(sc)->sc_rxtailp = NULL; \ 215 (sc)->sc_rxlen = 0; \ 216 } while (/*CONSTCOND*/0) 217 218 #define STGE_RXCHAIN_LINK(sc, m) \ 219 do { \ 220 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 221 (sc)->sc_rxtailp = &(m)->m_next; \ 222 } while (/*CONSTCOND*/0) 223 224 #ifdef STGE_EVENT_COUNTERS 225 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 226 #else 227 #define STGE_EVCNT_INCR(ev) /* nothing */ 228 #endif 229 230 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 231 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 232 233 #define STGE_CDTXSYNC(sc, x, ops) \ 234 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 235 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 236 237 #define STGE_CDRXSYNC(sc, x, ops) \ 238 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 239 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 240 241 #define STGE_INIT_RXDESC(sc, x) \ 242 do { \ 243 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 244 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 245 \ 246 /* \ 247 * Note: We scoot the packet forward 2 bytes in the buffer \ 248 * so that the payload after the Ethernet header is aligned \ 249 * to a 4-byte boundary. \ 250 */ \ 251 __rfd->rfd_frag.frag_word0 = \ 252 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 253 FRAG_LEN(MCLBYTES - 2)); \ 254 __rfd->rfd_next = \ 255 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 256 __rfd->rfd_status = 0; \ 257 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 258 } while (/*CONSTCOND*/0) 259 260 #define STGE_TIMEOUT 1000 261 262 void stge_start(struct ifnet *); 263 void stge_watchdog(struct ifnet *); 264 int stge_ioctl(struct ifnet *, u_long, caddr_t); 265 int stge_init(struct ifnet *); 266 void stge_stop(struct ifnet *, int); 267 268 void stge_shutdown(void *); 269 270 void stge_reset(struct stge_softc *); 271 void stge_rxdrain(struct stge_softc *); 272 int stge_add_rxbuf(struct stge_softc *, int); 273 #if 0 274 void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 275 #endif 276 void stge_tick(void *); 277 278 void stge_stats_update(struct stge_softc *); 279 280 void stge_set_filter(struct stge_softc *); 281 282 int stge_intr(void *); 283 void stge_txintr(struct stge_softc *); 284 void stge_rxintr(struct stge_softc *); 285 286 int stge_mii_readreg(struct device *, int, int); 287 void stge_mii_writereg(struct device *, int, int, int); 288 void stge_mii_statchg(struct device *); 289 290 int stge_mediachange(struct ifnet *); 291 void stge_mediastatus(struct ifnet *, struct ifmediareq *); 292 293 int stge_match(struct device *, struct cfdata *, void *); 294 void stge_attach(struct device *, struct device *, void *); 295 296 int stge_copy_small = 0; 297 298 struct cfattach stge_ca = { 299 sizeof(struct stge_softc), stge_match, stge_attach, 300 }; 301 302 uint32_t stge_mii_bitbang_read(struct device *); 303 void stge_mii_bitbang_write(struct device *, uint32_t); 304 305 const struct mii_bitbang_ops stge_mii_bitbang_ops = { 306 stge_mii_bitbang_read, 307 stge_mii_bitbang_write, 308 { 309 PC_MgmtData, /* MII_BIT_MDO */ 310 PC_MgmtData, /* MII_BIT_MDI */ 311 PC_MgmtClk, /* MII_BIT_MDC */ 312 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 313 0, /* MII_BIT_DIR_PHY_HOST */ 314 } 315 }; 316 317 /* 318 * Devices supported by this driver. 319 */ 320 const struct stge_product { 321 pci_vendor_id_t stge_vendor; 322 pci_product_id_t stge_product; 323 const char *stge_name; 324 } stge_products[] = { 325 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 326 "Sundance ST-2021 Gigabit Ethernet" }, 327 328 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 329 "Tamarack TC9021 Gigabit Ethernet" }, 330 331 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 332 "Tamarack TC9021 Gigabit Ethernet" }, 333 334 /* 335 * The Sundance sample boards use the Sundance vendor ID, 336 * but the Tamarack product ID. 337 */ 338 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 339 "Sundance TC9021 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 342 "Sundance TC9021 Gigabit Ethernet" }, 343 344 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 345 "D-Link DL-4000 Gigabit Ethernet" }, 346 347 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 348 "Antares Gigabit Ethernet" }, 349 350 { 0, 0, 351 NULL }, 352 }; 353 354 static const struct stge_product * 355 stge_lookup(const struct pci_attach_args *pa) 356 { 357 const struct stge_product *sp; 358 359 for (sp = stge_products; sp->stge_name != NULL; sp++) { 360 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 361 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 362 return (sp); 363 } 364 return (NULL); 365 } 366 367 int 368 stge_match(struct device *parent, struct cfdata *cf, void *aux) 369 { 370 struct pci_attach_args *pa = aux; 371 372 if (stge_lookup(pa) != NULL) 373 return (1); 374 375 return (0); 376 } 377 378 void 379 stge_attach(struct device *parent, struct device *self, void *aux) 380 { 381 struct stge_softc *sc = (struct stge_softc *) self; 382 struct pci_attach_args *pa = aux; 383 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pci_intr_handle_t ih; 386 const char *intrstr = NULL; 387 bus_space_tag_t iot, memt; 388 bus_space_handle_t ioh, memh; 389 bus_dma_segment_t seg; 390 int ioh_valid, memh_valid; 391 int i, rseg, error; 392 const struct stge_product *sp; 393 pcireg_t pmode; 394 uint8_t enaddr[ETHER_ADDR_LEN]; 395 int pmreg; 396 397 callout_init(&sc->sc_tick_ch); 398 399 sp = stge_lookup(pa); 400 if (sp == NULL) { 401 printf("\n"); 402 panic("ste_attach: impossible"); 403 } 404 405 sc->sc_rev = PCI_REVISION(pa->pa_class); 406 407 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 408 409 /* 410 * Map the device. 411 */ 412 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 413 PCI_MAPREG_TYPE_IO, 0, 414 &iot, &ioh, NULL, NULL) == 0); 415 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 416 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 417 &memt, &memh, NULL, NULL) == 0); 418 419 if (memh_valid) { 420 sc->sc_st = memt; 421 sc->sc_sh = memh; 422 } else if (ioh_valid) { 423 sc->sc_st = iot; 424 sc->sc_sh = ioh; 425 } else { 426 printf("%s: unable to map device registers\n", 427 sc->sc_dev.dv_xname); 428 return; 429 } 430 431 sc->sc_dmat = pa->pa_dmat; 432 433 /* Enable bus mastering. */ 434 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 435 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 436 PCI_COMMAND_MASTER_ENABLE); 437 438 /* Get it out of power save mode if needed. */ 439 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 440 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 441 if (pmode == 3) { 442 /* 443 * The card has lost all configuration data in 444 * this state, so punt. 445 */ 446 printf("%s: unable to wake up from power state D3\n", 447 sc->sc_dev.dv_xname); 448 return; 449 } 450 if (pmode != 0) { 451 printf("%s: waking up from power state D%d\n", 452 sc->sc_dev.dv_xname, pmode); 453 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 454 } 455 } 456 457 /* 458 * Map and establish our interrupt. 459 */ 460 if (pci_intr_map(pa, &ih)) { 461 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 462 return; 463 } 464 intrstr = pci_intr_string(pc, ih); 465 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 466 if (sc->sc_ih == NULL) { 467 printf("%s: unable to establish interrupt", 468 sc->sc_dev.dv_xname); 469 if (intrstr != NULL) 470 printf(" at %s", intrstr); 471 printf("\n"); 472 return; 473 } 474 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 475 476 /* 477 * Allocate the control data structures, and create and load the 478 * DMA map for it. 479 */ 480 if ((error = bus_dmamem_alloc(sc->sc_dmat, 481 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 482 0)) != 0) { 483 printf("%s: unable to allocate control data, error = %d\n", 484 sc->sc_dev.dv_xname, error); 485 goto fail_0; 486 } 487 488 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 489 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 490 BUS_DMA_COHERENT)) != 0) { 491 printf("%s: unable to map control data, error = %d\n", 492 sc->sc_dev.dv_xname, error); 493 goto fail_1; 494 } 495 496 if ((error = bus_dmamap_create(sc->sc_dmat, 497 sizeof(struct stge_control_data), 1, 498 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 499 printf("%s: unable to create control data DMA map, " 500 "error = %d\n", sc->sc_dev.dv_xname, error); 501 goto fail_2; 502 } 503 504 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 505 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 506 0)) != 0) { 507 printf("%s: unable to load control data DMA map, error = %d\n", 508 sc->sc_dev.dv_xname, error); 509 goto fail_3; 510 } 511 512 /* 513 * Create the transmit buffer DMA maps. Note that rev B.3 514 * and earlier seem to have a bug regarding multi-fragment 515 * packets. We need to limit the number of Tx segments on 516 * such chips to 1. 517 */ 518 for (i = 0; i < STGE_NTXDESC; i++) { 519 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 520 STGE_NTXFRAGS, MCLBYTES, 0, 0, 521 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 522 printf("%s: unable to create tx DMA map %d, " 523 "error = %d\n", sc->sc_dev.dv_xname, i, error); 524 goto fail_4; 525 } 526 } 527 528 /* 529 * Create the receive buffer DMA maps. 530 */ 531 for (i = 0; i < STGE_NRXDESC; i++) { 532 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 533 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 534 printf("%s: unable to create rx DMA map %d, " 535 "error = %d\n", sc->sc_dev.dv_xname, i, error); 536 goto fail_5; 537 } 538 sc->sc_rxsoft[i].ds_mbuf = NULL; 539 } 540 541 /* 542 * Determine if we're copper or fiber. It affects how we 543 * reset the card. 544 */ 545 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 546 AC_PhyMedia) 547 sc->sc_usefiber = 1; 548 else 549 sc->sc_usefiber = 0; 550 551 /* 552 * Reset the chip to a known state. 553 */ 554 stge_reset(sc); 555 556 /* 557 * Reading the station address from the EEPROM doesn't seem 558 * to work, at least on my sample boards. Instread, since 559 * the reset sequence does AutoInit, read it from the station 560 * address registers. 561 */ 562 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 563 STGE_StationAddress0) & 0xff; 564 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 565 STGE_StationAddress0) >> 8; 566 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 567 STGE_StationAddress1) & 0xff; 568 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 569 STGE_StationAddress1) >> 8; 570 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 571 STGE_StationAddress2) & 0xff; 572 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 573 STGE_StationAddress2) >> 8; 574 575 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 576 ether_sprintf(enaddr)); 577 578 /* 579 * Read some important bits from the PhyCtrl register. 580 */ 581 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 582 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 583 584 /* 585 * Initialize our media structures and probe the MII. 586 */ 587 sc->sc_mii.mii_ifp = ifp; 588 sc->sc_mii.mii_readreg = stge_mii_readreg; 589 sc->sc_mii.mii_writereg = stge_mii_writereg; 590 sc->sc_mii.mii_statchg = stge_mii_statchg; 591 ifmedia_init(&sc->sc_mii.mii_media, 0, stge_mediachange, 592 stge_mediastatus); 593 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 594 MII_OFFSET_ANY, MIIF_DOPAUSE); 595 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 596 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 597 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 598 } else 599 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 600 601 ifp = &sc->sc_ethercom.ec_if; 602 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 603 ifp->if_softc = sc; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = stge_ioctl; 606 ifp->if_start = stge_start; 607 ifp->if_watchdog = stge_watchdog; 608 ifp->if_init = stge_init; 609 ifp->if_stop = stge_stop; 610 IFQ_SET_READY(&ifp->if_snd); 611 612 /* 613 * The manual recommends disabling early transmit, so we 614 * do. It's disabled anyway, if using IP checksumming, 615 * since the entire packet must be in the FIFO in order 616 * for the chip to perform the checksum. 617 */ 618 sc->sc_txthresh = 0x0fff; 619 620 /* 621 * Disable MWI if the PCI layer tells us to. 622 */ 623 sc->sc_DMACtrl = 0; 624 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 625 sc->sc_DMACtrl |= DMAC_MWIDisable; 626 627 /* 628 * We can support 802.1Q VLAN-sized frames and jumbo 629 * Ethernet frames. 630 * 631 * XXX Figure out how to do hw-assisted VLAN tagging in 632 * XXX a reasonable way on this chip. 633 */ 634 sc->sc_ethercom.ec_capabilities |= 635 ETHERCAP_VLAN_MTU /* XXX | ETHERCAP_JUMBO_MTU */; 636 637 /* 638 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 639 */ 640 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 641 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 642 643 /* 644 * Attach the interface. 645 */ 646 if_attach(ifp); 647 ether_ifattach(ifp, enaddr); 648 649 #ifdef STGE_EVENT_COUNTERS 650 /* 651 * Attach event counters. 652 */ 653 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 654 NULL, sc->sc_dev.dv_xname, "txstall"); 655 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 656 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 657 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 658 NULL, sc->sc_dev.dv_xname, "txindintr"); 659 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 660 NULL, sc->sc_dev.dv_xname, "rxintr"); 661 662 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 663 NULL, sc->sc_dev.dv_xname, "txseg1"); 664 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 665 NULL, sc->sc_dev.dv_xname, "txseg2"); 666 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 667 NULL, sc->sc_dev.dv_xname, "txseg3"); 668 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 669 NULL, sc->sc_dev.dv_xname, "txseg4"); 670 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 671 NULL, sc->sc_dev.dv_xname, "txseg5"); 672 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 673 NULL, sc->sc_dev.dv_xname, "txsegmore"); 674 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 675 NULL, sc->sc_dev.dv_xname, "txcopy"); 676 677 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 678 NULL, sc->sc_dev.dv_xname, "rxipsum"); 679 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 680 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 681 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 682 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 683 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 684 NULL, sc->sc_dev.dv_xname, "txipsum"); 685 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 686 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 687 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 688 NULL, sc->sc_dev.dv_xname, "txudpsum"); 689 #endif /* STGE_EVENT_COUNTERS */ 690 691 /* 692 * Make sure the interface is shutdown during reboot. 693 */ 694 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 695 if (sc->sc_sdhook == NULL) 696 printf("%s: WARNING: unable to establish shutdown hook\n", 697 sc->sc_dev.dv_xname); 698 return; 699 700 /* 701 * Free any resources we've allocated during the failed attach 702 * attempt. Do this in reverse order and fall through. 703 */ 704 fail_5: 705 for (i = 0; i < STGE_NRXDESC; i++) { 706 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 707 bus_dmamap_destroy(sc->sc_dmat, 708 sc->sc_rxsoft[i].ds_dmamap); 709 } 710 fail_4: 711 for (i = 0; i < STGE_NTXDESC; i++) { 712 if (sc->sc_txsoft[i].ds_dmamap != NULL) 713 bus_dmamap_destroy(sc->sc_dmat, 714 sc->sc_txsoft[i].ds_dmamap); 715 } 716 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 717 fail_3: 718 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 719 fail_2: 720 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 721 sizeof(struct stge_control_data)); 722 fail_1: 723 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 724 fail_0: 725 return; 726 } 727 728 /* 729 * stge_shutdown: 730 * 731 * Make sure the interface is stopped at reboot time. 732 */ 733 void 734 stge_shutdown(void *arg) 735 { 736 struct stge_softc *sc = arg; 737 738 stge_stop(&sc->sc_ethercom.ec_if, 1); 739 } 740 741 static void 742 stge_dma_wait(struct stge_softc *sc) 743 { 744 int i; 745 746 for (i = 0; i < STGE_TIMEOUT; i++) { 747 delay(2); 748 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 749 DMAC_TxDMAInProg) == 0) 750 break; 751 } 752 753 if (i == STGE_TIMEOUT) 754 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 755 } 756 757 /* 758 * stge_start: [ifnet interface function] 759 * 760 * Start packet transmission on the interface. 761 */ 762 void 763 stge_start(struct ifnet *ifp) 764 { 765 struct stge_softc *sc = ifp->if_softc; 766 struct mbuf *m0; 767 struct stge_descsoft *ds; 768 struct stge_tfd *tfd; 769 bus_dmamap_t dmamap; 770 int error, firsttx, nexttx, opending, seg, totlen; 771 uint64_t csum_flags; 772 773 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 774 return; 775 776 /* 777 * Remember the previous number of pending transmissions 778 * and the first descriptor we will use. 779 */ 780 opending = sc->sc_txpending; 781 firsttx = STGE_NEXTTX(sc->sc_txlast); 782 783 /* 784 * Loop through the send queue, setting up transmit descriptors 785 * until we drain the queue, or use up all available transmit 786 * descriptors. 787 */ 788 for (;;) { 789 /* 790 * Grab a packet off the queue. 791 */ 792 IFQ_POLL(&ifp->if_snd, m0); 793 if (m0 == NULL) 794 break; 795 796 /* 797 * Leave one unused descriptor at the end of the 798 * list to prevent wrapping completely around. 799 */ 800 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 801 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 802 break; 803 } 804 805 /* 806 * Get the last and next available transmit descriptor. 807 */ 808 nexttx = STGE_NEXTTX(sc->sc_txlast); 809 tfd = &sc->sc_txdescs[nexttx]; 810 ds = &sc->sc_txsoft[nexttx]; 811 812 dmamap = ds->ds_dmamap; 813 814 /* 815 * Load the DMA map. If this fails, the packet either 816 * didn't fit in the alloted number of segments, or we 817 * were short on resources. For the too-may-segments 818 * case, we simply report an error and drop the packet, 819 * since we can't sanely copy a jumbo packet to a single 820 * buffer. 821 */ 822 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 823 BUS_DMA_NOWAIT); 824 if (error) { 825 if (error == EFBIG) { 826 printf("%s: Tx packet consumes too many " 827 "DMA segments, dropping...\n", 828 sc->sc_dev.dv_xname); 829 IFQ_DEQUEUE(&ifp->if_snd, m0); 830 m_freem(m0); 831 continue; 832 } 833 /* 834 * Short on resources, just stop for now. 835 */ 836 break; 837 } 838 839 IFQ_DEQUEUE(&ifp->if_snd, m0); 840 841 /* 842 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 843 */ 844 845 /* Sync the DMA map. */ 846 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 847 BUS_DMASYNC_PREWRITE); 848 849 /* Initialize the fragment list. */ 850 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 851 tfd->tfd_frags[seg].frag_word0 = 852 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 853 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 854 totlen += dmamap->dm_segs[seg].ds_len; 855 } 856 857 #ifdef STGE_EVENT_COUNTERS 858 switch (dmamap->dm_nsegs) { 859 case 1: 860 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 861 break; 862 case 2: 863 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 864 break; 865 case 3: 866 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 867 break; 868 case 4: 869 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 870 break; 871 case 5: 872 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 873 break; 874 default: 875 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 876 break; 877 } 878 #endif /* STGE_EVENT_COUNTERS */ 879 880 /* 881 * Initialize checksumming flags in the descriptor. 882 * Byte-swap constants so the compiler can optimize. 883 */ 884 csum_flags = 0; 885 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 886 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 887 csum_flags |= htole64(TFD_IPChecksumEnable); 888 } 889 890 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 891 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 892 csum_flags |= htole64(TFD_TCPChecksumEnable); 893 } 894 else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 895 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 896 csum_flags |= htole64(TFD_UDPChecksumEnable); 897 } 898 899 /* 900 * Initialize the descriptor and give it to the chip. 901 */ 902 tfd->tfd_control = htole64(TFD_FrameId(nexttx) | 903 TFD_WordAlign(/*totlen & */3) | 904 TFD_FragCount(seg) | csum_flags | 905 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 906 TFD_TxDMAIndicate : 0)); 907 908 /* Sync the descriptor. */ 909 STGE_CDTXSYNC(sc, nexttx, 910 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 911 912 /* 913 * Kick the transmit DMA logic. 914 */ 915 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 916 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 917 918 /* 919 * Store a pointer to the packet so we can free it later. 920 */ 921 ds->ds_mbuf = m0; 922 923 /* Advance the tx pointer. */ 924 sc->sc_txpending++; 925 sc->sc_txlast = nexttx; 926 927 #if NBPFILTER > 0 928 /* 929 * Pass the packet to any BPF listeners. 930 */ 931 if (ifp->if_bpf) 932 bpf_mtap(ifp->if_bpf, m0); 933 #endif /* NBPFILTER > 0 */ 934 } 935 936 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 937 /* No more slots left; notify upper layer. */ 938 ifp->if_flags |= IFF_OACTIVE; 939 } 940 941 if (sc->sc_txpending != opending) { 942 /* 943 * We enqueued packets. If the transmitter was idle, 944 * reset the txdirty pointer. 945 */ 946 if (opending == 0) 947 sc->sc_txdirty = firsttx; 948 949 /* Set a watchdog timer in case the chip flakes out. */ 950 ifp->if_timer = 5; 951 } 952 } 953 954 /* 955 * stge_watchdog: [ifnet interface function] 956 * 957 * Watchdog timer handler. 958 */ 959 void 960 stge_watchdog(struct ifnet *ifp) 961 { 962 struct stge_softc *sc = ifp->if_softc; 963 964 /* 965 * Sweep up first, since we don't interrupt every frame. 966 */ 967 stge_txintr(sc); 968 if (sc->sc_txpending != 0) { 969 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 970 ifp->if_oerrors++; 971 972 (void) stge_init(ifp); 973 974 /* Try to get more packets going. */ 975 stge_start(ifp); 976 } 977 } 978 979 /* 980 * stge_ioctl: [ifnet interface function] 981 * 982 * Handle control requests from the operator. 983 */ 984 int 985 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 986 { 987 struct stge_softc *sc = ifp->if_softc; 988 struct ifreq *ifr = (struct ifreq *)data; 989 int s, error; 990 991 s = splnet(); 992 993 switch (cmd) { 994 case SIOCSIFMEDIA: 995 case SIOCGIFMEDIA: 996 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 997 break; 998 999 default: 1000 error = ether_ioctl(ifp, cmd, data); 1001 if (error == ENETRESET) { 1002 /* 1003 * Multicast list has changed; set the hardware filter 1004 * accordingly. 1005 */ 1006 stge_set_filter(sc); 1007 error = 0; 1008 } 1009 break; 1010 } 1011 1012 /* Try to get more packets going. */ 1013 stge_start(ifp); 1014 1015 splx(s); 1016 return (error); 1017 } 1018 1019 /* 1020 * stge_intr: 1021 * 1022 * Interrupt service routine. 1023 */ 1024 int 1025 stge_intr(void *arg) 1026 { 1027 struct stge_softc *sc = arg; 1028 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1029 uint32_t txstat; 1030 int wantinit; 1031 uint16_t isr; 1032 1033 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1034 IS_InterruptStatus) == 0) 1035 return (0); 1036 1037 for (wantinit = 0; wantinit == 0;) { 1038 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1039 if ((isr & sc->sc_IntEnable) == 0) 1040 break; 1041 1042 /* Receive interrupts. */ 1043 if (isr & (IE_RxDMAComplete|IE_RFDListEnd)) { 1044 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1045 stge_rxintr(sc); 1046 if (isr & IE_RFDListEnd) { 1047 printf("%s: receive ring overflow\n", 1048 sc->sc_dev.dv_xname); 1049 /* 1050 * XXX Should try to recover from this 1051 * XXX more gracefully. 1052 */ 1053 wantinit = 1; 1054 } 1055 } 1056 1057 /* Transmit interrupts. */ 1058 if (isr & (IE_TxDMAComplete|IE_TxComplete)) { 1059 #ifdef STGE_EVENT_COUNTERS 1060 if (isr & IE_TxDMAComplete) 1061 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1062 #endif 1063 stge_txintr(sc); 1064 } 1065 1066 /* Statistics overflow. */ 1067 if (isr & IE_UpdateStats) 1068 stge_stats_update(sc); 1069 1070 /* Transmission errors. */ 1071 if (isr & IE_TxComplete) { 1072 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1073 for (;;) { 1074 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1075 STGE_TxStatus); 1076 if ((txstat & TS_TxComplete) == 0) 1077 break; 1078 if (txstat & TS_TxUnderrun) { 1079 sc->sc_txthresh++; 1080 if (sc->sc_txthresh > 0x0fff) 1081 sc->sc_txthresh = 0x0fff; 1082 printf("%s: transmit underrun, new " 1083 "threshold: %d bytes\n", 1084 sc->sc_dev.dv_xname, 1085 sc->sc_txthresh << 5); 1086 } 1087 if (txstat & TS_MaxCollisions) 1088 printf("%s: excessive collisions\n", 1089 sc->sc_dev.dv_xname); 1090 } 1091 wantinit = 1; 1092 } 1093 1094 /* Host interface errors. */ 1095 if (isr & IE_HostError) { 1096 printf("%s: Host interface error\n", 1097 sc->sc_dev.dv_xname); 1098 wantinit = 1; 1099 } 1100 } 1101 1102 if (wantinit) 1103 stge_init(ifp); 1104 1105 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1106 sc->sc_IntEnable); 1107 1108 /* Try to get more packets going. */ 1109 stge_start(ifp); 1110 1111 return (1); 1112 } 1113 1114 /* 1115 * stge_txintr: 1116 * 1117 * Helper; handle transmit interrupts. 1118 */ 1119 void 1120 stge_txintr(struct stge_softc *sc) 1121 { 1122 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1123 struct stge_descsoft *ds; 1124 uint64_t control; 1125 int i; 1126 1127 ifp->if_flags &= ~IFF_OACTIVE; 1128 1129 /* 1130 * Go through our Tx list and free mbufs for those 1131 * frames which have been transmitted. 1132 */ 1133 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1134 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1135 ds = &sc->sc_txsoft[i]; 1136 1137 STGE_CDTXSYNC(sc, i, 1138 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1139 1140 control = le64toh(sc->sc_txdescs[i].tfd_control); 1141 if ((control & TFD_TFDDone) == 0) 1142 break; 1143 1144 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1145 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1146 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1147 m_freem(ds->ds_mbuf); 1148 ds->ds_mbuf = NULL; 1149 } 1150 1151 /* Update the dirty transmit buffer pointer. */ 1152 sc->sc_txdirty = i; 1153 1154 /* 1155 * If there are no more pending transmissions, cancel the watchdog 1156 * timer. 1157 */ 1158 if (sc->sc_txpending == 0) 1159 ifp->if_timer = 0; 1160 } 1161 1162 /* 1163 * stge_rxintr: 1164 * 1165 * Helper; handle receive interrupts. 1166 */ 1167 void 1168 stge_rxintr(struct stge_softc *sc) 1169 { 1170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1171 struct stge_descsoft *ds; 1172 struct mbuf *m, *tailm; 1173 uint64_t status; 1174 int i, len; 1175 1176 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1177 ds = &sc->sc_rxsoft[i]; 1178 1179 STGE_CDRXSYNC(sc, i, 1180 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1181 1182 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1183 1184 if ((status & RFD_RFDDone) == 0) 1185 break; 1186 1187 if (__predict_false(sc->sc_rxdiscard)) { 1188 STGE_INIT_RXDESC(sc, i); 1189 if (status & RFD_FrameEnd) { 1190 /* Reset our state. */ 1191 sc->sc_rxdiscard = 0; 1192 } 1193 continue; 1194 } 1195 1196 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1197 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1198 1199 m = ds->ds_mbuf; 1200 1201 /* 1202 * Add a new receive buffer to the ring. 1203 */ 1204 if (stge_add_rxbuf(sc, i) != 0) { 1205 /* 1206 * Failed, throw away what we've done so 1207 * far, and discard the rest of the packet. 1208 */ 1209 ifp->if_ierrors++; 1210 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1211 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1212 STGE_INIT_RXDESC(sc, i); 1213 if ((status & RFD_FrameEnd) == 0) 1214 sc->sc_rxdiscard = 1; 1215 if (sc->sc_rxhead != NULL) 1216 m_freem(sc->sc_rxhead); 1217 STGE_RXCHAIN_RESET(sc); 1218 continue; 1219 } 1220 1221 #ifdef DIAGNOSTIC 1222 if (status & RFD_FrameStart) { 1223 KASSERT(sc->sc_rxhead == NULL); 1224 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1225 } 1226 #endif 1227 1228 STGE_RXCHAIN_LINK(sc, m); 1229 1230 /* 1231 * If this is not the end of the packet, keep 1232 * looking. 1233 */ 1234 if ((status & RFD_FrameEnd) == 0) { 1235 sc->sc_rxlen += m->m_len; 1236 continue; 1237 } 1238 1239 /* 1240 * Okay, we have the entire packet now... 1241 */ 1242 *sc->sc_rxtailp = NULL; 1243 m = sc->sc_rxhead; 1244 tailm = sc->sc_rxtail; 1245 1246 STGE_RXCHAIN_RESET(sc); 1247 1248 /* 1249 * If the packet had an error, drop it. Note we 1250 * count the error later in the periodic stats update. 1251 */ 1252 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1253 RFD_RxAlignmentError | RFD_RxFCSError | 1254 RFD_RxLengthError)) { 1255 m_freem(m); 1256 continue; 1257 } 1258 1259 /* 1260 * No errors. 1261 * 1262 * Note we have configured the chip to not include 1263 * the CRC at the end of the packet. 1264 */ 1265 len = RFD_RxDMAFrameLen(status); 1266 tailm->m_len = len - sc->sc_rxlen; 1267 1268 /* 1269 * If the packet is small enough to fit in a 1270 * single header mbuf, allocate one and copy 1271 * the data into it. This greatly reduces 1272 * memory consumption when we receive lots 1273 * of small packets. 1274 */ 1275 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1276 struct mbuf *nm; 1277 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1278 if (nm == NULL) { 1279 ifp->if_ierrors++; 1280 m_freem(m); 1281 continue; 1282 } 1283 nm->m_data += 2; 1284 nm->m_pkthdr.len = nm->m_len = len; 1285 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1286 m_freem(m); 1287 m = nm; 1288 } 1289 1290 /* 1291 * Set the incoming checksum information for the packet. 1292 */ 1293 if (status & RFD_IPDetected) { 1294 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1295 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1296 if (status & RFD_IPError) 1297 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1298 if (status & RFD_TCPDetected) { 1299 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1300 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1301 if (status & RFD_TCPError) 1302 m->m_pkthdr.csum_flags |= 1303 M_CSUM_TCP_UDP_BAD; 1304 } else if (status & RFD_UDPDetected) { 1305 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1306 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1307 if (status & RFD_UDPError) 1308 m->m_pkthdr.csum_flags |= 1309 M_CSUM_TCP_UDP_BAD; 1310 } 1311 } 1312 1313 m->m_pkthdr.rcvif = ifp; 1314 m->m_pkthdr.len = len; 1315 1316 #if NBPFILTER > 0 1317 /* 1318 * Pass this up to any BPF listeners, but only 1319 * pass if up the stack if it's for us. 1320 */ 1321 if (ifp->if_bpf) 1322 bpf_mtap(ifp->if_bpf, m); 1323 #endif /* NBPFILTER > 0 */ 1324 1325 /* Pass it on. */ 1326 (*ifp->if_input)(ifp, m); 1327 } 1328 1329 /* Update the receive pointer. */ 1330 sc->sc_rxptr = i; 1331 } 1332 1333 /* 1334 * stge_tick: 1335 * 1336 * One second timer, used to tick the MII. 1337 */ 1338 void 1339 stge_tick(void *arg) 1340 { 1341 struct stge_softc *sc = arg; 1342 int s; 1343 1344 s = splnet(); 1345 mii_tick(&sc->sc_mii); 1346 stge_stats_update(sc); 1347 splx(s); 1348 1349 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1350 } 1351 1352 /* 1353 * stge_stats_update: 1354 * 1355 * Read the TC9021 statistics counters. 1356 */ 1357 void 1358 stge_stats_update(struct stge_softc *sc) 1359 { 1360 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1361 bus_space_tag_t st = sc->sc_st; 1362 bus_space_handle_t sh = sc->sc_sh; 1363 1364 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1365 1366 ifp->if_ipackets += 1367 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1368 1369 ifp->if_ierrors += 1370 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1371 1372 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1373 1374 ifp->if_opackets += 1375 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1376 1377 ifp->if_collisions += 1378 bus_space_read_4(st, sh, STGE_LateCollisions) + 1379 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1380 bus_space_read_4(st, sh, STGE_SingleColFrames); 1381 1382 ifp->if_oerrors += 1383 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1384 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1385 } 1386 1387 /* 1388 * stge_reset: 1389 * 1390 * Perform a soft reset on the TC9021. 1391 */ 1392 void 1393 stge_reset(struct stge_softc *sc) 1394 { 1395 uint32_t ac; 1396 int i; 1397 1398 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1399 1400 /* 1401 * Only assert RstOut if we're fiber. We need GMII clocks 1402 * to be present in order for the reset to complete on fiber 1403 * cards. 1404 */ 1405 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1406 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1407 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1408 (sc->sc_usefiber ? AC_RstOut : 0)); 1409 1410 delay(50000); 1411 1412 for (i = 0; i < STGE_TIMEOUT; i++) { 1413 delay(5000); 1414 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1415 AC_ResetBusy) == 0) 1416 break; 1417 } 1418 1419 if (i == STGE_TIMEOUT) 1420 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1421 1422 delay(1000); 1423 } 1424 1425 /* 1426 * stge_init: [ ifnet interface function ] 1427 * 1428 * Initialize the interface. Must be called at splnet(). 1429 */ 1430 int 1431 stge_init(struct ifnet *ifp) 1432 { 1433 struct stge_softc *sc = ifp->if_softc; 1434 bus_space_tag_t st = sc->sc_st; 1435 bus_space_handle_t sh = sc->sc_sh; 1436 struct stge_descsoft *ds; 1437 int i, error = 0; 1438 1439 /* 1440 * Cancel any pending I/O. 1441 */ 1442 stge_stop(ifp, 0); 1443 1444 /* 1445 * Reset the chip to a known state. 1446 */ 1447 stge_reset(sc); 1448 1449 /* 1450 * Initialize the transmit descriptor ring. 1451 */ 1452 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1453 for (i = 0; i < STGE_NTXDESC; i++) { 1454 sc->sc_txdescs[i].tfd_next = 1455 (uint64_t) STGE_CDTXADDR(sc, STGE_NEXTTX(i)); 1456 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1457 } 1458 sc->sc_txpending = 0; 1459 sc->sc_txdirty = 0; 1460 sc->sc_txlast = STGE_NTXDESC - 1; 1461 1462 /* 1463 * Initialize the receive descriptor and receive job 1464 * descriptor rings. 1465 */ 1466 for (i = 0; i < STGE_NRXDESC; i++) { 1467 ds = &sc->sc_rxsoft[i]; 1468 if (ds->ds_mbuf == NULL) { 1469 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1470 printf("%s: unable to allocate or map rx " 1471 "buffer %d, error = %d\n", 1472 sc->sc_dev.dv_xname, i, error); 1473 /* 1474 * XXX Should attempt to run with fewer receive 1475 * XXX buffers instead of just failing. 1476 */ 1477 stge_rxdrain(sc); 1478 goto out; 1479 } 1480 } else 1481 STGE_INIT_RXDESC(sc, i); 1482 } 1483 sc->sc_rxptr = 0; 1484 sc->sc_rxdiscard = 0; 1485 STGE_RXCHAIN_RESET(sc); 1486 1487 /* Set the station address. */ 1488 bus_space_write_2(st, sh, STGE_StationAddress0, 1489 LLADDR(ifp->if_sadl)[0] | (LLADDR(ifp->if_sadl)[1] << 8)); 1490 bus_space_write_2(st, sh, STGE_StationAddress1, 1491 LLADDR(ifp->if_sadl)[2] | (LLADDR(ifp->if_sadl)[3] << 8)); 1492 bus_space_write_2(st, sh, STGE_StationAddress2, 1493 LLADDR(ifp->if_sadl)[4] | (LLADDR(ifp->if_sadl)[5] << 8)); 1494 1495 /* 1496 * Set the statistics masks. Disable all the RMON stats, 1497 * and disable selected stats in the non-RMON stats registers. 1498 */ 1499 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1500 bus_space_write_4(st, sh, STGE_StatisticsMask, 1501 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1502 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1503 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1504 (1U << 21)); 1505 1506 /* Set up the receive filter. */ 1507 stge_set_filter(sc); 1508 1509 /* 1510 * Give the transmit and receive ring to the chip. 1511 */ 1512 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1513 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1514 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1515 1516 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1517 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1518 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1519 1520 /* 1521 * Initialize the Tx auto-poll period. It's OK to make this number 1522 * large (255 is the max, but we use 127) -- we explicitly kick the 1523 * transmit engine when there's actually a packet. 1524 */ 1525 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1526 1527 /* ..and the Rx auto-poll period. */ 1528 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1529 1530 /* Initialize the Tx start threshold. */ 1531 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1532 1533 /* 1534 * Initialize the Rx DMA interrupt control register. We 1535 * request an interrupt after every incoming packet, but 1536 * defer it for 32us (64 * 512 ns). When the number of 1537 * interrupts pending reaches 8, we stop deferring the 1538 * interrupt, and signal it immediately. 1539 */ 1540 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1541 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1542 1543 /* 1544 * Initialize the interrupt mask. 1545 */ 1546 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1547 IE_TxDMAComplete | IE_RxDMAComplete | IE_RFDListEnd; 1548 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1549 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1550 1551 /* 1552 * Configure the DMA engine. 1553 * XXX Should auto-tune TxBurstLimit. 1554 */ 1555 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1556 DMAC_TxBurstLimit(3)); 1557 1558 /* 1559 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1560 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1561 * empty again. 1562 */ 1563 bus_space_write_4(st, sh, STGE_FlowOnTresh, 29696 / 16); 1564 bus_space_write_4(st, sh, STGE_FlowOffThresh, 0); 1565 1566 /* 1567 * Set the maximum frame size. 1568 */ 1569 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1570 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1571 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1572 ETHER_VLAN_ENCAP_LEN : 0)); 1573 1574 /* 1575 * Initialize MacCtrl -- do it before setting the media, 1576 * as setting the media will actually program the register. 1577 * 1578 * Note: We have to poke the IFS value before poking 1579 * anything else. 1580 */ 1581 sc->sc_MACCtrl = MC_IFSSelect(0); 1582 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1583 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1584 1585 if (sc->sc_rev >= 6) { /* >= B.2 */ 1586 /* Multi-frag frame bug work-around. */ 1587 bus_space_write_2(st, sh, STGE_DebugCtrl, 1588 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1589 1590 /* Tx Poll Now bug work-around. */ 1591 bus_space_write_2(st, sh, STGE_DebugCtrl, 1592 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1593 } 1594 1595 /* 1596 * Set the current media. 1597 */ 1598 mii_mediachg(&sc->sc_mii); 1599 1600 /* 1601 * Start the one second MII clock. 1602 */ 1603 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1604 1605 /* 1606 * ...all done! 1607 */ 1608 ifp->if_flags |= IFF_RUNNING; 1609 ifp->if_flags &= ~IFF_OACTIVE; 1610 1611 out: 1612 if (error) 1613 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1614 return (error); 1615 } 1616 1617 /* 1618 * stge_drain: 1619 * 1620 * Drain the receive queue. 1621 */ 1622 void 1623 stge_rxdrain(struct stge_softc *sc) 1624 { 1625 struct stge_descsoft *ds; 1626 int i; 1627 1628 for (i = 0; i < STGE_NRXDESC; i++) { 1629 ds = &sc->sc_rxsoft[i]; 1630 if (ds->ds_mbuf != NULL) { 1631 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1632 ds->ds_mbuf->m_next = NULL; 1633 m_freem(ds->ds_mbuf); 1634 ds->ds_mbuf = NULL; 1635 } 1636 } 1637 } 1638 1639 /* 1640 * stge_stop: [ ifnet interface function ] 1641 * 1642 * Stop transmission on the interface. 1643 */ 1644 void 1645 stge_stop(struct ifnet *ifp, int disable) 1646 { 1647 struct stge_softc *sc = ifp->if_softc; 1648 struct stge_descsoft *ds; 1649 int i; 1650 1651 /* 1652 * Stop the one second clock. 1653 */ 1654 callout_stop(&sc->sc_tick_ch); 1655 1656 /* Down the MII. */ 1657 mii_down(&sc->sc_mii); 1658 1659 /* 1660 * Disable interrupts. 1661 */ 1662 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1663 1664 /* 1665 * Stop receiver, transmitter, and stats update. 1666 */ 1667 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1668 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1669 1670 /* 1671 * Stop the transmit and receive DMA. 1672 */ 1673 stge_dma_wait(sc); 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1678 1679 /* 1680 * Release any queued transmit buffers. 1681 */ 1682 for (i = 0; i < STGE_NTXDESC; i++) { 1683 ds = &sc->sc_txsoft[i]; 1684 if (ds->ds_mbuf != NULL) { 1685 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1686 m_freem(ds->ds_mbuf); 1687 ds->ds_mbuf = NULL; 1688 } 1689 } 1690 1691 if (disable) 1692 stge_rxdrain(sc); 1693 1694 /* 1695 * Mark the interface down and cancel the watchdog timer. 1696 */ 1697 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1698 ifp->if_timer = 0; 1699 } 1700 1701 #if 0 1702 static int 1703 stge_eeprom_wait(struct stge_softc *sc) 1704 { 1705 int i; 1706 1707 for (i = 0; i < STGE_TIMEOUT; i++) { 1708 delay(1000); 1709 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1710 EC_EepromBusy) == 0) 1711 return (0); 1712 } 1713 return (1); 1714 } 1715 1716 /* 1717 * stge_read_eeprom: 1718 * 1719 * Read data from the serial EEPROM. 1720 */ 1721 void 1722 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1723 { 1724 1725 if (stge_eeprom_wait(sc)) 1726 printf("%s: EEPROM failed to come ready\n", 1727 sc->sc_dev.dv_xname); 1728 1729 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1730 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1731 if (stge_eeprom_wait(sc)) 1732 printf("%s: EEPROM read timed out\n", 1733 sc->sc_dev.dv_xname); 1734 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1735 } 1736 #endif /* 0 */ 1737 1738 /* 1739 * stge_add_rxbuf: 1740 * 1741 * Add a receive buffer to the indicated descriptor. 1742 */ 1743 int 1744 stge_add_rxbuf(struct stge_softc *sc, int idx) 1745 { 1746 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1747 struct mbuf *m; 1748 int error; 1749 1750 MGETHDR(m, M_DONTWAIT, MT_DATA); 1751 if (m == NULL) 1752 return (ENOBUFS); 1753 1754 MCLGET(m, M_DONTWAIT); 1755 if ((m->m_flags & M_EXT) == 0) { 1756 m_freem(m); 1757 return (ENOBUFS); 1758 } 1759 1760 m->m_data = m->m_ext.ext_buf + 2; 1761 m->m_len = MCLBYTES - 2; 1762 1763 if (ds->ds_mbuf != NULL) 1764 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1765 1766 ds->ds_mbuf = m; 1767 1768 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1769 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1770 if (error) { 1771 printf("%s: can't load rx DMA map %d, error = %d\n", 1772 sc->sc_dev.dv_xname, idx, error); 1773 panic("stge_add_rxbuf"); /* XXX */ 1774 } 1775 1776 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1777 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1778 1779 STGE_INIT_RXDESC(sc, idx); 1780 1781 return (0); 1782 } 1783 1784 /* 1785 * stge_set_filter: 1786 * 1787 * Set up the receive filter. 1788 */ 1789 void 1790 stge_set_filter(struct stge_softc *sc) 1791 { 1792 struct ethercom *ec = &sc->sc_ethercom; 1793 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1794 struct ether_multi *enm; 1795 struct ether_multistep step; 1796 uint32_t crc; 1797 uint32_t mchash[2]; 1798 1799 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1800 if (ifp->if_flags & IFF_BROADCAST) 1801 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1802 1803 if (ifp->if_flags & IFF_PROMISC) { 1804 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1805 goto allmulti; 1806 } 1807 1808 /* 1809 * Set up the multicast address filter by passing all multicast 1810 * addresses through a CRC generator, and then using the low-order 1811 * 6 bits as an index into the 64 bit multicast hash table. The 1812 * high order bits select the register, while the rest of the bits 1813 * select the bit within the register. 1814 */ 1815 1816 memset(mchash, 0, sizeof(mchash)); 1817 1818 ETHER_FIRST_MULTI(step, ec, enm); 1819 if (enm == NULL) 1820 goto done; 1821 1822 while (enm != NULL) { 1823 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1824 /* 1825 * We must listen to a range of multicast addresses. 1826 * For now, just accept all multicasts, rather than 1827 * trying to set only those filter bits needed to match 1828 * the range. (At this time, the only use of address 1829 * ranges is for IP multicast routing, for which the 1830 * range is big enough to require all bits set.) 1831 */ 1832 goto allmulti; 1833 } 1834 1835 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1836 1837 /* Just want the 6 least significant bits. */ 1838 crc &= 0x3f; 1839 1840 /* Set the corresponding bit in the hash table. */ 1841 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1842 1843 ETHER_NEXT_MULTI(step, enm); 1844 } 1845 1846 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1847 1848 ifp->if_flags &= ~IFF_ALLMULTI; 1849 goto done; 1850 1851 allmulti: 1852 ifp->if_flags |= IFF_ALLMULTI; 1853 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1854 1855 done: 1856 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1857 /* 1858 * Program the multicast hash table. 1859 */ 1860 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1861 mchash[0]); 1862 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1863 mchash[1]); 1864 } 1865 1866 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1867 sc->sc_ReceiveMode); 1868 } 1869 1870 /* 1871 * stge_mii_readreg: [mii interface function] 1872 * 1873 * Read a PHY register on the MII of the TC9021. 1874 */ 1875 int 1876 stge_mii_readreg(struct device *self, int phy, int reg) 1877 { 1878 1879 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1880 } 1881 1882 /* 1883 * stge_mii_writereg: [mii interface function] 1884 * 1885 * Write a PHY register on the MII of the TC9021. 1886 */ 1887 void 1888 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1889 { 1890 1891 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1892 } 1893 1894 /* 1895 * stge_mii_statchg: [mii interface function] 1896 * 1897 * Callback from MII layer when media changes. 1898 */ 1899 void 1900 stge_mii_statchg(struct device *self) 1901 { 1902 struct stge_softc *sc = (struct stge_softc *) self; 1903 1904 if (sc->sc_mii.mii_media_active & IFM_FDX) 1905 sc->sc_MACCtrl |= MC_DuplexSelect; 1906 else 1907 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1908 1909 /* XXX 802.1x flow-control? */ 1910 1911 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1912 } 1913 1914 /* 1915 * sste_mii_bitbang_read: [mii bit-bang interface function] 1916 * 1917 * Read the MII serial port for the MII bit-bang module. 1918 */ 1919 uint32_t 1920 stge_mii_bitbang_read(struct device *self) 1921 { 1922 struct stge_softc *sc = (void *) self; 1923 1924 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1925 } 1926 1927 /* 1928 * stge_mii_bitbang_write: [mii big-bang interface function] 1929 * 1930 * Write the MII serial port for the MII bit-bang module. 1931 */ 1932 void 1933 stge_mii_bitbang_write(struct device *self, uint32_t val) 1934 { 1935 struct stge_softc *sc = (void *) self; 1936 1937 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1938 val | sc->sc_PhyCtrl); 1939 } 1940 1941 /* 1942 * stge_mediastatus: [ifmedia interface function] 1943 * 1944 * Get the current interface media status. 1945 */ 1946 void 1947 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1948 { 1949 struct stge_softc *sc = ifp->if_softc; 1950 1951 mii_pollstat(&sc->sc_mii); 1952 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1953 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1954 } 1955 1956 /* 1957 * stge_mediachange: [ifmedia interface function] 1958 * 1959 * Set hardware to newly-selected media. 1960 */ 1961 int 1962 stge_mediachange(struct ifnet *ifp) 1963 { 1964 struct stge_softc *sc = ifp->if_softc; 1965 1966 if (ifp->if_flags & IFF_UP) 1967 mii_mediachg(&sc->sc_mii); 1968 return (0); 1969 } 1970