1 /* $NetBSD: if_stge.c,v 1.48 2009/09/14 12:02:48 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.48 2009/09/14 12:02:48 tsutsui Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/mii/mii_bitbang.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_stgereg.h> 77 78 /* #define STGE_CU_BUG 1 */ 79 #define STGE_VLAN_UNTAG 1 80 /* #define STGE_VLAN_CFI 1 */ 81 82 /* 83 * Transmit descriptor list size. 84 */ 85 #define STGE_NTXDESC 256 86 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 87 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 88 89 /* 90 * Receive descriptor list size. 91 */ 92 #define STGE_NRXDESC 256 93 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 94 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 95 96 /* 97 * Only interrupt every N frames. Must be a power-of-two. 98 */ 99 #define STGE_TXINTR_SPACING 16 100 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 101 102 /* 103 * Control structures are DMA'd to the TC9021 chip. We allocate them in 104 * a single clump that maps to a single DMA segment to make several things 105 * easier. 106 */ 107 struct stge_control_data { 108 /* 109 * The transmit descriptors. 110 */ 111 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 112 113 /* 114 * The receive descriptors. 115 */ 116 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 117 }; 118 119 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 120 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 121 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 122 123 /* 124 * Software state for transmit and receive jobs. 125 */ 126 struct stge_descsoft { 127 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 128 bus_dmamap_t ds_dmamap; /* our DMA map */ 129 }; 130 131 /* 132 * Software state per device. 133 */ 134 struct stge_softc { 135 device_t sc_dev; /* generic device information */ 136 bus_space_tag_t sc_st; /* bus space tag */ 137 bus_space_handle_t sc_sh; /* bus space handle */ 138 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 139 struct ethercom sc_ethercom; /* ethernet common data */ 140 int sc_rev; /* silicon revision */ 141 142 void *sc_ih; /* interrupt cookie */ 143 144 struct mii_data sc_mii; /* MII/media information */ 145 146 callout_t sc_tick_ch; /* tick callout */ 147 148 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 149 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 150 151 /* 152 * Software state for transmit and receive descriptors. 153 */ 154 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 155 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 156 157 /* 158 * Control data structures. 159 */ 160 struct stge_control_data *sc_control_data; 161 #define sc_txdescs sc_control_data->scd_txdescs 162 #define sc_rxdescs sc_control_data->scd_rxdescs 163 164 #ifdef STGE_EVENT_COUNTERS 165 /* 166 * Event counters. 167 */ 168 struct evcnt sc_ev_txstall; /* Tx stalled */ 169 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 170 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 171 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 172 173 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 174 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 175 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 176 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 177 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 178 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 179 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 180 181 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 182 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 183 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 184 185 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 186 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 187 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 188 #endif /* STGE_EVENT_COUNTERS */ 189 190 int sc_txpending; /* number of Tx requests pending */ 191 int sc_txdirty; /* first dirty Tx descriptor */ 192 int sc_txlast; /* last used Tx descriptor */ 193 194 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 195 int sc_rxdiscard; 196 int sc_rxlen; 197 struct mbuf *sc_rxhead; 198 struct mbuf *sc_rxtail; 199 struct mbuf **sc_rxtailp; 200 201 int sc_txthresh; /* Tx threshold */ 202 uint32_t sc_usefiber:1; /* if we're fiber */ 203 uint32_t sc_stge1023:1; /* are we a 1023 */ 204 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 205 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 206 uint16_t sc_IntEnable; /* prototype IntEnable register */ 207 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 208 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 209 }; 210 211 #define STGE_RXCHAIN_RESET(sc) \ 212 do { \ 213 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 214 *(sc)->sc_rxtailp = NULL; \ 215 (sc)->sc_rxlen = 0; \ 216 } while (/*CONSTCOND*/0) 217 218 #define STGE_RXCHAIN_LINK(sc, m) \ 219 do { \ 220 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 221 (sc)->sc_rxtailp = &(m)->m_next; \ 222 } while (/*CONSTCOND*/0) 223 224 #ifdef STGE_EVENT_COUNTERS 225 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 226 #else 227 #define STGE_EVCNT_INCR(ev) /* nothing */ 228 #endif 229 230 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 231 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 232 233 #define STGE_CDTXSYNC(sc, x, ops) \ 234 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 235 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 236 237 #define STGE_CDRXSYNC(sc, x, ops) \ 238 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 239 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 240 241 #define STGE_INIT_RXDESC(sc, x) \ 242 do { \ 243 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 244 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 245 \ 246 /* \ 247 * Note: We scoot the packet forward 2 bytes in the buffer \ 248 * so that the payload after the Ethernet header is aligned \ 249 * to a 4-byte boundary. \ 250 */ \ 251 __rfd->rfd_frag.frag_word0 = \ 252 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 253 FRAG_LEN(MCLBYTES - 2)); \ 254 __rfd->rfd_next = \ 255 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 256 __rfd->rfd_status = 0; \ 257 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 258 } while (/*CONSTCOND*/0) 259 260 #define STGE_TIMEOUT 1000 261 262 static void stge_start(struct ifnet *); 263 static void stge_watchdog(struct ifnet *); 264 static int stge_ioctl(struct ifnet *, u_long, void *); 265 static int stge_init(struct ifnet *); 266 static void stge_stop(struct ifnet *, int); 267 268 static bool stge_shutdown(device_t, int); 269 270 static void stge_reset(struct stge_softc *); 271 static void stge_rxdrain(struct stge_softc *); 272 static int stge_add_rxbuf(struct stge_softc *, int); 273 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 274 static void stge_tick(void *); 275 276 static void stge_stats_update(struct stge_softc *); 277 278 static void stge_set_filter(struct stge_softc *); 279 280 static int stge_intr(void *); 281 static void stge_txintr(struct stge_softc *); 282 static void stge_rxintr(struct stge_softc *); 283 284 static int stge_mii_readreg(device_t, int, int); 285 static void stge_mii_writereg(device_t, int, int, int); 286 static void stge_mii_statchg(device_t); 287 288 static int stge_match(device_t, cfdata_t, void *); 289 static void stge_attach(device_t, device_t, void *); 290 291 int stge_copy_small = 0; 292 293 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 294 stge_match, stge_attach, NULL, NULL); 295 296 static uint32_t stge_mii_bitbang_read(device_t); 297 static void stge_mii_bitbang_write(device_t, uint32_t); 298 299 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 300 stge_mii_bitbang_read, 301 stge_mii_bitbang_write, 302 { 303 PC_MgmtData, /* MII_BIT_MDO */ 304 PC_MgmtData, /* MII_BIT_MDI */ 305 PC_MgmtClk, /* MII_BIT_MDC */ 306 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 307 0, /* MII_BIT_DIR_PHY_HOST */ 308 } 309 }; 310 311 /* 312 * Devices supported by this driver. 313 */ 314 static const struct stge_product { 315 pci_vendor_id_t stge_vendor; 316 pci_product_id_t stge_product; 317 const char *stge_name; 318 } stge_products[] = { 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 320 "Sundance ST-1023 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 323 "Sundance ST-2021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 329 "Tamarack TC9021 Gigabit Ethernet" }, 330 331 /* 332 * The Sundance sample boards use the Sundance vendor ID, 333 * but the Tamarack product ID. 334 */ 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 339 "Sundance TC9021 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 342 "D-Link DL-4000 Gigabit Ethernet" }, 343 344 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 345 "Antares Gigabit Ethernet" }, 346 347 { 0, 0, 348 NULL }, 349 }; 350 351 static const struct stge_product * 352 stge_lookup(const struct pci_attach_args *pa) 353 { 354 const struct stge_product *sp; 355 356 for (sp = stge_products; sp->stge_name != NULL; sp++) { 357 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 358 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 359 return (sp); 360 } 361 return (NULL); 362 } 363 364 static int 365 stge_match(device_t parent, cfdata_t cf, void *aux) 366 { 367 struct pci_attach_args *pa = aux; 368 369 if (stge_lookup(pa) != NULL) 370 return (1); 371 372 return (0); 373 } 374 375 static void 376 stge_attach(device_t parent, device_t self, void *aux) 377 { 378 struct stge_softc *sc = device_private(self); 379 struct pci_attach_args *pa = aux; 380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 381 pci_chipset_tag_t pc = pa->pa_pc; 382 pci_intr_handle_t ih; 383 const char *intrstr = NULL; 384 bus_space_tag_t iot, memt; 385 bus_space_handle_t ioh, memh; 386 bus_dma_segment_t seg; 387 int ioh_valid, memh_valid; 388 int i, rseg, error; 389 const struct stge_product *sp; 390 uint8_t enaddr[ETHER_ADDR_LEN]; 391 392 callout_init(&sc->sc_tick_ch, 0); 393 394 sp = stge_lookup(pa); 395 if (sp == NULL) { 396 printf("\n"); 397 panic("ste_attach: impossible"); 398 } 399 400 sc->sc_rev = PCI_REVISION(pa->pa_class); 401 402 aprint_normal(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 403 404 /* 405 * Map the device. 406 */ 407 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 408 PCI_MAPREG_TYPE_IO, 0, 409 &iot, &ioh, NULL, NULL) == 0); 410 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 411 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 412 &memt, &memh, NULL, NULL) == 0); 413 414 if (memh_valid) { 415 sc->sc_st = memt; 416 sc->sc_sh = memh; 417 } else if (ioh_valid) { 418 sc->sc_st = iot; 419 sc->sc_sh = ioh; 420 } else { 421 aprint_error_dev(self, "unable to map device registers\n"); 422 return; 423 } 424 425 sc->sc_dmat = pa->pa_dmat; 426 427 /* Enable bus mastering. */ 428 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 429 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 430 PCI_COMMAND_MASTER_ENABLE); 431 432 /* power up chip */ 433 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 434 error != EOPNOTSUPP) { 435 aprint_error_dev(self, "cannot activate %d\n", 436 error); 437 return; 438 } 439 /* 440 * Map and establish our interrupt. 441 */ 442 if (pci_intr_map(pa, &ih)) { 443 aprint_error_dev(self, "unable to map interrupt\n"); 444 return; 445 } 446 intrstr = pci_intr_string(pc, ih); 447 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 448 if (sc->sc_ih == NULL) { 449 aprint_error_dev(self, "unable to establish interrupt"); 450 if (intrstr != NULL) 451 aprint_error(" at %s", intrstr); 452 aprint_error("\n"); 453 return; 454 } 455 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 456 457 /* 458 * Allocate the control data structures, and create and load the 459 * DMA map for it. 460 */ 461 if ((error = bus_dmamem_alloc(sc->sc_dmat, 462 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 463 0)) != 0) { 464 aprint_error_dev(self, 465 "unable to allocate control data, error = %d\n", 466 error); 467 goto fail_0; 468 } 469 470 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 471 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 472 BUS_DMA_COHERENT)) != 0) { 473 aprint_error_dev(self, 474 "unable to map control data, error = %d\n", 475 error); 476 goto fail_1; 477 } 478 479 if ((error = bus_dmamap_create(sc->sc_dmat, 480 sizeof(struct stge_control_data), 1, 481 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 482 aprint_error_dev(self, 483 "unable to create control data DMA map, error = %d\n", 484 error); 485 goto fail_2; 486 } 487 488 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 489 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 490 0)) != 0) { 491 aprint_error_dev(self, 492 "unable to load control data DMA map, error = %d\n", 493 error); 494 goto fail_3; 495 } 496 497 /* 498 * Create the transmit buffer DMA maps. Note that rev B.3 499 * and earlier seem to have a bug regarding multi-fragment 500 * packets. We need to limit the number of Tx segments on 501 * such chips to 1. 502 */ 503 for (i = 0; i < STGE_NTXDESC; i++) { 504 if ((error = bus_dmamap_create(sc->sc_dmat, 505 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 506 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 507 aprint_error_dev(self, 508 "unable to create tx DMA map %d, error = %d\n", 509 i, error); 510 goto fail_4; 511 } 512 } 513 514 /* 515 * Create the receive buffer DMA maps. 516 */ 517 for (i = 0; i < STGE_NRXDESC; i++) { 518 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 519 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 520 aprint_error_dev(self, 521 "unable to create rx DMA map %d, error = %d\n", 522 i, error); 523 goto fail_5; 524 } 525 sc->sc_rxsoft[i].ds_mbuf = NULL; 526 } 527 528 /* 529 * Determine if we're copper or fiber. It affects how we 530 * reset the card. 531 */ 532 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 533 AC_PhyMedia) 534 sc->sc_usefiber = 1; 535 else 536 sc->sc_usefiber = 0; 537 538 /* 539 * Reset the chip to a known state. 540 */ 541 stge_reset(sc); 542 543 /* 544 * Reading the station address from the EEPROM doesn't seem 545 * to work, at least on my sample boards. Instead, since 546 * the reset sequence does AutoInit, read it from the station 547 * address registers. For Sundance 1023 you can only read it 548 * from EEPROM. 549 */ 550 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 551 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress0) & 0xff; 553 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress0) >> 8; 555 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress1) & 0xff; 557 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress1) >> 8; 559 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress2) & 0xff; 561 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 562 STGE_StationAddress2) >> 8; 563 sc->sc_stge1023 = 0; 564 } else { 565 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 566 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 567 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 568 &myaddr[i]); 569 myaddr[i] = le16toh(myaddr[i]); 570 } 571 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 572 sc->sc_stge1023 = 1; 573 } 574 575 aprint_normal_dev(self, "Ethernet address %s\n", 576 ether_sprintf(enaddr)); 577 578 /* 579 * Read some important bits from the PhyCtrl register. 580 */ 581 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 582 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 583 584 /* 585 * Initialize our media structures and probe the MII. 586 */ 587 sc->sc_mii.mii_ifp = ifp; 588 sc->sc_mii.mii_readreg = stge_mii_readreg; 589 sc->sc_mii.mii_writereg = stge_mii_writereg; 590 sc->sc_mii.mii_statchg = stge_mii_statchg; 591 sc->sc_ethercom.ec_mii = &sc->sc_mii; 592 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 593 ether_mediastatus); 594 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 595 MII_OFFSET_ANY, MIIF_DOPAUSE); 596 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 597 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 598 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 599 } else 600 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 601 602 ifp = &sc->sc_ethercom.ec_if; 603 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 604 ifp->if_softc = sc; 605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 606 ifp->if_ioctl = stge_ioctl; 607 ifp->if_start = stge_start; 608 ifp->if_watchdog = stge_watchdog; 609 ifp->if_init = stge_init; 610 ifp->if_stop = stge_stop; 611 IFQ_SET_READY(&ifp->if_snd); 612 613 /* 614 * The manual recommends disabling early transmit, so we 615 * do. It's disabled anyway, if using IP checksumming, 616 * since the entire packet must be in the FIFO in order 617 * for the chip to perform the checksum. 618 */ 619 sc->sc_txthresh = 0x0fff; 620 621 /* 622 * Disable MWI if the PCI layer tells us to. 623 */ 624 sc->sc_DMACtrl = 0; 625 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 626 sc->sc_DMACtrl |= DMAC_MWIDisable; 627 628 /* 629 * We can support 802.1Q VLAN-sized frames and jumbo 630 * Ethernet frames. 631 * 632 * XXX Figure out how to do hw-assisted VLAN tagging in 633 * XXX a reasonable way on this chip. 634 */ 635 sc->sc_ethercom.ec_capabilities |= 636 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 637 ETHERCAP_VLAN_HWTAGGING; 638 639 /* 640 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 641 */ 642 sc->sc_ethercom.ec_if.if_capabilities |= 643 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 644 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 645 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 646 647 /* 648 * Attach the interface. 649 */ 650 if_attach(ifp); 651 ether_ifattach(ifp, enaddr); 652 653 #ifdef STGE_EVENT_COUNTERS 654 /* 655 * Attach event counters. 656 */ 657 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 658 NULL, device_xname(self), "txstall"); 659 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 660 NULL, device_xname(self), "txdmaintr"); 661 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 662 NULL, device_xname(self), "txindintr"); 663 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 664 NULL, device_xname(self), "rxintr"); 665 666 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 667 NULL, device_xname(self), "txseg1"); 668 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 669 NULL, device_xname(self), "txseg2"); 670 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 671 NULL, device_xname(self), "txseg3"); 672 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 673 NULL, device_xname(self), "txseg4"); 674 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 675 NULL, device_xname(self), "txseg5"); 676 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 677 NULL, device_xname(self), "txsegmore"); 678 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 679 NULL, device_xname(self), "txcopy"); 680 681 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 682 NULL, device_xname(self), "rxipsum"); 683 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 684 NULL, device_xname(self), "rxtcpsum"); 685 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 686 NULL, device_xname(self), "rxudpsum"); 687 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 688 NULL, device_xname(self), "txipsum"); 689 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 690 NULL, device_xname(self), "txtcpsum"); 691 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 692 NULL, device_xname(self), "txudpsum"); 693 #endif /* STGE_EVENT_COUNTERS */ 694 695 /* 696 * Make sure the interface is shutdown during reboot. 697 */ 698 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 699 pmf_class_network_register(self, ifp); 700 else 701 aprint_error_dev(self, "couldn't establish power handler\n"); 702 703 return; 704 705 /* 706 * Free any resources we've allocated during the failed attach 707 * attempt. Do this in reverse order and fall through. 708 */ 709 fail_5: 710 for (i = 0; i < STGE_NRXDESC; i++) { 711 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 712 bus_dmamap_destroy(sc->sc_dmat, 713 sc->sc_rxsoft[i].ds_dmamap); 714 } 715 fail_4: 716 for (i = 0; i < STGE_NTXDESC; i++) { 717 if (sc->sc_txsoft[i].ds_dmamap != NULL) 718 bus_dmamap_destroy(sc->sc_dmat, 719 sc->sc_txsoft[i].ds_dmamap); 720 } 721 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 722 fail_3: 723 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 724 fail_2: 725 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 726 sizeof(struct stge_control_data)); 727 fail_1: 728 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 729 fail_0: 730 return; 731 } 732 733 /* 734 * stge_shutdown: 735 * 736 * Make sure the interface is stopped at reboot time. 737 */ 738 static bool 739 stge_shutdown(device_t self, int howto) 740 { 741 struct stge_softc *sc = device_private(self); 742 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 743 744 stge_stop(ifp, 1); 745 746 return true; 747 } 748 749 static void 750 stge_dma_wait(struct stge_softc *sc) 751 { 752 int i; 753 754 for (i = 0; i < STGE_TIMEOUT; i++) { 755 delay(2); 756 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 757 DMAC_TxDMAInProg) == 0) 758 break; 759 } 760 761 if (i == STGE_TIMEOUT) 762 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 763 } 764 765 /* 766 * stge_start: [ifnet interface function] 767 * 768 * Start packet transmission on the interface. 769 */ 770 static void 771 stge_start(struct ifnet *ifp) 772 { 773 struct stge_softc *sc = ifp->if_softc; 774 struct mbuf *m0; 775 struct stge_descsoft *ds; 776 struct stge_tfd *tfd; 777 bus_dmamap_t dmamap; 778 int error, firsttx, nexttx, opending, seg, totlen; 779 uint64_t csum_flags; 780 781 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 782 return; 783 784 /* 785 * Remember the previous number of pending transmissions 786 * and the first descriptor we will use. 787 */ 788 opending = sc->sc_txpending; 789 firsttx = STGE_NEXTTX(sc->sc_txlast); 790 791 /* 792 * Loop through the send queue, setting up transmit descriptors 793 * until we drain the queue, or use up all available transmit 794 * descriptors. 795 */ 796 for (;;) { 797 struct m_tag *mtag; 798 uint64_t tfc; 799 800 /* 801 * Grab a packet off the queue. 802 */ 803 IFQ_POLL(&ifp->if_snd, m0); 804 if (m0 == NULL) 805 break; 806 807 /* 808 * Leave one unused descriptor at the end of the 809 * list to prevent wrapping completely around. 810 */ 811 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 812 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 813 break; 814 } 815 816 /* 817 * See if we have any VLAN stuff. 818 */ 819 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 820 821 /* 822 * Get the last and next available transmit descriptor. 823 */ 824 nexttx = STGE_NEXTTX(sc->sc_txlast); 825 tfd = &sc->sc_txdescs[nexttx]; 826 ds = &sc->sc_txsoft[nexttx]; 827 828 dmamap = ds->ds_dmamap; 829 830 /* 831 * Load the DMA map. If this fails, the packet either 832 * didn't fit in the alloted number of segments, or we 833 * were short on resources. For the too-many-segments 834 * case, we simply report an error and drop the packet, 835 * since we can't sanely copy a jumbo packet to a single 836 * buffer. 837 */ 838 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 839 BUS_DMA_NOWAIT); 840 if (error) { 841 if (error == EFBIG) { 842 printf("%s: Tx packet consumes too many " 843 "DMA segments, dropping...\n", 844 device_xname(sc->sc_dev)); 845 IFQ_DEQUEUE(&ifp->if_snd, m0); 846 m_freem(m0); 847 continue; 848 } 849 /* 850 * Short on resources, just stop for now. 851 */ 852 break; 853 } 854 855 IFQ_DEQUEUE(&ifp->if_snd, m0); 856 857 /* 858 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 859 */ 860 861 /* Sync the DMA map. */ 862 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 863 BUS_DMASYNC_PREWRITE); 864 865 /* Initialize the fragment list. */ 866 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 867 tfd->tfd_frags[seg].frag_word0 = 868 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 869 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 870 totlen += dmamap->dm_segs[seg].ds_len; 871 } 872 873 #ifdef STGE_EVENT_COUNTERS 874 switch (dmamap->dm_nsegs) { 875 case 1: 876 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 877 break; 878 case 2: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 880 break; 881 case 3: 882 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 883 break; 884 case 4: 885 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 886 break; 887 case 5: 888 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 889 break; 890 default: 891 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 892 break; 893 } 894 #endif /* STGE_EVENT_COUNTERS */ 895 896 /* 897 * Initialize checksumming flags in the descriptor. 898 * Byte-swap constants so the compiler can optimize. 899 */ 900 csum_flags = 0; 901 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 902 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 903 csum_flags |= TFD_IPChecksumEnable; 904 } 905 906 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 907 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 908 csum_flags |= TFD_TCPChecksumEnable; 909 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 910 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 911 csum_flags |= TFD_UDPChecksumEnable; 912 } 913 914 /* 915 * Initialize the descriptor and give it to the chip. 916 * Check to see if we have a VLAN tag to insert. 917 */ 918 919 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 920 TFD_FragCount(seg) | csum_flags | 921 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 922 TFD_TxDMAIndicate : 0); 923 if (mtag) { 924 #if 0 925 struct ether_header *eh = 926 mtod(m0, struct ether_header *); 927 u_int16_t etype = ntohs(eh->ether_type); 928 printf("%s: xmit (tag %d) etype %x\n", 929 ifp->if_xname, *mtod(n, int *), etype); 930 #endif 931 tfc |= TFD_VLANTagInsert | 932 #ifdef STGE_VLAN_CFI 933 TFD_CFI | 934 #endif 935 TFD_VID(VLAN_TAG_VALUE(mtag)); 936 } 937 tfd->tfd_control = htole64(tfc); 938 939 /* Sync the descriptor. */ 940 STGE_CDTXSYNC(sc, nexttx, 941 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 942 943 /* 944 * Kick the transmit DMA logic. 945 */ 946 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 947 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 948 949 /* 950 * Store a pointer to the packet so we can free it later. 951 */ 952 ds->ds_mbuf = m0; 953 954 /* Advance the tx pointer. */ 955 sc->sc_txpending++; 956 sc->sc_txlast = nexttx; 957 958 #if NBPFILTER > 0 959 /* 960 * Pass the packet to any BPF listeners. 961 */ 962 if (ifp->if_bpf) 963 bpf_mtap(ifp->if_bpf, m0); 964 #endif /* NBPFILTER > 0 */ 965 } 966 967 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 968 /* No more slots left; notify upper layer. */ 969 ifp->if_flags |= IFF_OACTIVE; 970 } 971 972 if (sc->sc_txpending != opending) { 973 /* 974 * We enqueued packets. If the transmitter was idle, 975 * reset the txdirty pointer. 976 */ 977 if (opending == 0) 978 sc->sc_txdirty = firsttx; 979 980 /* Set a watchdog timer in case the chip flakes out. */ 981 ifp->if_timer = 5; 982 } 983 } 984 985 /* 986 * stge_watchdog: [ifnet interface function] 987 * 988 * Watchdog timer handler. 989 */ 990 static void 991 stge_watchdog(struct ifnet *ifp) 992 { 993 struct stge_softc *sc = ifp->if_softc; 994 995 /* 996 * Sweep up first, since we don't interrupt every frame. 997 */ 998 stge_txintr(sc); 999 if (sc->sc_txpending != 0) { 1000 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1001 ifp->if_oerrors++; 1002 1003 (void) stge_init(ifp); 1004 1005 /* Try to get more packets going. */ 1006 stge_start(ifp); 1007 } 1008 } 1009 1010 /* 1011 * stge_ioctl: [ifnet interface function] 1012 * 1013 * Handle control requests from the operator. 1014 */ 1015 static int 1016 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1017 { 1018 struct stge_softc *sc = ifp->if_softc; 1019 int s, error; 1020 1021 s = splnet(); 1022 1023 error = ether_ioctl(ifp, cmd, data); 1024 if (error == ENETRESET) { 1025 error = 0; 1026 1027 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1028 ; 1029 else if (ifp->if_flags & IFF_RUNNING) { 1030 /* 1031 * Multicast list has changed; set the hardware filter 1032 * accordingly. 1033 */ 1034 stge_set_filter(sc); 1035 } 1036 } 1037 1038 /* Try to get more packets going. */ 1039 stge_start(ifp); 1040 1041 splx(s); 1042 return (error); 1043 } 1044 1045 /* 1046 * stge_intr: 1047 * 1048 * Interrupt service routine. 1049 */ 1050 static int 1051 stge_intr(void *arg) 1052 { 1053 struct stge_softc *sc = arg; 1054 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1055 uint32_t txstat; 1056 int wantinit; 1057 uint16_t isr; 1058 1059 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1060 IS_InterruptStatus) == 0) 1061 return (0); 1062 1063 for (wantinit = 0; wantinit == 0;) { 1064 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1065 if ((isr & sc->sc_IntEnable) == 0) 1066 break; 1067 1068 /* Host interface errors. */ 1069 if (isr & IS_HostError) { 1070 printf("%s: Host interface error\n", 1071 device_xname(sc->sc_dev)); 1072 wantinit = 1; 1073 continue; 1074 } 1075 1076 /* Receive interrupts. */ 1077 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1078 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1079 stge_rxintr(sc); 1080 if (isr & IS_RFDListEnd) { 1081 printf("%s: receive ring overflow\n", 1082 device_xname(sc->sc_dev)); 1083 /* 1084 * XXX Should try to recover from this 1085 * XXX more gracefully. 1086 */ 1087 wantinit = 1; 1088 } 1089 } 1090 1091 /* Transmit interrupts. */ 1092 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1093 #ifdef STGE_EVENT_COUNTERS 1094 if (isr & IS_TxDMAComplete) 1095 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1096 #endif 1097 stge_txintr(sc); 1098 } 1099 1100 /* Statistics overflow. */ 1101 if (isr & IS_UpdateStats) 1102 stge_stats_update(sc); 1103 1104 /* Transmission errors. */ 1105 if (isr & IS_TxComplete) { 1106 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1107 for (;;) { 1108 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1109 STGE_TxStatus); 1110 if ((txstat & TS_TxComplete) == 0) 1111 break; 1112 if (txstat & TS_TxUnderrun) { 1113 sc->sc_txthresh++; 1114 if (sc->sc_txthresh > 0x0fff) 1115 sc->sc_txthresh = 0x0fff; 1116 printf("%s: transmit underrun, new " 1117 "threshold: %d bytes\n", 1118 device_xname(sc->sc_dev), 1119 sc->sc_txthresh << 5); 1120 } 1121 if (txstat & TS_MaxCollisions) 1122 printf("%s: excessive collisions\n", 1123 device_xname(sc->sc_dev)); 1124 } 1125 wantinit = 1; 1126 } 1127 1128 } 1129 1130 if (wantinit) 1131 stge_init(ifp); 1132 1133 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1134 sc->sc_IntEnable); 1135 1136 /* Try to get more packets going. */ 1137 stge_start(ifp); 1138 1139 return (1); 1140 } 1141 1142 /* 1143 * stge_txintr: 1144 * 1145 * Helper; handle transmit interrupts. 1146 */ 1147 static void 1148 stge_txintr(struct stge_softc *sc) 1149 { 1150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1151 struct stge_descsoft *ds; 1152 uint64_t control; 1153 int i; 1154 1155 ifp->if_flags &= ~IFF_OACTIVE; 1156 1157 /* 1158 * Go through our Tx list and free mbufs for those 1159 * frames which have been transmitted. 1160 */ 1161 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1162 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1163 ds = &sc->sc_txsoft[i]; 1164 1165 STGE_CDTXSYNC(sc, i, 1166 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1167 1168 control = le64toh(sc->sc_txdescs[i].tfd_control); 1169 if ((control & TFD_TFDDone) == 0) 1170 break; 1171 1172 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1173 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1174 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1175 m_freem(ds->ds_mbuf); 1176 ds->ds_mbuf = NULL; 1177 } 1178 1179 /* Update the dirty transmit buffer pointer. */ 1180 sc->sc_txdirty = i; 1181 1182 /* 1183 * If there are no more pending transmissions, cancel the watchdog 1184 * timer. 1185 */ 1186 if (sc->sc_txpending == 0) 1187 ifp->if_timer = 0; 1188 } 1189 1190 /* 1191 * stge_rxintr: 1192 * 1193 * Helper; handle receive interrupts. 1194 */ 1195 static void 1196 stge_rxintr(struct stge_softc *sc) 1197 { 1198 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1199 struct stge_descsoft *ds; 1200 struct mbuf *m, *tailm; 1201 uint64_t status; 1202 int i, len; 1203 1204 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1205 ds = &sc->sc_rxsoft[i]; 1206 1207 STGE_CDRXSYNC(sc, i, 1208 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1209 1210 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1211 1212 if ((status & RFD_RFDDone) == 0) 1213 break; 1214 1215 if (__predict_false(sc->sc_rxdiscard)) { 1216 STGE_INIT_RXDESC(sc, i); 1217 if (status & RFD_FrameEnd) { 1218 /* Reset our state. */ 1219 sc->sc_rxdiscard = 0; 1220 } 1221 continue; 1222 } 1223 1224 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1225 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1226 1227 m = ds->ds_mbuf; 1228 1229 /* 1230 * Add a new receive buffer to the ring. 1231 */ 1232 if (stge_add_rxbuf(sc, i) != 0) { 1233 /* 1234 * Failed, throw away what we've done so 1235 * far, and discard the rest of the packet. 1236 */ 1237 ifp->if_ierrors++; 1238 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1239 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1240 STGE_INIT_RXDESC(sc, i); 1241 if ((status & RFD_FrameEnd) == 0) 1242 sc->sc_rxdiscard = 1; 1243 if (sc->sc_rxhead != NULL) 1244 m_freem(sc->sc_rxhead); 1245 STGE_RXCHAIN_RESET(sc); 1246 continue; 1247 } 1248 1249 #ifdef DIAGNOSTIC 1250 if (status & RFD_FrameStart) { 1251 KASSERT(sc->sc_rxhead == NULL); 1252 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1253 } 1254 #endif 1255 1256 STGE_RXCHAIN_LINK(sc, m); 1257 1258 /* 1259 * If this is not the end of the packet, keep 1260 * looking. 1261 */ 1262 if ((status & RFD_FrameEnd) == 0) { 1263 sc->sc_rxlen += m->m_len; 1264 continue; 1265 } 1266 1267 /* 1268 * Okay, we have the entire packet now... 1269 */ 1270 *sc->sc_rxtailp = NULL; 1271 m = sc->sc_rxhead; 1272 tailm = sc->sc_rxtail; 1273 1274 STGE_RXCHAIN_RESET(sc); 1275 1276 /* 1277 * If the packet had an error, drop it. Note we 1278 * count the error later in the periodic stats update. 1279 */ 1280 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1281 RFD_RxAlignmentError | RFD_RxFCSError | 1282 RFD_RxLengthError)) { 1283 m_freem(m); 1284 continue; 1285 } 1286 1287 /* 1288 * No errors. 1289 * 1290 * Note we have configured the chip to not include 1291 * the CRC at the end of the packet. 1292 */ 1293 len = RFD_RxDMAFrameLen(status); 1294 tailm->m_len = len - sc->sc_rxlen; 1295 1296 /* 1297 * If the packet is small enough to fit in a 1298 * single header mbuf, allocate one and copy 1299 * the data into it. This greatly reduces 1300 * memory consumption when we receive lots 1301 * of small packets. 1302 */ 1303 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1304 struct mbuf *nm; 1305 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1306 if (nm == NULL) { 1307 ifp->if_ierrors++; 1308 m_freem(m); 1309 continue; 1310 } 1311 nm->m_data += 2; 1312 nm->m_pkthdr.len = nm->m_len = len; 1313 m_copydata(m, 0, len, mtod(nm, void *)); 1314 m_freem(m); 1315 m = nm; 1316 } 1317 1318 /* 1319 * Set the incoming checksum information for the packet. 1320 */ 1321 if (status & RFD_IPDetected) { 1322 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1323 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1324 if (status & RFD_IPError) 1325 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1326 if (status & RFD_TCPDetected) { 1327 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1328 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1329 if (status & RFD_TCPError) 1330 m->m_pkthdr.csum_flags |= 1331 M_CSUM_TCP_UDP_BAD; 1332 } else if (status & RFD_UDPDetected) { 1333 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1334 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1335 if (status & RFD_UDPError) 1336 m->m_pkthdr.csum_flags |= 1337 M_CSUM_TCP_UDP_BAD; 1338 } 1339 } 1340 1341 m->m_pkthdr.rcvif = ifp; 1342 m->m_pkthdr.len = len; 1343 1344 #if NBPFILTER > 0 1345 /* 1346 * Pass this up to any BPF listeners, but only 1347 * pass if up the stack if it's for us. 1348 */ 1349 if (ifp->if_bpf) 1350 bpf_mtap(ifp->if_bpf, m); 1351 #endif /* NBPFILTER > 0 */ 1352 #ifdef STGE_VLAN_UNTAG 1353 /* 1354 * Check for VLAN tagged packets 1355 */ 1356 if (status & RFD_VLANDetected) 1357 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1358 1359 #endif 1360 #if 0 1361 if (status & RFD_VLANDetected) { 1362 struct ether_header *eh; 1363 u_int16_t etype; 1364 1365 eh = mtod(m, struct ether_header *); 1366 etype = ntohs(eh->ether_type); 1367 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1368 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1369 etype); 1370 } 1371 #endif 1372 /* Pass it on. */ 1373 (*ifp->if_input)(ifp, m); 1374 } 1375 1376 /* Update the receive pointer. */ 1377 sc->sc_rxptr = i; 1378 } 1379 1380 /* 1381 * stge_tick: 1382 * 1383 * One second timer, used to tick the MII. 1384 */ 1385 static void 1386 stge_tick(void *arg) 1387 { 1388 struct stge_softc *sc = arg; 1389 int s; 1390 1391 s = splnet(); 1392 mii_tick(&sc->sc_mii); 1393 stge_stats_update(sc); 1394 splx(s); 1395 1396 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1397 } 1398 1399 /* 1400 * stge_stats_update: 1401 * 1402 * Read the TC9021 statistics counters. 1403 */ 1404 static void 1405 stge_stats_update(struct stge_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1408 bus_space_tag_t st = sc->sc_st; 1409 bus_space_handle_t sh = sc->sc_sh; 1410 1411 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1412 1413 ifp->if_ipackets += 1414 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1415 1416 ifp->if_ierrors += 1417 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1418 1419 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1420 1421 ifp->if_opackets += 1422 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1423 1424 ifp->if_collisions += 1425 bus_space_read_4(st, sh, STGE_LateCollisions) + 1426 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1427 bus_space_read_4(st, sh, STGE_SingleColFrames); 1428 1429 ifp->if_oerrors += 1430 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1431 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1432 } 1433 1434 /* 1435 * stge_reset: 1436 * 1437 * Perform a soft reset on the TC9021. 1438 */ 1439 static void 1440 stge_reset(struct stge_softc *sc) 1441 { 1442 uint32_t ac; 1443 int i; 1444 1445 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1446 1447 /* 1448 * Only assert RstOut if we're fiber. We need GMII clocks 1449 * to be present in order for the reset to complete on fiber 1450 * cards. 1451 */ 1452 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1453 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1454 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1455 (sc->sc_usefiber ? AC_RstOut : 0)); 1456 1457 delay(50000); 1458 1459 for (i = 0; i < STGE_TIMEOUT; i++) { 1460 delay(5000); 1461 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1462 AC_ResetBusy) == 0) 1463 break; 1464 } 1465 1466 if (i == STGE_TIMEOUT) 1467 printf("%s: reset failed to complete\n", 1468 device_xname(sc->sc_dev)); 1469 1470 delay(1000); 1471 } 1472 1473 /* 1474 * stge_init: [ ifnet interface function ] 1475 * 1476 * Initialize the interface. Must be called at splnet(). 1477 */ 1478 static int 1479 stge_init(struct ifnet *ifp) 1480 { 1481 struct stge_softc *sc = ifp->if_softc; 1482 bus_space_tag_t st = sc->sc_st; 1483 bus_space_handle_t sh = sc->sc_sh; 1484 struct stge_descsoft *ds; 1485 int i, error = 0; 1486 1487 /* 1488 * Cancel any pending I/O. 1489 */ 1490 stge_stop(ifp, 0); 1491 1492 /* 1493 * Reset the chip to a known state. 1494 */ 1495 stge_reset(sc); 1496 1497 /* 1498 * Initialize the transmit descriptor ring. 1499 */ 1500 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1501 for (i = 0; i < STGE_NTXDESC; i++) { 1502 sc->sc_txdescs[i].tfd_next = htole64( 1503 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1504 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1505 } 1506 sc->sc_txpending = 0; 1507 sc->sc_txdirty = 0; 1508 sc->sc_txlast = STGE_NTXDESC - 1; 1509 1510 /* 1511 * Initialize the receive descriptor and receive job 1512 * descriptor rings. 1513 */ 1514 for (i = 0; i < STGE_NRXDESC; i++) { 1515 ds = &sc->sc_rxsoft[i]; 1516 if (ds->ds_mbuf == NULL) { 1517 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1518 printf("%s: unable to allocate or map rx " 1519 "buffer %d, error = %d\n", 1520 device_xname(sc->sc_dev), i, error); 1521 /* 1522 * XXX Should attempt to run with fewer receive 1523 * XXX buffers instead of just failing. 1524 */ 1525 stge_rxdrain(sc); 1526 goto out; 1527 } 1528 } else 1529 STGE_INIT_RXDESC(sc, i); 1530 } 1531 sc->sc_rxptr = 0; 1532 sc->sc_rxdiscard = 0; 1533 STGE_RXCHAIN_RESET(sc); 1534 1535 /* Set the station address. */ 1536 for (i = 0; i < 6; i++) 1537 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1538 CLLADDR(ifp->if_sadl)[i]); 1539 1540 /* 1541 * Set the statistics masks. Disable all the RMON stats, 1542 * and disable selected stats in the non-RMON stats registers. 1543 */ 1544 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1545 bus_space_write_4(st, sh, STGE_StatisticsMask, 1546 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1547 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1548 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1549 (1U << 21)); 1550 1551 /* Set up the receive filter. */ 1552 stge_set_filter(sc); 1553 1554 /* 1555 * Give the transmit and receive ring to the chip. 1556 */ 1557 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1558 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1559 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1560 1561 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1562 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1563 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1564 1565 /* 1566 * Initialize the Tx auto-poll period. It's OK to make this number 1567 * large (255 is the max, but we use 127) -- we explicitly kick the 1568 * transmit engine when there's actually a packet. 1569 */ 1570 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1571 1572 /* ..and the Rx auto-poll period. */ 1573 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1574 1575 /* Initialize the Tx start threshold. */ 1576 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1577 1578 /* RX DMA thresholds, from linux */ 1579 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1580 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1581 1582 /* 1583 * Initialize the Rx DMA interrupt control register. We 1584 * request an interrupt after every incoming packet, but 1585 * defer it for 32us (64 * 512 ns). When the number of 1586 * interrupts pending reaches 8, we stop deferring the 1587 * interrupt, and signal it immediately. 1588 */ 1589 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1590 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1591 1592 /* 1593 * Initialize the interrupt mask. 1594 */ 1595 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1596 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1597 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1598 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1599 1600 /* 1601 * Configure the DMA engine. 1602 * XXX Should auto-tune TxBurstLimit. 1603 */ 1604 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1605 DMAC_TxBurstLimit(3)); 1606 1607 /* 1608 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1609 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1610 * empty again. 1611 */ 1612 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1613 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1614 1615 /* 1616 * Set the maximum frame size. 1617 */ 1618 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1619 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1620 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1621 ETHER_VLAN_ENCAP_LEN : 0)); 1622 1623 /* 1624 * Initialize MacCtrl -- do it before setting the media, 1625 * as setting the media will actually program the register. 1626 * 1627 * Note: We have to poke the IFS value before poking 1628 * anything else. 1629 */ 1630 sc->sc_MACCtrl = MC_IFSSelect(0); 1631 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1632 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1633 #ifdef STGE_VLAN_UNTAG 1634 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1635 #endif 1636 1637 if (sc->sc_rev >= 6) { /* >= B.2 */ 1638 /* Multi-frag frame bug work-around. */ 1639 bus_space_write_2(st, sh, STGE_DebugCtrl, 1640 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1641 1642 /* Tx Poll Now bug work-around. */ 1643 bus_space_write_2(st, sh, STGE_DebugCtrl, 1644 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1645 /* XXX ? from linux */ 1646 bus_space_write_2(st, sh, STGE_DebugCtrl, 1647 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1648 } 1649 1650 /* 1651 * Set the current media. 1652 */ 1653 if ((error = ether_mediachange(ifp)) != 0) 1654 goto out; 1655 1656 /* 1657 * Start the one second MII clock. 1658 */ 1659 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1660 1661 /* 1662 * ...all done! 1663 */ 1664 ifp->if_flags |= IFF_RUNNING; 1665 ifp->if_flags &= ~IFF_OACTIVE; 1666 1667 out: 1668 if (error) 1669 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1670 return (error); 1671 } 1672 1673 /* 1674 * stge_drain: 1675 * 1676 * Drain the receive queue. 1677 */ 1678 static void 1679 stge_rxdrain(struct stge_softc *sc) 1680 { 1681 struct stge_descsoft *ds; 1682 int i; 1683 1684 for (i = 0; i < STGE_NRXDESC; i++) { 1685 ds = &sc->sc_rxsoft[i]; 1686 if (ds->ds_mbuf != NULL) { 1687 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1688 ds->ds_mbuf->m_next = NULL; 1689 m_freem(ds->ds_mbuf); 1690 ds->ds_mbuf = NULL; 1691 } 1692 } 1693 } 1694 1695 /* 1696 * stge_stop: [ ifnet interface function ] 1697 * 1698 * Stop transmission on the interface. 1699 */ 1700 static void 1701 stge_stop(struct ifnet *ifp, int disable) 1702 { 1703 struct stge_softc *sc = ifp->if_softc; 1704 struct stge_descsoft *ds; 1705 int i; 1706 1707 /* 1708 * Stop the one second clock. 1709 */ 1710 callout_stop(&sc->sc_tick_ch); 1711 1712 /* Down the MII. */ 1713 mii_down(&sc->sc_mii); 1714 1715 /* 1716 * Disable interrupts. 1717 */ 1718 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1719 1720 /* 1721 * Stop receiver, transmitter, and stats update. 1722 */ 1723 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1724 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1725 1726 /* 1727 * Stop the transmit and receive DMA. 1728 */ 1729 stge_dma_wait(sc); 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1731 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1732 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1733 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1734 1735 /* 1736 * Release any queued transmit buffers. 1737 */ 1738 for (i = 0; i < STGE_NTXDESC; i++) { 1739 ds = &sc->sc_txsoft[i]; 1740 if (ds->ds_mbuf != NULL) { 1741 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1742 m_freem(ds->ds_mbuf); 1743 ds->ds_mbuf = NULL; 1744 } 1745 } 1746 1747 /* 1748 * Mark the interface down and cancel the watchdog timer. 1749 */ 1750 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1751 ifp->if_timer = 0; 1752 1753 if (disable) 1754 stge_rxdrain(sc); 1755 } 1756 1757 static int 1758 stge_eeprom_wait(struct stge_softc *sc) 1759 { 1760 int i; 1761 1762 for (i = 0; i < STGE_TIMEOUT; i++) { 1763 delay(1000); 1764 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1765 EC_EepromBusy) == 0) 1766 return (0); 1767 } 1768 return (1); 1769 } 1770 1771 /* 1772 * stge_read_eeprom: 1773 * 1774 * Read data from the serial EEPROM. 1775 */ 1776 static void 1777 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1778 { 1779 1780 if (stge_eeprom_wait(sc)) 1781 printf("%s: EEPROM failed to come ready\n", 1782 device_xname(sc->sc_dev)); 1783 1784 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1785 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1786 if (stge_eeprom_wait(sc)) 1787 printf("%s: EEPROM read timed out\n", 1788 device_xname(sc->sc_dev)); 1789 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1790 } 1791 1792 /* 1793 * stge_add_rxbuf: 1794 * 1795 * Add a receive buffer to the indicated descriptor. 1796 */ 1797 static int 1798 stge_add_rxbuf(struct stge_softc *sc, int idx) 1799 { 1800 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1801 struct mbuf *m; 1802 int error; 1803 1804 MGETHDR(m, M_DONTWAIT, MT_DATA); 1805 if (m == NULL) 1806 return (ENOBUFS); 1807 1808 MCLGET(m, M_DONTWAIT); 1809 if ((m->m_flags & M_EXT) == 0) { 1810 m_freem(m); 1811 return (ENOBUFS); 1812 } 1813 1814 m->m_data = m->m_ext.ext_buf + 2; 1815 m->m_len = MCLBYTES - 2; 1816 1817 if (ds->ds_mbuf != NULL) 1818 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1819 1820 ds->ds_mbuf = m; 1821 1822 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1823 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1824 if (error) { 1825 printf("%s: can't load rx DMA map %d, error = %d\n", 1826 device_xname(sc->sc_dev), idx, error); 1827 panic("stge_add_rxbuf"); /* XXX */ 1828 } 1829 1830 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1831 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1832 1833 STGE_INIT_RXDESC(sc, idx); 1834 1835 return (0); 1836 } 1837 1838 /* 1839 * stge_set_filter: 1840 * 1841 * Set up the receive filter. 1842 */ 1843 static void 1844 stge_set_filter(struct stge_softc *sc) 1845 { 1846 struct ethercom *ec = &sc->sc_ethercom; 1847 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1848 struct ether_multi *enm; 1849 struct ether_multistep step; 1850 uint32_t crc; 1851 uint32_t mchash[2]; 1852 1853 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1854 if (ifp->if_flags & IFF_BROADCAST) 1855 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1856 1857 /* XXX: ST1023 only works in promiscuous mode */ 1858 if (sc->sc_stge1023) 1859 ifp->if_flags |= IFF_PROMISC; 1860 1861 if (ifp->if_flags & IFF_PROMISC) { 1862 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1863 goto allmulti; 1864 } 1865 1866 /* 1867 * Set up the multicast address filter by passing all multicast 1868 * addresses through a CRC generator, and then using the low-order 1869 * 6 bits as an index into the 64 bit multicast hash table. The 1870 * high order bits select the register, while the rest of the bits 1871 * select the bit within the register. 1872 */ 1873 1874 memset(mchash, 0, sizeof(mchash)); 1875 1876 ETHER_FIRST_MULTI(step, ec, enm); 1877 if (enm == NULL) 1878 goto done; 1879 1880 while (enm != NULL) { 1881 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1882 /* 1883 * We must listen to a range of multicast addresses. 1884 * For now, just accept all multicasts, rather than 1885 * trying to set only those filter bits needed to match 1886 * the range. (At this time, the only use of address 1887 * ranges is for IP multicast routing, for which the 1888 * range is big enough to require all bits set.) 1889 */ 1890 goto allmulti; 1891 } 1892 1893 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1894 1895 /* Just want the 6 least significant bits. */ 1896 crc &= 0x3f; 1897 1898 /* Set the corresponding bit in the hash table. */ 1899 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1900 1901 ETHER_NEXT_MULTI(step, enm); 1902 } 1903 1904 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1905 1906 ifp->if_flags &= ~IFF_ALLMULTI; 1907 goto done; 1908 1909 allmulti: 1910 ifp->if_flags |= IFF_ALLMULTI; 1911 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1912 1913 done: 1914 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1915 /* 1916 * Program the multicast hash table. 1917 */ 1918 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1919 mchash[0]); 1920 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1921 mchash[1]); 1922 } 1923 1924 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1925 sc->sc_ReceiveMode); 1926 } 1927 1928 /* 1929 * stge_mii_readreg: [mii interface function] 1930 * 1931 * Read a PHY register on the MII of the TC9021. 1932 */ 1933 static int 1934 stge_mii_readreg(device_t self, int phy, int reg) 1935 { 1936 1937 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1938 } 1939 1940 /* 1941 * stge_mii_writereg: [mii interface function] 1942 * 1943 * Write a PHY register on the MII of the TC9021. 1944 */ 1945 static void 1946 stge_mii_writereg(device_t self, int phy, int reg, int val) 1947 { 1948 1949 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1950 } 1951 1952 /* 1953 * stge_mii_statchg: [mii interface function] 1954 * 1955 * Callback from MII layer when media changes. 1956 */ 1957 static void 1958 stge_mii_statchg(device_t self) 1959 { 1960 struct stge_softc *sc = device_private(self); 1961 1962 if (sc->sc_mii.mii_media_active & IFM_FDX) 1963 sc->sc_MACCtrl |= MC_DuplexSelect; 1964 else 1965 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1966 1967 /* XXX 802.1x flow-control? */ 1968 1969 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1970 } 1971 1972 /* 1973 * sste_mii_bitbang_read: [mii bit-bang interface function] 1974 * 1975 * Read the MII serial port for the MII bit-bang module. 1976 */ 1977 static uint32_t 1978 stge_mii_bitbang_read(device_t self) 1979 { 1980 struct stge_softc *sc = device_private(self); 1981 1982 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1983 } 1984 1985 /* 1986 * stge_mii_bitbang_write: [mii big-bang interface function] 1987 * 1988 * Write the MII serial port for the MII bit-bang module. 1989 */ 1990 static void 1991 stge_mii_bitbang_write(device_t self, uint32_t val) 1992 { 1993 struct stge_softc *sc = device_private(self); 1994 1995 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1996 val | sc->sc_PhyCtrl); 1997 } 1998