1 /* $NetBSD: if_stge.c,v 1.47 2009/05/17 02:08:35 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.47 2009/05/17 02:08:35 tsutsui Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/mii/mii_bitbang.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_stgereg.h> 77 78 /* #define STGE_CU_BUG 1 */ 79 #define STGE_VLAN_UNTAG 1 80 /* #define STGE_VLAN_CFI 1 */ 81 82 /* 83 * Transmit descriptor list size. 84 */ 85 #define STGE_NTXDESC 256 86 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 87 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 88 89 /* 90 * Receive descriptor list size. 91 */ 92 #define STGE_NRXDESC 256 93 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 94 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 95 96 /* 97 * Only interrupt every N frames. Must be a power-of-two. 98 */ 99 #define STGE_TXINTR_SPACING 16 100 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 101 102 /* 103 * Control structures are DMA'd to the TC9021 chip. We allocate them in 104 * a single clump that maps to a single DMA segment to make several things 105 * easier. 106 */ 107 struct stge_control_data { 108 /* 109 * The transmit descriptors. 110 */ 111 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 112 113 /* 114 * The receive descriptors. 115 */ 116 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 117 }; 118 119 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 120 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 121 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 122 123 /* 124 * Software state for transmit and receive jobs. 125 */ 126 struct stge_descsoft { 127 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 128 bus_dmamap_t ds_dmamap; /* our DMA map */ 129 }; 130 131 /* 132 * Software state per device. 133 */ 134 struct stge_softc { 135 device_t sc_dev; /* generic device information */ 136 bus_space_tag_t sc_st; /* bus space tag */ 137 bus_space_handle_t sc_sh; /* bus space handle */ 138 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 139 struct ethercom sc_ethercom; /* ethernet common data */ 140 void *sc_sdhook; /* shutdown hook */ 141 int sc_rev; /* silicon revision */ 142 143 void *sc_ih; /* interrupt cookie */ 144 145 struct mii_data sc_mii; /* MII/media information */ 146 147 callout_t sc_tick_ch; /* tick callout */ 148 149 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 150 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 151 152 /* 153 * Software state for transmit and receive descriptors. 154 */ 155 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 156 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 157 158 /* 159 * Control data structures. 160 */ 161 struct stge_control_data *sc_control_data; 162 #define sc_txdescs sc_control_data->scd_txdescs 163 #define sc_rxdescs sc_control_data->scd_rxdescs 164 165 #ifdef STGE_EVENT_COUNTERS 166 /* 167 * Event counters. 168 */ 169 struct evcnt sc_ev_txstall; /* Tx stalled */ 170 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 171 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 172 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 173 174 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 175 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 176 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 177 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 178 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 179 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 180 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 181 182 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 183 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 184 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 185 186 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 187 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 188 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 189 #endif /* STGE_EVENT_COUNTERS */ 190 191 int sc_txpending; /* number of Tx requests pending */ 192 int sc_txdirty; /* first dirty Tx descriptor */ 193 int sc_txlast; /* last used Tx descriptor */ 194 195 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 196 int sc_rxdiscard; 197 int sc_rxlen; 198 struct mbuf *sc_rxhead; 199 struct mbuf *sc_rxtail; 200 struct mbuf **sc_rxtailp; 201 202 int sc_txthresh; /* Tx threshold */ 203 uint32_t sc_usefiber:1; /* if we're fiber */ 204 uint32_t sc_stge1023:1; /* are we a 1023 */ 205 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 206 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 207 uint16_t sc_IntEnable; /* prototype IntEnable register */ 208 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 209 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 210 }; 211 212 #define STGE_RXCHAIN_RESET(sc) \ 213 do { \ 214 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 215 *(sc)->sc_rxtailp = NULL; \ 216 (sc)->sc_rxlen = 0; \ 217 } while (/*CONSTCOND*/0) 218 219 #define STGE_RXCHAIN_LINK(sc, m) \ 220 do { \ 221 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 222 (sc)->sc_rxtailp = &(m)->m_next; \ 223 } while (/*CONSTCOND*/0) 224 225 #ifdef STGE_EVENT_COUNTERS 226 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 227 #else 228 #define STGE_EVCNT_INCR(ev) /* nothing */ 229 #endif 230 231 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 232 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 233 234 #define STGE_CDTXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 237 238 #define STGE_CDRXSYNC(sc, x, ops) \ 239 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 240 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 241 242 #define STGE_INIT_RXDESC(sc, x) \ 243 do { \ 244 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 245 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 246 \ 247 /* \ 248 * Note: We scoot the packet forward 2 bytes in the buffer \ 249 * so that the payload after the Ethernet header is aligned \ 250 * to a 4-byte boundary. \ 251 */ \ 252 __rfd->rfd_frag.frag_word0 = \ 253 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 254 FRAG_LEN(MCLBYTES - 2)); \ 255 __rfd->rfd_next = \ 256 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 257 __rfd->rfd_status = 0; \ 258 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 259 } while (/*CONSTCOND*/0) 260 261 #define STGE_TIMEOUT 1000 262 263 static void stge_start(struct ifnet *); 264 static void stge_watchdog(struct ifnet *); 265 static int stge_ioctl(struct ifnet *, u_long, void *); 266 static int stge_init(struct ifnet *); 267 static void stge_stop(struct ifnet *, int); 268 269 static void stge_shutdown(void *); 270 271 static void stge_reset(struct stge_softc *); 272 static void stge_rxdrain(struct stge_softc *); 273 static int stge_add_rxbuf(struct stge_softc *, int); 274 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 275 static void stge_tick(void *); 276 277 static void stge_stats_update(struct stge_softc *); 278 279 static void stge_set_filter(struct stge_softc *); 280 281 static int stge_intr(void *); 282 static void stge_txintr(struct stge_softc *); 283 static void stge_rxintr(struct stge_softc *); 284 285 static int stge_mii_readreg(device_t, int, int); 286 static void stge_mii_writereg(device_t, int, int, int); 287 static void stge_mii_statchg(device_t); 288 289 static int stge_match(device_t, cfdata_t, void *); 290 static void stge_attach(device_t, device_t, void *); 291 292 int stge_copy_small = 0; 293 294 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 295 stge_match, stge_attach, NULL, NULL); 296 297 static uint32_t stge_mii_bitbang_read(device_t); 298 static void stge_mii_bitbang_write(device_t, uint32_t); 299 300 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 301 stge_mii_bitbang_read, 302 stge_mii_bitbang_write, 303 { 304 PC_MgmtData, /* MII_BIT_MDO */ 305 PC_MgmtData, /* MII_BIT_MDI */ 306 PC_MgmtClk, /* MII_BIT_MDC */ 307 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 308 0, /* MII_BIT_DIR_PHY_HOST */ 309 } 310 }; 311 312 /* 313 * Devices supported by this driver. 314 */ 315 static const struct stge_product { 316 pci_vendor_id_t stge_vendor; 317 pci_product_id_t stge_product; 318 const char *stge_name; 319 } stge_products[] = { 320 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 321 "Sundance ST-1023 Gigabit Ethernet" }, 322 323 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 324 "Sundance ST-2021 Gigabit Ethernet" }, 325 326 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 327 "Tamarack TC9021 Gigabit Ethernet" }, 328 329 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 330 "Tamarack TC9021 Gigabit Ethernet" }, 331 332 /* 333 * The Sundance sample boards use the Sundance vendor ID, 334 * but the Tamarack product ID. 335 */ 336 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 337 "Sundance TC9021 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 340 "Sundance TC9021 Gigabit Ethernet" }, 341 342 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 343 "D-Link DL-4000 Gigabit Ethernet" }, 344 345 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 346 "Antares Gigabit Ethernet" }, 347 348 { 0, 0, 349 NULL }, 350 }; 351 352 static const struct stge_product * 353 stge_lookup(const struct pci_attach_args *pa) 354 { 355 const struct stge_product *sp; 356 357 for (sp = stge_products; sp->stge_name != NULL; sp++) { 358 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 359 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 360 return (sp); 361 } 362 return (NULL); 363 } 364 365 static int 366 stge_match(device_t parent, cfdata_t cf, void *aux) 367 { 368 struct pci_attach_args *pa = aux; 369 370 if (stge_lookup(pa) != NULL) 371 return (1); 372 373 return (0); 374 } 375 376 static void 377 stge_attach(device_t parent, device_t self, void *aux) 378 { 379 struct stge_softc *sc = device_private(self); 380 struct pci_attach_args *pa = aux; 381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pci_intr_handle_t ih; 384 const char *intrstr = NULL; 385 bus_space_tag_t iot, memt; 386 bus_space_handle_t ioh, memh; 387 bus_dma_segment_t seg; 388 int ioh_valid, memh_valid; 389 int i, rseg, error; 390 const struct stge_product *sp; 391 uint8_t enaddr[ETHER_ADDR_LEN]; 392 393 callout_init(&sc->sc_tick_ch, 0); 394 395 sp = stge_lookup(pa); 396 if (sp == NULL) { 397 printf("\n"); 398 panic("ste_attach: impossible"); 399 } 400 401 sc->sc_rev = PCI_REVISION(pa->pa_class); 402 403 aprint_normal(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 404 405 /* 406 * Map the device. 407 */ 408 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 409 PCI_MAPREG_TYPE_IO, 0, 410 &iot, &ioh, NULL, NULL) == 0); 411 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 412 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 413 &memt, &memh, NULL, NULL) == 0); 414 415 if (memh_valid) { 416 sc->sc_st = memt; 417 sc->sc_sh = memh; 418 } else if (ioh_valid) { 419 sc->sc_st = iot; 420 sc->sc_sh = ioh; 421 } else { 422 aprint_error_dev(self, "unable to map device registers\n"); 423 return; 424 } 425 426 sc->sc_dmat = pa->pa_dmat; 427 428 /* Enable bus mastering. */ 429 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 430 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 431 PCI_COMMAND_MASTER_ENABLE); 432 433 /* power up chip */ 434 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 435 error != EOPNOTSUPP) { 436 aprint_error_dev(self, "cannot activate %d\n", 437 error); 438 return; 439 } 440 /* 441 * Map and establish our interrupt. 442 */ 443 if (pci_intr_map(pa, &ih)) { 444 aprint_error_dev(self, "unable to map interrupt\n"); 445 return; 446 } 447 intrstr = pci_intr_string(pc, ih); 448 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 449 if (sc->sc_ih == NULL) { 450 aprint_error_dev(self, "unable to establish interrupt"); 451 if (intrstr != NULL) 452 aprint_error(" at %s", intrstr); 453 aprint_error("\n"); 454 return; 455 } 456 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 457 458 /* 459 * Allocate the control data structures, and create and load the 460 * DMA map for it. 461 */ 462 if ((error = bus_dmamem_alloc(sc->sc_dmat, 463 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 464 0)) != 0) { 465 aprint_error_dev(self, 466 "unable to allocate control data, error = %d\n", 467 error); 468 goto fail_0; 469 } 470 471 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 472 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 473 BUS_DMA_COHERENT)) != 0) { 474 aprint_error_dev(self, 475 "unable to map control data, error = %d\n", 476 error); 477 goto fail_1; 478 } 479 480 if ((error = bus_dmamap_create(sc->sc_dmat, 481 sizeof(struct stge_control_data), 1, 482 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 483 aprint_error_dev(self, 484 "unable to create control data DMA map, error = %d\n", 485 error); 486 goto fail_2; 487 } 488 489 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 490 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 491 0)) != 0) { 492 aprint_error_dev(self, 493 "unable to load control data DMA map, error = %d\n", 494 error); 495 goto fail_3; 496 } 497 498 /* 499 * Create the transmit buffer DMA maps. Note that rev B.3 500 * and earlier seem to have a bug regarding multi-fragment 501 * packets. We need to limit the number of Tx segments on 502 * such chips to 1. 503 */ 504 for (i = 0; i < STGE_NTXDESC; i++) { 505 if ((error = bus_dmamap_create(sc->sc_dmat, 506 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 507 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 508 aprint_error_dev(self, 509 "unable to create tx DMA map %d, error = %d\n", 510 i, error); 511 goto fail_4; 512 } 513 } 514 515 /* 516 * Create the receive buffer DMA maps. 517 */ 518 for (i = 0; i < STGE_NRXDESC; i++) { 519 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 520 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 521 aprint_error_dev(self, 522 "unable to create rx DMA map %d, error = %d\n", 523 i, error); 524 goto fail_5; 525 } 526 sc->sc_rxsoft[i].ds_mbuf = NULL; 527 } 528 529 /* 530 * Determine if we're copper or fiber. It affects how we 531 * reset the card. 532 */ 533 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 534 AC_PhyMedia) 535 sc->sc_usefiber = 1; 536 else 537 sc->sc_usefiber = 0; 538 539 /* 540 * Reset the chip to a known state. 541 */ 542 stge_reset(sc); 543 544 /* 545 * Reading the station address from the EEPROM doesn't seem 546 * to work, at least on my sample boards. Instead, since 547 * the reset sequence does AutoInit, read it from the station 548 * address registers. For Sundance 1023 you can only read it 549 * from EEPROM. 550 */ 551 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 552 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 553 STGE_StationAddress0) & 0xff; 554 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 555 STGE_StationAddress0) >> 8; 556 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 557 STGE_StationAddress1) & 0xff; 558 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 559 STGE_StationAddress1) >> 8; 560 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 561 STGE_StationAddress2) & 0xff; 562 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 563 STGE_StationAddress2) >> 8; 564 sc->sc_stge1023 = 0; 565 } else { 566 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 567 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 568 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 569 &myaddr[i]); 570 myaddr[i] = le16toh(myaddr[i]); 571 } 572 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 573 sc->sc_stge1023 = 1; 574 } 575 576 aprint_normal_dev(self, "Ethernet address %s\n", 577 ether_sprintf(enaddr)); 578 579 /* 580 * Read some important bits from the PhyCtrl register. 581 */ 582 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 583 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 584 585 /* 586 * Initialize our media structures and probe the MII. 587 */ 588 sc->sc_mii.mii_ifp = ifp; 589 sc->sc_mii.mii_readreg = stge_mii_readreg; 590 sc->sc_mii.mii_writereg = stge_mii_writereg; 591 sc->sc_mii.mii_statchg = stge_mii_statchg; 592 sc->sc_ethercom.ec_mii = &sc->sc_mii; 593 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 594 ether_mediastatus); 595 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 596 MII_OFFSET_ANY, MIIF_DOPAUSE); 597 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 598 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 599 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 600 } else 601 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 602 603 ifp = &sc->sc_ethercom.ec_if; 604 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 605 ifp->if_softc = sc; 606 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 607 ifp->if_ioctl = stge_ioctl; 608 ifp->if_start = stge_start; 609 ifp->if_watchdog = stge_watchdog; 610 ifp->if_init = stge_init; 611 ifp->if_stop = stge_stop; 612 IFQ_SET_READY(&ifp->if_snd); 613 614 /* 615 * The manual recommends disabling early transmit, so we 616 * do. It's disabled anyway, if using IP checksumming, 617 * since the entire packet must be in the FIFO in order 618 * for the chip to perform the checksum. 619 */ 620 sc->sc_txthresh = 0x0fff; 621 622 /* 623 * Disable MWI if the PCI layer tells us to. 624 */ 625 sc->sc_DMACtrl = 0; 626 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 627 sc->sc_DMACtrl |= DMAC_MWIDisable; 628 629 /* 630 * We can support 802.1Q VLAN-sized frames and jumbo 631 * Ethernet frames. 632 * 633 * XXX Figure out how to do hw-assisted VLAN tagging in 634 * XXX a reasonable way on this chip. 635 */ 636 sc->sc_ethercom.ec_capabilities |= 637 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 638 ETHERCAP_VLAN_HWTAGGING; 639 640 /* 641 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 642 */ 643 sc->sc_ethercom.ec_if.if_capabilities |= 644 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 645 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 646 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 647 648 /* 649 * Attach the interface. 650 */ 651 if_attach(ifp); 652 ether_ifattach(ifp, enaddr); 653 654 #ifdef STGE_EVENT_COUNTERS 655 /* 656 * Attach event counters. 657 */ 658 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 659 NULL, device_xname(self), "txstall"); 660 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 661 NULL, device_xname(self), "txdmaintr"); 662 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 663 NULL, device_xname(self), "txindintr"); 664 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 665 NULL, device_xname(self), "rxintr"); 666 667 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 668 NULL, device_xname(self), "txseg1"); 669 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "txseg2"); 671 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "txseg3"); 673 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 674 NULL, device_xname(self), "txseg4"); 675 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 676 NULL, device_xname(self), "txseg5"); 677 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 678 NULL, device_xname(self), "txsegmore"); 679 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 680 NULL, device_xname(self), "txcopy"); 681 682 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "rxipsum"); 684 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "rxtcpsum"); 686 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "rxudpsum"); 688 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "txipsum"); 690 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 691 NULL, device_xname(self), "txtcpsum"); 692 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 693 NULL, device_xname(self), "txudpsum"); 694 #endif /* STGE_EVENT_COUNTERS */ 695 696 /* 697 * Make sure the interface is shutdown during reboot. 698 */ 699 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 700 if (sc->sc_sdhook == NULL) 701 aprint_error_dev(self, 702 "WARNING: unable to establish shutdown hook\n"); 703 return; 704 705 /* 706 * Free any resources we've allocated during the failed attach 707 * attempt. Do this in reverse order and fall through. 708 */ 709 fail_5: 710 for (i = 0; i < STGE_NRXDESC; i++) { 711 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 712 bus_dmamap_destroy(sc->sc_dmat, 713 sc->sc_rxsoft[i].ds_dmamap); 714 } 715 fail_4: 716 for (i = 0; i < STGE_NTXDESC; i++) { 717 if (sc->sc_txsoft[i].ds_dmamap != NULL) 718 bus_dmamap_destroy(sc->sc_dmat, 719 sc->sc_txsoft[i].ds_dmamap); 720 } 721 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 722 fail_3: 723 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 724 fail_2: 725 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 726 sizeof(struct stge_control_data)); 727 fail_1: 728 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 729 fail_0: 730 return; 731 } 732 733 /* 734 * stge_shutdown: 735 * 736 * Make sure the interface is stopped at reboot time. 737 */ 738 static void 739 stge_shutdown(void *arg) 740 { 741 struct stge_softc *sc = arg; 742 743 stge_stop(&sc->sc_ethercom.ec_if, 1); 744 } 745 746 static void 747 stge_dma_wait(struct stge_softc *sc) 748 { 749 int i; 750 751 for (i = 0; i < STGE_TIMEOUT; i++) { 752 delay(2); 753 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 754 DMAC_TxDMAInProg) == 0) 755 break; 756 } 757 758 if (i == STGE_TIMEOUT) 759 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 760 } 761 762 /* 763 * stge_start: [ifnet interface function] 764 * 765 * Start packet transmission on the interface. 766 */ 767 static void 768 stge_start(struct ifnet *ifp) 769 { 770 struct stge_softc *sc = ifp->if_softc; 771 struct mbuf *m0; 772 struct stge_descsoft *ds; 773 struct stge_tfd *tfd; 774 bus_dmamap_t dmamap; 775 int error, firsttx, nexttx, opending, seg, totlen; 776 uint64_t csum_flags; 777 778 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 779 return; 780 781 /* 782 * Remember the previous number of pending transmissions 783 * and the first descriptor we will use. 784 */ 785 opending = sc->sc_txpending; 786 firsttx = STGE_NEXTTX(sc->sc_txlast); 787 788 /* 789 * Loop through the send queue, setting up transmit descriptors 790 * until we drain the queue, or use up all available transmit 791 * descriptors. 792 */ 793 for (;;) { 794 struct m_tag *mtag; 795 uint64_t tfc; 796 797 /* 798 * Grab a packet off the queue. 799 */ 800 IFQ_POLL(&ifp->if_snd, m0); 801 if (m0 == NULL) 802 break; 803 804 /* 805 * Leave one unused descriptor at the end of the 806 * list to prevent wrapping completely around. 807 */ 808 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 809 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 810 break; 811 } 812 813 /* 814 * See if we have any VLAN stuff. 815 */ 816 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 817 818 /* 819 * Get the last and next available transmit descriptor. 820 */ 821 nexttx = STGE_NEXTTX(sc->sc_txlast); 822 tfd = &sc->sc_txdescs[nexttx]; 823 ds = &sc->sc_txsoft[nexttx]; 824 825 dmamap = ds->ds_dmamap; 826 827 /* 828 * Load the DMA map. If this fails, the packet either 829 * didn't fit in the alloted number of segments, or we 830 * were short on resources. For the too-many-segments 831 * case, we simply report an error and drop the packet, 832 * since we can't sanely copy a jumbo packet to a single 833 * buffer. 834 */ 835 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 836 BUS_DMA_NOWAIT); 837 if (error) { 838 if (error == EFBIG) { 839 printf("%s: Tx packet consumes too many " 840 "DMA segments, dropping...\n", 841 device_xname(sc->sc_dev)); 842 IFQ_DEQUEUE(&ifp->if_snd, m0); 843 m_freem(m0); 844 continue; 845 } 846 /* 847 * Short on resources, just stop for now. 848 */ 849 break; 850 } 851 852 IFQ_DEQUEUE(&ifp->if_snd, m0); 853 854 /* 855 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 856 */ 857 858 /* Sync the DMA map. */ 859 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 860 BUS_DMASYNC_PREWRITE); 861 862 /* Initialize the fragment list. */ 863 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 864 tfd->tfd_frags[seg].frag_word0 = 865 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 866 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 867 totlen += dmamap->dm_segs[seg].ds_len; 868 } 869 870 #ifdef STGE_EVENT_COUNTERS 871 switch (dmamap->dm_nsegs) { 872 case 1: 873 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 874 break; 875 case 2: 876 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 877 break; 878 case 3: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 880 break; 881 case 4: 882 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 883 break; 884 case 5: 885 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 886 break; 887 default: 888 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 889 break; 890 } 891 #endif /* STGE_EVENT_COUNTERS */ 892 893 /* 894 * Initialize checksumming flags in the descriptor. 895 * Byte-swap constants so the compiler can optimize. 896 */ 897 csum_flags = 0; 898 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 899 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 900 csum_flags |= TFD_IPChecksumEnable; 901 } 902 903 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 904 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 905 csum_flags |= TFD_TCPChecksumEnable; 906 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 907 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 908 csum_flags |= TFD_UDPChecksumEnable; 909 } 910 911 /* 912 * Initialize the descriptor and give it to the chip. 913 * Check to see if we have a VLAN tag to insert. 914 */ 915 916 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 917 TFD_FragCount(seg) | csum_flags | 918 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 919 TFD_TxDMAIndicate : 0); 920 if (mtag) { 921 #if 0 922 struct ether_header *eh = 923 mtod(m0, struct ether_header *); 924 u_int16_t etype = ntohs(eh->ether_type); 925 printf("%s: xmit (tag %d) etype %x\n", 926 ifp->if_xname, *mtod(n, int *), etype); 927 #endif 928 tfc |= TFD_VLANTagInsert | 929 #ifdef STGE_VLAN_CFI 930 TFD_CFI | 931 #endif 932 TFD_VID(VLAN_TAG_VALUE(mtag)); 933 } 934 tfd->tfd_control = htole64(tfc); 935 936 /* Sync the descriptor. */ 937 STGE_CDTXSYNC(sc, nexttx, 938 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 939 940 /* 941 * Kick the transmit DMA logic. 942 */ 943 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 944 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 945 946 /* 947 * Store a pointer to the packet so we can free it later. 948 */ 949 ds->ds_mbuf = m0; 950 951 /* Advance the tx pointer. */ 952 sc->sc_txpending++; 953 sc->sc_txlast = nexttx; 954 955 #if NBPFILTER > 0 956 /* 957 * Pass the packet to any BPF listeners. 958 */ 959 if (ifp->if_bpf) 960 bpf_mtap(ifp->if_bpf, m0); 961 #endif /* NBPFILTER > 0 */ 962 } 963 964 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 965 /* No more slots left; notify upper layer. */ 966 ifp->if_flags |= IFF_OACTIVE; 967 } 968 969 if (sc->sc_txpending != opending) { 970 /* 971 * We enqueued packets. If the transmitter was idle, 972 * reset the txdirty pointer. 973 */ 974 if (opending == 0) 975 sc->sc_txdirty = firsttx; 976 977 /* Set a watchdog timer in case the chip flakes out. */ 978 ifp->if_timer = 5; 979 } 980 } 981 982 /* 983 * stge_watchdog: [ifnet interface function] 984 * 985 * Watchdog timer handler. 986 */ 987 static void 988 stge_watchdog(struct ifnet *ifp) 989 { 990 struct stge_softc *sc = ifp->if_softc; 991 992 /* 993 * Sweep up first, since we don't interrupt every frame. 994 */ 995 stge_txintr(sc); 996 if (sc->sc_txpending != 0) { 997 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 998 ifp->if_oerrors++; 999 1000 (void) stge_init(ifp); 1001 1002 /* Try to get more packets going. */ 1003 stge_start(ifp); 1004 } 1005 } 1006 1007 /* 1008 * stge_ioctl: [ifnet interface function] 1009 * 1010 * Handle control requests from the operator. 1011 */ 1012 static int 1013 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1014 { 1015 struct stge_softc *sc = ifp->if_softc; 1016 int s, error; 1017 1018 s = splnet(); 1019 1020 error = ether_ioctl(ifp, cmd, data); 1021 if (error == ENETRESET) { 1022 error = 0; 1023 1024 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1025 ; 1026 else if (ifp->if_flags & IFF_RUNNING) { 1027 /* 1028 * Multicast list has changed; set the hardware filter 1029 * accordingly. 1030 */ 1031 stge_set_filter(sc); 1032 } 1033 } 1034 1035 /* Try to get more packets going. */ 1036 stge_start(ifp); 1037 1038 splx(s); 1039 return (error); 1040 } 1041 1042 /* 1043 * stge_intr: 1044 * 1045 * Interrupt service routine. 1046 */ 1047 static int 1048 stge_intr(void *arg) 1049 { 1050 struct stge_softc *sc = arg; 1051 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1052 uint32_t txstat; 1053 int wantinit; 1054 uint16_t isr; 1055 1056 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1057 IS_InterruptStatus) == 0) 1058 return (0); 1059 1060 for (wantinit = 0; wantinit == 0;) { 1061 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1062 if ((isr & sc->sc_IntEnable) == 0) 1063 break; 1064 1065 /* Host interface errors. */ 1066 if (isr & IS_HostError) { 1067 printf("%s: Host interface error\n", 1068 device_xname(sc->sc_dev)); 1069 wantinit = 1; 1070 continue; 1071 } 1072 1073 /* Receive interrupts. */ 1074 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1075 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1076 stge_rxintr(sc); 1077 if (isr & IS_RFDListEnd) { 1078 printf("%s: receive ring overflow\n", 1079 device_xname(sc->sc_dev)); 1080 /* 1081 * XXX Should try to recover from this 1082 * XXX more gracefully. 1083 */ 1084 wantinit = 1; 1085 } 1086 } 1087 1088 /* Transmit interrupts. */ 1089 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1090 #ifdef STGE_EVENT_COUNTERS 1091 if (isr & IS_TxDMAComplete) 1092 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1093 #endif 1094 stge_txintr(sc); 1095 } 1096 1097 /* Statistics overflow. */ 1098 if (isr & IS_UpdateStats) 1099 stge_stats_update(sc); 1100 1101 /* Transmission errors. */ 1102 if (isr & IS_TxComplete) { 1103 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1104 for (;;) { 1105 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1106 STGE_TxStatus); 1107 if ((txstat & TS_TxComplete) == 0) 1108 break; 1109 if (txstat & TS_TxUnderrun) { 1110 sc->sc_txthresh++; 1111 if (sc->sc_txthresh > 0x0fff) 1112 sc->sc_txthresh = 0x0fff; 1113 printf("%s: transmit underrun, new " 1114 "threshold: %d bytes\n", 1115 device_xname(sc->sc_dev), 1116 sc->sc_txthresh << 5); 1117 } 1118 if (txstat & TS_MaxCollisions) 1119 printf("%s: excessive collisions\n", 1120 device_xname(sc->sc_dev)); 1121 } 1122 wantinit = 1; 1123 } 1124 1125 } 1126 1127 if (wantinit) 1128 stge_init(ifp); 1129 1130 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1131 sc->sc_IntEnable); 1132 1133 /* Try to get more packets going. */ 1134 stge_start(ifp); 1135 1136 return (1); 1137 } 1138 1139 /* 1140 * stge_txintr: 1141 * 1142 * Helper; handle transmit interrupts. 1143 */ 1144 static void 1145 stge_txintr(struct stge_softc *sc) 1146 { 1147 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1148 struct stge_descsoft *ds; 1149 uint64_t control; 1150 int i; 1151 1152 ifp->if_flags &= ~IFF_OACTIVE; 1153 1154 /* 1155 * Go through our Tx list and free mbufs for those 1156 * frames which have been transmitted. 1157 */ 1158 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1159 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1160 ds = &sc->sc_txsoft[i]; 1161 1162 STGE_CDTXSYNC(sc, i, 1163 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1164 1165 control = le64toh(sc->sc_txdescs[i].tfd_control); 1166 if ((control & TFD_TFDDone) == 0) 1167 break; 1168 1169 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1170 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1171 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1172 m_freem(ds->ds_mbuf); 1173 ds->ds_mbuf = NULL; 1174 } 1175 1176 /* Update the dirty transmit buffer pointer. */ 1177 sc->sc_txdirty = i; 1178 1179 /* 1180 * If there are no more pending transmissions, cancel the watchdog 1181 * timer. 1182 */ 1183 if (sc->sc_txpending == 0) 1184 ifp->if_timer = 0; 1185 } 1186 1187 /* 1188 * stge_rxintr: 1189 * 1190 * Helper; handle receive interrupts. 1191 */ 1192 static void 1193 stge_rxintr(struct stge_softc *sc) 1194 { 1195 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1196 struct stge_descsoft *ds; 1197 struct mbuf *m, *tailm; 1198 uint64_t status; 1199 int i, len; 1200 1201 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1202 ds = &sc->sc_rxsoft[i]; 1203 1204 STGE_CDRXSYNC(sc, i, 1205 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1206 1207 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1208 1209 if ((status & RFD_RFDDone) == 0) 1210 break; 1211 1212 if (__predict_false(sc->sc_rxdiscard)) { 1213 STGE_INIT_RXDESC(sc, i); 1214 if (status & RFD_FrameEnd) { 1215 /* Reset our state. */ 1216 sc->sc_rxdiscard = 0; 1217 } 1218 continue; 1219 } 1220 1221 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1222 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1223 1224 m = ds->ds_mbuf; 1225 1226 /* 1227 * Add a new receive buffer to the ring. 1228 */ 1229 if (stge_add_rxbuf(sc, i) != 0) { 1230 /* 1231 * Failed, throw away what we've done so 1232 * far, and discard the rest of the packet. 1233 */ 1234 ifp->if_ierrors++; 1235 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1236 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1237 STGE_INIT_RXDESC(sc, i); 1238 if ((status & RFD_FrameEnd) == 0) 1239 sc->sc_rxdiscard = 1; 1240 if (sc->sc_rxhead != NULL) 1241 m_freem(sc->sc_rxhead); 1242 STGE_RXCHAIN_RESET(sc); 1243 continue; 1244 } 1245 1246 #ifdef DIAGNOSTIC 1247 if (status & RFD_FrameStart) { 1248 KASSERT(sc->sc_rxhead == NULL); 1249 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1250 } 1251 #endif 1252 1253 STGE_RXCHAIN_LINK(sc, m); 1254 1255 /* 1256 * If this is not the end of the packet, keep 1257 * looking. 1258 */ 1259 if ((status & RFD_FrameEnd) == 0) { 1260 sc->sc_rxlen += m->m_len; 1261 continue; 1262 } 1263 1264 /* 1265 * Okay, we have the entire packet now... 1266 */ 1267 *sc->sc_rxtailp = NULL; 1268 m = sc->sc_rxhead; 1269 tailm = sc->sc_rxtail; 1270 1271 STGE_RXCHAIN_RESET(sc); 1272 1273 /* 1274 * If the packet had an error, drop it. Note we 1275 * count the error later in the periodic stats update. 1276 */ 1277 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1278 RFD_RxAlignmentError | RFD_RxFCSError | 1279 RFD_RxLengthError)) { 1280 m_freem(m); 1281 continue; 1282 } 1283 1284 /* 1285 * No errors. 1286 * 1287 * Note we have configured the chip to not include 1288 * the CRC at the end of the packet. 1289 */ 1290 len = RFD_RxDMAFrameLen(status); 1291 tailm->m_len = len - sc->sc_rxlen; 1292 1293 /* 1294 * If the packet is small enough to fit in a 1295 * single header mbuf, allocate one and copy 1296 * the data into it. This greatly reduces 1297 * memory consumption when we receive lots 1298 * of small packets. 1299 */ 1300 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1301 struct mbuf *nm; 1302 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1303 if (nm == NULL) { 1304 ifp->if_ierrors++; 1305 m_freem(m); 1306 continue; 1307 } 1308 nm->m_data += 2; 1309 nm->m_pkthdr.len = nm->m_len = len; 1310 m_copydata(m, 0, len, mtod(nm, void *)); 1311 m_freem(m); 1312 m = nm; 1313 } 1314 1315 /* 1316 * Set the incoming checksum information for the packet. 1317 */ 1318 if (status & RFD_IPDetected) { 1319 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1320 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1321 if (status & RFD_IPError) 1322 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1323 if (status & RFD_TCPDetected) { 1324 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1325 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1326 if (status & RFD_TCPError) 1327 m->m_pkthdr.csum_flags |= 1328 M_CSUM_TCP_UDP_BAD; 1329 } else if (status & RFD_UDPDetected) { 1330 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1331 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1332 if (status & RFD_UDPError) 1333 m->m_pkthdr.csum_flags |= 1334 M_CSUM_TCP_UDP_BAD; 1335 } 1336 } 1337 1338 m->m_pkthdr.rcvif = ifp; 1339 m->m_pkthdr.len = len; 1340 1341 #if NBPFILTER > 0 1342 /* 1343 * Pass this up to any BPF listeners, but only 1344 * pass if up the stack if it's for us. 1345 */ 1346 if (ifp->if_bpf) 1347 bpf_mtap(ifp->if_bpf, m); 1348 #endif /* NBPFILTER > 0 */ 1349 #ifdef STGE_VLAN_UNTAG 1350 /* 1351 * Check for VLAN tagged packets 1352 */ 1353 if (status & RFD_VLANDetected) 1354 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1355 1356 #endif 1357 #if 0 1358 if (status & RFD_VLANDetected) { 1359 struct ether_header *eh; 1360 u_int16_t etype; 1361 1362 eh = mtod(m, struct ether_header *); 1363 etype = ntohs(eh->ether_type); 1364 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1365 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1366 etype); 1367 } 1368 #endif 1369 /* Pass it on. */ 1370 (*ifp->if_input)(ifp, m); 1371 } 1372 1373 /* Update the receive pointer. */ 1374 sc->sc_rxptr = i; 1375 } 1376 1377 /* 1378 * stge_tick: 1379 * 1380 * One second timer, used to tick the MII. 1381 */ 1382 static void 1383 stge_tick(void *arg) 1384 { 1385 struct stge_softc *sc = arg; 1386 int s; 1387 1388 s = splnet(); 1389 mii_tick(&sc->sc_mii); 1390 stge_stats_update(sc); 1391 splx(s); 1392 1393 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1394 } 1395 1396 /* 1397 * stge_stats_update: 1398 * 1399 * Read the TC9021 statistics counters. 1400 */ 1401 static void 1402 stge_stats_update(struct stge_softc *sc) 1403 { 1404 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1405 bus_space_tag_t st = sc->sc_st; 1406 bus_space_handle_t sh = sc->sc_sh; 1407 1408 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1409 1410 ifp->if_ipackets += 1411 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1412 1413 ifp->if_ierrors += 1414 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1415 1416 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1417 1418 ifp->if_opackets += 1419 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1420 1421 ifp->if_collisions += 1422 bus_space_read_4(st, sh, STGE_LateCollisions) + 1423 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1424 bus_space_read_4(st, sh, STGE_SingleColFrames); 1425 1426 ifp->if_oerrors += 1427 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1428 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1429 } 1430 1431 /* 1432 * stge_reset: 1433 * 1434 * Perform a soft reset on the TC9021. 1435 */ 1436 static void 1437 stge_reset(struct stge_softc *sc) 1438 { 1439 uint32_t ac; 1440 int i; 1441 1442 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1443 1444 /* 1445 * Only assert RstOut if we're fiber. We need GMII clocks 1446 * to be present in order for the reset to complete on fiber 1447 * cards. 1448 */ 1449 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1450 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1451 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1452 (sc->sc_usefiber ? AC_RstOut : 0)); 1453 1454 delay(50000); 1455 1456 for (i = 0; i < STGE_TIMEOUT; i++) { 1457 delay(5000); 1458 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1459 AC_ResetBusy) == 0) 1460 break; 1461 } 1462 1463 if (i == STGE_TIMEOUT) 1464 printf("%s: reset failed to complete\n", 1465 device_xname(sc->sc_dev)); 1466 1467 delay(1000); 1468 } 1469 1470 /* 1471 * stge_init: [ ifnet interface function ] 1472 * 1473 * Initialize the interface. Must be called at splnet(). 1474 */ 1475 static int 1476 stge_init(struct ifnet *ifp) 1477 { 1478 struct stge_softc *sc = ifp->if_softc; 1479 bus_space_tag_t st = sc->sc_st; 1480 bus_space_handle_t sh = sc->sc_sh; 1481 struct stge_descsoft *ds; 1482 int i, error = 0; 1483 1484 /* 1485 * Cancel any pending I/O. 1486 */ 1487 stge_stop(ifp, 0); 1488 1489 /* 1490 * Reset the chip to a known state. 1491 */ 1492 stge_reset(sc); 1493 1494 /* 1495 * Initialize the transmit descriptor ring. 1496 */ 1497 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1498 for (i = 0; i < STGE_NTXDESC; i++) { 1499 sc->sc_txdescs[i].tfd_next = htole64( 1500 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1501 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1502 } 1503 sc->sc_txpending = 0; 1504 sc->sc_txdirty = 0; 1505 sc->sc_txlast = STGE_NTXDESC - 1; 1506 1507 /* 1508 * Initialize the receive descriptor and receive job 1509 * descriptor rings. 1510 */ 1511 for (i = 0; i < STGE_NRXDESC; i++) { 1512 ds = &sc->sc_rxsoft[i]; 1513 if (ds->ds_mbuf == NULL) { 1514 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1515 printf("%s: unable to allocate or map rx " 1516 "buffer %d, error = %d\n", 1517 device_xname(sc->sc_dev), i, error); 1518 /* 1519 * XXX Should attempt to run with fewer receive 1520 * XXX buffers instead of just failing. 1521 */ 1522 stge_rxdrain(sc); 1523 goto out; 1524 } 1525 } else 1526 STGE_INIT_RXDESC(sc, i); 1527 } 1528 sc->sc_rxptr = 0; 1529 sc->sc_rxdiscard = 0; 1530 STGE_RXCHAIN_RESET(sc); 1531 1532 /* Set the station address. */ 1533 for (i = 0; i < 6; i++) 1534 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1535 CLLADDR(ifp->if_sadl)[i]); 1536 1537 /* 1538 * Set the statistics masks. Disable all the RMON stats, 1539 * and disable selected stats in the non-RMON stats registers. 1540 */ 1541 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1542 bus_space_write_4(st, sh, STGE_StatisticsMask, 1543 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1544 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1545 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1546 (1U << 21)); 1547 1548 /* Set up the receive filter. */ 1549 stge_set_filter(sc); 1550 1551 /* 1552 * Give the transmit and receive ring to the chip. 1553 */ 1554 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1555 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1556 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1557 1558 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1559 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1560 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1561 1562 /* 1563 * Initialize the Tx auto-poll period. It's OK to make this number 1564 * large (255 is the max, but we use 127) -- we explicitly kick the 1565 * transmit engine when there's actually a packet. 1566 */ 1567 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1568 1569 /* ..and the Rx auto-poll period. */ 1570 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1571 1572 /* Initialize the Tx start threshold. */ 1573 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1574 1575 /* RX DMA thresholds, from linux */ 1576 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1577 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1578 1579 /* 1580 * Initialize the Rx DMA interrupt control register. We 1581 * request an interrupt after every incoming packet, but 1582 * defer it for 32us (64 * 512 ns). When the number of 1583 * interrupts pending reaches 8, we stop deferring the 1584 * interrupt, and signal it immediately. 1585 */ 1586 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1587 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1588 1589 /* 1590 * Initialize the interrupt mask. 1591 */ 1592 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1593 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1594 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1595 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1596 1597 /* 1598 * Configure the DMA engine. 1599 * XXX Should auto-tune TxBurstLimit. 1600 */ 1601 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1602 DMAC_TxBurstLimit(3)); 1603 1604 /* 1605 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1606 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1607 * empty again. 1608 */ 1609 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1610 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1611 1612 /* 1613 * Set the maximum frame size. 1614 */ 1615 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1616 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1617 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1618 ETHER_VLAN_ENCAP_LEN : 0)); 1619 1620 /* 1621 * Initialize MacCtrl -- do it before setting the media, 1622 * as setting the media will actually program the register. 1623 * 1624 * Note: We have to poke the IFS value before poking 1625 * anything else. 1626 */ 1627 sc->sc_MACCtrl = MC_IFSSelect(0); 1628 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1629 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1630 #ifdef STGE_VLAN_UNTAG 1631 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1632 #endif 1633 1634 if (sc->sc_rev >= 6) { /* >= B.2 */ 1635 /* Multi-frag frame bug work-around. */ 1636 bus_space_write_2(st, sh, STGE_DebugCtrl, 1637 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1638 1639 /* Tx Poll Now bug work-around. */ 1640 bus_space_write_2(st, sh, STGE_DebugCtrl, 1641 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1642 /* XXX ? from linux */ 1643 bus_space_write_2(st, sh, STGE_DebugCtrl, 1644 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1645 } 1646 1647 /* 1648 * Set the current media. 1649 */ 1650 if ((error = ether_mediachange(ifp)) != 0) 1651 goto out; 1652 1653 /* 1654 * Start the one second MII clock. 1655 */ 1656 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1657 1658 /* 1659 * ...all done! 1660 */ 1661 ifp->if_flags |= IFF_RUNNING; 1662 ifp->if_flags &= ~IFF_OACTIVE; 1663 1664 out: 1665 if (error) 1666 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1667 return (error); 1668 } 1669 1670 /* 1671 * stge_drain: 1672 * 1673 * Drain the receive queue. 1674 */ 1675 static void 1676 stge_rxdrain(struct stge_softc *sc) 1677 { 1678 struct stge_descsoft *ds; 1679 int i; 1680 1681 for (i = 0; i < STGE_NRXDESC; i++) { 1682 ds = &sc->sc_rxsoft[i]; 1683 if (ds->ds_mbuf != NULL) { 1684 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1685 ds->ds_mbuf->m_next = NULL; 1686 m_freem(ds->ds_mbuf); 1687 ds->ds_mbuf = NULL; 1688 } 1689 } 1690 } 1691 1692 /* 1693 * stge_stop: [ ifnet interface function ] 1694 * 1695 * Stop transmission on the interface. 1696 */ 1697 static void 1698 stge_stop(struct ifnet *ifp, int disable) 1699 { 1700 struct stge_softc *sc = ifp->if_softc; 1701 struct stge_descsoft *ds; 1702 int i; 1703 1704 /* 1705 * Stop the one second clock. 1706 */ 1707 callout_stop(&sc->sc_tick_ch); 1708 1709 /* Down the MII. */ 1710 mii_down(&sc->sc_mii); 1711 1712 /* 1713 * Disable interrupts. 1714 */ 1715 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1716 1717 /* 1718 * Stop receiver, transmitter, and stats update. 1719 */ 1720 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1721 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1722 1723 /* 1724 * Stop the transmit and receive DMA. 1725 */ 1726 stge_dma_wait(sc); 1727 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1728 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1729 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1731 1732 /* 1733 * Release any queued transmit buffers. 1734 */ 1735 for (i = 0; i < STGE_NTXDESC; i++) { 1736 ds = &sc->sc_txsoft[i]; 1737 if (ds->ds_mbuf != NULL) { 1738 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1739 m_freem(ds->ds_mbuf); 1740 ds->ds_mbuf = NULL; 1741 } 1742 } 1743 1744 /* 1745 * Mark the interface down and cancel the watchdog timer. 1746 */ 1747 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1748 ifp->if_timer = 0; 1749 1750 if (disable) 1751 stge_rxdrain(sc); 1752 } 1753 1754 static int 1755 stge_eeprom_wait(struct stge_softc *sc) 1756 { 1757 int i; 1758 1759 for (i = 0; i < STGE_TIMEOUT; i++) { 1760 delay(1000); 1761 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1762 EC_EepromBusy) == 0) 1763 return (0); 1764 } 1765 return (1); 1766 } 1767 1768 /* 1769 * stge_read_eeprom: 1770 * 1771 * Read data from the serial EEPROM. 1772 */ 1773 static void 1774 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1775 { 1776 1777 if (stge_eeprom_wait(sc)) 1778 printf("%s: EEPROM failed to come ready\n", 1779 device_xname(sc->sc_dev)); 1780 1781 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1782 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1783 if (stge_eeprom_wait(sc)) 1784 printf("%s: EEPROM read timed out\n", 1785 device_xname(sc->sc_dev)); 1786 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1787 } 1788 1789 /* 1790 * stge_add_rxbuf: 1791 * 1792 * Add a receive buffer to the indicated descriptor. 1793 */ 1794 static int 1795 stge_add_rxbuf(struct stge_softc *sc, int idx) 1796 { 1797 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1798 struct mbuf *m; 1799 int error; 1800 1801 MGETHDR(m, M_DONTWAIT, MT_DATA); 1802 if (m == NULL) 1803 return (ENOBUFS); 1804 1805 MCLGET(m, M_DONTWAIT); 1806 if ((m->m_flags & M_EXT) == 0) { 1807 m_freem(m); 1808 return (ENOBUFS); 1809 } 1810 1811 m->m_data = m->m_ext.ext_buf + 2; 1812 m->m_len = MCLBYTES - 2; 1813 1814 if (ds->ds_mbuf != NULL) 1815 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1816 1817 ds->ds_mbuf = m; 1818 1819 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1820 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1821 if (error) { 1822 printf("%s: can't load rx DMA map %d, error = %d\n", 1823 device_xname(sc->sc_dev), idx, error); 1824 panic("stge_add_rxbuf"); /* XXX */ 1825 } 1826 1827 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1828 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1829 1830 STGE_INIT_RXDESC(sc, idx); 1831 1832 return (0); 1833 } 1834 1835 /* 1836 * stge_set_filter: 1837 * 1838 * Set up the receive filter. 1839 */ 1840 static void 1841 stge_set_filter(struct stge_softc *sc) 1842 { 1843 struct ethercom *ec = &sc->sc_ethercom; 1844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1845 struct ether_multi *enm; 1846 struct ether_multistep step; 1847 uint32_t crc; 1848 uint32_t mchash[2]; 1849 1850 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1851 if (ifp->if_flags & IFF_BROADCAST) 1852 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1853 1854 /* XXX: ST1023 only works in promiscuous mode */ 1855 if (sc->sc_stge1023) 1856 ifp->if_flags |= IFF_PROMISC; 1857 1858 if (ifp->if_flags & IFF_PROMISC) { 1859 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1860 goto allmulti; 1861 } 1862 1863 /* 1864 * Set up the multicast address filter by passing all multicast 1865 * addresses through a CRC generator, and then using the low-order 1866 * 6 bits as an index into the 64 bit multicast hash table. The 1867 * high order bits select the register, while the rest of the bits 1868 * select the bit within the register. 1869 */ 1870 1871 memset(mchash, 0, sizeof(mchash)); 1872 1873 ETHER_FIRST_MULTI(step, ec, enm); 1874 if (enm == NULL) 1875 goto done; 1876 1877 while (enm != NULL) { 1878 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1879 /* 1880 * We must listen to a range of multicast addresses. 1881 * For now, just accept all multicasts, rather than 1882 * trying to set only those filter bits needed to match 1883 * the range. (At this time, the only use of address 1884 * ranges is for IP multicast routing, for which the 1885 * range is big enough to require all bits set.) 1886 */ 1887 goto allmulti; 1888 } 1889 1890 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1891 1892 /* Just want the 6 least significant bits. */ 1893 crc &= 0x3f; 1894 1895 /* Set the corresponding bit in the hash table. */ 1896 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1897 1898 ETHER_NEXT_MULTI(step, enm); 1899 } 1900 1901 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1902 1903 ifp->if_flags &= ~IFF_ALLMULTI; 1904 goto done; 1905 1906 allmulti: 1907 ifp->if_flags |= IFF_ALLMULTI; 1908 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1909 1910 done: 1911 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1912 /* 1913 * Program the multicast hash table. 1914 */ 1915 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1916 mchash[0]); 1917 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1918 mchash[1]); 1919 } 1920 1921 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1922 sc->sc_ReceiveMode); 1923 } 1924 1925 /* 1926 * stge_mii_readreg: [mii interface function] 1927 * 1928 * Read a PHY register on the MII of the TC9021. 1929 */ 1930 static int 1931 stge_mii_readreg(device_t self, int phy, int reg) 1932 { 1933 1934 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1935 } 1936 1937 /* 1938 * stge_mii_writereg: [mii interface function] 1939 * 1940 * Write a PHY register on the MII of the TC9021. 1941 */ 1942 static void 1943 stge_mii_writereg(device_t self, int phy, int reg, int val) 1944 { 1945 1946 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1947 } 1948 1949 /* 1950 * stge_mii_statchg: [mii interface function] 1951 * 1952 * Callback from MII layer when media changes. 1953 */ 1954 static void 1955 stge_mii_statchg(device_t self) 1956 { 1957 struct stge_softc *sc = device_private(self); 1958 1959 if (sc->sc_mii.mii_media_active & IFM_FDX) 1960 sc->sc_MACCtrl |= MC_DuplexSelect; 1961 else 1962 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1963 1964 /* XXX 802.1x flow-control? */ 1965 1966 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1967 } 1968 1969 /* 1970 * sste_mii_bitbang_read: [mii bit-bang interface function] 1971 * 1972 * Read the MII serial port for the MII bit-bang module. 1973 */ 1974 static uint32_t 1975 stge_mii_bitbang_read(device_t self) 1976 { 1977 struct stge_softc *sc = device_private(self); 1978 1979 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1980 } 1981 1982 /* 1983 * stge_mii_bitbang_write: [mii big-bang interface function] 1984 * 1985 * Write the MII serial port for the MII bit-bang module. 1986 */ 1987 static void 1988 stge_mii_bitbang_write(device_t self, uint32_t val) 1989 { 1990 struct stge_softc *sc = device_private(self); 1991 1992 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1993 val | sc->sc_PhyCtrl); 1994 } 1995