1 /* $NetBSD: if_ste.c,v 1.48 2016/07/07 06:55:41 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.48 2016/07/07 06:55:41 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 device_t sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, u_int32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, u_int8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int); 219 static void ste_mii_writereg(device_t, int, int, int); 220 static void ste_mii_statchg(struct ifnet *); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 bus_space_tag_t iot, memt; 300 bus_space_handle_t ioh, memh; 301 bus_dma_segment_t seg; 302 int ioh_valid, memh_valid; 303 int i, rseg, error; 304 const struct ste_product *sp; 305 uint8_t enaddr[ETHER_ADDR_LEN]; 306 uint16_t myea[ETHER_ADDR_LEN / 2]; 307 char intrbuf[PCI_INTRSTR_LEN]; 308 309 sc->sc_dev = self; 310 311 callout_init(&sc->sc_tick_ch, 0); 312 313 sp = ste_lookup(pa); 314 if (sp == NULL) { 315 printf("\n"); 316 panic("ste_attach: impossible"); 317 } 318 319 printf(": %s\n", sp->ste_name); 320 321 /* 322 * Map the device. 323 */ 324 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 325 PCI_MAPREG_TYPE_IO, 0, 326 &iot, &ioh, NULL, NULL) == 0); 327 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 328 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 329 &memt, &memh, NULL, NULL) == 0); 330 331 if (memh_valid) { 332 sc->sc_st = memt; 333 sc->sc_sh = memh; 334 } else if (ioh_valid) { 335 sc->sc_st = iot; 336 sc->sc_sh = ioh; 337 } else { 338 aprint_error_dev(self, "unable to map device registers\n"); 339 return; 340 } 341 342 sc->sc_dmat = pa->pa_dmat; 343 344 /* Enable bus mastering. */ 345 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 346 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 347 PCI_COMMAND_MASTER_ENABLE); 348 349 /* power up chip */ 350 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 351 NULL)) && error != EOPNOTSUPP) { 352 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 353 return; 354 } 355 356 /* 357 * Map and establish our interrupt. 358 */ 359 if (pci_intr_map(pa, &ih)) { 360 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 361 return; 362 } 363 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 364 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 365 if (sc->sc_ih == NULL) { 366 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 367 if (intrstr != NULL) 368 aprint_error(" at %s", intrstr); 369 aprint_error("\n"); 370 return; 371 } 372 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 373 374 /* 375 * Allocate the control data structures, and create and load the 376 * DMA map for it. 377 */ 378 if ((error = bus_dmamem_alloc(sc->sc_dmat, 379 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 380 0)) != 0) { 381 aprint_error_dev(sc->sc_dev, 382 "unable to allocate control data, error = %d\n", error); 383 goto fail_0; 384 } 385 386 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 387 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 388 BUS_DMA_COHERENT)) != 0) { 389 aprint_error_dev(sc->sc_dev, 390 "unable to map control data, error = %d\n", error); 391 goto fail_1; 392 } 393 394 if ((error = bus_dmamap_create(sc->sc_dmat, 395 sizeof(struct ste_control_data), 1, 396 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 397 aprint_error_dev(sc->sc_dev, 398 "unable to create control data DMA map, error = %d\n", 399 error); 400 goto fail_2; 401 } 402 403 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 404 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 405 0)) != 0) { 406 aprint_error_dev(sc->sc_dev, 407 "unable to load control data DMA map, error = %d\n", 408 error); 409 goto fail_3; 410 } 411 412 /* 413 * Create the transmit buffer DMA maps. 414 */ 415 for (i = 0; i < STE_NTXDESC; i++) { 416 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 417 STE_NTXFRAGS, MCLBYTES, 0, 0, 418 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 419 aprint_error_dev(sc->sc_dev, 420 "unable to create tx DMA map %d, error = %d\n", i, 421 error); 422 goto fail_4; 423 } 424 } 425 426 /* 427 * Create the receive buffer DMA maps. 428 */ 429 for (i = 0; i < STE_NRXDESC; i++) { 430 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 431 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 432 aprint_error_dev(sc->sc_dev, 433 "unable to create rx DMA map %d, error = %d\n", i, 434 error); 435 goto fail_5; 436 } 437 sc->sc_rxsoft[i].ds_mbuf = NULL; 438 } 439 440 /* 441 * Reset the chip to a known state. 442 */ 443 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 444 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 445 446 /* 447 * Read the Ethernet address from the EEPROM. 448 */ 449 for (i = 0; i < 3; i++) { 450 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 451 myea[i] = le16toh(myea[i]); 452 } 453 memcpy(enaddr, myea, sizeof(enaddr)); 454 455 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 456 ether_sprintf(enaddr)); 457 458 /* 459 * Initialize our media structures and probe the MII. 460 */ 461 sc->sc_mii.mii_ifp = ifp; 462 sc->sc_mii.mii_readreg = ste_mii_readreg; 463 sc->sc_mii.mii_writereg = ste_mii_writereg; 464 sc->sc_mii.mii_statchg = ste_mii_statchg; 465 sc->sc_ethercom.ec_mii = &sc->sc_mii; 466 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 467 ether_mediastatus); 468 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 469 MII_OFFSET_ANY, 0); 470 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 471 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0,NULL); 472 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 473 } else 474 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 475 476 ifp = &sc->sc_ethercom.ec_if; 477 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 478 ifp->if_softc = sc; 479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 480 ifp->if_ioctl = ste_ioctl; 481 ifp->if_start = ste_start; 482 ifp->if_watchdog = ste_watchdog; 483 ifp->if_init = ste_init; 484 ifp->if_stop = ste_stop; 485 IFQ_SET_READY(&ifp->if_snd); 486 487 /* 488 * Default the transmit threshold to 128 bytes. 489 */ 490 sc->sc_txthresh = 128; 491 492 /* 493 * Disable MWI if the PCI layer tells us to. 494 */ 495 sc->sc_DMACtrl = 0; 496 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 497 sc->sc_DMACtrl |= DC_MWIDisable; 498 499 /* 500 * We can support 802.1Q VLAN-sized frames. 501 */ 502 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 503 504 /* 505 * Attach the interface. 506 */ 507 if_attach(ifp); 508 ether_ifattach(ifp, enaddr); 509 510 /* 511 * Make sure the interface is shutdown during reboot. 512 */ 513 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 514 pmf_class_network_register(self, ifp); 515 else 516 aprint_error_dev(self, "couldn't establish power handler\n"); 517 518 return; 519 520 /* 521 * Free any resources we've allocated during the failed attach 522 * attempt. Do this in reverse order and fall through. 523 */ 524 fail_5: 525 for (i = 0; i < STE_NRXDESC; i++) { 526 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 527 bus_dmamap_destroy(sc->sc_dmat, 528 sc->sc_rxsoft[i].ds_dmamap); 529 } 530 fail_4: 531 for (i = 0; i < STE_NTXDESC; i++) { 532 if (sc->sc_txsoft[i].ds_dmamap != NULL) 533 bus_dmamap_destroy(sc->sc_dmat, 534 sc->sc_txsoft[i].ds_dmamap); 535 } 536 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 537 fail_3: 538 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 539 fail_2: 540 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 541 sizeof(struct ste_control_data)); 542 fail_1: 543 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 544 fail_0: 545 return; 546 } 547 548 /* 549 * ste_shutdown: 550 * 551 * Make sure the interface is stopped at reboot time. 552 */ 553 static bool 554 ste_shutdown(device_t self, int howto) 555 { 556 struct ste_softc *sc; 557 558 sc = device_private(self); 559 ste_stop(&sc->sc_ethercom.ec_if, 1); 560 561 return true; 562 } 563 564 static void 565 ste_dmahalt_wait(struct ste_softc *sc) 566 { 567 int i; 568 569 for (i = 0; i < STE_TIMEOUT; i++) { 570 delay(2); 571 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 572 DC_DMAHaltBusy) == 0) 573 break; 574 } 575 576 if (i == STE_TIMEOUT) 577 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 578 } 579 580 /* 581 * ste_start: [ifnet interface function] 582 * 583 * Start packet transmission on the interface. 584 */ 585 static void 586 ste_start(struct ifnet *ifp) 587 { 588 struct ste_softc *sc = ifp->if_softc; 589 struct mbuf *m0, *m; 590 struct ste_descsoft *ds; 591 struct ste_tfd *tfd; 592 bus_dmamap_t dmamap; 593 int error, olasttx, nexttx, opending, seg, totlen; 594 595 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 596 return; 597 598 /* 599 * Remember the previous number of pending transmissions 600 * and the current last descriptor in the list. 601 */ 602 opending = sc->sc_txpending; 603 olasttx = sc->sc_txlast; 604 605 /* 606 * Loop through the send queue, setting up transmit descriptors 607 * until we drain the queue, or use up all available transmit 608 * descriptors. 609 */ 610 while (sc->sc_txpending < STE_NTXDESC) { 611 /* 612 * Grab a packet off the queue. 613 */ 614 IFQ_POLL(&ifp->if_snd, m0); 615 if (m0 == NULL) 616 break; 617 m = NULL; 618 619 /* 620 * Get the last and next available transmit descriptor. 621 */ 622 nexttx = STE_NEXTTX(sc->sc_txlast); 623 tfd = &sc->sc_txdescs[nexttx]; 624 ds = &sc->sc_txsoft[nexttx]; 625 626 dmamap = ds->ds_dmamap; 627 628 /* 629 * Load the DMA map. If this fails, the packet either 630 * didn't fit in the alloted number of segments, or we 631 * were short on resources. In this case, we'll copy 632 * and try again. 633 */ 634 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 635 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 636 MGETHDR(m, M_DONTWAIT, MT_DATA); 637 if (m == NULL) { 638 printf("%s: unable to allocate Tx mbuf\n", 639 device_xname(sc->sc_dev)); 640 break; 641 } 642 if (m0->m_pkthdr.len > MHLEN) { 643 MCLGET(m, M_DONTWAIT); 644 if ((m->m_flags & M_EXT) == 0) { 645 printf("%s: unable to allocate Tx " 646 "cluster\n", 647 device_xname(sc->sc_dev)); 648 m_freem(m); 649 break; 650 } 651 } 652 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 653 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 654 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 655 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 656 if (error) { 657 printf("%s: unable to load Tx buffer, " 658 "error = %d\n", device_xname(sc->sc_dev), 659 error); 660 break; 661 } 662 } 663 664 IFQ_DEQUEUE(&ifp->if_snd, m0); 665 if (m != NULL) { 666 m_freem(m0); 667 m0 = m; 668 } 669 670 /* 671 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 672 */ 673 674 /* Sync the DMA map. */ 675 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 676 BUS_DMASYNC_PREWRITE); 677 678 /* Initialize the fragment list. */ 679 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 680 tfd->tfd_frags[seg].frag_addr = 681 htole32(dmamap->dm_segs[seg].ds_addr); 682 tfd->tfd_frags[seg].frag_len = 683 htole32(dmamap->dm_segs[seg].ds_len); 684 totlen += dmamap->dm_segs[seg].ds_len; 685 } 686 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 687 688 /* Initialize the descriptor. */ 689 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 690 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 691 692 /* Sync the descriptor. */ 693 STE_CDTXSYNC(sc, nexttx, 694 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 695 696 /* 697 * Store a pointer to the packet so we can free it later, 698 * and remember what txdirty will be once the packet is 699 * done. 700 */ 701 ds->ds_mbuf = m0; 702 703 /* Advance the tx pointer. */ 704 sc->sc_txpending++; 705 sc->sc_txlast = nexttx; 706 707 /* 708 * Pass the packet to any BPF listeners. 709 */ 710 bpf_mtap(ifp, m0); 711 } 712 713 if (sc->sc_txpending == STE_NTXDESC) { 714 /* No more slots left; notify upper layer. */ 715 ifp->if_flags |= IFF_OACTIVE; 716 } 717 718 if (sc->sc_txpending != opending) { 719 /* 720 * We enqueued packets. If the transmitter was idle, 721 * reset the txdirty pointer. 722 */ 723 if (opending == 0) 724 sc->sc_txdirty = STE_NEXTTX(olasttx); 725 726 /* 727 * Cause a descriptor interrupt to happen on the 728 * last packet we enqueued, and also cause the 729 * DMA engine to wait after is has finished processing 730 * it. 731 */ 732 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 733 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 734 htole32(TFD_TxDMAIndicate); 735 STE_CDTXSYNC(sc, sc->sc_txlast, 736 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 737 738 /* 739 * Link up the new chain of descriptors to the 740 * last. 741 */ 742 sc->sc_txdescs[olasttx].tfd_next = 743 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 744 STE_CDTXSYNC(sc, olasttx, 745 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 746 747 /* 748 * Kick the transmit DMA logic. Note that since we're 749 * using auto-polling, reading the Tx desc pointer will 750 * give it the nudge it needs to get going. 751 */ 752 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 753 STE_TxDMAListPtr) == 0) { 754 bus_space_write_4(sc->sc_st, sc->sc_sh, 755 STE_DMACtrl, DC_TxDMAHalt); 756 ste_dmahalt_wait(sc); 757 bus_space_write_4(sc->sc_st, sc->sc_sh, 758 STE_TxDMAListPtr, 759 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 760 bus_space_write_4(sc->sc_st, sc->sc_sh, 761 STE_DMACtrl, DC_TxDMAResume); 762 } 763 764 /* Set a watchdog timer in case the chip flakes out. */ 765 ifp->if_timer = 5; 766 } 767 } 768 769 /* 770 * ste_watchdog: [ifnet interface function] 771 * 772 * Watchdog timer handler. 773 */ 774 static void 775 ste_watchdog(struct ifnet *ifp) 776 { 777 struct ste_softc *sc = ifp->if_softc; 778 779 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 780 ifp->if_oerrors++; 781 782 ste_txintr(sc); 783 ste_rxintr(sc); 784 (void) ste_init(ifp); 785 786 /* Try to get more packets going. */ 787 ste_start(ifp); 788 } 789 790 /* 791 * ste_ioctl: [ifnet interface function] 792 * 793 * Handle control requests from the operator. 794 */ 795 static int 796 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 797 { 798 struct ste_softc *sc = ifp->if_softc; 799 int s, error; 800 801 s = splnet(); 802 803 error = ether_ioctl(ifp, cmd, data); 804 if (error == ENETRESET) { 805 /* 806 * Multicast list has changed; set the hardware filter 807 * accordingly. 808 */ 809 if (ifp->if_flags & IFF_RUNNING) 810 ste_set_filter(sc); 811 error = 0; 812 } 813 814 /* Try to get more packets going. */ 815 ste_start(ifp); 816 817 splx(s); 818 return (error); 819 } 820 821 /* 822 * ste_intr: 823 * 824 * Interrupt service routine. 825 */ 826 static int 827 ste_intr(void *arg) 828 { 829 struct ste_softc *sc = arg; 830 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 831 uint16_t isr; 832 uint8_t txstat; 833 int wantinit; 834 835 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 836 IS_InterruptStatus) == 0) 837 return (0); 838 839 for (wantinit = 0; wantinit == 0;) { 840 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 841 if ((isr & sc->sc_IntEnable) == 0) 842 break; 843 844 /* Receive interrupts. */ 845 if (isr & IE_RxDMAComplete) 846 ste_rxintr(sc); 847 848 /* Transmit interrupts. */ 849 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 850 ste_txintr(sc); 851 852 /* Statistics overflow. */ 853 if (isr & IE_UpdateStats) 854 ste_stats_update(sc); 855 856 /* Transmission errors. */ 857 if (isr & IE_TxComplete) { 858 for (;;) { 859 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 860 STE_TxStatus); 861 if ((txstat & TS_TxComplete) == 0) 862 break; 863 if (txstat & TS_TxUnderrun) { 864 sc->sc_txthresh += 32; 865 if (sc->sc_txthresh > 0x1ffc) 866 sc->sc_txthresh = 0x1ffc; 867 printf("%s: transmit underrun, new " 868 "threshold: %d bytes\n", 869 device_xname(sc->sc_dev), 870 sc->sc_txthresh); 871 ste_reset(sc, AC_TxReset | AC_DMA | 872 AC_FIFO | AC_Network); 873 ste_setthresh(sc); 874 bus_space_write_1(sc->sc_st, sc->sc_sh, 875 STE_TxDMAPollPeriod, 127); 876 ste_txrestart(sc, 877 bus_space_read_1(sc->sc_st, 878 sc->sc_sh, STE_TxFrameId)); 879 } 880 if (txstat & TS_TxReleaseError) { 881 printf("%s: Tx FIFO release error\n", 882 device_xname(sc->sc_dev)); 883 wantinit = 1; 884 } 885 if (txstat & TS_MaxCollisions) { 886 printf("%s: excessive collisions\n", 887 device_xname(sc->sc_dev)); 888 wantinit = 1; 889 } 890 if (txstat & TS_TxStatusOverflow) { 891 printf("%s: status overflow\n", 892 device_xname(sc->sc_dev)); 893 wantinit = 1; 894 } 895 bus_space_write_2(sc->sc_st, sc->sc_sh, 896 STE_TxStatus, 0); 897 } 898 } 899 900 /* Host interface errors. */ 901 if (isr & IE_HostError) { 902 printf("%s: Host interface error\n", 903 device_xname(sc->sc_dev)); 904 wantinit = 1; 905 } 906 } 907 908 if (wantinit) 909 ste_init(ifp); 910 911 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 912 sc->sc_IntEnable); 913 914 /* Try to get more packets going. */ 915 ste_start(ifp); 916 917 return (1); 918 } 919 920 /* 921 * ste_txintr: 922 * 923 * Helper; handle transmit interrupts. 924 */ 925 static void 926 ste_txintr(struct ste_softc *sc) 927 { 928 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 929 struct ste_descsoft *ds; 930 uint32_t control; 931 int i; 932 933 ifp->if_flags &= ~IFF_OACTIVE; 934 935 /* 936 * Go through our Tx list and free mbufs for those 937 * frames which have been transmitted. 938 */ 939 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 940 i = STE_NEXTTX(i), sc->sc_txpending--) { 941 ds = &sc->sc_txsoft[i]; 942 943 STE_CDTXSYNC(sc, i, 944 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 945 946 control = le32toh(sc->sc_txdescs[i].tfd_control); 947 if ((control & TFD_TxDMAComplete) == 0) 948 break; 949 950 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 951 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 952 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 953 m_freem(ds->ds_mbuf); 954 ds->ds_mbuf = NULL; 955 } 956 957 /* Update the dirty transmit buffer pointer. */ 958 sc->sc_txdirty = i; 959 960 /* 961 * If there are no more pending transmissions, cancel the watchdog 962 * timer. 963 */ 964 if (sc->sc_txpending == 0) 965 ifp->if_timer = 0; 966 } 967 968 /* 969 * ste_rxintr: 970 * 971 * Helper; handle receive interrupts. 972 */ 973 static void 974 ste_rxintr(struct ste_softc *sc) 975 { 976 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 977 struct ste_descsoft *ds; 978 struct mbuf *m; 979 uint32_t status; 980 int i, len; 981 982 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 983 ds = &sc->sc_rxsoft[i]; 984 985 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 986 987 status = le32toh(sc->sc_rxdescs[i].rfd_status); 988 989 if ((status & RFD_RxDMAComplete) == 0) 990 break; 991 992 /* 993 * If the packet had an error, simply recycle the 994 * buffer. Note, we count the error later in the 995 * periodic stats update. 996 */ 997 if (status & RFD_RxFrameError) { 998 STE_INIT_RXDESC(sc, i); 999 continue; 1000 } 1001 1002 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1003 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1004 1005 /* 1006 * No errors; receive the packet. Note, we have 1007 * configured the chip to not include the CRC at 1008 * the end of the packet. 1009 */ 1010 len = RFD_RxDMAFrameLen(status); 1011 1012 /* 1013 * If the packet is small enough to fit in a 1014 * single header mbuf, allocate one and copy 1015 * the data into it. This greatly reduces 1016 * memory consumption when we receive lots 1017 * of small packets. 1018 * 1019 * Otherwise, we add a new buffer to the receive 1020 * chain. If this fails, we drop the packet and 1021 * recycle the old buffer. 1022 */ 1023 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1024 MGETHDR(m, M_DONTWAIT, MT_DATA); 1025 if (m == NULL) 1026 goto dropit; 1027 m->m_data += 2; 1028 memcpy(mtod(m, void *), 1029 mtod(ds->ds_mbuf, void *), len); 1030 STE_INIT_RXDESC(sc, i); 1031 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1032 ds->ds_dmamap->dm_mapsize, 1033 BUS_DMASYNC_PREREAD); 1034 } else { 1035 m = ds->ds_mbuf; 1036 if (ste_add_rxbuf(sc, i) != 0) { 1037 dropit: 1038 ifp->if_ierrors++; 1039 STE_INIT_RXDESC(sc, i); 1040 bus_dmamap_sync(sc->sc_dmat, 1041 ds->ds_dmamap, 0, 1042 ds->ds_dmamap->dm_mapsize, 1043 BUS_DMASYNC_PREREAD); 1044 continue; 1045 } 1046 } 1047 1048 m_set_rcvif(m, ifp); 1049 m->m_pkthdr.len = m->m_len = len; 1050 1051 /* 1052 * Pass this up to any BPF listeners, but only 1053 * pass if up the stack if it's for us. 1054 */ 1055 bpf_mtap(ifp, m); 1056 1057 /* Pass it on. */ 1058 if_percpuq_enqueue(ifp->if_percpuq, m); 1059 } 1060 1061 /* Update the receive pointer. */ 1062 sc->sc_rxptr = i; 1063 } 1064 1065 /* 1066 * ste_tick: 1067 * 1068 * One second timer, used to tick the MII. 1069 */ 1070 static void 1071 ste_tick(void *arg) 1072 { 1073 struct ste_softc *sc = arg; 1074 int s; 1075 1076 s = splnet(); 1077 mii_tick(&sc->sc_mii); 1078 ste_stats_update(sc); 1079 splx(s); 1080 1081 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1082 } 1083 1084 /* 1085 * ste_stats_update: 1086 * 1087 * Read the ST-201 statistics counters. 1088 */ 1089 static void 1090 ste_stats_update(struct ste_softc *sc) 1091 { 1092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1093 bus_space_tag_t st = sc->sc_st; 1094 bus_space_handle_t sh = sc->sc_sh; 1095 1096 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1097 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1098 1099 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1100 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1101 1102 ifp->if_opackets += 1103 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1104 ifp->if_ipackets += 1105 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1106 1107 ifp->if_collisions += 1108 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1109 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1110 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1111 1112 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1113 1114 ifp->if_ierrors += 1115 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1116 1117 ifp->if_oerrors += 1118 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1119 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1120 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1121 1122 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1123 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1124 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1125 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1126 } 1127 1128 /* 1129 * ste_reset: 1130 * 1131 * Perform a soft reset on the ST-201. 1132 */ 1133 static void 1134 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1135 { 1136 uint32_t ac; 1137 int i; 1138 1139 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1140 1141 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1142 1143 delay(50000); 1144 1145 for (i = 0; i < STE_TIMEOUT; i++) { 1146 delay(1000); 1147 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1148 AC_ResetBusy) == 0) 1149 break; 1150 } 1151 1152 if (i == STE_TIMEOUT) 1153 printf("%s: reset failed to complete\n", 1154 device_xname(sc->sc_dev)); 1155 1156 delay(1000); 1157 } 1158 1159 /* 1160 * ste_setthresh: 1161 * 1162 * set the various transmit threshold registers 1163 */ 1164 static void 1165 ste_setthresh(struct ste_softc *sc) 1166 { 1167 /* set the TX threhold */ 1168 bus_space_write_2(sc->sc_st, sc->sc_sh, 1169 STE_TxStartThresh, sc->sc_txthresh); 1170 /* Urgent threshold: set to sc_txthresh / 2 */ 1171 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1172 sc->sc_txthresh >> 6); 1173 /* Burst threshold: use default value (256 bytes) */ 1174 } 1175 1176 /* 1177 * restart TX at the given frame ID in the transmitter ring 1178 */ 1179 static void 1180 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1181 { 1182 u_int32_t control; 1183 1184 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1185 control = le32toh(sc->sc_txdescs[id].tfd_control); 1186 control &= ~TFD_TxDMAComplete; 1187 sc->sc_txdescs[id].tfd_control = htole32(control); 1188 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1189 1190 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1191 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1192 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1193 ste_dmahalt_wait(sc); 1194 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1195 STE_CDTXADDR(sc, id)); 1196 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1197 } 1198 1199 /* 1200 * ste_init: [ ifnet interface function ] 1201 * 1202 * Initialize the interface. Must be called at splnet(). 1203 */ 1204 static int 1205 ste_init(struct ifnet *ifp) 1206 { 1207 struct ste_softc *sc = ifp->if_softc; 1208 bus_space_tag_t st = sc->sc_st; 1209 bus_space_handle_t sh = sc->sc_sh; 1210 struct ste_descsoft *ds; 1211 int i, error = 0; 1212 1213 /* 1214 * Cancel any pending I/O. 1215 */ 1216 ste_stop(ifp, 0); 1217 1218 /* 1219 * Reset the chip to a known state. 1220 */ 1221 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1222 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1223 1224 /* 1225 * Initialize the transmit descriptor ring. 1226 */ 1227 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1228 sc->sc_txpending = 0; 1229 sc->sc_txdirty = 0; 1230 sc->sc_txlast = STE_NTXDESC - 1; 1231 1232 /* 1233 * Initialize the receive descriptor and receive job 1234 * descriptor rings. 1235 */ 1236 for (i = 0; i < STE_NRXDESC; i++) { 1237 ds = &sc->sc_rxsoft[i]; 1238 if (ds->ds_mbuf == NULL) { 1239 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1240 printf("%s: unable to allocate or map rx " 1241 "buffer %d, error = %d\n", 1242 device_xname(sc->sc_dev), i, error); 1243 /* 1244 * XXX Should attempt to run with fewer receive 1245 * XXX buffers instead of just failing. 1246 */ 1247 ste_rxdrain(sc); 1248 goto out; 1249 } 1250 } else 1251 STE_INIT_RXDESC(sc, i); 1252 } 1253 sc->sc_rxptr = 0; 1254 1255 /* Set the station address. */ 1256 for (i = 0; i < ETHER_ADDR_LEN; i++) 1257 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1258 CLLADDR(ifp->if_sadl)[i]); 1259 1260 /* Set up the receive filter. */ 1261 ste_set_filter(sc); 1262 1263 /* 1264 * Give the receive ring to the chip. 1265 */ 1266 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1267 STE_CDRXADDR(sc, sc->sc_rxptr)); 1268 1269 /* 1270 * We defer giving the transmit ring to the chip until we 1271 * transmit the first packet. 1272 */ 1273 1274 /* 1275 * Initialize the Tx auto-poll period. It's OK to make this number 1276 * large (127 is the max) -- we explicitly kick the transmit engine 1277 * when there's actually a packet. We are using auto-polling only 1278 * to make the interface to the transmit engine not suck. 1279 */ 1280 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1281 1282 /* ..and the Rx auto-poll period. */ 1283 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1284 1285 /* Initialize the Tx start threshold. */ 1286 ste_setthresh(sc); 1287 1288 /* Set the FIFO release threshold to 512 bytes. */ 1289 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1290 1291 /* Set maximum packet size for VLAN. */ 1292 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1293 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1294 else 1295 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1296 1297 /* 1298 * Initialize the interrupt mask. 1299 */ 1300 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1301 IE_TxDMAComplete | IE_RxDMAComplete; 1302 1303 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1304 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1305 1306 /* 1307 * Start the receive DMA engine. 1308 */ 1309 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1310 1311 /* 1312 * Initialize MacCtrl0 -- do it before setting the media, 1313 * as setting the media will actually program the register. 1314 */ 1315 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1316 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1317 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1318 1319 /* 1320 * Set the current media. 1321 */ 1322 if ((error = ether_mediachange(ifp)) != 0) 1323 goto out; 1324 1325 /* 1326 * Start the MAC. 1327 */ 1328 bus_space_write_2(st, sh, STE_MacCtrl1, 1329 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1330 1331 /* 1332 * Start the one second MII clock. 1333 */ 1334 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1335 1336 /* 1337 * ...all done! 1338 */ 1339 ifp->if_flags |= IFF_RUNNING; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 1342 out: 1343 if (error) 1344 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1345 return (error); 1346 } 1347 1348 /* 1349 * ste_drain: 1350 * 1351 * Drain the receive queue. 1352 */ 1353 static void 1354 ste_rxdrain(struct ste_softc *sc) 1355 { 1356 struct ste_descsoft *ds; 1357 int i; 1358 1359 for (i = 0; i < STE_NRXDESC; i++) { 1360 ds = &sc->sc_rxsoft[i]; 1361 if (ds->ds_mbuf != NULL) { 1362 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1363 m_freem(ds->ds_mbuf); 1364 ds->ds_mbuf = NULL; 1365 } 1366 } 1367 } 1368 1369 /* 1370 * ste_stop: [ ifnet interface function ] 1371 * 1372 * Stop transmission on the interface. 1373 */ 1374 static void 1375 ste_stop(struct ifnet *ifp, int disable) 1376 { 1377 struct ste_softc *sc = ifp->if_softc; 1378 struct ste_descsoft *ds; 1379 int i; 1380 1381 /* 1382 * Stop the one second clock. 1383 */ 1384 callout_stop(&sc->sc_tick_ch); 1385 1386 /* Down the MII. */ 1387 mii_down(&sc->sc_mii); 1388 1389 /* 1390 * Disable interrupts. 1391 */ 1392 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1393 1394 /* 1395 * Stop receiver, transmitter, and stats update. 1396 */ 1397 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1398 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1399 1400 /* 1401 * Stop the transmit and receive DMA. 1402 */ 1403 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1404 DC_RxDMAHalt | DC_TxDMAHalt); 1405 ste_dmahalt_wait(sc); 1406 1407 /* 1408 * Release any queued transmit buffers. 1409 */ 1410 for (i = 0; i < STE_NTXDESC; i++) { 1411 ds = &sc->sc_txsoft[i]; 1412 if (ds->ds_mbuf != NULL) { 1413 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1414 m_freem(ds->ds_mbuf); 1415 ds->ds_mbuf = NULL; 1416 } 1417 } 1418 1419 /* 1420 * Mark the interface down and cancel the watchdog timer. 1421 */ 1422 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1423 ifp->if_timer = 0; 1424 1425 if (disable) 1426 ste_rxdrain(sc); 1427 } 1428 1429 static int 1430 ste_eeprom_wait(struct ste_softc *sc) 1431 { 1432 int i; 1433 1434 for (i = 0; i < STE_TIMEOUT; i++) { 1435 delay(1000); 1436 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1437 EC_EepromBusy) == 0) 1438 return (0); 1439 } 1440 return (1); 1441 } 1442 1443 /* 1444 * ste_read_eeprom: 1445 * 1446 * Read data from the serial EEPROM. 1447 */ 1448 static void 1449 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1450 { 1451 1452 if (ste_eeprom_wait(sc)) 1453 printf("%s: EEPROM failed to come ready\n", 1454 device_xname(sc->sc_dev)); 1455 1456 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1457 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1458 if (ste_eeprom_wait(sc)) 1459 printf("%s: EEPROM read timed out\n", 1460 device_xname(sc->sc_dev)); 1461 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1462 } 1463 1464 /* 1465 * ste_add_rxbuf: 1466 * 1467 * Add a receive buffer to the indicated descriptor. 1468 */ 1469 static int 1470 ste_add_rxbuf(struct ste_softc *sc, int idx) 1471 { 1472 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1473 struct mbuf *m; 1474 int error; 1475 1476 MGETHDR(m, M_DONTWAIT, MT_DATA); 1477 if (m == NULL) 1478 return (ENOBUFS); 1479 1480 MCLGET(m, M_DONTWAIT); 1481 if ((m->m_flags & M_EXT) == 0) { 1482 m_freem(m); 1483 return (ENOBUFS); 1484 } 1485 1486 if (ds->ds_mbuf != NULL) 1487 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1488 1489 ds->ds_mbuf = m; 1490 1491 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1492 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1493 BUS_DMA_READ|BUS_DMA_NOWAIT); 1494 if (error) { 1495 printf("%s: can't load rx DMA map %d, error = %d\n", 1496 device_xname(sc->sc_dev), idx, error); 1497 panic("ste_add_rxbuf"); /* XXX */ 1498 } 1499 1500 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1501 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1502 1503 STE_INIT_RXDESC(sc, idx); 1504 1505 return (0); 1506 } 1507 1508 /* 1509 * ste_set_filter: 1510 * 1511 * Set up the receive filter. 1512 */ 1513 static void 1514 ste_set_filter(struct ste_softc *sc) 1515 { 1516 struct ethercom *ec = &sc->sc_ethercom; 1517 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1518 struct ether_multi *enm; 1519 struct ether_multistep step; 1520 uint32_t crc; 1521 uint16_t mchash[4]; 1522 1523 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1524 if (ifp->if_flags & IFF_BROADCAST) 1525 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1526 1527 if (ifp->if_flags & IFF_PROMISC) { 1528 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1529 goto allmulti; 1530 } 1531 1532 /* 1533 * Set up the multicast address filter by passing all multicast 1534 * addresses through a CRC generator, and then using the low-order 1535 * 6 bits as an index into the 64 bit multicast hash table. The 1536 * high order bits select the register, while the rest of the bits 1537 * select the bit within the register. 1538 */ 1539 1540 memset(mchash, 0, sizeof(mchash)); 1541 1542 ETHER_FIRST_MULTI(step, ec, enm); 1543 if (enm == NULL) 1544 goto done; 1545 1546 while (enm != NULL) { 1547 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1548 /* 1549 * We must listen to a range of multicast addresses. 1550 * For now, just accept all multicasts, rather than 1551 * trying to set only those filter bits needed to match 1552 * the range. (At this time, the only use of address 1553 * ranges is for IP multicast routing, for which the 1554 * range is big enough to require all bits set.) 1555 */ 1556 goto allmulti; 1557 } 1558 1559 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1560 1561 /* Just want the 6 least significant bits. */ 1562 crc &= 0x3f; 1563 1564 /* Set the corresponding bit in the hash table. */ 1565 mchash[crc >> 4] |= 1 << (crc & 0xf); 1566 1567 ETHER_NEXT_MULTI(step, enm); 1568 } 1569 1570 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1571 1572 ifp->if_flags &= ~IFF_ALLMULTI; 1573 goto done; 1574 1575 allmulti: 1576 ifp->if_flags |= IFF_ALLMULTI; 1577 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1578 1579 done: 1580 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1581 /* 1582 * Program the multicast hash table. 1583 */ 1584 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1585 mchash[0]); 1586 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1587 mchash[1]); 1588 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1589 mchash[2]); 1590 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1591 mchash[3]); 1592 } 1593 1594 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1595 sc->sc_ReceiveMode); 1596 } 1597 1598 /* 1599 * ste_mii_readreg: [mii interface function] 1600 * 1601 * Read a PHY register on the MII of the ST-201. 1602 */ 1603 static int 1604 ste_mii_readreg(device_t self, int phy, int reg) 1605 { 1606 1607 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1608 } 1609 1610 /* 1611 * ste_mii_writereg: [mii interface function] 1612 * 1613 * Write a PHY register on the MII of the ST-201. 1614 */ 1615 static void 1616 ste_mii_writereg(device_t self, int phy, int reg, int val) 1617 { 1618 1619 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1620 } 1621 1622 /* 1623 * ste_mii_statchg: [mii interface function] 1624 * 1625 * Callback from MII layer when media changes. 1626 */ 1627 static void 1628 ste_mii_statchg(struct ifnet *ifp) 1629 { 1630 struct ste_softc *sc = ifp->if_softc; 1631 1632 if (sc->sc_mii.mii_media_active & IFM_FDX) 1633 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1634 else 1635 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1636 1637 /* XXX 802.1x flow-control? */ 1638 1639 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1640 } 1641 1642 /* 1643 * ste_mii_bitbang_read: [mii bit-bang interface function] 1644 * 1645 * Read the MII serial port for the MII bit-bang module. 1646 */ 1647 static uint32_t 1648 ste_mii_bitbang_read(device_t self) 1649 { 1650 struct ste_softc *sc = device_private(self); 1651 1652 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1653 } 1654 1655 /* 1656 * ste_mii_bitbang_write: [mii big-bang interface function] 1657 * 1658 * Write the MII serial port for the MII bit-bang module. 1659 */ 1660 static void 1661 ste_mii_bitbang_write(device_t self, uint32_t val) 1662 { 1663 struct ste_softc *sc = device_private(self); 1664 1665 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1666 } 1667