1 /* $NetBSD: if_ste.c,v 1.23 2006/06/17 23:34:27 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.23 2006/06/17 23:34:27 christos Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 struct callout sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 static void ste_start(struct ifnet *); 208 static void ste_watchdog(struct ifnet *); 209 static int ste_ioctl(struct ifnet *, u_long, caddr_t); 210 static int ste_init(struct ifnet *); 211 static void ste_stop(struct ifnet *, int); 212 213 static void ste_shutdown(void *); 214 215 static void ste_reset(struct ste_softc *, u_int32_t); 216 static void ste_setthresh(struct ste_softc *); 217 static void ste_txrestart(struct ste_softc *, u_int8_t); 218 static void ste_rxdrain(struct ste_softc *); 219 static int ste_add_rxbuf(struct ste_softc *, int); 220 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 221 static void ste_tick(void *); 222 223 static void ste_stats_update(struct ste_softc *); 224 225 static void ste_set_filter(struct ste_softc *); 226 227 static int ste_intr(void *); 228 static void ste_txintr(struct ste_softc *); 229 static void ste_rxintr(struct ste_softc *); 230 231 static int ste_mii_readreg(struct device *, int, int); 232 static void ste_mii_writereg(struct device *, int, int, int); 233 static void ste_mii_statchg(struct device *); 234 235 static int ste_mediachange(struct ifnet *); 236 static void ste_mediastatus(struct ifnet *, struct ifmediareq *); 237 238 static int ste_match(struct device *, struct cfdata *, void *); 239 static void ste_attach(struct device *, struct device *, void *); 240 241 int ste_copy_small = 0; 242 243 CFATTACH_DECL(ste, sizeof(struct ste_softc), 244 ste_match, ste_attach, NULL, NULL); 245 246 static uint32_t ste_mii_bitbang_read(struct device *); 247 static void ste_mii_bitbang_write(struct device *, uint32_t); 248 249 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 250 ste_mii_bitbang_read, 251 ste_mii_bitbang_write, 252 { 253 PC_MgmtData, /* MII_BIT_MDO */ 254 PC_MgmtData, /* MII_BIT_MDI */ 255 PC_MgmtClk, /* MII_BIT_MDC */ 256 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 257 0, /* MII_BIT_DIR_PHY_HOST */ 258 } 259 }; 260 261 /* 262 * Devices supported by this driver. 263 */ 264 static const struct ste_product { 265 pci_vendor_id_t ste_vendor; 266 pci_product_id_t ste_product; 267 const char *ste_name; 268 } ste_products[] = { 269 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 270 "Sundance ST-201 10/100 Ethernet" }, 271 272 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 273 "D-Link DL-1002 10/100 Ethernet" }, 274 275 { 0, 0, 276 NULL }, 277 }; 278 279 static const struct ste_product * 280 ste_lookup(const struct pci_attach_args *pa) 281 { 282 const struct ste_product *sp; 283 284 for (sp = ste_products; sp->ste_name != NULL; sp++) { 285 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 286 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 287 return (sp); 288 } 289 return (NULL); 290 } 291 292 static int 293 ste_match(struct device *parent, struct cfdata *cf, void *aux) 294 { 295 struct pci_attach_args *pa = aux; 296 297 if (ste_lookup(pa) != NULL) 298 return (1); 299 300 return (0); 301 } 302 303 static void 304 ste_attach(struct device *parent, struct device *self, void *aux) 305 { 306 struct ste_softc *sc = (struct ste_softc *) self; 307 struct pci_attach_args *pa = aux; 308 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 309 pci_chipset_tag_t pc = pa->pa_pc; 310 pci_intr_handle_t ih; 311 const char *intrstr = NULL; 312 bus_space_tag_t iot, memt; 313 bus_space_handle_t ioh, memh; 314 bus_dma_segment_t seg; 315 int ioh_valid, memh_valid; 316 int i, rseg, error; 317 const struct ste_product *sp; 318 uint8_t enaddr[ETHER_ADDR_LEN]; 319 uint16_t myea[ETHER_ADDR_LEN / 2]; 320 321 callout_init(&sc->sc_tick_ch); 322 323 sp = ste_lookup(pa); 324 if (sp == NULL) { 325 printf("\n"); 326 panic("ste_attach: impossible"); 327 } 328 329 printf(": %s\n", sp->ste_name); 330 331 /* 332 * Map the device. 333 */ 334 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 335 PCI_MAPREG_TYPE_IO, 0, 336 &iot, &ioh, NULL, NULL) == 0); 337 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 338 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 339 &memt, &memh, NULL, NULL) == 0); 340 341 if (memh_valid) { 342 sc->sc_st = memt; 343 sc->sc_sh = memh; 344 } else if (ioh_valid) { 345 sc->sc_st = iot; 346 sc->sc_sh = ioh; 347 } else { 348 printf("%s: unable to map device registers\n", 349 sc->sc_dev.dv_xname); 350 return; 351 } 352 353 sc->sc_dmat = pa->pa_dmat; 354 355 /* Enable bus mastering. */ 356 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 357 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 358 PCI_COMMAND_MASTER_ENABLE); 359 360 /* power up chip */ 361 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 362 NULL)) && error != EOPNOTSUPP) { 363 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 364 error); 365 return; 366 } 367 368 /* 369 * Map and establish our interrupt. 370 */ 371 if (pci_intr_map(pa, &ih)) { 372 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 373 return; 374 } 375 intrstr = pci_intr_string(pc, ih); 376 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 377 if (sc->sc_ih == NULL) { 378 printf("%s: unable to establish interrupt", 379 sc->sc_dev.dv_xname); 380 if (intrstr != NULL) 381 printf(" at %s", intrstr); 382 printf("\n"); 383 return; 384 } 385 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 386 387 /* 388 * Allocate the control data structures, and create and load the 389 * DMA map for it. 390 */ 391 if ((error = bus_dmamem_alloc(sc->sc_dmat, 392 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 393 0)) != 0) { 394 printf("%s: unable to allocate control data, error = %d\n", 395 sc->sc_dev.dv_xname, error); 396 goto fail_0; 397 } 398 399 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 400 sizeof(struct ste_control_data), (caddr_t *)&sc->sc_control_data, 401 BUS_DMA_COHERENT)) != 0) { 402 printf("%s: unable to map control data, error = %d\n", 403 sc->sc_dev.dv_xname, error); 404 goto fail_1; 405 } 406 407 if ((error = bus_dmamap_create(sc->sc_dmat, 408 sizeof(struct ste_control_data), 1, 409 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 410 printf("%s: unable to create control data DMA map, " 411 "error = %d\n", sc->sc_dev.dv_xname, error); 412 goto fail_2; 413 } 414 415 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 416 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 417 0)) != 0) { 418 printf("%s: unable to load control data DMA map, error = %d\n", 419 sc->sc_dev.dv_xname, error); 420 goto fail_3; 421 } 422 423 /* 424 * Create the transmit buffer DMA maps. 425 */ 426 for (i = 0; i < STE_NTXDESC; i++) { 427 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 428 STE_NTXFRAGS, MCLBYTES, 0, 0, 429 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 430 printf("%s: unable to create tx DMA map %d, " 431 "error = %d\n", sc->sc_dev.dv_xname, i, error); 432 goto fail_4; 433 } 434 } 435 436 /* 437 * Create the receive buffer DMA maps. 438 */ 439 for (i = 0; i < STE_NRXDESC; i++) { 440 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 441 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 442 printf("%s: unable to create rx DMA map %d, " 443 "error = %d\n", sc->sc_dev.dv_xname, i, error); 444 goto fail_5; 445 } 446 sc->sc_rxsoft[i].ds_mbuf = NULL; 447 } 448 449 /* 450 * Reset the chip to a known state. 451 */ 452 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 453 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 454 455 /* 456 * Read the Ethernet address from the EEPROM. 457 */ 458 for (i = 0; i < 3; i++) { 459 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 460 myea[i] = le16toh(myea[i]); 461 } 462 memcpy(enaddr, myea, sizeof(enaddr)); 463 464 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 465 ether_sprintf(enaddr)); 466 467 /* 468 * Initialize our media structures and probe the MII. 469 */ 470 sc->sc_mii.mii_ifp = ifp; 471 sc->sc_mii.mii_readreg = ste_mii_readreg; 472 sc->sc_mii.mii_writereg = ste_mii_writereg; 473 sc->sc_mii.mii_statchg = ste_mii_statchg; 474 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ste_mediachange, 475 ste_mediastatus); 476 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 477 MII_OFFSET_ANY, 0); 478 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 479 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 480 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 481 } else 482 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 483 484 ifp = &sc->sc_ethercom.ec_if; 485 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 486 ifp->if_softc = sc; 487 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 488 ifp->if_ioctl = ste_ioctl; 489 ifp->if_start = ste_start; 490 ifp->if_watchdog = ste_watchdog; 491 ifp->if_init = ste_init; 492 ifp->if_stop = ste_stop; 493 IFQ_SET_READY(&ifp->if_snd); 494 495 /* 496 * Default the transmit threshold to 128 bytes. 497 */ 498 sc->sc_txthresh = 128; 499 500 /* 501 * Disable MWI if the PCI layer tells us to. 502 */ 503 sc->sc_DMACtrl = 0; 504 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 505 sc->sc_DMACtrl |= DC_MWIDisable; 506 507 /* 508 * We can support 802.1Q VLAN-sized frames. 509 */ 510 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 511 512 /* 513 * Attach the interface. 514 */ 515 if_attach(ifp); 516 ether_ifattach(ifp, enaddr); 517 518 /* 519 * Make sure the interface is shutdown during reboot. 520 */ 521 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 522 if (sc->sc_sdhook == NULL) 523 printf("%s: WARNING: unable to establish shutdown hook\n", 524 sc->sc_dev.dv_xname); 525 return; 526 527 /* 528 * Free any resources we've allocated during the failed attach 529 * attempt. Do this in reverse order and fall through. 530 */ 531 fail_5: 532 for (i = 0; i < STE_NRXDESC; i++) { 533 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 534 bus_dmamap_destroy(sc->sc_dmat, 535 sc->sc_rxsoft[i].ds_dmamap); 536 } 537 fail_4: 538 for (i = 0; i < STE_NTXDESC; i++) { 539 if (sc->sc_txsoft[i].ds_dmamap != NULL) 540 bus_dmamap_destroy(sc->sc_dmat, 541 sc->sc_txsoft[i].ds_dmamap); 542 } 543 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 544 fail_3: 545 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 546 fail_2: 547 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 548 sizeof(struct ste_control_data)); 549 fail_1: 550 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 551 fail_0: 552 return; 553 } 554 555 /* 556 * ste_shutdown: 557 * 558 * Make sure the interface is stopped at reboot time. 559 */ 560 static void 561 ste_shutdown(void *arg) 562 { 563 struct ste_softc *sc = arg; 564 565 ste_stop(&sc->sc_ethercom.ec_if, 1); 566 } 567 568 static void 569 ste_dmahalt_wait(struct ste_softc *sc) 570 { 571 int i; 572 573 for (i = 0; i < STE_TIMEOUT; i++) { 574 delay(2); 575 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 576 DC_DMAHaltBusy) == 0) 577 break; 578 } 579 580 if (i == STE_TIMEOUT) 581 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 582 } 583 584 /* 585 * ste_start: [ifnet interface function] 586 * 587 * Start packet transmission on the interface. 588 */ 589 static void 590 ste_start(struct ifnet *ifp) 591 { 592 struct ste_softc *sc = ifp->if_softc; 593 struct mbuf *m0, *m; 594 struct ste_descsoft *ds; 595 struct ste_tfd *tfd; 596 bus_dmamap_t dmamap; 597 int error, olasttx, nexttx, opending, seg, totlen; 598 599 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 600 return; 601 602 /* 603 * Remember the previous number of pending transmissions 604 * and the current last descriptor in the list. 605 */ 606 opending = sc->sc_txpending; 607 olasttx = sc->sc_txlast; 608 609 /* 610 * Loop through the send queue, setting up transmit descriptors 611 * until we drain the queue, or use up all available transmit 612 * descriptors. 613 */ 614 while (sc->sc_txpending < STE_NTXDESC) { 615 /* 616 * Grab a packet off the queue. 617 */ 618 IFQ_POLL(&ifp->if_snd, m0); 619 if (m0 == NULL) 620 break; 621 m = NULL; 622 623 /* 624 * Get the last and next available transmit descriptor. 625 */ 626 nexttx = STE_NEXTTX(sc->sc_txlast); 627 tfd = &sc->sc_txdescs[nexttx]; 628 ds = &sc->sc_txsoft[nexttx]; 629 630 dmamap = ds->ds_dmamap; 631 632 /* 633 * Load the DMA map. If this fails, the packet either 634 * didn't fit in the alloted number of segments, or we 635 * were short on resources. In this case, we'll copy 636 * and try again. 637 */ 638 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 639 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 640 MGETHDR(m, M_DONTWAIT, MT_DATA); 641 if (m == NULL) { 642 printf("%s: unable to allocate Tx mbuf\n", 643 sc->sc_dev.dv_xname); 644 break; 645 } 646 if (m0->m_pkthdr.len > MHLEN) { 647 MCLGET(m, M_DONTWAIT); 648 if ((m->m_flags & M_EXT) == 0) { 649 printf("%s: unable to allocate Tx " 650 "cluster\n", sc->sc_dev.dv_xname); 651 m_freem(m); 652 break; 653 } 654 } 655 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 656 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 657 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 658 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 659 if (error) { 660 printf("%s: unable to load Tx buffer, " 661 "error = %d\n", sc->sc_dev.dv_xname, error); 662 break; 663 } 664 } 665 666 IFQ_DEQUEUE(&ifp->if_snd, m0); 667 if (m != NULL) { 668 m_freem(m0); 669 m0 = m; 670 } 671 672 /* 673 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 674 */ 675 676 /* Sync the DMA map. */ 677 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 678 BUS_DMASYNC_PREWRITE); 679 680 /* Initialize the fragment list. */ 681 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 682 tfd->tfd_frags[seg].frag_addr = 683 htole32(dmamap->dm_segs[seg].ds_addr); 684 tfd->tfd_frags[seg].frag_len = 685 htole32(dmamap->dm_segs[seg].ds_len); 686 totlen += dmamap->dm_segs[seg].ds_len; 687 } 688 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 689 690 /* Initialize the descriptor. */ 691 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 692 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 693 694 /* Sync the descriptor. */ 695 STE_CDTXSYNC(sc, nexttx, 696 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 697 698 /* 699 * Store a pointer to the packet so we can free it later, 700 * and remember what txdirty will be once the packet is 701 * done. 702 */ 703 ds->ds_mbuf = m0; 704 705 /* Advance the tx pointer. */ 706 sc->sc_txpending++; 707 sc->sc_txlast = nexttx; 708 709 #if NBPFILTER > 0 710 /* 711 * Pass the packet to any BPF listeners. 712 */ 713 if (ifp->if_bpf) 714 bpf_mtap(ifp->if_bpf, m0); 715 #endif /* NBPFILTER > 0 */ 716 } 717 718 if (sc->sc_txpending == STE_NTXDESC) { 719 /* No more slots left; notify upper layer. */ 720 ifp->if_flags |= IFF_OACTIVE; 721 } 722 723 if (sc->sc_txpending != opending) { 724 /* 725 * We enqueued packets. If the transmitter was idle, 726 * reset the txdirty pointer. 727 */ 728 if (opending == 0) 729 sc->sc_txdirty = STE_NEXTTX(olasttx); 730 731 /* 732 * Cause a descriptor interrupt to happen on the 733 * last packet we enqueued, and also cause the 734 * DMA engine to wait after is has finished processing 735 * it. 736 */ 737 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 738 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 739 htole32(TFD_TxDMAIndicate); 740 STE_CDTXSYNC(sc, sc->sc_txlast, 741 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 742 743 /* 744 * Link up the new chain of descriptors to the 745 * last. 746 */ 747 sc->sc_txdescs[olasttx].tfd_next = 748 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 749 STE_CDTXSYNC(sc, olasttx, 750 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 751 752 /* 753 * Kick the transmit DMA logic. Note that since we're 754 * using auto-polling, reading the Tx desc pointer will 755 * give it the nudge it needs to get going. 756 */ 757 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 758 STE_TxDMAListPtr) == 0) { 759 bus_space_write_4(sc->sc_st, sc->sc_sh, 760 STE_DMACtrl, DC_TxDMAHalt); 761 ste_dmahalt_wait(sc); 762 bus_space_write_4(sc->sc_st, sc->sc_sh, 763 STE_TxDMAListPtr, 764 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 765 bus_space_write_4(sc->sc_st, sc->sc_sh, 766 STE_DMACtrl, DC_TxDMAResume); 767 } 768 769 /* Set a watchdog timer in case the chip flakes out. */ 770 ifp->if_timer = 5; 771 } 772 } 773 774 /* 775 * ste_watchdog: [ifnet interface function] 776 * 777 * Watchdog timer handler. 778 */ 779 static void 780 ste_watchdog(struct ifnet *ifp) 781 { 782 struct ste_softc *sc = ifp->if_softc; 783 784 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 785 ifp->if_oerrors++; 786 787 (void) ste_init(ifp); 788 789 /* Try to get more packets going. */ 790 ste_start(ifp); 791 } 792 793 /* 794 * ste_ioctl: [ifnet interface function] 795 * 796 * Handle control requests from the operator. 797 */ 798 static int 799 ste_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 800 { 801 struct ste_softc *sc = ifp->if_softc; 802 struct ifreq *ifr = (struct ifreq *)data; 803 int s, error; 804 805 s = splnet(); 806 807 switch (cmd) { 808 case SIOCSIFMEDIA: 809 case SIOCGIFMEDIA: 810 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 811 break; 812 813 default: 814 error = ether_ioctl(ifp, cmd, data); 815 if (error == ENETRESET) { 816 /* 817 * Multicast list has changed; set the hardware filter 818 * accordingly. 819 */ 820 if (ifp->if_flags & IFF_RUNNING) 821 ste_set_filter(sc); 822 error = 0; 823 } 824 break; 825 } 826 827 /* Try to get more packets going. */ 828 ste_start(ifp); 829 830 splx(s); 831 return (error); 832 } 833 834 /* 835 * ste_intr: 836 * 837 * Interrupt service routine. 838 */ 839 static int 840 ste_intr(void *arg) 841 { 842 struct ste_softc *sc = arg; 843 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 844 uint16_t isr; 845 uint8_t txstat; 846 int wantinit; 847 848 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 849 IS_InterruptStatus) == 0) 850 return (0); 851 852 for (wantinit = 0; wantinit == 0;) { 853 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 854 if ((isr & sc->sc_IntEnable) == 0) 855 break; 856 857 /* Receive interrupts. */ 858 if (isr & IE_RxDMAComplete) 859 ste_rxintr(sc); 860 861 /* Transmit interrupts. */ 862 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 863 ste_txintr(sc); 864 865 /* Statistics overflow. */ 866 if (isr & IE_UpdateStats) 867 ste_stats_update(sc); 868 869 /* Transmission errors. */ 870 if (isr & IE_TxComplete) { 871 for (;;) { 872 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 873 STE_TxStatus); 874 if ((txstat & TS_TxComplete) == 0) 875 break; 876 if (txstat & TS_TxUnderrun) { 877 sc->sc_txthresh += 32; 878 if (sc->sc_txthresh > 0x1ffc) 879 sc->sc_txthresh = 0x1ffc; 880 printf("%s: transmit underrun, new " 881 "threshold: %d bytes\n", 882 sc->sc_dev.dv_xname, 883 sc->sc_txthresh); 884 ste_reset(sc, AC_TxReset | AC_DMA | 885 AC_FIFO | AC_Network); 886 ste_setthresh(sc); 887 bus_space_write_1(sc->sc_st, sc->sc_sh, 888 STE_TxDMAPollPeriod, 127); 889 ste_txrestart(sc, 890 bus_space_read_1(sc->sc_st, 891 sc->sc_sh, STE_TxFrameId)); 892 } 893 if (txstat & TS_TxReleaseError) { 894 printf("%s: Tx FIFO release error\n", 895 sc->sc_dev.dv_xname); 896 wantinit = 1; 897 } 898 if (txstat & TS_MaxCollisions) { 899 printf("%s: excessive collisions\n", 900 sc->sc_dev.dv_xname); 901 wantinit = 1; 902 } 903 if (txstat & TS_TxStatusOverflow) { 904 printf("%s: status overflow\n", 905 sc->sc_dev.dv_xname); 906 wantinit = 1; 907 } 908 bus_space_write_2(sc->sc_st, sc->sc_sh, 909 STE_TxStatus, 0); 910 } 911 } 912 913 /* Host interface errors. */ 914 if (isr & IE_HostError) { 915 printf("%s: Host interface error\n", 916 sc->sc_dev.dv_xname); 917 wantinit = 1; 918 } 919 } 920 921 if (wantinit) 922 ste_init(ifp); 923 924 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 925 sc->sc_IntEnable); 926 927 /* Try to get more packets going. */ 928 ste_start(ifp); 929 930 return (1); 931 } 932 933 /* 934 * ste_txintr: 935 * 936 * Helper; handle transmit interrupts. 937 */ 938 static void 939 ste_txintr(struct ste_softc *sc) 940 { 941 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 942 struct ste_descsoft *ds; 943 uint32_t control; 944 int i; 945 946 ifp->if_flags &= ~IFF_OACTIVE; 947 948 /* 949 * Go through our Tx list and free mbufs for those 950 * frames which have been transmitted. 951 */ 952 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 953 i = STE_NEXTTX(i), sc->sc_txpending--) { 954 ds = &sc->sc_txsoft[i]; 955 956 STE_CDTXSYNC(sc, i, 957 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 958 959 control = le32toh(sc->sc_txdescs[i].tfd_control); 960 if ((control & TFD_TxDMAComplete) == 0) 961 break; 962 963 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 964 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 965 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 966 m_freem(ds->ds_mbuf); 967 ds->ds_mbuf = NULL; 968 } 969 970 /* Update the dirty transmit buffer pointer. */ 971 sc->sc_txdirty = i; 972 973 /* 974 * If there are no more pending transmissions, cancel the watchdog 975 * timer. 976 */ 977 if (sc->sc_txpending == 0) 978 ifp->if_timer = 0; 979 } 980 981 /* 982 * ste_rxintr: 983 * 984 * Helper; handle receive interrupts. 985 */ 986 static void 987 ste_rxintr(struct ste_softc *sc) 988 { 989 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 990 struct ste_descsoft *ds; 991 struct mbuf *m; 992 uint32_t status; 993 int i, len; 994 995 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 996 ds = &sc->sc_rxsoft[i]; 997 998 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 999 1000 status = le32toh(sc->sc_rxdescs[i].rfd_status); 1001 1002 if ((status & RFD_RxDMAComplete) == 0) 1003 break; 1004 1005 /* 1006 * If the packet had an error, simply recycle the 1007 * buffer. Note, we count the error later in the 1008 * periodic stats update. 1009 */ 1010 if (status & RFD_RxFrameError) { 1011 STE_INIT_RXDESC(sc, i); 1012 continue; 1013 } 1014 1015 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1016 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1017 1018 /* 1019 * No errors; receive the packet. Note, we have 1020 * configured the chip to not include the CRC at 1021 * the end of the packet. 1022 */ 1023 len = RFD_RxDMAFrameLen(status); 1024 1025 /* 1026 * If the packet is small enough to fit in a 1027 * single header mbuf, allocate one and copy 1028 * the data into it. This greatly reduces 1029 * memory consumption when we receive lots 1030 * of small packets. 1031 * 1032 * Otherwise, we add a new buffer to the receive 1033 * chain. If this fails, we drop the packet and 1034 * recycle the old buffer. 1035 */ 1036 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1037 MGETHDR(m, M_DONTWAIT, MT_DATA); 1038 if (m == NULL) 1039 goto dropit; 1040 m->m_data += 2; 1041 memcpy(mtod(m, caddr_t), 1042 mtod(ds->ds_mbuf, caddr_t), len); 1043 STE_INIT_RXDESC(sc, i); 1044 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1045 ds->ds_dmamap->dm_mapsize, 1046 BUS_DMASYNC_PREREAD); 1047 } else { 1048 m = ds->ds_mbuf; 1049 if (ste_add_rxbuf(sc, i) != 0) { 1050 dropit: 1051 ifp->if_ierrors++; 1052 STE_INIT_RXDESC(sc, i); 1053 bus_dmamap_sync(sc->sc_dmat, 1054 ds->ds_dmamap, 0, 1055 ds->ds_dmamap->dm_mapsize, 1056 BUS_DMASYNC_PREREAD); 1057 continue; 1058 } 1059 } 1060 1061 m->m_pkthdr.rcvif = ifp; 1062 m->m_pkthdr.len = m->m_len = len; 1063 1064 #if NBPFILTER > 0 1065 /* 1066 * Pass this up to any BPF listeners, but only 1067 * pass if up the stack if it's for us. 1068 */ 1069 if (ifp->if_bpf) 1070 bpf_mtap(ifp->if_bpf, m); 1071 #endif /* NBPFILTER > 0 */ 1072 1073 /* Pass it on. */ 1074 (*ifp->if_input)(ifp, m); 1075 } 1076 1077 /* Update the receive pointer. */ 1078 sc->sc_rxptr = i; 1079 } 1080 1081 /* 1082 * ste_tick: 1083 * 1084 * One second timer, used to tick the MII. 1085 */ 1086 static void 1087 ste_tick(void *arg) 1088 { 1089 struct ste_softc *sc = arg; 1090 int s; 1091 1092 s = splnet(); 1093 mii_tick(&sc->sc_mii); 1094 ste_stats_update(sc); 1095 splx(s); 1096 1097 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1098 } 1099 1100 /* 1101 * ste_stats_update: 1102 * 1103 * Read the ST-201 statistics counters. 1104 */ 1105 static void 1106 ste_stats_update(struct ste_softc *sc) 1107 { 1108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1109 bus_space_tag_t st = sc->sc_st; 1110 bus_space_handle_t sh = sc->sc_sh; 1111 1112 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1113 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1114 1115 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1116 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1117 1118 ifp->if_opackets += 1119 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1120 ifp->if_ipackets += 1121 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1122 1123 ifp->if_collisions += 1124 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1125 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1126 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1127 1128 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1129 1130 ifp->if_ierrors += 1131 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1132 1133 ifp->if_oerrors += 1134 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1135 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1136 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1137 1138 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1139 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1140 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1141 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1142 } 1143 1144 /* 1145 * ste_reset: 1146 * 1147 * Perform a soft reset on the ST-201. 1148 */ 1149 static void 1150 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1151 { 1152 uint32_t ac; 1153 int i; 1154 1155 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1156 1157 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1158 1159 delay(50000); 1160 1161 for (i = 0; i < STE_TIMEOUT; i++) { 1162 delay(1000); 1163 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1164 AC_ResetBusy) == 0) 1165 break; 1166 } 1167 1168 if (i == STE_TIMEOUT) 1169 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1170 1171 delay(1000); 1172 } 1173 1174 /* 1175 * ste_setthresh: 1176 * 1177 * set the various transmit threshold registers 1178 */ 1179 static void 1180 ste_setthresh(struct ste_softc *sc) 1181 { 1182 /* set the TX threhold */ 1183 bus_space_write_2(sc->sc_st, sc->sc_sh, 1184 STE_TxStartThresh, sc->sc_txthresh); 1185 /* Urgent threshold: set to sc_txthresh / 2 */ 1186 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1187 sc->sc_txthresh >> 6); 1188 /* Burst threshold: use default value (256 bytes) */ 1189 } 1190 1191 /* 1192 * restart TX at the given frame ID in the transmitter ring 1193 */ 1194 static void 1195 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1196 { 1197 u_int32_t control; 1198 1199 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1200 control = le32toh(sc->sc_txdescs[id].tfd_control); 1201 control &= ~TFD_TxDMAComplete; 1202 sc->sc_txdescs[id].tfd_control = htole32(control); 1203 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1204 1205 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1206 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1207 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1208 ste_dmahalt_wait(sc); 1209 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1210 STE_CDTXADDR(sc, id)); 1211 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1212 } 1213 1214 /* 1215 * ste_init: [ ifnet interface function ] 1216 * 1217 * Initialize the interface. Must be called at splnet(). 1218 */ 1219 static int 1220 ste_init(struct ifnet *ifp) 1221 { 1222 struct ste_softc *sc = ifp->if_softc; 1223 bus_space_tag_t st = sc->sc_st; 1224 bus_space_handle_t sh = sc->sc_sh; 1225 struct ste_descsoft *ds; 1226 int i, error = 0; 1227 1228 /* 1229 * Cancel any pending I/O. 1230 */ 1231 ste_stop(ifp, 0); 1232 1233 /* 1234 * Reset the chip to a known state. 1235 */ 1236 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1237 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1238 1239 /* 1240 * Initialize the transmit descriptor ring. 1241 */ 1242 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1243 sc->sc_txpending = 0; 1244 sc->sc_txdirty = 0; 1245 sc->sc_txlast = STE_NTXDESC - 1; 1246 1247 /* 1248 * Initialize the receive descriptor and receive job 1249 * descriptor rings. 1250 */ 1251 for (i = 0; i < STE_NRXDESC; i++) { 1252 ds = &sc->sc_rxsoft[i]; 1253 if (ds->ds_mbuf == NULL) { 1254 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1255 printf("%s: unable to allocate or map rx " 1256 "buffer %d, error = %d\n", 1257 sc->sc_dev.dv_xname, i, error); 1258 /* 1259 * XXX Should attempt to run with fewer receive 1260 * XXX buffers instead of just failing. 1261 */ 1262 ste_rxdrain(sc); 1263 goto out; 1264 } 1265 } else 1266 STE_INIT_RXDESC(sc, i); 1267 } 1268 sc->sc_rxptr = 0; 1269 1270 /* Set the station address. */ 1271 for (i = 0; i < ETHER_ADDR_LEN; i++) 1272 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1273 LLADDR(ifp->if_sadl)[i]); 1274 1275 /* Set up the receive filter. */ 1276 ste_set_filter(sc); 1277 1278 /* 1279 * Give the receive ring to the chip. 1280 */ 1281 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1282 STE_CDRXADDR(sc, sc->sc_rxptr)); 1283 1284 /* 1285 * We defer giving the transmit ring to the chip until we 1286 * transmit the first packet. 1287 */ 1288 1289 /* 1290 * Initialize the Tx auto-poll period. It's OK to make this number 1291 * large (127 is the max) -- we explicitly kick the transmit engine 1292 * when there's actually a packet. We are using auto-polling only 1293 * to make the interface to the transmit engine not suck. 1294 */ 1295 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1296 1297 /* ..and the Rx auto-poll period. */ 1298 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1299 1300 /* Initialize the Tx start threshold. */ 1301 ste_setthresh(sc); 1302 1303 /* Set the FIFO release threshold to 512 bytes. */ 1304 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1305 1306 /* Set maximum packet size for VLAN. */ 1307 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1308 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1309 else 1310 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1311 1312 /* 1313 * Initialize the interrupt mask. 1314 */ 1315 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1316 IE_TxDMAComplete | IE_RxDMAComplete; 1317 1318 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1319 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1320 1321 /* 1322 * Start the receive DMA engine. 1323 */ 1324 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1325 1326 /* 1327 * Initialize MacCtrl0 -- do it before setting the media, 1328 * as setting the media will actually program the register. 1329 */ 1330 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1331 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1332 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1333 1334 /* 1335 * Set the current media. 1336 */ 1337 mii_mediachg(&sc->sc_mii); 1338 1339 /* 1340 * Start the MAC. 1341 */ 1342 bus_space_write_2(st, sh, STE_MacCtrl1, 1343 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1344 1345 /* 1346 * Start the one second MII clock. 1347 */ 1348 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1349 1350 /* 1351 * ...all done! 1352 */ 1353 ifp->if_flags |= IFF_RUNNING; 1354 ifp->if_flags &= ~IFF_OACTIVE; 1355 1356 out: 1357 if (error) 1358 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1359 return (error); 1360 } 1361 1362 /* 1363 * ste_drain: 1364 * 1365 * Drain the receive queue. 1366 */ 1367 static void 1368 ste_rxdrain(struct ste_softc *sc) 1369 { 1370 struct ste_descsoft *ds; 1371 int i; 1372 1373 for (i = 0; i < STE_NRXDESC; i++) { 1374 ds = &sc->sc_rxsoft[i]; 1375 if (ds->ds_mbuf != NULL) { 1376 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1377 m_freem(ds->ds_mbuf); 1378 ds->ds_mbuf = NULL; 1379 } 1380 } 1381 } 1382 1383 /* 1384 * ste_stop: [ ifnet interface function ] 1385 * 1386 * Stop transmission on the interface. 1387 */ 1388 static void 1389 ste_stop(struct ifnet *ifp, int disable) 1390 { 1391 struct ste_softc *sc = ifp->if_softc; 1392 struct ste_descsoft *ds; 1393 int i; 1394 1395 /* 1396 * Stop the one second clock. 1397 */ 1398 callout_stop(&sc->sc_tick_ch); 1399 1400 /* Down the MII. */ 1401 mii_down(&sc->sc_mii); 1402 1403 /* 1404 * Disable interrupts. 1405 */ 1406 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1407 1408 /* 1409 * Stop receiver, transmitter, and stats update. 1410 */ 1411 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1412 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1413 1414 /* 1415 * Stop the transmit and receive DMA. 1416 */ 1417 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1418 DC_RxDMAHalt | DC_TxDMAHalt); 1419 ste_dmahalt_wait(sc); 1420 1421 /* 1422 * Release any queued transmit buffers. 1423 */ 1424 for (i = 0; i < STE_NTXDESC; i++) { 1425 ds = &sc->sc_txsoft[i]; 1426 if (ds->ds_mbuf != NULL) { 1427 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1428 m_freem(ds->ds_mbuf); 1429 ds->ds_mbuf = NULL; 1430 } 1431 } 1432 1433 if (disable) 1434 ste_rxdrain(sc); 1435 1436 /* 1437 * Mark the interface down and cancel the watchdog timer. 1438 */ 1439 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1440 ifp->if_timer = 0; 1441 } 1442 1443 static int 1444 ste_eeprom_wait(struct ste_softc *sc) 1445 { 1446 int i; 1447 1448 for (i = 0; i < STE_TIMEOUT; i++) { 1449 delay(1000); 1450 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1451 EC_EepromBusy) == 0) 1452 return (0); 1453 } 1454 return (1); 1455 } 1456 1457 /* 1458 * ste_read_eeprom: 1459 * 1460 * Read data from the serial EEPROM. 1461 */ 1462 static void 1463 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1464 { 1465 1466 if (ste_eeprom_wait(sc)) 1467 printf("%s: EEPROM failed to come ready\n", 1468 sc->sc_dev.dv_xname); 1469 1470 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1471 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1472 if (ste_eeprom_wait(sc)) 1473 printf("%s: EEPROM read timed out\n", 1474 sc->sc_dev.dv_xname); 1475 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1476 } 1477 1478 /* 1479 * ste_add_rxbuf: 1480 * 1481 * Add a receive buffer to the indicated descriptor. 1482 */ 1483 static int 1484 ste_add_rxbuf(struct ste_softc *sc, int idx) 1485 { 1486 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1487 struct mbuf *m; 1488 int error; 1489 1490 MGETHDR(m, M_DONTWAIT, MT_DATA); 1491 if (m == NULL) 1492 return (ENOBUFS); 1493 1494 MCLGET(m, M_DONTWAIT); 1495 if ((m->m_flags & M_EXT) == 0) { 1496 m_freem(m); 1497 return (ENOBUFS); 1498 } 1499 1500 if (ds->ds_mbuf != NULL) 1501 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1502 1503 ds->ds_mbuf = m; 1504 1505 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1506 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1507 BUS_DMA_READ|BUS_DMA_NOWAIT); 1508 if (error) { 1509 printf("%s: can't load rx DMA map %d, error = %d\n", 1510 sc->sc_dev.dv_xname, idx, error); 1511 panic("ste_add_rxbuf"); /* XXX */ 1512 } 1513 1514 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1515 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1516 1517 STE_INIT_RXDESC(sc, idx); 1518 1519 return (0); 1520 } 1521 1522 /* 1523 * ste_set_filter: 1524 * 1525 * Set up the receive filter. 1526 */ 1527 static void 1528 ste_set_filter(struct ste_softc *sc) 1529 { 1530 struct ethercom *ec = &sc->sc_ethercom; 1531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1532 struct ether_multi *enm; 1533 struct ether_multistep step; 1534 uint32_t crc; 1535 uint16_t mchash[4]; 1536 1537 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1538 if (ifp->if_flags & IFF_BROADCAST) 1539 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1540 1541 if (ifp->if_flags & IFF_PROMISC) { 1542 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1543 goto allmulti; 1544 } 1545 1546 /* 1547 * Set up the multicast address filter by passing all multicast 1548 * addresses through a CRC generator, and then using the low-order 1549 * 6 bits as an index into the 64 bit multicast hash table. The 1550 * high order bits select the register, while the rest of the bits 1551 * select the bit within the register. 1552 */ 1553 1554 memset(mchash, 0, sizeof(mchash)); 1555 1556 ETHER_FIRST_MULTI(step, ec, enm); 1557 if (enm == NULL) 1558 goto done; 1559 1560 while (enm != NULL) { 1561 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1562 /* 1563 * We must listen to a range of multicast addresses. 1564 * For now, just accept all multicasts, rather than 1565 * trying to set only those filter bits needed to match 1566 * the range. (At this time, the only use of address 1567 * ranges is for IP multicast routing, for which the 1568 * range is big enough to require all bits set.) 1569 */ 1570 goto allmulti; 1571 } 1572 1573 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1574 1575 /* Just want the 6 least significant bits. */ 1576 crc &= 0x3f; 1577 1578 /* Set the corresponding bit in the hash table. */ 1579 mchash[crc >> 4] |= 1 << (crc & 0xf); 1580 1581 ETHER_NEXT_MULTI(step, enm); 1582 } 1583 1584 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1585 1586 ifp->if_flags &= ~IFF_ALLMULTI; 1587 goto done; 1588 1589 allmulti: 1590 ifp->if_flags |= IFF_ALLMULTI; 1591 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1592 1593 done: 1594 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1595 /* 1596 * Program the multicast hash table. 1597 */ 1598 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1599 mchash[0]); 1600 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1601 mchash[1]); 1602 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1603 mchash[2]); 1604 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1605 mchash[3]); 1606 } 1607 1608 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1609 sc->sc_ReceiveMode); 1610 } 1611 1612 /* 1613 * ste_mii_readreg: [mii interface function] 1614 * 1615 * Read a PHY register on the MII of the ST-201. 1616 */ 1617 static int 1618 ste_mii_readreg(struct device *self, int phy, int reg) 1619 { 1620 1621 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1622 } 1623 1624 /* 1625 * ste_mii_writereg: [mii interface function] 1626 * 1627 * Write a PHY register on the MII of the ST-201. 1628 */ 1629 static void 1630 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1631 { 1632 1633 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1634 } 1635 1636 /* 1637 * ste_mii_statchg: [mii interface function] 1638 * 1639 * Callback from MII layer when media changes. 1640 */ 1641 static void 1642 ste_mii_statchg(struct device *self) 1643 { 1644 struct ste_softc *sc = (struct ste_softc *) self; 1645 1646 if (sc->sc_mii.mii_media_active & IFM_FDX) 1647 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1648 else 1649 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1650 1651 /* XXX 802.1x flow-control? */ 1652 1653 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1654 } 1655 1656 /* 1657 * ste_mii_bitbang_read: [mii bit-bang interface function] 1658 * 1659 * Read the MII serial port for the MII bit-bang module. 1660 */ 1661 static uint32_t 1662 ste_mii_bitbang_read(struct device *self) 1663 { 1664 struct ste_softc *sc = (void *) self; 1665 1666 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1667 } 1668 1669 /* 1670 * ste_mii_bitbang_write: [mii big-bang interface function] 1671 * 1672 * Write the MII serial port for the MII bit-bang module. 1673 */ 1674 static void 1675 ste_mii_bitbang_write(struct device *self, uint32_t val) 1676 { 1677 struct ste_softc *sc = (void *) self; 1678 1679 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1680 } 1681 1682 /* 1683 * ste_mediastatus: [ifmedia interface function] 1684 * 1685 * Get the current interface media status. 1686 */ 1687 static void 1688 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1689 { 1690 struct ste_softc *sc = ifp->if_softc; 1691 1692 mii_pollstat(&sc->sc_mii); 1693 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1694 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1695 } 1696 1697 /* 1698 * ste_mediachange: [ifmedia interface function] 1699 * 1700 * Set hardware to newly-selected media. 1701 */ 1702 static int 1703 ste_mediachange(struct ifnet *ifp) 1704 { 1705 struct ste_softc *sc = ifp->if_softc; 1706 1707 if (ifp->if_flags & IFF_UP) 1708 mii_mediachg(&sc->sc_mii); 1709 return (0); 1710 } 1711