1 /* $NetBSD: if_ste.c,v 1.36 2008/04/28 20:23:55 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.36 2008/04/28 20:23:55 martin Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/mii/mii_bitbang.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_stereg.h> 77 78 /* 79 * Transmit descriptor list size. 80 */ 81 #define STE_NTXDESC 256 82 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 83 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 84 85 /* 86 * Receive descriptor list size. 87 */ 88 #define STE_NRXDESC 128 89 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 90 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 91 92 /* 93 * Control structures are DMA'd to the ST-201 chip. We allocate them in 94 * a single clump that maps to a single DMA segment to make several things 95 * easier. 96 */ 97 struct ste_control_data { 98 /* 99 * The transmit descriptors. 100 */ 101 struct ste_tfd scd_txdescs[STE_NTXDESC]; 102 103 /* 104 * The receive descriptors. 105 */ 106 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 107 }; 108 109 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 110 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 111 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 112 113 /* 114 * Software state for transmit and receive jobs. 115 */ 116 struct ste_descsoft { 117 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t ds_dmamap; /* our DMA map */ 119 }; 120 121 /* 122 * Software state per device. 123 */ 124 struct ste_softc { 125 struct device sc_dev; /* generic device information */ 126 bus_space_tag_t sc_st; /* bus space tag */ 127 bus_space_handle_t sc_sh; /* bus space handle */ 128 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 129 struct ethercom sc_ethercom; /* ethernet common data */ 130 void *sc_sdhook; /* shutdown hook */ 131 132 void *sc_ih; /* interrupt cookie */ 133 134 struct mii_data sc_mii; /* MII/media information */ 135 136 callout_t sc_tick_ch; /* tick callout */ 137 138 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 139 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 140 141 /* 142 * Software state for transmit and receive descriptors. 143 */ 144 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 145 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 146 147 /* 148 * Control data structures. 149 */ 150 struct ste_control_data *sc_control_data; 151 #define sc_txdescs sc_control_data->scd_txdescs 152 #define sc_rxdescs sc_control_data->scd_rxdescs 153 154 int sc_txpending; /* number of Tx requests pending */ 155 int sc_txdirty; /* first dirty Tx descriptor */ 156 int sc_txlast; /* last used Tx descriptor */ 157 158 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 159 160 int sc_txthresh; /* Tx threshold */ 161 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 162 uint16_t sc_IntEnable; /* prototype IntEnable register */ 163 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 164 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 165 }; 166 167 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 168 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 169 170 #define STE_CDTXSYNC(sc, x, ops) \ 171 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 172 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 173 174 #define STE_CDRXSYNC(sc, x, ops) \ 175 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 176 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 177 178 #define STE_INIT_RXDESC(sc, x) \ 179 do { \ 180 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 181 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 182 struct mbuf *__m = __ds->ds_mbuf; \ 183 \ 184 /* \ 185 * Note: We scoot the packet forward 2 bytes in the buffer \ 186 * so that the payload after the Ethernet header is aligned \ 187 * to a 4-byte boundary. \ 188 */ \ 189 __m->m_data = __m->m_ext.ext_buf + 2; \ 190 __rfd->rfd_frag.frag_addr = \ 191 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 192 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 193 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 194 __rfd->rfd_status = 0; \ 195 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 196 } while (/*CONSTCOND*/0) 197 198 #define STE_TIMEOUT 1000 199 200 static void ste_start(struct ifnet *); 201 static void ste_watchdog(struct ifnet *); 202 static int ste_ioctl(struct ifnet *, u_long, void *); 203 static int ste_init(struct ifnet *); 204 static void ste_stop(struct ifnet *, int); 205 206 static void ste_shutdown(void *); 207 208 static void ste_reset(struct ste_softc *, u_int32_t); 209 static void ste_setthresh(struct ste_softc *); 210 static void ste_txrestart(struct ste_softc *, u_int8_t); 211 static void ste_rxdrain(struct ste_softc *); 212 static int ste_add_rxbuf(struct ste_softc *, int); 213 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 214 static void ste_tick(void *); 215 216 static void ste_stats_update(struct ste_softc *); 217 218 static void ste_set_filter(struct ste_softc *); 219 220 static int ste_intr(void *); 221 static void ste_txintr(struct ste_softc *); 222 static void ste_rxintr(struct ste_softc *); 223 224 static int ste_mii_readreg(device_t, int, int); 225 static void ste_mii_writereg(device_t, int, int, int); 226 static void ste_mii_statchg(device_t); 227 228 static int ste_match(device_t, struct cfdata *, void *); 229 static void ste_attach(device_t, device_t, void *); 230 231 int ste_copy_small = 0; 232 233 CFATTACH_DECL(ste, sizeof(struct ste_softc), 234 ste_match, ste_attach, NULL, NULL); 235 236 static uint32_t ste_mii_bitbang_read(device_t); 237 static void ste_mii_bitbang_write(device_t, uint32_t); 238 239 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 240 ste_mii_bitbang_read, 241 ste_mii_bitbang_write, 242 { 243 PC_MgmtData, /* MII_BIT_MDO */ 244 PC_MgmtData, /* MII_BIT_MDI */ 245 PC_MgmtClk, /* MII_BIT_MDC */ 246 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 247 0, /* MII_BIT_DIR_PHY_HOST */ 248 } 249 }; 250 251 /* 252 * Devices supported by this driver. 253 */ 254 static const struct ste_product { 255 pci_vendor_id_t ste_vendor; 256 pci_product_id_t ste_product; 257 const char *ste_name; 258 } ste_products[] = { 259 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 260 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 261 262 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 263 "Sundance ST-201 10/100 Ethernet" }, 264 265 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 266 "D-Link DL-1002 10/100 Ethernet" }, 267 268 { 0, 0, 269 NULL }, 270 }; 271 272 static const struct ste_product * 273 ste_lookup(const struct pci_attach_args *pa) 274 { 275 const struct ste_product *sp; 276 277 for (sp = ste_products; sp->ste_name != NULL; sp++) { 278 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 279 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 280 return (sp); 281 } 282 return (NULL); 283 } 284 285 static int 286 ste_match(device_t parent, struct cfdata *cf, void *aux) 287 { 288 struct pci_attach_args *pa = aux; 289 290 if (ste_lookup(pa) != NULL) 291 return (1); 292 293 return (0); 294 } 295 296 static void 297 ste_attach(device_t parent, device_t self, void *aux) 298 { 299 struct ste_softc *sc = device_private(self); 300 struct pci_attach_args *pa = aux; 301 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 302 pci_chipset_tag_t pc = pa->pa_pc; 303 pci_intr_handle_t ih; 304 const char *intrstr = NULL; 305 bus_space_tag_t iot, memt; 306 bus_space_handle_t ioh, memh; 307 bus_dma_segment_t seg; 308 int ioh_valid, memh_valid; 309 int i, rseg, error; 310 const struct ste_product *sp; 311 uint8_t enaddr[ETHER_ADDR_LEN]; 312 uint16_t myea[ETHER_ADDR_LEN / 2]; 313 314 callout_init(&sc->sc_tick_ch, 0); 315 316 sp = ste_lookup(pa); 317 if (sp == NULL) { 318 printf("\n"); 319 panic("ste_attach: impossible"); 320 } 321 322 printf(": %s\n", sp->ste_name); 323 324 /* 325 * Map the device. 326 */ 327 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 328 PCI_MAPREG_TYPE_IO, 0, 329 &iot, &ioh, NULL, NULL) == 0); 330 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 331 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 332 &memt, &memh, NULL, NULL) == 0); 333 334 if (memh_valid) { 335 sc->sc_st = memt; 336 sc->sc_sh = memh; 337 } else if (ioh_valid) { 338 sc->sc_st = iot; 339 sc->sc_sh = ioh; 340 } else { 341 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 342 return; 343 } 344 345 sc->sc_dmat = pa->pa_dmat; 346 347 /* Enable bus mastering. */ 348 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 349 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 350 PCI_COMMAND_MASTER_ENABLE); 351 352 /* power up chip */ 353 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 354 NULL)) && error != EOPNOTSUPP) { 355 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 356 error); 357 return; 358 } 359 360 /* 361 * Map and establish our interrupt. 362 */ 363 if (pci_intr_map(pa, &ih)) { 364 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 365 return; 366 } 367 intrstr = pci_intr_string(pc, ih); 368 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 369 if (sc->sc_ih == NULL) { 370 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 371 if (intrstr != NULL) 372 printf(" at %s", intrstr); 373 printf("\n"); 374 return; 375 } 376 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 377 378 /* 379 * Allocate the control data structures, and create and load the 380 * DMA map for it. 381 */ 382 if ((error = bus_dmamem_alloc(sc->sc_dmat, 383 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 384 0)) != 0) { 385 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 386 error); 387 goto fail_0; 388 } 389 390 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 391 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 392 BUS_DMA_COHERENT)) != 0) { 393 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 394 error); 395 goto fail_1; 396 } 397 398 if ((error = bus_dmamap_create(sc->sc_dmat, 399 sizeof(struct ste_control_data), 1, 400 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 401 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 402 "error = %d\n", error); 403 goto fail_2; 404 } 405 406 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 407 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 408 0)) != 0) { 409 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 410 error); 411 goto fail_3; 412 } 413 414 /* 415 * Create the transmit buffer DMA maps. 416 */ 417 for (i = 0; i < STE_NTXDESC; i++) { 418 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 419 STE_NTXFRAGS, MCLBYTES, 0, 0, 420 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 421 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 422 "error = %d\n", i, error); 423 goto fail_4; 424 } 425 } 426 427 /* 428 * Create the receive buffer DMA maps. 429 */ 430 for (i = 0; i < STE_NRXDESC; i++) { 431 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 432 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 433 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 434 "error = %d\n", i, error); 435 goto fail_5; 436 } 437 sc->sc_rxsoft[i].ds_mbuf = NULL; 438 } 439 440 /* 441 * Reset the chip to a known state. 442 */ 443 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 444 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 445 446 /* 447 * Read the Ethernet address from the EEPROM. 448 */ 449 for (i = 0; i < 3; i++) { 450 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 451 myea[i] = le16toh(myea[i]); 452 } 453 memcpy(enaddr, myea, sizeof(enaddr)); 454 455 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 456 ether_sprintf(enaddr)); 457 458 /* 459 * Initialize our media structures and probe the MII. 460 */ 461 sc->sc_mii.mii_ifp = ifp; 462 sc->sc_mii.mii_readreg = ste_mii_readreg; 463 sc->sc_mii.mii_writereg = ste_mii_writereg; 464 sc->sc_mii.mii_statchg = ste_mii_statchg; 465 sc->sc_ethercom.ec_mii = &sc->sc_mii; 466 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 467 ether_mediastatus); 468 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 469 MII_OFFSET_ANY, 0); 470 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 471 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 472 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 473 } else 474 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 475 476 ifp = &sc->sc_ethercom.ec_if; 477 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 478 ifp->if_softc = sc; 479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 480 ifp->if_ioctl = ste_ioctl; 481 ifp->if_start = ste_start; 482 ifp->if_watchdog = ste_watchdog; 483 ifp->if_init = ste_init; 484 ifp->if_stop = ste_stop; 485 IFQ_SET_READY(&ifp->if_snd); 486 487 /* 488 * Default the transmit threshold to 128 bytes. 489 */ 490 sc->sc_txthresh = 128; 491 492 /* 493 * Disable MWI if the PCI layer tells us to. 494 */ 495 sc->sc_DMACtrl = 0; 496 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 497 sc->sc_DMACtrl |= DC_MWIDisable; 498 499 /* 500 * We can support 802.1Q VLAN-sized frames. 501 */ 502 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 503 504 /* 505 * Attach the interface. 506 */ 507 if_attach(ifp); 508 ether_ifattach(ifp, enaddr); 509 510 /* 511 * Make sure the interface is shutdown during reboot. 512 */ 513 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 514 if (sc->sc_sdhook == NULL) 515 printf("%s: WARNING: unable to establish shutdown hook\n", 516 device_xname(&sc->sc_dev)); 517 return; 518 519 /* 520 * Free any resources we've allocated during the failed attach 521 * attempt. Do this in reverse order and fall through. 522 */ 523 fail_5: 524 for (i = 0; i < STE_NRXDESC; i++) { 525 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 526 bus_dmamap_destroy(sc->sc_dmat, 527 sc->sc_rxsoft[i].ds_dmamap); 528 } 529 fail_4: 530 for (i = 0; i < STE_NTXDESC; i++) { 531 if (sc->sc_txsoft[i].ds_dmamap != NULL) 532 bus_dmamap_destroy(sc->sc_dmat, 533 sc->sc_txsoft[i].ds_dmamap); 534 } 535 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 536 fail_3: 537 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 538 fail_2: 539 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 540 sizeof(struct ste_control_data)); 541 fail_1: 542 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 543 fail_0: 544 return; 545 } 546 547 /* 548 * ste_shutdown: 549 * 550 * Make sure the interface is stopped at reboot time. 551 */ 552 static void 553 ste_shutdown(void *arg) 554 { 555 struct ste_softc *sc = arg; 556 557 ste_stop(&sc->sc_ethercom.ec_if, 1); 558 } 559 560 static void 561 ste_dmahalt_wait(struct ste_softc *sc) 562 { 563 int i; 564 565 for (i = 0; i < STE_TIMEOUT; i++) { 566 delay(2); 567 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 568 DC_DMAHaltBusy) == 0) 569 break; 570 } 571 572 if (i == STE_TIMEOUT) 573 printf("%s: DMA halt timed out\n", device_xname(&sc->sc_dev)); 574 } 575 576 /* 577 * ste_start: [ifnet interface function] 578 * 579 * Start packet transmission on the interface. 580 */ 581 static void 582 ste_start(struct ifnet *ifp) 583 { 584 struct ste_softc *sc = ifp->if_softc; 585 struct mbuf *m0, *m; 586 struct ste_descsoft *ds; 587 struct ste_tfd *tfd; 588 bus_dmamap_t dmamap; 589 int error, olasttx, nexttx, opending, seg, totlen; 590 591 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 592 return; 593 594 /* 595 * Remember the previous number of pending transmissions 596 * and the current last descriptor in the list. 597 */ 598 opending = sc->sc_txpending; 599 olasttx = sc->sc_txlast; 600 601 /* 602 * Loop through the send queue, setting up transmit descriptors 603 * until we drain the queue, or use up all available transmit 604 * descriptors. 605 */ 606 while (sc->sc_txpending < STE_NTXDESC) { 607 /* 608 * Grab a packet off the queue. 609 */ 610 IFQ_POLL(&ifp->if_snd, m0); 611 if (m0 == NULL) 612 break; 613 m = NULL; 614 615 /* 616 * Get the last and next available transmit descriptor. 617 */ 618 nexttx = STE_NEXTTX(sc->sc_txlast); 619 tfd = &sc->sc_txdescs[nexttx]; 620 ds = &sc->sc_txsoft[nexttx]; 621 622 dmamap = ds->ds_dmamap; 623 624 /* 625 * Load the DMA map. If this fails, the packet either 626 * didn't fit in the alloted number of segments, or we 627 * were short on resources. In this case, we'll copy 628 * and try again. 629 */ 630 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 631 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 632 MGETHDR(m, M_DONTWAIT, MT_DATA); 633 if (m == NULL) { 634 printf("%s: unable to allocate Tx mbuf\n", 635 device_xname(&sc->sc_dev)); 636 break; 637 } 638 if (m0->m_pkthdr.len > MHLEN) { 639 MCLGET(m, M_DONTWAIT); 640 if ((m->m_flags & M_EXT) == 0) { 641 printf("%s: unable to allocate Tx " 642 "cluster\n", device_xname(&sc->sc_dev)); 643 m_freem(m); 644 break; 645 } 646 } 647 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 648 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 649 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 650 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 651 if (error) { 652 printf("%s: unable to load Tx buffer, " 653 "error = %d\n", device_xname(&sc->sc_dev), error); 654 break; 655 } 656 } 657 658 IFQ_DEQUEUE(&ifp->if_snd, m0); 659 if (m != NULL) { 660 m_freem(m0); 661 m0 = m; 662 } 663 664 /* 665 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 666 */ 667 668 /* Sync the DMA map. */ 669 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 /* Initialize the fragment list. */ 673 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 674 tfd->tfd_frags[seg].frag_addr = 675 htole32(dmamap->dm_segs[seg].ds_addr); 676 tfd->tfd_frags[seg].frag_len = 677 htole32(dmamap->dm_segs[seg].ds_len); 678 totlen += dmamap->dm_segs[seg].ds_len; 679 } 680 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 681 682 /* Initialize the descriptor. */ 683 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 684 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 685 686 /* Sync the descriptor. */ 687 STE_CDTXSYNC(sc, nexttx, 688 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 689 690 /* 691 * Store a pointer to the packet so we can free it later, 692 * and remember what txdirty will be once the packet is 693 * done. 694 */ 695 ds->ds_mbuf = m0; 696 697 /* Advance the tx pointer. */ 698 sc->sc_txpending++; 699 sc->sc_txlast = nexttx; 700 701 #if NBPFILTER > 0 702 /* 703 * Pass the packet to any BPF listeners. 704 */ 705 if (ifp->if_bpf) 706 bpf_mtap(ifp->if_bpf, m0); 707 #endif /* NBPFILTER > 0 */ 708 } 709 710 if (sc->sc_txpending == STE_NTXDESC) { 711 /* No more slots left; notify upper layer. */ 712 ifp->if_flags |= IFF_OACTIVE; 713 } 714 715 if (sc->sc_txpending != opending) { 716 /* 717 * We enqueued packets. If the transmitter was idle, 718 * reset the txdirty pointer. 719 */ 720 if (opending == 0) 721 sc->sc_txdirty = STE_NEXTTX(olasttx); 722 723 /* 724 * Cause a descriptor interrupt to happen on the 725 * last packet we enqueued, and also cause the 726 * DMA engine to wait after is has finished processing 727 * it. 728 */ 729 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 730 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 731 htole32(TFD_TxDMAIndicate); 732 STE_CDTXSYNC(sc, sc->sc_txlast, 733 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 734 735 /* 736 * Link up the new chain of descriptors to the 737 * last. 738 */ 739 sc->sc_txdescs[olasttx].tfd_next = 740 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 741 STE_CDTXSYNC(sc, olasttx, 742 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 743 744 /* 745 * Kick the transmit DMA logic. Note that since we're 746 * using auto-polling, reading the Tx desc pointer will 747 * give it the nudge it needs to get going. 748 */ 749 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 750 STE_TxDMAListPtr) == 0) { 751 bus_space_write_4(sc->sc_st, sc->sc_sh, 752 STE_DMACtrl, DC_TxDMAHalt); 753 ste_dmahalt_wait(sc); 754 bus_space_write_4(sc->sc_st, sc->sc_sh, 755 STE_TxDMAListPtr, 756 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 757 bus_space_write_4(sc->sc_st, sc->sc_sh, 758 STE_DMACtrl, DC_TxDMAResume); 759 } 760 761 /* Set a watchdog timer in case the chip flakes out. */ 762 ifp->if_timer = 5; 763 } 764 } 765 766 /* 767 * ste_watchdog: [ifnet interface function] 768 * 769 * Watchdog timer handler. 770 */ 771 static void 772 ste_watchdog(struct ifnet *ifp) 773 { 774 struct ste_softc *sc = ifp->if_softc; 775 776 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 777 ifp->if_oerrors++; 778 779 ste_txintr(sc); 780 ste_rxintr(sc); 781 (void) ste_init(ifp); 782 783 /* Try to get more packets going. */ 784 ste_start(ifp); 785 } 786 787 /* 788 * ste_ioctl: [ifnet interface function] 789 * 790 * Handle control requests from the operator. 791 */ 792 static int 793 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 794 { 795 struct ste_softc *sc = ifp->if_softc; 796 int s, error; 797 798 s = splnet(); 799 800 error = ether_ioctl(ifp, cmd, data); 801 if (error == ENETRESET) { 802 /* 803 * Multicast list has changed; set the hardware filter 804 * accordingly. 805 */ 806 if (ifp->if_flags & IFF_RUNNING) 807 ste_set_filter(sc); 808 error = 0; 809 } 810 811 /* Try to get more packets going. */ 812 ste_start(ifp); 813 814 splx(s); 815 return (error); 816 } 817 818 /* 819 * ste_intr: 820 * 821 * Interrupt service routine. 822 */ 823 static int 824 ste_intr(void *arg) 825 { 826 struct ste_softc *sc = arg; 827 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 828 uint16_t isr; 829 uint8_t txstat; 830 int wantinit; 831 832 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 833 IS_InterruptStatus) == 0) 834 return (0); 835 836 for (wantinit = 0; wantinit == 0;) { 837 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 838 if ((isr & sc->sc_IntEnable) == 0) 839 break; 840 841 /* Receive interrupts. */ 842 if (isr & IE_RxDMAComplete) 843 ste_rxintr(sc); 844 845 /* Transmit interrupts. */ 846 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 847 ste_txintr(sc); 848 849 /* Statistics overflow. */ 850 if (isr & IE_UpdateStats) 851 ste_stats_update(sc); 852 853 /* Transmission errors. */ 854 if (isr & IE_TxComplete) { 855 for (;;) { 856 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 857 STE_TxStatus); 858 if ((txstat & TS_TxComplete) == 0) 859 break; 860 if (txstat & TS_TxUnderrun) { 861 sc->sc_txthresh += 32; 862 if (sc->sc_txthresh > 0x1ffc) 863 sc->sc_txthresh = 0x1ffc; 864 printf("%s: transmit underrun, new " 865 "threshold: %d bytes\n", 866 device_xname(&sc->sc_dev), 867 sc->sc_txthresh); 868 ste_reset(sc, AC_TxReset | AC_DMA | 869 AC_FIFO | AC_Network); 870 ste_setthresh(sc); 871 bus_space_write_1(sc->sc_st, sc->sc_sh, 872 STE_TxDMAPollPeriod, 127); 873 ste_txrestart(sc, 874 bus_space_read_1(sc->sc_st, 875 sc->sc_sh, STE_TxFrameId)); 876 } 877 if (txstat & TS_TxReleaseError) { 878 printf("%s: Tx FIFO release error\n", 879 device_xname(&sc->sc_dev)); 880 wantinit = 1; 881 } 882 if (txstat & TS_MaxCollisions) { 883 printf("%s: excessive collisions\n", 884 device_xname(&sc->sc_dev)); 885 wantinit = 1; 886 } 887 if (txstat & TS_TxStatusOverflow) { 888 printf("%s: status overflow\n", 889 device_xname(&sc->sc_dev)); 890 wantinit = 1; 891 } 892 bus_space_write_2(sc->sc_st, sc->sc_sh, 893 STE_TxStatus, 0); 894 } 895 } 896 897 /* Host interface errors. */ 898 if (isr & IE_HostError) { 899 printf("%s: Host interface error\n", 900 device_xname(&sc->sc_dev)); 901 wantinit = 1; 902 } 903 } 904 905 if (wantinit) 906 ste_init(ifp); 907 908 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 909 sc->sc_IntEnable); 910 911 /* Try to get more packets going. */ 912 ste_start(ifp); 913 914 return (1); 915 } 916 917 /* 918 * ste_txintr: 919 * 920 * Helper; handle transmit interrupts. 921 */ 922 static void 923 ste_txintr(struct ste_softc *sc) 924 { 925 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 926 struct ste_descsoft *ds; 927 uint32_t control; 928 int i; 929 930 ifp->if_flags &= ~IFF_OACTIVE; 931 932 /* 933 * Go through our Tx list and free mbufs for those 934 * frames which have been transmitted. 935 */ 936 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 937 i = STE_NEXTTX(i), sc->sc_txpending--) { 938 ds = &sc->sc_txsoft[i]; 939 940 STE_CDTXSYNC(sc, i, 941 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 942 943 control = le32toh(sc->sc_txdescs[i].tfd_control); 944 if ((control & TFD_TxDMAComplete) == 0) 945 break; 946 947 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 948 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 949 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 950 m_freem(ds->ds_mbuf); 951 ds->ds_mbuf = NULL; 952 } 953 954 /* Update the dirty transmit buffer pointer. */ 955 sc->sc_txdirty = i; 956 957 /* 958 * If there are no more pending transmissions, cancel the watchdog 959 * timer. 960 */ 961 if (sc->sc_txpending == 0) 962 ifp->if_timer = 0; 963 } 964 965 /* 966 * ste_rxintr: 967 * 968 * Helper; handle receive interrupts. 969 */ 970 static void 971 ste_rxintr(struct ste_softc *sc) 972 { 973 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 974 struct ste_descsoft *ds; 975 struct mbuf *m; 976 uint32_t status; 977 int i, len; 978 979 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 980 ds = &sc->sc_rxsoft[i]; 981 982 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 983 984 status = le32toh(sc->sc_rxdescs[i].rfd_status); 985 986 if ((status & RFD_RxDMAComplete) == 0) 987 break; 988 989 /* 990 * If the packet had an error, simply recycle the 991 * buffer. Note, we count the error later in the 992 * periodic stats update. 993 */ 994 if (status & RFD_RxFrameError) { 995 STE_INIT_RXDESC(sc, i); 996 continue; 997 } 998 999 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1000 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1001 1002 /* 1003 * No errors; receive the packet. Note, we have 1004 * configured the chip to not include the CRC at 1005 * the end of the packet. 1006 */ 1007 len = RFD_RxDMAFrameLen(status); 1008 1009 /* 1010 * If the packet is small enough to fit in a 1011 * single header mbuf, allocate one and copy 1012 * the data into it. This greatly reduces 1013 * memory consumption when we receive lots 1014 * of small packets. 1015 * 1016 * Otherwise, we add a new buffer to the receive 1017 * chain. If this fails, we drop the packet and 1018 * recycle the old buffer. 1019 */ 1020 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1021 MGETHDR(m, M_DONTWAIT, MT_DATA); 1022 if (m == NULL) 1023 goto dropit; 1024 m->m_data += 2; 1025 memcpy(mtod(m, void *), 1026 mtod(ds->ds_mbuf, void *), len); 1027 STE_INIT_RXDESC(sc, i); 1028 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1029 ds->ds_dmamap->dm_mapsize, 1030 BUS_DMASYNC_PREREAD); 1031 } else { 1032 m = ds->ds_mbuf; 1033 if (ste_add_rxbuf(sc, i) != 0) { 1034 dropit: 1035 ifp->if_ierrors++; 1036 STE_INIT_RXDESC(sc, i); 1037 bus_dmamap_sync(sc->sc_dmat, 1038 ds->ds_dmamap, 0, 1039 ds->ds_dmamap->dm_mapsize, 1040 BUS_DMASYNC_PREREAD); 1041 continue; 1042 } 1043 } 1044 1045 m->m_pkthdr.rcvif = ifp; 1046 m->m_pkthdr.len = m->m_len = len; 1047 1048 #if NBPFILTER > 0 1049 /* 1050 * Pass this up to any BPF listeners, but only 1051 * pass if up the stack if it's for us. 1052 */ 1053 if (ifp->if_bpf) 1054 bpf_mtap(ifp->if_bpf, m); 1055 #endif /* NBPFILTER > 0 */ 1056 1057 /* Pass it on. */ 1058 (*ifp->if_input)(ifp, m); 1059 } 1060 1061 /* Update the receive pointer. */ 1062 sc->sc_rxptr = i; 1063 } 1064 1065 /* 1066 * ste_tick: 1067 * 1068 * One second timer, used to tick the MII. 1069 */ 1070 static void 1071 ste_tick(void *arg) 1072 { 1073 struct ste_softc *sc = arg; 1074 int s; 1075 1076 s = splnet(); 1077 mii_tick(&sc->sc_mii); 1078 ste_stats_update(sc); 1079 splx(s); 1080 1081 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1082 } 1083 1084 /* 1085 * ste_stats_update: 1086 * 1087 * Read the ST-201 statistics counters. 1088 */ 1089 static void 1090 ste_stats_update(struct ste_softc *sc) 1091 { 1092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1093 bus_space_tag_t st = sc->sc_st; 1094 bus_space_handle_t sh = sc->sc_sh; 1095 1096 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1097 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1098 1099 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1100 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1101 1102 ifp->if_opackets += 1103 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1104 ifp->if_ipackets += 1105 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1106 1107 ifp->if_collisions += 1108 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1109 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1110 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1111 1112 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1113 1114 ifp->if_ierrors += 1115 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1116 1117 ifp->if_oerrors += 1118 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1119 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1120 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1121 1122 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1123 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1124 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1125 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1126 } 1127 1128 /* 1129 * ste_reset: 1130 * 1131 * Perform a soft reset on the ST-201. 1132 */ 1133 static void 1134 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1135 { 1136 uint32_t ac; 1137 int i; 1138 1139 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1140 1141 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1142 1143 delay(50000); 1144 1145 for (i = 0; i < STE_TIMEOUT; i++) { 1146 delay(1000); 1147 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1148 AC_ResetBusy) == 0) 1149 break; 1150 } 1151 1152 if (i == STE_TIMEOUT) 1153 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1154 1155 delay(1000); 1156 } 1157 1158 /* 1159 * ste_setthresh: 1160 * 1161 * set the various transmit threshold registers 1162 */ 1163 static void 1164 ste_setthresh(struct ste_softc *sc) 1165 { 1166 /* set the TX threhold */ 1167 bus_space_write_2(sc->sc_st, sc->sc_sh, 1168 STE_TxStartThresh, sc->sc_txthresh); 1169 /* Urgent threshold: set to sc_txthresh / 2 */ 1170 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1171 sc->sc_txthresh >> 6); 1172 /* Burst threshold: use default value (256 bytes) */ 1173 } 1174 1175 /* 1176 * restart TX at the given frame ID in the transmitter ring 1177 */ 1178 static void 1179 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1180 { 1181 u_int32_t control; 1182 1183 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1184 control = le32toh(sc->sc_txdescs[id].tfd_control); 1185 control &= ~TFD_TxDMAComplete; 1186 sc->sc_txdescs[id].tfd_control = htole32(control); 1187 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1188 1189 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1190 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1191 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1192 ste_dmahalt_wait(sc); 1193 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1194 STE_CDTXADDR(sc, id)); 1195 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1196 } 1197 1198 /* 1199 * ste_init: [ ifnet interface function ] 1200 * 1201 * Initialize the interface. Must be called at splnet(). 1202 */ 1203 static int 1204 ste_init(struct ifnet *ifp) 1205 { 1206 struct ste_softc *sc = ifp->if_softc; 1207 bus_space_tag_t st = sc->sc_st; 1208 bus_space_handle_t sh = sc->sc_sh; 1209 struct ste_descsoft *ds; 1210 int i, error = 0; 1211 1212 /* 1213 * Cancel any pending I/O. 1214 */ 1215 ste_stop(ifp, 0); 1216 1217 /* 1218 * Reset the chip to a known state. 1219 */ 1220 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1221 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1222 1223 /* 1224 * Initialize the transmit descriptor ring. 1225 */ 1226 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1227 sc->sc_txpending = 0; 1228 sc->sc_txdirty = 0; 1229 sc->sc_txlast = STE_NTXDESC - 1; 1230 1231 /* 1232 * Initialize the receive descriptor and receive job 1233 * descriptor rings. 1234 */ 1235 for (i = 0; i < STE_NRXDESC; i++) { 1236 ds = &sc->sc_rxsoft[i]; 1237 if (ds->ds_mbuf == NULL) { 1238 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1239 printf("%s: unable to allocate or map rx " 1240 "buffer %d, error = %d\n", 1241 device_xname(&sc->sc_dev), i, error); 1242 /* 1243 * XXX Should attempt to run with fewer receive 1244 * XXX buffers instead of just failing. 1245 */ 1246 ste_rxdrain(sc); 1247 goto out; 1248 } 1249 } else 1250 STE_INIT_RXDESC(sc, i); 1251 } 1252 sc->sc_rxptr = 0; 1253 1254 /* Set the station address. */ 1255 for (i = 0; i < ETHER_ADDR_LEN; i++) 1256 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1257 CLLADDR(ifp->if_sadl)[i]); 1258 1259 /* Set up the receive filter. */ 1260 ste_set_filter(sc); 1261 1262 /* 1263 * Give the receive ring to the chip. 1264 */ 1265 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1266 STE_CDRXADDR(sc, sc->sc_rxptr)); 1267 1268 /* 1269 * We defer giving the transmit ring to the chip until we 1270 * transmit the first packet. 1271 */ 1272 1273 /* 1274 * Initialize the Tx auto-poll period. It's OK to make this number 1275 * large (127 is the max) -- we explicitly kick the transmit engine 1276 * when there's actually a packet. We are using auto-polling only 1277 * to make the interface to the transmit engine not suck. 1278 */ 1279 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1280 1281 /* ..and the Rx auto-poll period. */ 1282 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1283 1284 /* Initialize the Tx start threshold. */ 1285 ste_setthresh(sc); 1286 1287 /* Set the FIFO release threshold to 512 bytes. */ 1288 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1289 1290 /* Set maximum packet size for VLAN. */ 1291 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1292 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1293 else 1294 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1295 1296 /* 1297 * Initialize the interrupt mask. 1298 */ 1299 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1300 IE_TxDMAComplete | IE_RxDMAComplete; 1301 1302 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1303 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1304 1305 /* 1306 * Start the receive DMA engine. 1307 */ 1308 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1309 1310 /* 1311 * Initialize MacCtrl0 -- do it before setting the media, 1312 * as setting the media will actually program the register. 1313 */ 1314 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1315 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1316 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1317 1318 /* 1319 * Set the current media. 1320 */ 1321 if ((error = ether_mediachange(ifp)) != 0) 1322 goto out; 1323 1324 /* 1325 * Start the MAC. 1326 */ 1327 bus_space_write_2(st, sh, STE_MacCtrl1, 1328 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1329 1330 /* 1331 * Start the one second MII clock. 1332 */ 1333 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1334 1335 /* 1336 * ...all done! 1337 */ 1338 ifp->if_flags |= IFF_RUNNING; 1339 ifp->if_flags &= ~IFF_OACTIVE; 1340 1341 out: 1342 if (error) 1343 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1344 return (error); 1345 } 1346 1347 /* 1348 * ste_drain: 1349 * 1350 * Drain the receive queue. 1351 */ 1352 static void 1353 ste_rxdrain(struct ste_softc *sc) 1354 { 1355 struct ste_descsoft *ds; 1356 int i; 1357 1358 for (i = 0; i < STE_NRXDESC; i++) { 1359 ds = &sc->sc_rxsoft[i]; 1360 if (ds->ds_mbuf != NULL) { 1361 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1362 m_freem(ds->ds_mbuf); 1363 ds->ds_mbuf = NULL; 1364 } 1365 } 1366 } 1367 1368 /* 1369 * ste_stop: [ ifnet interface function ] 1370 * 1371 * Stop transmission on the interface. 1372 */ 1373 static void 1374 ste_stop(struct ifnet *ifp, int disable) 1375 { 1376 struct ste_softc *sc = ifp->if_softc; 1377 struct ste_descsoft *ds; 1378 int i; 1379 1380 /* 1381 * Stop the one second clock. 1382 */ 1383 callout_stop(&sc->sc_tick_ch); 1384 1385 /* Down the MII. */ 1386 mii_down(&sc->sc_mii); 1387 1388 /* 1389 * Disable interrupts. 1390 */ 1391 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1392 1393 /* 1394 * Stop receiver, transmitter, and stats update. 1395 */ 1396 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1397 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1398 1399 /* 1400 * Stop the transmit and receive DMA. 1401 */ 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1403 DC_RxDMAHalt | DC_TxDMAHalt); 1404 ste_dmahalt_wait(sc); 1405 1406 /* 1407 * Release any queued transmit buffers. 1408 */ 1409 for (i = 0; i < STE_NTXDESC; i++) { 1410 ds = &sc->sc_txsoft[i]; 1411 if (ds->ds_mbuf != NULL) { 1412 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1413 m_freem(ds->ds_mbuf); 1414 ds->ds_mbuf = NULL; 1415 } 1416 } 1417 1418 /* 1419 * Mark the interface down and cancel the watchdog timer. 1420 */ 1421 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1422 ifp->if_timer = 0; 1423 1424 if (disable) 1425 ste_rxdrain(sc); 1426 } 1427 1428 static int 1429 ste_eeprom_wait(struct ste_softc *sc) 1430 { 1431 int i; 1432 1433 for (i = 0; i < STE_TIMEOUT; i++) { 1434 delay(1000); 1435 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1436 EC_EepromBusy) == 0) 1437 return (0); 1438 } 1439 return (1); 1440 } 1441 1442 /* 1443 * ste_read_eeprom: 1444 * 1445 * Read data from the serial EEPROM. 1446 */ 1447 static void 1448 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1449 { 1450 1451 if (ste_eeprom_wait(sc)) 1452 printf("%s: EEPROM failed to come ready\n", 1453 device_xname(&sc->sc_dev)); 1454 1455 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1456 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1457 if (ste_eeprom_wait(sc)) 1458 printf("%s: EEPROM read timed out\n", 1459 device_xname(&sc->sc_dev)); 1460 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1461 } 1462 1463 /* 1464 * ste_add_rxbuf: 1465 * 1466 * Add a receive buffer to the indicated descriptor. 1467 */ 1468 static int 1469 ste_add_rxbuf(struct ste_softc *sc, int idx) 1470 { 1471 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1472 struct mbuf *m; 1473 int error; 1474 1475 MGETHDR(m, M_DONTWAIT, MT_DATA); 1476 if (m == NULL) 1477 return (ENOBUFS); 1478 1479 MCLGET(m, M_DONTWAIT); 1480 if ((m->m_flags & M_EXT) == 0) { 1481 m_freem(m); 1482 return (ENOBUFS); 1483 } 1484 1485 if (ds->ds_mbuf != NULL) 1486 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1487 1488 ds->ds_mbuf = m; 1489 1490 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1491 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1492 BUS_DMA_READ|BUS_DMA_NOWAIT); 1493 if (error) { 1494 printf("%s: can't load rx DMA map %d, error = %d\n", 1495 device_xname(&sc->sc_dev), idx, error); 1496 panic("ste_add_rxbuf"); /* XXX */ 1497 } 1498 1499 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1500 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1501 1502 STE_INIT_RXDESC(sc, idx); 1503 1504 return (0); 1505 } 1506 1507 /* 1508 * ste_set_filter: 1509 * 1510 * Set up the receive filter. 1511 */ 1512 static void 1513 ste_set_filter(struct ste_softc *sc) 1514 { 1515 struct ethercom *ec = &sc->sc_ethercom; 1516 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1517 struct ether_multi *enm; 1518 struct ether_multistep step; 1519 uint32_t crc; 1520 uint16_t mchash[4]; 1521 1522 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1523 if (ifp->if_flags & IFF_BROADCAST) 1524 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1525 1526 if (ifp->if_flags & IFF_PROMISC) { 1527 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1528 goto allmulti; 1529 } 1530 1531 /* 1532 * Set up the multicast address filter by passing all multicast 1533 * addresses through a CRC generator, and then using the low-order 1534 * 6 bits as an index into the 64 bit multicast hash table. The 1535 * high order bits select the register, while the rest of the bits 1536 * select the bit within the register. 1537 */ 1538 1539 memset(mchash, 0, sizeof(mchash)); 1540 1541 ETHER_FIRST_MULTI(step, ec, enm); 1542 if (enm == NULL) 1543 goto done; 1544 1545 while (enm != NULL) { 1546 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1547 /* 1548 * We must listen to a range of multicast addresses. 1549 * For now, just accept all multicasts, rather than 1550 * trying to set only those filter bits needed to match 1551 * the range. (At this time, the only use of address 1552 * ranges is for IP multicast routing, for which the 1553 * range is big enough to require all bits set.) 1554 */ 1555 goto allmulti; 1556 } 1557 1558 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1559 1560 /* Just want the 6 least significant bits. */ 1561 crc &= 0x3f; 1562 1563 /* Set the corresponding bit in the hash table. */ 1564 mchash[crc >> 4] |= 1 << (crc & 0xf); 1565 1566 ETHER_NEXT_MULTI(step, enm); 1567 } 1568 1569 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1570 1571 ifp->if_flags &= ~IFF_ALLMULTI; 1572 goto done; 1573 1574 allmulti: 1575 ifp->if_flags |= IFF_ALLMULTI; 1576 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1577 1578 done: 1579 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1580 /* 1581 * Program the multicast hash table. 1582 */ 1583 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1584 mchash[0]); 1585 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1586 mchash[1]); 1587 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1588 mchash[2]); 1589 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1590 mchash[3]); 1591 } 1592 1593 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1594 sc->sc_ReceiveMode); 1595 } 1596 1597 /* 1598 * ste_mii_readreg: [mii interface function] 1599 * 1600 * Read a PHY register on the MII of the ST-201. 1601 */ 1602 static int 1603 ste_mii_readreg(device_t self, int phy, int reg) 1604 { 1605 1606 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1607 } 1608 1609 /* 1610 * ste_mii_writereg: [mii interface function] 1611 * 1612 * Write a PHY register on the MII of the ST-201. 1613 */ 1614 static void 1615 ste_mii_writereg(device_t self, int phy, int reg, int val) 1616 { 1617 1618 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1619 } 1620 1621 /* 1622 * ste_mii_statchg: [mii interface function] 1623 * 1624 * Callback from MII layer when media changes. 1625 */ 1626 static void 1627 ste_mii_statchg(device_t self) 1628 { 1629 struct ste_softc *sc = device_private(self); 1630 1631 if (sc->sc_mii.mii_media_active & IFM_FDX) 1632 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1633 else 1634 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1635 1636 /* XXX 802.1x flow-control? */ 1637 1638 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1639 } 1640 1641 /* 1642 * ste_mii_bitbang_read: [mii bit-bang interface function] 1643 * 1644 * Read the MII serial port for the MII bit-bang module. 1645 */ 1646 static uint32_t 1647 ste_mii_bitbang_read(device_t self) 1648 { 1649 struct ste_softc *sc = device_private(self); 1650 1651 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1652 } 1653 1654 /* 1655 * ste_mii_bitbang_write: [mii big-bang interface function] 1656 * 1657 * Write the MII serial port for the MII bit-bang module. 1658 */ 1659 static void 1660 ste_mii_bitbang_write(device_t self, uint32_t val) 1661 { 1662 struct ste_softc *sc = device_private(self); 1663 1664 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1665 } 1666