1 /* $NetBSD: if_ste.c,v 1.31 2007/10/19 12:00:48 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.31 2007/10/19 12:00:48 ad Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <sys/bus.h> 73 #include <sys/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 static void ste_start(struct ifnet *); 208 static void ste_watchdog(struct ifnet *); 209 static int ste_ioctl(struct ifnet *, u_long, void *); 210 static int ste_init(struct ifnet *); 211 static void ste_stop(struct ifnet *, int); 212 213 static void ste_shutdown(void *); 214 215 static void ste_reset(struct ste_softc *, u_int32_t); 216 static void ste_setthresh(struct ste_softc *); 217 static void ste_txrestart(struct ste_softc *, u_int8_t); 218 static void ste_rxdrain(struct ste_softc *); 219 static int ste_add_rxbuf(struct ste_softc *, int); 220 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 221 static void ste_tick(void *); 222 223 static void ste_stats_update(struct ste_softc *); 224 225 static void ste_set_filter(struct ste_softc *); 226 227 static int ste_intr(void *); 228 static void ste_txintr(struct ste_softc *); 229 static void ste_rxintr(struct ste_softc *); 230 231 static int ste_mii_readreg(struct device *, int, int); 232 static void ste_mii_writereg(struct device *, int, int, int); 233 static void ste_mii_statchg(struct device *); 234 235 static int ste_mediachange(struct ifnet *); 236 static void ste_mediastatus(struct ifnet *, struct ifmediareq *); 237 238 static int ste_match(struct device *, struct cfdata *, void *); 239 static void ste_attach(struct device *, struct device *, void *); 240 241 int ste_copy_small = 0; 242 243 CFATTACH_DECL(ste, sizeof(struct ste_softc), 244 ste_match, ste_attach, NULL, NULL); 245 246 static uint32_t ste_mii_bitbang_read(struct device *); 247 static void ste_mii_bitbang_write(struct device *, uint32_t); 248 249 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 250 ste_mii_bitbang_read, 251 ste_mii_bitbang_write, 252 { 253 PC_MgmtData, /* MII_BIT_MDO */ 254 PC_MgmtData, /* MII_BIT_MDI */ 255 PC_MgmtClk, /* MII_BIT_MDC */ 256 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 257 0, /* MII_BIT_DIR_PHY_HOST */ 258 } 259 }; 260 261 /* 262 * Devices supported by this driver. 263 */ 264 static const struct ste_product { 265 pci_vendor_id_t ste_vendor; 266 pci_product_id_t ste_product; 267 const char *ste_name; 268 } ste_products[] = { 269 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 270 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 271 272 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 273 "Sundance ST-201 10/100 Ethernet" }, 274 275 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 276 "D-Link DL-1002 10/100 Ethernet" }, 277 278 { 0, 0, 279 NULL }, 280 }; 281 282 static const struct ste_product * 283 ste_lookup(const struct pci_attach_args *pa) 284 { 285 const struct ste_product *sp; 286 287 for (sp = ste_products; sp->ste_name != NULL; sp++) { 288 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 289 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 290 return (sp); 291 } 292 return (NULL); 293 } 294 295 static int 296 ste_match(struct device *parent, struct cfdata *cf, void *aux) 297 { 298 struct pci_attach_args *pa = aux; 299 300 if (ste_lookup(pa) != NULL) 301 return (1); 302 303 return (0); 304 } 305 306 static void 307 ste_attach(struct device *parent, struct device *self, void *aux) 308 { 309 struct ste_softc *sc = (struct ste_softc *) self; 310 struct pci_attach_args *pa = aux; 311 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 312 pci_chipset_tag_t pc = pa->pa_pc; 313 pci_intr_handle_t ih; 314 const char *intrstr = NULL; 315 bus_space_tag_t iot, memt; 316 bus_space_handle_t ioh, memh; 317 bus_dma_segment_t seg; 318 int ioh_valid, memh_valid; 319 int i, rseg, error; 320 const struct ste_product *sp; 321 uint8_t enaddr[ETHER_ADDR_LEN]; 322 uint16_t myea[ETHER_ADDR_LEN / 2]; 323 324 callout_init(&sc->sc_tick_ch, 0); 325 326 sp = ste_lookup(pa); 327 if (sp == NULL) { 328 printf("\n"); 329 panic("ste_attach: impossible"); 330 } 331 332 printf(": %s\n", sp->ste_name); 333 334 /* 335 * Map the device. 336 */ 337 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 338 PCI_MAPREG_TYPE_IO, 0, 339 &iot, &ioh, NULL, NULL) == 0); 340 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 341 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 342 &memt, &memh, NULL, NULL) == 0); 343 344 if (memh_valid) { 345 sc->sc_st = memt; 346 sc->sc_sh = memh; 347 } else if (ioh_valid) { 348 sc->sc_st = iot; 349 sc->sc_sh = ioh; 350 } else { 351 printf("%s: unable to map device registers\n", 352 sc->sc_dev.dv_xname); 353 return; 354 } 355 356 sc->sc_dmat = pa->pa_dmat; 357 358 /* Enable bus mastering. */ 359 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 360 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 361 PCI_COMMAND_MASTER_ENABLE); 362 363 /* power up chip */ 364 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 365 NULL)) && error != EOPNOTSUPP) { 366 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 367 error); 368 return; 369 } 370 371 /* 372 * Map and establish our interrupt. 373 */ 374 if (pci_intr_map(pa, &ih)) { 375 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 376 return; 377 } 378 intrstr = pci_intr_string(pc, ih); 379 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 380 if (sc->sc_ih == NULL) { 381 printf("%s: unable to establish interrupt", 382 sc->sc_dev.dv_xname); 383 if (intrstr != NULL) 384 printf(" at %s", intrstr); 385 printf("\n"); 386 return; 387 } 388 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 389 390 /* 391 * Allocate the control data structures, and create and load the 392 * DMA map for it. 393 */ 394 if ((error = bus_dmamem_alloc(sc->sc_dmat, 395 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 396 0)) != 0) { 397 printf("%s: unable to allocate control data, error = %d\n", 398 sc->sc_dev.dv_xname, error); 399 goto fail_0; 400 } 401 402 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 403 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 404 BUS_DMA_COHERENT)) != 0) { 405 printf("%s: unable to map control data, error = %d\n", 406 sc->sc_dev.dv_xname, error); 407 goto fail_1; 408 } 409 410 if ((error = bus_dmamap_create(sc->sc_dmat, 411 sizeof(struct ste_control_data), 1, 412 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 413 printf("%s: unable to create control data DMA map, " 414 "error = %d\n", sc->sc_dev.dv_xname, error); 415 goto fail_2; 416 } 417 418 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 419 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 420 0)) != 0) { 421 printf("%s: unable to load control data DMA map, error = %d\n", 422 sc->sc_dev.dv_xname, error); 423 goto fail_3; 424 } 425 426 /* 427 * Create the transmit buffer DMA maps. 428 */ 429 for (i = 0; i < STE_NTXDESC; i++) { 430 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 431 STE_NTXFRAGS, MCLBYTES, 0, 0, 432 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 433 printf("%s: unable to create tx DMA map %d, " 434 "error = %d\n", sc->sc_dev.dv_xname, i, error); 435 goto fail_4; 436 } 437 } 438 439 /* 440 * Create the receive buffer DMA maps. 441 */ 442 for (i = 0; i < STE_NRXDESC; i++) { 443 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 444 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 445 printf("%s: unable to create rx DMA map %d, " 446 "error = %d\n", sc->sc_dev.dv_xname, i, error); 447 goto fail_5; 448 } 449 sc->sc_rxsoft[i].ds_mbuf = NULL; 450 } 451 452 /* 453 * Reset the chip to a known state. 454 */ 455 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 456 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 457 458 /* 459 * Read the Ethernet address from the EEPROM. 460 */ 461 for (i = 0; i < 3; i++) { 462 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 463 myea[i] = le16toh(myea[i]); 464 } 465 memcpy(enaddr, myea, sizeof(enaddr)); 466 467 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 468 ether_sprintf(enaddr)); 469 470 /* 471 * Initialize our media structures and probe the MII. 472 */ 473 sc->sc_mii.mii_ifp = ifp; 474 sc->sc_mii.mii_readreg = ste_mii_readreg; 475 sc->sc_mii.mii_writereg = ste_mii_writereg; 476 sc->sc_mii.mii_statchg = ste_mii_statchg; 477 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ste_mediachange, 478 ste_mediastatus); 479 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 480 MII_OFFSET_ANY, 0); 481 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 482 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 483 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 484 } else 485 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 486 487 ifp = &sc->sc_ethercom.ec_if; 488 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 489 ifp->if_softc = sc; 490 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 491 ifp->if_ioctl = ste_ioctl; 492 ifp->if_start = ste_start; 493 ifp->if_watchdog = ste_watchdog; 494 ifp->if_init = ste_init; 495 ifp->if_stop = ste_stop; 496 IFQ_SET_READY(&ifp->if_snd); 497 498 /* 499 * Default the transmit threshold to 128 bytes. 500 */ 501 sc->sc_txthresh = 128; 502 503 /* 504 * Disable MWI if the PCI layer tells us to. 505 */ 506 sc->sc_DMACtrl = 0; 507 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 508 sc->sc_DMACtrl |= DC_MWIDisable; 509 510 /* 511 * We can support 802.1Q VLAN-sized frames. 512 */ 513 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 514 515 /* 516 * Attach the interface. 517 */ 518 if_attach(ifp); 519 ether_ifattach(ifp, enaddr); 520 521 /* 522 * Make sure the interface is shutdown during reboot. 523 */ 524 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 525 if (sc->sc_sdhook == NULL) 526 printf("%s: WARNING: unable to establish shutdown hook\n", 527 sc->sc_dev.dv_xname); 528 return; 529 530 /* 531 * Free any resources we've allocated during the failed attach 532 * attempt. Do this in reverse order and fall through. 533 */ 534 fail_5: 535 for (i = 0; i < STE_NRXDESC; i++) { 536 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 537 bus_dmamap_destroy(sc->sc_dmat, 538 sc->sc_rxsoft[i].ds_dmamap); 539 } 540 fail_4: 541 for (i = 0; i < STE_NTXDESC; i++) { 542 if (sc->sc_txsoft[i].ds_dmamap != NULL) 543 bus_dmamap_destroy(sc->sc_dmat, 544 sc->sc_txsoft[i].ds_dmamap); 545 } 546 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 547 fail_3: 548 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 549 fail_2: 550 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 551 sizeof(struct ste_control_data)); 552 fail_1: 553 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 fail_0: 555 return; 556 } 557 558 /* 559 * ste_shutdown: 560 * 561 * Make sure the interface is stopped at reboot time. 562 */ 563 static void 564 ste_shutdown(void *arg) 565 { 566 struct ste_softc *sc = arg; 567 568 ste_stop(&sc->sc_ethercom.ec_if, 1); 569 } 570 571 static void 572 ste_dmahalt_wait(struct ste_softc *sc) 573 { 574 int i; 575 576 for (i = 0; i < STE_TIMEOUT; i++) { 577 delay(2); 578 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 579 DC_DMAHaltBusy) == 0) 580 break; 581 } 582 583 if (i == STE_TIMEOUT) 584 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 585 } 586 587 /* 588 * ste_start: [ifnet interface function] 589 * 590 * Start packet transmission on the interface. 591 */ 592 static void 593 ste_start(struct ifnet *ifp) 594 { 595 struct ste_softc *sc = ifp->if_softc; 596 struct mbuf *m0, *m; 597 struct ste_descsoft *ds; 598 struct ste_tfd *tfd; 599 bus_dmamap_t dmamap; 600 int error, olasttx, nexttx, opending, seg, totlen; 601 602 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 603 return; 604 605 /* 606 * Remember the previous number of pending transmissions 607 * and the current last descriptor in the list. 608 */ 609 opending = sc->sc_txpending; 610 olasttx = sc->sc_txlast; 611 612 /* 613 * Loop through the send queue, setting up transmit descriptors 614 * until we drain the queue, or use up all available transmit 615 * descriptors. 616 */ 617 while (sc->sc_txpending < STE_NTXDESC) { 618 /* 619 * Grab a packet off the queue. 620 */ 621 IFQ_POLL(&ifp->if_snd, m0); 622 if (m0 == NULL) 623 break; 624 m = NULL; 625 626 /* 627 * Get the last and next available transmit descriptor. 628 */ 629 nexttx = STE_NEXTTX(sc->sc_txlast); 630 tfd = &sc->sc_txdescs[nexttx]; 631 ds = &sc->sc_txsoft[nexttx]; 632 633 dmamap = ds->ds_dmamap; 634 635 /* 636 * Load the DMA map. If this fails, the packet either 637 * didn't fit in the alloted number of segments, or we 638 * were short on resources. In this case, we'll copy 639 * and try again. 640 */ 641 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 642 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 643 MGETHDR(m, M_DONTWAIT, MT_DATA); 644 if (m == NULL) { 645 printf("%s: unable to allocate Tx mbuf\n", 646 sc->sc_dev.dv_xname); 647 break; 648 } 649 if (m0->m_pkthdr.len > MHLEN) { 650 MCLGET(m, M_DONTWAIT); 651 if ((m->m_flags & M_EXT) == 0) { 652 printf("%s: unable to allocate Tx " 653 "cluster\n", sc->sc_dev.dv_xname); 654 m_freem(m); 655 break; 656 } 657 } 658 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 659 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 660 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 661 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 662 if (error) { 663 printf("%s: unable to load Tx buffer, " 664 "error = %d\n", sc->sc_dev.dv_xname, error); 665 break; 666 } 667 } 668 669 IFQ_DEQUEUE(&ifp->if_snd, m0); 670 if (m != NULL) { 671 m_freem(m0); 672 m0 = m; 673 } 674 675 /* 676 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 677 */ 678 679 /* Sync the DMA map. */ 680 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 681 BUS_DMASYNC_PREWRITE); 682 683 /* Initialize the fragment list. */ 684 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 685 tfd->tfd_frags[seg].frag_addr = 686 htole32(dmamap->dm_segs[seg].ds_addr); 687 tfd->tfd_frags[seg].frag_len = 688 htole32(dmamap->dm_segs[seg].ds_len); 689 totlen += dmamap->dm_segs[seg].ds_len; 690 } 691 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 692 693 /* Initialize the descriptor. */ 694 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 695 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 696 697 /* Sync the descriptor. */ 698 STE_CDTXSYNC(sc, nexttx, 699 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 700 701 /* 702 * Store a pointer to the packet so we can free it later, 703 * and remember what txdirty will be once the packet is 704 * done. 705 */ 706 ds->ds_mbuf = m0; 707 708 /* Advance the tx pointer. */ 709 sc->sc_txpending++; 710 sc->sc_txlast = nexttx; 711 712 #if NBPFILTER > 0 713 /* 714 * Pass the packet to any BPF listeners. 715 */ 716 if (ifp->if_bpf) 717 bpf_mtap(ifp->if_bpf, m0); 718 #endif /* NBPFILTER > 0 */ 719 } 720 721 if (sc->sc_txpending == STE_NTXDESC) { 722 /* No more slots left; notify upper layer. */ 723 ifp->if_flags |= IFF_OACTIVE; 724 } 725 726 if (sc->sc_txpending != opending) { 727 /* 728 * We enqueued packets. If the transmitter was idle, 729 * reset the txdirty pointer. 730 */ 731 if (opending == 0) 732 sc->sc_txdirty = STE_NEXTTX(olasttx); 733 734 /* 735 * Cause a descriptor interrupt to happen on the 736 * last packet we enqueued, and also cause the 737 * DMA engine to wait after is has finished processing 738 * it. 739 */ 740 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 741 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 742 htole32(TFD_TxDMAIndicate); 743 STE_CDTXSYNC(sc, sc->sc_txlast, 744 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 745 746 /* 747 * Link up the new chain of descriptors to the 748 * last. 749 */ 750 sc->sc_txdescs[olasttx].tfd_next = 751 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 752 STE_CDTXSYNC(sc, olasttx, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 755 /* 756 * Kick the transmit DMA logic. Note that since we're 757 * using auto-polling, reading the Tx desc pointer will 758 * give it the nudge it needs to get going. 759 */ 760 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 761 STE_TxDMAListPtr) == 0) { 762 bus_space_write_4(sc->sc_st, sc->sc_sh, 763 STE_DMACtrl, DC_TxDMAHalt); 764 ste_dmahalt_wait(sc); 765 bus_space_write_4(sc->sc_st, sc->sc_sh, 766 STE_TxDMAListPtr, 767 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 768 bus_space_write_4(sc->sc_st, sc->sc_sh, 769 STE_DMACtrl, DC_TxDMAResume); 770 } 771 772 /* Set a watchdog timer in case the chip flakes out. */ 773 ifp->if_timer = 5; 774 } 775 } 776 777 /* 778 * ste_watchdog: [ifnet interface function] 779 * 780 * Watchdog timer handler. 781 */ 782 static void 783 ste_watchdog(struct ifnet *ifp) 784 { 785 struct ste_softc *sc = ifp->if_softc; 786 787 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 788 ifp->if_oerrors++; 789 790 ste_txintr(sc); 791 ste_rxintr(sc); 792 (void) ste_init(ifp); 793 794 /* Try to get more packets going. */ 795 ste_start(ifp); 796 } 797 798 /* 799 * ste_ioctl: [ifnet interface function] 800 * 801 * Handle control requests from the operator. 802 */ 803 static int 804 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 805 { 806 struct ste_softc *sc = ifp->if_softc; 807 struct ifreq *ifr = (struct ifreq *)data; 808 int s, error; 809 810 s = splnet(); 811 812 switch (cmd) { 813 case SIOCSIFMEDIA: 814 case SIOCGIFMEDIA: 815 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 816 break; 817 818 default: 819 error = ether_ioctl(ifp, cmd, data); 820 if (error == ENETRESET) { 821 /* 822 * Multicast list has changed; set the hardware filter 823 * accordingly. 824 */ 825 if (ifp->if_flags & IFF_RUNNING) 826 ste_set_filter(sc); 827 error = 0; 828 } 829 break; 830 } 831 832 /* Try to get more packets going. */ 833 ste_start(ifp); 834 835 splx(s); 836 return (error); 837 } 838 839 /* 840 * ste_intr: 841 * 842 * Interrupt service routine. 843 */ 844 static int 845 ste_intr(void *arg) 846 { 847 struct ste_softc *sc = arg; 848 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 849 uint16_t isr; 850 uint8_t txstat; 851 int wantinit; 852 853 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 854 IS_InterruptStatus) == 0) 855 return (0); 856 857 for (wantinit = 0; wantinit == 0;) { 858 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 859 if ((isr & sc->sc_IntEnable) == 0) 860 break; 861 862 /* Receive interrupts. */ 863 if (isr & IE_RxDMAComplete) 864 ste_rxintr(sc); 865 866 /* Transmit interrupts. */ 867 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 868 ste_txintr(sc); 869 870 /* Statistics overflow. */ 871 if (isr & IE_UpdateStats) 872 ste_stats_update(sc); 873 874 /* Transmission errors. */ 875 if (isr & IE_TxComplete) { 876 for (;;) { 877 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 878 STE_TxStatus); 879 if ((txstat & TS_TxComplete) == 0) 880 break; 881 if (txstat & TS_TxUnderrun) { 882 sc->sc_txthresh += 32; 883 if (sc->sc_txthresh > 0x1ffc) 884 sc->sc_txthresh = 0x1ffc; 885 printf("%s: transmit underrun, new " 886 "threshold: %d bytes\n", 887 sc->sc_dev.dv_xname, 888 sc->sc_txthresh); 889 ste_reset(sc, AC_TxReset | AC_DMA | 890 AC_FIFO | AC_Network); 891 ste_setthresh(sc); 892 bus_space_write_1(sc->sc_st, sc->sc_sh, 893 STE_TxDMAPollPeriod, 127); 894 ste_txrestart(sc, 895 bus_space_read_1(sc->sc_st, 896 sc->sc_sh, STE_TxFrameId)); 897 } 898 if (txstat & TS_TxReleaseError) { 899 printf("%s: Tx FIFO release error\n", 900 sc->sc_dev.dv_xname); 901 wantinit = 1; 902 } 903 if (txstat & TS_MaxCollisions) { 904 printf("%s: excessive collisions\n", 905 sc->sc_dev.dv_xname); 906 wantinit = 1; 907 } 908 if (txstat & TS_TxStatusOverflow) { 909 printf("%s: status overflow\n", 910 sc->sc_dev.dv_xname); 911 wantinit = 1; 912 } 913 bus_space_write_2(sc->sc_st, sc->sc_sh, 914 STE_TxStatus, 0); 915 } 916 } 917 918 /* Host interface errors. */ 919 if (isr & IE_HostError) { 920 printf("%s: Host interface error\n", 921 sc->sc_dev.dv_xname); 922 wantinit = 1; 923 } 924 } 925 926 if (wantinit) 927 ste_init(ifp); 928 929 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 930 sc->sc_IntEnable); 931 932 /* Try to get more packets going. */ 933 ste_start(ifp); 934 935 return (1); 936 } 937 938 /* 939 * ste_txintr: 940 * 941 * Helper; handle transmit interrupts. 942 */ 943 static void 944 ste_txintr(struct ste_softc *sc) 945 { 946 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 947 struct ste_descsoft *ds; 948 uint32_t control; 949 int i; 950 951 ifp->if_flags &= ~IFF_OACTIVE; 952 953 /* 954 * Go through our Tx list and free mbufs for those 955 * frames which have been transmitted. 956 */ 957 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 958 i = STE_NEXTTX(i), sc->sc_txpending--) { 959 ds = &sc->sc_txsoft[i]; 960 961 STE_CDTXSYNC(sc, i, 962 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 963 964 control = le32toh(sc->sc_txdescs[i].tfd_control); 965 if ((control & TFD_TxDMAComplete) == 0) 966 break; 967 968 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 969 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 970 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 971 m_freem(ds->ds_mbuf); 972 ds->ds_mbuf = NULL; 973 } 974 975 /* Update the dirty transmit buffer pointer. */ 976 sc->sc_txdirty = i; 977 978 /* 979 * If there are no more pending transmissions, cancel the watchdog 980 * timer. 981 */ 982 if (sc->sc_txpending == 0) 983 ifp->if_timer = 0; 984 } 985 986 /* 987 * ste_rxintr: 988 * 989 * Helper; handle receive interrupts. 990 */ 991 static void 992 ste_rxintr(struct ste_softc *sc) 993 { 994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 995 struct ste_descsoft *ds; 996 struct mbuf *m; 997 uint32_t status; 998 int i, len; 999 1000 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 1001 ds = &sc->sc_rxsoft[i]; 1002 1003 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1004 1005 status = le32toh(sc->sc_rxdescs[i].rfd_status); 1006 1007 if ((status & RFD_RxDMAComplete) == 0) 1008 break; 1009 1010 /* 1011 * If the packet had an error, simply recycle the 1012 * buffer. Note, we count the error later in the 1013 * periodic stats update. 1014 */ 1015 if (status & RFD_RxFrameError) { 1016 STE_INIT_RXDESC(sc, i); 1017 continue; 1018 } 1019 1020 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1021 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1022 1023 /* 1024 * No errors; receive the packet. Note, we have 1025 * configured the chip to not include the CRC at 1026 * the end of the packet. 1027 */ 1028 len = RFD_RxDMAFrameLen(status); 1029 1030 /* 1031 * If the packet is small enough to fit in a 1032 * single header mbuf, allocate one and copy 1033 * the data into it. This greatly reduces 1034 * memory consumption when we receive lots 1035 * of small packets. 1036 * 1037 * Otherwise, we add a new buffer to the receive 1038 * chain. If this fails, we drop the packet and 1039 * recycle the old buffer. 1040 */ 1041 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1042 MGETHDR(m, M_DONTWAIT, MT_DATA); 1043 if (m == NULL) 1044 goto dropit; 1045 m->m_data += 2; 1046 memcpy(mtod(m, void *), 1047 mtod(ds->ds_mbuf, void *), len); 1048 STE_INIT_RXDESC(sc, i); 1049 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1050 ds->ds_dmamap->dm_mapsize, 1051 BUS_DMASYNC_PREREAD); 1052 } else { 1053 m = ds->ds_mbuf; 1054 if (ste_add_rxbuf(sc, i) != 0) { 1055 dropit: 1056 ifp->if_ierrors++; 1057 STE_INIT_RXDESC(sc, i); 1058 bus_dmamap_sync(sc->sc_dmat, 1059 ds->ds_dmamap, 0, 1060 ds->ds_dmamap->dm_mapsize, 1061 BUS_DMASYNC_PREREAD); 1062 continue; 1063 } 1064 } 1065 1066 m->m_pkthdr.rcvif = ifp; 1067 m->m_pkthdr.len = m->m_len = len; 1068 1069 #if NBPFILTER > 0 1070 /* 1071 * Pass this up to any BPF listeners, but only 1072 * pass if up the stack if it's for us. 1073 */ 1074 if (ifp->if_bpf) 1075 bpf_mtap(ifp->if_bpf, m); 1076 #endif /* NBPFILTER > 0 */ 1077 1078 /* Pass it on. */ 1079 (*ifp->if_input)(ifp, m); 1080 } 1081 1082 /* Update the receive pointer. */ 1083 sc->sc_rxptr = i; 1084 } 1085 1086 /* 1087 * ste_tick: 1088 * 1089 * One second timer, used to tick the MII. 1090 */ 1091 static void 1092 ste_tick(void *arg) 1093 { 1094 struct ste_softc *sc = arg; 1095 int s; 1096 1097 s = splnet(); 1098 mii_tick(&sc->sc_mii); 1099 ste_stats_update(sc); 1100 splx(s); 1101 1102 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1103 } 1104 1105 /* 1106 * ste_stats_update: 1107 * 1108 * Read the ST-201 statistics counters. 1109 */ 1110 static void 1111 ste_stats_update(struct ste_softc *sc) 1112 { 1113 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1114 bus_space_tag_t st = sc->sc_st; 1115 bus_space_handle_t sh = sc->sc_sh; 1116 1117 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1118 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1119 1120 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1121 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1122 1123 ifp->if_opackets += 1124 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1125 ifp->if_ipackets += 1126 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1127 1128 ifp->if_collisions += 1129 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1130 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1131 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1132 1133 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1134 1135 ifp->if_ierrors += 1136 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1137 1138 ifp->if_oerrors += 1139 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1140 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1141 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1142 1143 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1144 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1145 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1146 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1147 } 1148 1149 /* 1150 * ste_reset: 1151 * 1152 * Perform a soft reset on the ST-201. 1153 */ 1154 static void 1155 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1156 { 1157 uint32_t ac; 1158 int i; 1159 1160 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1161 1162 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1163 1164 delay(50000); 1165 1166 for (i = 0; i < STE_TIMEOUT; i++) { 1167 delay(1000); 1168 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1169 AC_ResetBusy) == 0) 1170 break; 1171 } 1172 1173 if (i == STE_TIMEOUT) 1174 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1175 1176 delay(1000); 1177 } 1178 1179 /* 1180 * ste_setthresh: 1181 * 1182 * set the various transmit threshold registers 1183 */ 1184 static void 1185 ste_setthresh(struct ste_softc *sc) 1186 { 1187 /* set the TX threhold */ 1188 bus_space_write_2(sc->sc_st, sc->sc_sh, 1189 STE_TxStartThresh, sc->sc_txthresh); 1190 /* Urgent threshold: set to sc_txthresh / 2 */ 1191 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1192 sc->sc_txthresh >> 6); 1193 /* Burst threshold: use default value (256 bytes) */ 1194 } 1195 1196 /* 1197 * restart TX at the given frame ID in the transmitter ring 1198 */ 1199 static void 1200 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1201 { 1202 u_int32_t control; 1203 1204 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1205 control = le32toh(sc->sc_txdescs[id].tfd_control); 1206 control &= ~TFD_TxDMAComplete; 1207 sc->sc_txdescs[id].tfd_control = htole32(control); 1208 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1209 1210 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1211 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1212 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1213 ste_dmahalt_wait(sc); 1214 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1215 STE_CDTXADDR(sc, id)); 1216 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1217 } 1218 1219 /* 1220 * ste_init: [ ifnet interface function ] 1221 * 1222 * Initialize the interface. Must be called at splnet(). 1223 */ 1224 static int 1225 ste_init(struct ifnet *ifp) 1226 { 1227 struct ste_softc *sc = ifp->if_softc; 1228 bus_space_tag_t st = sc->sc_st; 1229 bus_space_handle_t sh = sc->sc_sh; 1230 struct ste_descsoft *ds; 1231 int i, error = 0; 1232 1233 /* 1234 * Cancel any pending I/O. 1235 */ 1236 ste_stop(ifp, 0); 1237 1238 /* 1239 * Reset the chip to a known state. 1240 */ 1241 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1242 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1243 1244 /* 1245 * Initialize the transmit descriptor ring. 1246 */ 1247 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1248 sc->sc_txpending = 0; 1249 sc->sc_txdirty = 0; 1250 sc->sc_txlast = STE_NTXDESC - 1; 1251 1252 /* 1253 * Initialize the receive descriptor and receive job 1254 * descriptor rings. 1255 */ 1256 for (i = 0; i < STE_NRXDESC; i++) { 1257 ds = &sc->sc_rxsoft[i]; 1258 if (ds->ds_mbuf == NULL) { 1259 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1260 printf("%s: unable to allocate or map rx " 1261 "buffer %d, error = %d\n", 1262 sc->sc_dev.dv_xname, i, error); 1263 /* 1264 * XXX Should attempt to run with fewer receive 1265 * XXX buffers instead of just failing. 1266 */ 1267 ste_rxdrain(sc); 1268 goto out; 1269 } 1270 } else 1271 STE_INIT_RXDESC(sc, i); 1272 } 1273 sc->sc_rxptr = 0; 1274 1275 /* Set the station address. */ 1276 for (i = 0; i < ETHER_ADDR_LEN; i++) 1277 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1278 CLLADDR(ifp->if_sadl)[i]); 1279 1280 /* Set up the receive filter. */ 1281 ste_set_filter(sc); 1282 1283 /* 1284 * Give the receive ring to the chip. 1285 */ 1286 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1287 STE_CDRXADDR(sc, sc->sc_rxptr)); 1288 1289 /* 1290 * We defer giving the transmit ring to the chip until we 1291 * transmit the first packet. 1292 */ 1293 1294 /* 1295 * Initialize the Tx auto-poll period. It's OK to make this number 1296 * large (127 is the max) -- we explicitly kick the transmit engine 1297 * when there's actually a packet. We are using auto-polling only 1298 * to make the interface to the transmit engine not suck. 1299 */ 1300 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1301 1302 /* ..and the Rx auto-poll period. */ 1303 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1304 1305 /* Initialize the Tx start threshold. */ 1306 ste_setthresh(sc); 1307 1308 /* Set the FIFO release threshold to 512 bytes. */ 1309 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1310 1311 /* Set maximum packet size for VLAN. */ 1312 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1313 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1314 else 1315 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1316 1317 /* 1318 * Initialize the interrupt mask. 1319 */ 1320 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1321 IE_TxDMAComplete | IE_RxDMAComplete; 1322 1323 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1324 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1325 1326 /* 1327 * Start the receive DMA engine. 1328 */ 1329 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1330 1331 /* 1332 * Initialize MacCtrl0 -- do it before setting the media, 1333 * as setting the media will actually program the register. 1334 */ 1335 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1336 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1337 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1338 1339 /* 1340 * Set the current media. 1341 */ 1342 mii_mediachg(&sc->sc_mii); 1343 1344 /* 1345 * Start the MAC. 1346 */ 1347 bus_space_write_2(st, sh, STE_MacCtrl1, 1348 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1349 1350 /* 1351 * Start the one second MII clock. 1352 */ 1353 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1354 1355 /* 1356 * ...all done! 1357 */ 1358 ifp->if_flags |= IFF_RUNNING; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 1361 out: 1362 if (error) 1363 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1364 return (error); 1365 } 1366 1367 /* 1368 * ste_drain: 1369 * 1370 * Drain the receive queue. 1371 */ 1372 static void 1373 ste_rxdrain(struct ste_softc *sc) 1374 { 1375 struct ste_descsoft *ds; 1376 int i; 1377 1378 for (i = 0; i < STE_NRXDESC; i++) { 1379 ds = &sc->sc_rxsoft[i]; 1380 if (ds->ds_mbuf != NULL) { 1381 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1382 m_freem(ds->ds_mbuf); 1383 ds->ds_mbuf = NULL; 1384 } 1385 } 1386 } 1387 1388 /* 1389 * ste_stop: [ ifnet interface function ] 1390 * 1391 * Stop transmission on the interface. 1392 */ 1393 static void 1394 ste_stop(struct ifnet *ifp, int disable) 1395 { 1396 struct ste_softc *sc = ifp->if_softc; 1397 struct ste_descsoft *ds; 1398 int i; 1399 1400 /* 1401 * Stop the one second clock. 1402 */ 1403 callout_stop(&sc->sc_tick_ch); 1404 1405 /* Down the MII. */ 1406 mii_down(&sc->sc_mii); 1407 1408 /* 1409 * Disable interrupts. 1410 */ 1411 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1412 1413 /* 1414 * Stop receiver, transmitter, and stats update. 1415 */ 1416 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1417 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1418 1419 /* 1420 * Stop the transmit and receive DMA. 1421 */ 1422 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1423 DC_RxDMAHalt | DC_TxDMAHalt); 1424 ste_dmahalt_wait(sc); 1425 1426 /* 1427 * Release any queued transmit buffers. 1428 */ 1429 for (i = 0; i < STE_NTXDESC; i++) { 1430 ds = &sc->sc_txsoft[i]; 1431 if (ds->ds_mbuf != NULL) { 1432 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1433 m_freem(ds->ds_mbuf); 1434 ds->ds_mbuf = NULL; 1435 } 1436 } 1437 1438 if (disable) 1439 ste_rxdrain(sc); 1440 1441 /* 1442 * Mark the interface down and cancel the watchdog timer. 1443 */ 1444 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1445 ifp->if_timer = 0; 1446 } 1447 1448 static int 1449 ste_eeprom_wait(struct ste_softc *sc) 1450 { 1451 int i; 1452 1453 for (i = 0; i < STE_TIMEOUT; i++) { 1454 delay(1000); 1455 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1456 EC_EepromBusy) == 0) 1457 return (0); 1458 } 1459 return (1); 1460 } 1461 1462 /* 1463 * ste_read_eeprom: 1464 * 1465 * Read data from the serial EEPROM. 1466 */ 1467 static void 1468 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1469 { 1470 1471 if (ste_eeprom_wait(sc)) 1472 printf("%s: EEPROM failed to come ready\n", 1473 sc->sc_dev.dv_xname); 1474 1475 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1476 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1477 if (ste_eeprom_wait(sc)) 1478 printf("%s: EEPROM read timed out\n", 1479 sc->sc_dev.dv_xname); 1480 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1481 } 1482 1483 /* 1484 * ste_add_rxbuf: 1485 * 1486 * Add a receive buffer to the indicated descriptor. 1487 */ 1488 static int 1489 ste_add_rxbuf(struct ste_softc *sc, int idx) 1490 { 1491 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1492 struct mbuf *m; 1493 int error; 1494 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m == NULL) 1497 return (ENOBUFS); 1498 1499 MCLGET(m, M_DONTWAIT); 1500 if ((m->m_flags & M_EXT) == 0) { 1501 m_freem(m); 1502 return (ENOBUFS); 1503 } 1504 1505 if (ds->ds_mbuf != NULL) 1506 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1507 1508 ds->ds_mbuf = m; 1509 1510 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1511 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1512 BUS_DMA_READ|BUS_DMA_NOWAIT); 1513 if (error) { 1514 printf("%s: can't load rx DMA map %d, error = %d\n", 1515 sc->sc_dev.dv_xname, idx, error); 1516 panic("ste_add_rxbuf"); /* XXX */ 1517 } 1518 1519 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1520 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1521 1522 STE_INIT_RXDESC(sc, idx); 1523 1524 return (0); 1525 } 1526 1527 /* 1528 * ste_set_filter: 1529 * 1530 * Set up the receive filter. 1531 */ 1532 static void 1533 ste_set_filter(struct ste_softc *sc) 1534 { 1535 struct ethercom *ec = &sc->sc_ethercom; 1536 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1537 struct ether_multi *enm; 1538 struct ether_multistep step; 1539 uint32_t crc; 1540 uint16_t mchash[4]; 1541 1542 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1543 if (ifp->if_flags & IFF_BROADCAST) 1544 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1545 1546 if (ifp->if_flags & IFF_PROMISC) { 1547 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1548 goto allmulti; 1549 } 1550 1551 /* 1552 * Set up the multicast address filter by passing all multicast 1553 * addresses through a CRC generator, and then using the low-order 1554 * 6 bits as an index into the 64 bit multicast hash table. The 1555 * high order bits select the register, while the rest of the bits 1556 * select the bit within the register. 1557 */ 1558 1559 memset(mchash, 0, sizeof(mchash)); 1560 1561 ETHER_FIRST_MULTI(step, ec, enm); 1562 if (enm == NULL) 1563 goto done; 1564 1565 while (enm != NULL) { 1566 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1567 /* 1568 * We must listen to a range of multicast addresses. 1569 * For now, just accept all multicasts, rather than 1570 * trying to set only those filter bits needed to match 1571 * the range. (At this time, the only use of address 1572 * ranges is for IP multicast routing, for which the 1573 * range is big enough to require all bits set.) 1574 */ 1575 goto allmulti; 1576 } 1577 1578 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1579 1580 /* Just want the 6 least significant bits. */ 1581 crc &= 0x3f; 1582 1583 /* Set the corresponding bit in the hash table. */ 1584 mchash[crc >> 4] |= 1 << (crc & 0xf); 1585 1586 ETHER_NEXT_MULTI(step, enm); 1587 } 1588 1589 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1590 1591 ifp->if_flags &= ~IFF_ALLMULTI; 1592 goto done; 1593 1594 allmulti: 1595 ifp->if_flags |= IFF_ALLMULTI; 1596 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1597 1598 done: 1599 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1600 /* 1601 * Program the multicast hash table. 1602 */ 1603 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1604 mchash[0]); 1605 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1606 mchash[1]); 1607 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1608 mchash[2]); 1609 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1610 mchash[3]); 1611 } 1612 1613 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1614 sc->sc_ReceiveMode); 1615 } 1616 1617 /* 1618 * ste_mii_readreg: [mii interface function] 1619 * 1620 * Read a PHY register on the MII of the ST-201. 1621 */ 1622 static int 1623 ste_mii_readreg(struct device *self, int phy, int reg) 1624 { 1625 1626 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1627 } 1628 1629 /* 1630 * ste_mii_writereg: [mii interface function] 1631 * 1632 * Write a PHY register on the MII of the ST-201. 1633 */ 1634 static void 1635 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1636 { 1637 1638 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1639 } 1640 1641 /* 1642 * ste_mii_statchg: [mii interface function] 1643 * 1644 * Callback from MII layer when media changes. 1645 */ 1646 static void 1647 ste_mii_statchg(struct device *self) 1648 { 1649 struct ste_softc *sc = (struct ste_softc *) self; 1650 1651 if (sc->sc_mii.mii_media_active & IFM_FDX) 1652 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1653 else 1654 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1655 1656 /* XXX 802.1x flow-control? */ 1657 1658 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1659 } 1660 1661 /* 1662 * ste_mii_bitbang_read: [mii bit-bang interface function] 1663 * 1664 * Read the MII serial port for the MII bit-bang module. 1665 */ 1666 static uint32_t 1667 ste_mii_bitbang_read(struct device *self) 1668 { 1669 struct ste_softc *sc = (void *) self; 1670 1671 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1672 } 1673 1674 /* 1675 * ste_mii_bitbang_write: [mii big-bang interface function] 1676 * 1677 * Write the MII serial port for the MII bit-bang module. 1678 */ 1679 static void 1680 ste_mii_bitbang_write(struct device *self, uint32_t val) 1681 { 1682 struct ste_softc *sc = (void *) self; 1683 1684 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1685 } 1686 1687 /* 1688 * ste_mediastatus: [ifmedia interface function] 1689 * 1690 * Get the current interface media status. 1691 */ 1692 static void 1693 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1694 { 1695 struct ste_softc *sc = ifp->if_softc; 1696 1697 mii_pollstat(&sc->sc_mii); 1698 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1699 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1700 } 1701 1702 /* 1703 * ste_mediachange: [ifmedia interface function] 1704 * 1705 * Set hardware to newly-selected media. 1706 */ 1707 static int 1708 ste_mediachange(struct ifnet *ifp) 1709 { 1710 struct ste_softc *sc = ifp->if_softc; 1711 1712 if (ifp->if_flags & IFF_UP) 1713 mii_mediachg(&sc->sc_mii); 1714 return (0); 1715 } 1716