1 /* $NetBSD: if_ste.c,v 1.35 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.35 2008/04/10 19:13:37 cegger Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <sys/bus.h> 73 #include <sys/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 static void ste_start(struct ifnet *); 208 static void ste_watchdog(struct ifnet *); 209 static int ste_ioctl(struct ifnet *, u_long, void *); 210 static int ste_init(struct ifnet *); 211 static void ste_stop(struct ifnet *, int); 212 213 static void ste_shutdown(void *); 214 215 static void ste_reset(struct ste_softc *, u_int32_t); 216 static void ste_setthresh(struct ste_softc *); 217 static void ste_txrestart(struct ste_softc *, u_int8_t); 218 static void ste_rxdrain(struct ste_softc *); 219 static int ste_add_rxbuf(struct ste_softc *, int); 220 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 221 static void ste_tick(void *); 222 223 static void ste_stats_update(struct ste_softc *); 224 225 static void ste_set_filter(struct ste_softc *); 226 227 static int ste_intr(void *); 228 static void ste_txintr(struct ste_softc *); 229 static void ste_rxintr(struct ste_softc *); 230 231 static int ste_mii_readreg(device_t, int, int); 232 static void ste_mii_writereg(device_t, int, int, int); 233 static void ste_mii_statchg(device_t); 234 235 static int ste_match(device_t, struct cfdata *, void *); 236 static void ste_attach(device_t, device_t, void *); 237 238 int ste_copy_small = 0; 239 240 CFATTACH_DECL(ste, sizeof(struct ste_softc), 241 ste_match, ste_attach, NULL, NULL); 242 243 static uint32_t ste_mii_bitbang_read(device_t); 244 static void ste_mii_bitbang_write(device_t, uint32_t); 245 246 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 247 ste_mii_bitbang_read, 248 ste_mii_bitbang_write, 249 { 250 PC_MgmtData, /* MII_BIT_MDO */ 251 PC_MgmtData, /* MII_BIT_MDI */ 252 PC_MgmtClk, /* MII_BIT_MDC */ 253 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 254 0, /* MII_BIT_DIR_PHY_HOST */ 255 } 256 }; 257 258 /* 259 * Devices supported by this driver. 260 */ 261 static const struct ste_product { 262 pci_vendor_id_t ste_vendor; 263 pci_product_id_t ste_product; 264 const char *ste_name; 265 } ste_products[] = { 266 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 267 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 268 269 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 270 "Sundance ST-201 10/100 Ethernet" }, 271 272 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 273 "D-Link DL-1002 10/100 Ethernet" }, 274 275 { 0, 0, 276 NULL }, 277 }; 278 279 static const struct ste_product * 280 ste_lookup(const struct pci_attach_args *pa) 281 { 282 const struct ste_product *sp; 283 284 for (sp = ste_products; sp->ste_name != NULL; sp++) { 285 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 286 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 287 return (sp); 288 } 289 return (NULL); 290 } 291 292 static int 293 ste_match(device_t parent, struct cfdata *cf, void *aux) 294 { 295 struct pci_attach_args *pa = aux; 296 297 if (ste_lookup(pa) != NULL) 298 return (1); 299 300 return (0); 301 } 302 303 static void 304 ste_attach(device_t parent, device_t self, void *aux) 305 { 306 struct ste_softc *sc = device_private(self); 307 struct pci_attach_args *pa = aux; 308 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 309 pci_chipset_tag_t pc = pa->pa_pc; 310 pci_intr_handle_t ih; 311 const char *intrstr = NULL; 312 bus_space_tag_t iot, memt; 313 bus_space_handle_t ioh, memh; 314 bus_dma_segment_t seg; 315 int ioh_valid, memh_valid; 316 int i, rseg, error; 317 const struct ste_product *sp; 318 uint8_t enaddr[ETHER_ADDR_LEN]; 319 uint16_t myea[ETHER_ADDR_LEN / 2]; 320 321 callout_init(&sc->sc_tick_ch, 0); 322 323 sp = ste_lookup(pa); 324 if (sp == NULL) { 325 printf("\n"); 326 panic("ste_attach: impossible"); 327 } 328 329 printf(": %s\n", sp->ste_name); 330 331 /* 332 * Map the device. 333 */ 334 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 335 PCI_MAPREG_TYPE_IO, 0, 336 &iot, &ioh, NULL, NULL) == 0); 337 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 338 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 339 &memt, &memh, NULL, NULL) == 0); 340 341 if (memh_valid) { 342 sc->sc_st = memt; 343 sc->sc_sh = memh; 344 } else if (ioh_valid) { 345 sc->sc_st = iot; 346 sc->sc_sh = ioh; 347 } else { 348 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 349 return; 350 } 351 352 sc->sc_dmat = pa->pa_dmat; 353 354 /* Enable bus mastering. */ 355 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 356 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 357 PCI_COMMAND_MASTER_ENABLE); 358 359 /* power up chip */ 360 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 361 NULL)) && error != EOPNOTSUPP) { 362 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 363 error); 364 return; 365 } 366 367 /* 368 * Map and establish our interrupt. 369 */ 370 if (pci_intr_map(pa, &ih)) { 371 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 372 return; 373 } 374 intrstr = pci_intr_string(pc, ih); 375 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 376 if (sc->sc_ih == NULL) { 377 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 378 if (intrstr != NULL) 379 printf(" at %s", intrstr); 380 printf("\n"); 381 return; 382 } 383 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 384 385 /* 386 * Allocate the control data structures, and create and load the 387 * DMA map for it. 388 */ 389 if ((error = bus_dmamem_alloc(sc->sc_dmat, 390 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 391 0)) != 0) { 392 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 393 error); 394 goto fail_0; 395 } 396 397 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 398 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 399 BUS_DMA_COHERENT)) != 0) { 400 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 401 error); 402 goto fail_1; 403 } 404 405 if ((error = bus_dmamap_create(sc->sc_dmat, 406 sizeof(struct ste_control_data), 1, 407 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 408 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 409 "error = %d\n", error); 410 goto fail_2; 411 } 412 413 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 414 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 415 0)) != 0) { 416 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 417 error); 418 goto fail_3; 419 } 420 421 /* 422 * Create the transmit buffer DMA maps. 423 */ 424 for (i = 0; i < STE_NTXDESC; i++) { 425 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 426 STE_NTXFRAGS, MCLBYTES, 0, 0, 427 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 428 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 429 "error = %d\n", i, error); 430 goto fail_4; 431 } 432 } 433 434 /* 435 * Create the receive buffer DMA maps. 436 */ 437 for (i = 0; i < STE_NRXDESC; i++) { 438 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 439 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 440 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 441 "error = %d\n", i, error); 442 goto fail_5; 443 } 444 sc->sc_rxsoft[i].ds_mbuf = NULL; 445 } 446 447 /* 448 * Reset the chip to a known state. 449 */ 450 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 451 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 452 453 /* 454 * Read the Ethernet address from the EEPROM. 455 */ 456 for (i = 0; i < 3; i++) { 457 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 458 myea[i] = le16toh(myea[i]); 459 } 460 memcpy(enaddr, myea, sizeof(enaddr)); 461 462 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 463 ether_sprintf(enaddr)); 464 465 /* 466 * Initialize our media structures and probe the MII. 467 */ 468 sc->sc_mii.mii_ifp = ifp; 469 sc->sc_mii.mii_readreg = ste_mii_readreg; 470 sc->sc_mii.mii_writereg = ste_mii_writereg; 471 sc->sc_mii.mii_statchg = ste_mii_statchg; 472 sc->sc_ethercom.ec_mii = &sc->sc_mii; 473 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 474 ether_mediastatus); 475 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 476 MII_OFFSET_ANY, 0); 477 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 478 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 479 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 480 } else 481 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 482 483 ifp = &sc->sc_ethercom.ec_if; 484 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 485 ifp->if_softc = sc; 486 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 487 ifp->if_ioctl = ste_ioctl; 488 ifp->if_start = ste_start; 489 ifp->if_watchdog = ste_watchdog; 490 ifp->if_init = ste_init; 491 ifp->if_stop = ste_stop; 492 IFQ_SET_READY(&ifp->if_snd); 493 494 /* 495 * Default the transmit threshold to 128 bytes. 496 */ 497 sc->sc_txthresh = 128; 498 499 /* 500 * Disable MWI if the PCI layer tells us to. 501 */ 502 sc->sc_DMACtrl = 0; 503 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 504 sc->sc_DMACtrl |= DC_MWIDisable; 505 506 /* 507 * We can support 802.1Q VLAN-sized frames. 508 */ 509 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 510 511 /* 512 * Attach the interface. 513 */ 514 if_attach(ifp); 515 ether_ifattach(ifp, enaddr); 516 517 /* 518 * Make sure the interface is shutdown during reboot. 519 */ 520 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 521 if (sc->sc_sdhook == NULL) 522 printf("%s: WARNING: unable to establish shutdown hook\n", 523 device_xname(&sc->sc_dev)); 524 return; 525 526 /* 527 * Free any resources we've allocated during the failed attach 528 * attempt. Do this in reverse order and fall through. 529 */ 530 fail_5: 531 for (i = 0; i < STE_NRXDESC; i++) { 532 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 533 bus_dmamap_destroy(sc->sc_dmat, 534 sc->sc_rxsoft[i].ds_dmamap); 535 } 536 fail_4: 537 for (i = 0; i < STE_NTXDESC; i++) { 538 if (sc->sc_txsoft[i].ds_dmamap != NULL) 539 bus_dmamap_destroy(sc->sc_dmat, 540 sc->sc_txsoft[i].ds_dmamap); 541 } 542 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 543 fail_3: 544 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 545 fail_2: 546 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 547 sizeof(struct ste_control_data)); 548 fail_1: 549 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 550 fail_0: 551 return; 552 } 553 554 /* 555 * ste_shutdown: 556 * 557 * Make sure the interface is stopped at reboot time. 558 */ 559 static void 560 ste_shutdown(void *arg) 561 { 562 struct ste_softc *sc = arg; 563 564 ste_stop(&sc->sc_ethercom.ec_if, 1); 565 } 566 567 static void 568 ste_dmahalt_wait(struct ste_softc *sc) 569 { 570 int i; 571 572 for (i = 0; i < STE_TIMEOUT; i++) { 573 delay(2); 574 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 575 DC_DMAHaltBusy) == 0) 576 break; 577 } 578 579 if (i == STE_TIMEOUT) 580 printf("%s: DMA halt timed out\n", device_xname(&sc->sc_dev)); 581 } 582 583 /* 584 * ste_start: [ifnet interface function] 585 * 586 * Start packet transmission on the interface. 587 */ 588 static void 589 ste_start(struct ifnet *ifp) 590 { 591 struct ste_softc *sc = ifp->if_softc; 592 struct mbuf *m0, *m; 593 struct ste_descsoft *ds; 594 struct ste_tfd *tfd; 595 bus_dmamap_t dmamap; 596 int error, olasttx, nexttx, opending, seg, totlen; 597 598 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 599 return; 600 601 /* 602 * Remember the previous number of pending transmissions 603 * and the current last descriptor in the list. 604 */ 605 opending = sc->sc_txpending; 606 olasttx = sc->sc_txlast; 607 608 /* 609 * Loop through the send queue, setting up transmit descriptors 610 * until we drain the queue, or use up all available transmit 611 * descriptors. 612 */ 613 while (sc->sc_txpending < STE_NTXDESC) { 614 /* 615 * Grab a packet off the queue. 616 */ 617 IFQ_POLL(&ifp->if_snd, m0); 618 if (m0 == NULL) 619 break; 620 m = NULL; 621 622 /* 623 * Get the last and next available transmit descriptor. 624 */ 625 nexttx = STE_NEXTTX(sc->sc_txlast); 626 tfd = &sc->sc_txdescs[nexttx]; 627 ds = &sc->sc_txsoft[nexttx]; 628 629 dmamap = ds->ds_dmamap; 630 631 /* 632 * Load the DMA map. If this fails, the packet either 633 * didn't fit in the alloted number of segments, or we 634 * were short on resources. In this case, we'll copy 635 * and try again. 636 */ 637 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 638 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 639 MGETHDR(m, M_DONTWAIT, MT_DATA); 640 if (m == NULL) { 641 printf("%s: unable to allocate Tx mbuf\n", 642 device_xname(&sc->sc_dev)); 643 break; 644 } 645 if (m0->m_pkthdr.len > MHLEN) { 646 MCLGET(m, M_DONTWAIT); 647 if ((m->m_flags & M_EXT) == 0) { 648 printf("%s: unable to allocate Tx " 649 "cluster\n", device_xname(&sc->sc_dev)); 650 m_freem(m); 651 break; 652 } 653 } 654 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 655 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 656 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 657 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 658 if (error) { 659 printf("%s: unable to load Tx buffer, " 660 "error = %d\n", device_xname(&sc->sc_dev), error); 661 break; 662 } 663 } 664 665 IFQ_DEQUEUE(&ifp->if_snd, m0); 666 if (m != NULL) { 667 m_freem(m0); 668 m0 = m; 669 } 670 671 /* 672 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 673 */ 674 675 /* Sync the DMA map. */ 676 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 677 BUS_DMASYNC_PREWRITE); 678 679 /* Initialize the fragment list. */ 680 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 681 tfd->tfd_frags[seg].frag_addr = 682 htole32(dmamap->dm_segs[seg].ds_addr); 683 tfd->tfd_frags[seg].frag_len = 684 htole32(dmamap->dm_segs[seg].ds_len); 685 totlen += dmamap->dm_segs[seg].ds_len; 686 } 687 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 688 689 /* Initialize the descriptor. */ 690 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 691 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 692 693 /* Sync the descriptor. */ 694 STE_CDTXSYNC(sc, nexttx, 695 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 696 697 /* 698 * Store a pointer to the packet so we can free it later, 699 * and remember what txdirty will be once the packet is 700 * done. 701 */ 702 ds->ds_mbuf = m0; 703 704 /* Advance the tx pointer. */ 705 sc->sc_txpending++; 706 sc->sc_txlast = nexttx; 707 708 #if NBPFILTER > 0 709 /* 710 * Pass the packet to any BPF listeners. 711 */ 712 if (ifp->if_bpf) 713 bpf_mtap(ifp->if_bpf, m0); 714 #endif /* NBPFILTER > 0 */ 715 } 716 717 if (sc->sc_txpending == STE_NTXDESC) { 718 /* No more slots left; notify upper layer. */ 719 ifp->if_flags |= IFF_OACTIVE; 720 } 721 722 if (sc->sc_txpending != opending) { 723 /* 724 * We enqueued packets. If the transmitter was idle, 725 * reset the txdirty pointer. 726 */ 727 if (opending == 0) 728 sc->sc_txdirty = STE_NEXTTX(olasttx); 729 730 /* 731 * Cause a descriptor interrupt to happen on the 732 * last packet we enqueued, and also cause the 733 * DMA engine to wait after is has finished processing 734 * it. 735 */ 736 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 737 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 738 htole32(TFD_TxDMAIndicate); 739 STE_CDTXSYNC(sc, sc->sc_txlast, 740 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 741 742 /* 743 * Link up the new chain of descriptors to the 744 * last. 745 */ 746 sc->sc_txdescs[olasttx].tfd_next = 747 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 748 STE_CDTXSYNC(sc, olasttx, 749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 750 751 /* 752 * Kick the transmit DMA logic. Note that since we're 753 * using auto-polling, reading the Tx desc pointer will 754 * give it the nudge it needs to get going. 755 */ 756 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 757 STE_TxDMAListPtr) == 0) { 758 bus_space_write_4(sc->sc_st, sc->sc_sh, 759 STE_DMACtrl, DC_TxDMAHalt); 760 ste_dmahalt_wait(sc); 761 bus_space_write_4(sc->sc_st, sc->sc_sh, 762 STE_TxDMAListPtr, 763 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 764 bus_space_write_4(sc->sc_st, sc->sc_sh, 765 STE_DMACtrl, DC_TxDMAResume); 766 } 767 768 /* Set a watchdog timer in case the chip flakes out. */ 769 ifp->if_timer = 5; 770 } 771 } 772 773 /* 774 * ste_watchdog: [ifnet interface function] 775 * 776 * Watchdog timer handler. 777 */ 778 static void 779 ste_watchdog(struct ifnet *ifp) 780 { 781 struct ste_softc *sc = ifp->if_softc; 782 783 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 784 ifp->if_oerrors++; 785 786 ste_txintr(sc); 787 ste_rxintr(sc); 788 (void) ste_init(ifp); 789 790 /* Try to get more packets going. */ 791 ste_start(ifp); 792 } 793 794 /* 795 * ste_ioctl: [ifnet interface function] 796 * 797 * Handle control requests from the operator. 798 */ 799 static int 800 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 801 { 802 struct ste_softc *sc = ifp->if_softc; 803 int s, error; 804 805 s = splnet(); 806 807 error = ether_ioctl(ifp, cmd, data); 808 if (error == ENETRESET) { 809 /* 810 * Multicast list has changed; set the hardware filter 811 * accordingly. 812 */ 813 if (ifp->if_flags & IFF_RUNNING) 814 ste_set_filter(sc); 815 error = 0; 816 } 817 818 /* Try to get more packets going. */ 819 ste_start(ifp); 820 821 splx(s); 822 return (error); 823 } 824 825 /* 826 * ste_intr: 827 * 828 * Interrupt service routine. 829 */ 830 static int 831 ste_intr(void *arg) 832 { 833 struct ste_softc *sc = arg; 834 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 835 uint16_t isr; 836 uint8_t txstat; 837 int wantinit; 838 839 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 840 IS_InterruptStatus) == 0) 841 return (0); 842 843 for (wantinit = 0; wantinit == 0;) { 844 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 845 if ((isr & sc->sc_IntEnable) == 0) 846 break; 847 848 /* Receive interrupts. */ 849 if (isr & IE_RxDMAComplete) 850 ste_rxintr(sc); 851 852 /* Transmit interrupts. */ 853 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 854 ste_txintr(sc); 855 856 /* Statistics overflow. */ 857 if (isr & IE_UpdateStats) 858 ste_stats_update(sc); 859 860 /* Transmission errors. */ 861 if (isr & IE_TxComplete) { 862 for (;;) { 863 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 864 STE_TxStatus); 865 if ((txstat & TS_TxComplete) == 0) 866 break; 867 if (txstat & TS_TxUnderrun) { 868 sc->sc_txthresh += 32; 869 if (sc->sc_txthresh > 0x1ffc) 870 sc->sc_txthresh = 0x1ffc; 871 printf("%s: transmit underrun, new " 872 "threshold: %d bytes\n", 873 device_xname(&sc->sc_dev), 874 sc->sc_txthresh); 875 ste_reset(sc, AC_TxReset | AC_DMA | 876 AC_FIFO | AC_Network); 877 ste_setthresh(sc); 878 bus_space_write_1(sc->sc_st, sc->sc_sh, 879 STE_TxDMAPollPeriod, 127); 880 ste_txrestart(sc, 881 bus_space_read_1(sc->sc_st, 882 sc->sc_sh, STE_TxFrameId)); 883 } 884 if (txstat & TS_TxReleaseError) { 885 printf("%s: Tx FIFO release error\n", 886 device_xname(&sc->sc_dev)); 887 wantinit = 1; 888 } 889 if (txstat & TS_MaxCollisions) { 890 printf("%s: excessive collisions\n", 891 device_xname(&sc->sc_dev)); 892 wantinit = 1; 893 } 894 if (txstat & TS_TxStatusOverflow) { 895 printf("%s: status overflow\n", 896 device_xname(&sc->sc_dev)); 897 wantinit = 1; 898 } 899 bus_space_write_2(sc->sc_st, sc->sc_sh, 900 STE_TxStatus, 0); 901 } 902 } 903 904 /* Host interface errors. */ 905 if (isr & IE_HostError) { 906 printf("%s: Host interface error\n", 907 device_xname(&sc->sc_dev)); 908 wantinit = 1; 909 } 910 } 911 912 if (wantinit) 913 ste_init(ifp); 914 915 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 916 sc->sc_IntEnable); 917 918 /* Try to get more packets going. */ 919 ste_start(ifp); 920 921 return (1); 922 } 923 924 /* 925 * ste_txintr: 926 * 927 * Helper; handle transmit interrupts. 928 */ 929 static void 930 ste_txintr(struct ste_softc *sc) 931 { 932 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 933 struct ste_descsoft *ds; 934 uint32_t control; 935 int i; 936 937 ifp->if_flags &= ~IFF_OACTIVE; 938 939 /* 940 * Go through our Tx list and free mbufs for those 941 * frames which have been transmitted. 942 */ 943 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 944 i = STE_NEXTTX(i), sc->sc_txpending--) { 945 ds = &sc->sc_txsoft[i]; 946 947 STE_CDTXSYNC(sc, i, 948 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 949 950 control = le32toh(sc->sc_txdescs[i].tfd_control); 951 if ((control & TFD_TxDMAComplete) == 0) 952 break; 953 954 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 955 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 956 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 957 m_freem(ds->ds_mbuf); 958 ds->ds_mbuf = NULL; 959 } 960 961 /* Update the dirty transmit buffer pointer. */ 962 sc->sc_txdirty = i; 963 964 /* 965 * If there are no more pending transmissions, cancel the watchdog 966 * timer. 967 */ 968 if (sc->sc_txpending == 0) 969 ifp->if_timer = 0; 970 } 971 972 /* 973 * ste_rxintr: 974 * 975 * Helper; handle receive interrupts. 976 */ 977 static void 978 ste_rxintr(struct ste_softc *sc) 979 { 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 struct ste_descsoft *ds; 982 struct mbuf *m; 983 uint32_t status; 984 int i, len; 985 986 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 987 ds = &sc->sc_rxsoft[i]; 988 989 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 990 991 status = le32toh(sc->sc_rxdescs[i].rfd_status); 992 993 if ((status & RFD_RxDMAComplete) == 0) 994 break; 995 996 /* 997 * If the packet had an error, simply recycle the 998 * buffer. Note, we count the error later in the 999 * periodic stats update. 1000 */ 1001 if (status & RFD_RxFrameError) { 1002 STE_INIT_RXDESC(sc, i); 1003 continue; 1004 } 1005 1006 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1007 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1008 1009 /* 1010 * No errors; receive the packet. Note, we have 1011 * configured the chip to not include the CRC at 1012 * the end of the packet. 1013 */ 1014 len = RFD_RxDMAFrameLen(status); 1015 1016 /* 1017 * If the packet is small enough to fit in a 1018 * single header mbuf, allocate one and copy 1019 * the data into it. This greatly reduces 1020 * memory consumption when we receive lots 1021 * of small packets. 1022 * 1023 * Otherwise, we add a new buffer to the receive 1024 * chain. If this fails, we drop the packet and 1025 * recycle the old buffer. 1026 */ 1027 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1028 MGETHDR(m, M_DONTWAIT, MT_DATA); 1029 if (m == NULL) 1030 goto dropit; 1031 m->m_data += 2; 1032 memcpy(mtod(m, void *), 1033 mtod(ds->ds_mbuf, void *), len); 1034 STE_INIT_RXDESC(sc, i); 1035 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1036 ds->ds_dmamap->dm_mapsize, 1037 BUS_DMASYNC_PREREAD); 1038 } else { 1039 m = ds->ds_mbuf; 1040 if (ste_add_rxbuf(sc, i) != 0) { 1041 dropit: 1042 ifp->if_ierrors++; 1043 STE_INIT_RXDESC(sc, i); 1044 bus_dmamap_sync(sc->sc_dmat, 1045 ds->ds_dmamap, 0, 1046 ds->ds_dmamap->dm_mapsize, 1047 BUS_DMASYNC_PREREAD); 1048 continue; 1049 } 1050 } 1051 1052 m->m_pkthdr.rcvif = ifp; 1053 m->m_pkthdr.len = m->m_len = len; 1054 1055 #if NBPFILTER > 0 1056 /* 1057 * Pass this up to any BPF listeners, but only 1058 * pass if up the stack if it's for us. 1059 */ 1060 if (ifp->if_bpf) 1061 bpf_mtap(ifp->if_bpf, m); 1062 #endif /* NBPFILTER > 0 */ 1063 1064 /* Pass it on. */ 1065 (*ifp->if_input)(ifp, m); 1066 } 1067 1068 /* Update the receive pointer. */ 1069 sc->sc_rxptr = i; 1070 } 1071 1072 /* 1073 * ste_tick: 1074 * 1075 * One second timer, used to tick the MII. 1076 */ 1077 static void 1078 ste_tick(void *arg) 1079 { 1080 struct ste_softc *sc = arg; 1081 int s; 1082 1083 s = splnet(); 1084 mii_tick(&sc->sc_mii); 1085 ste_stats_update(sc); 1086 splx(s); 1087 1088 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1089 } 1090 1091 /* 1092 * ste_stats_update: 1093 * 1094 * Read the ST-201 statistics counters. 1095 */ 1096 static void 1097 ste_stats_update(struct ste_softc *sc) 1098 { 1099 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1100 bus_space_tag_t st = sc->sc_st; 1101 bus_space_handle_t sh = sc->sc_sh; 1102 1103 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1104 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1105 1106 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1107 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1108 1109 ifp->if_opackets += 1110 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1111 ifp->if_ipackets += 1112 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1113 1114 ifp->if_collisions += 1115 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1116 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1117 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1118 1119 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1120 1121 ifp->if_ierrors += 1122 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1123 1124 ifp->if_oerrors += 1125 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1126 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1127 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1128 1129 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1130 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1131 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1132 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1133 } 1134 1135 /* 1136 * ste_reset: 1137 * 1138 * Perform a soft reset on the ST-201. 1139 */ 1140 static void 1141 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1142 { 1143 uint32_t ac; 1144 int i; 1145 1146 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1147 1148 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1149 1150 delay(50000); 1151 1152 for (i = 0; i < STE_TIMEOUT; i++) { 1153 delay(1000); 1154 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1155 AC_ResetBusy) == 0) 1156 break; 1157 } 1158 1159 if (i == STE_TIMEOUT) 1160 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1161 1162 delay(1000); 1163 } 1164 1165 /* 1166 * ste_setthresh: 1167 * 1168 * set the various transmit threshold registers 1169 */ 1170 static void 1171 ste_setthresh(struct ste_softc *sc) 1172 { 1173 /* set the TX threhold */ 1174 bus_space_write_2(sc->sc_st, sc->sc_sh, 1175 STE_TxStartThresh, sc->sc_txthresh); 1176 /* Urgent threshold: set to sc_txthresh / 2 */ 1177 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1178 sc->sc_txthresh >> 6); 1179 /* Burst threshold: use default value (256 bytes) */ 1180 } 1181 1182 /* 1183 * restart TX at the given frame ID in the transmitter ring 1184 */ 1185 static void 1186 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1187 { 1188 u_int32_t control; 1189 1190 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1191 control = le32toh(sc->sc_txdescs[id].tfd_control); 1192 control &= ~TFD_TxDMAComplete; 1193 sc->sc_txdescs[id].tfd_control = htole32(control); 1194 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1195 1196 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1197 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1198 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1199 ste_dmahalt_wait(sc); 1200 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1201 STE_CDTXADDR(sc, id)); 1202 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1203 } 1204 1205 /* 1206 * ste_init: [ ifnet interface function ] 1207 * 1208 * Initialize the interface. Must be called at splnet(). 1209 */ 1210 static int 1211 ste_init(struct ifnet *ifp) 1212 { 1213 struct ste_softc *sc = ifp->if_softc; 1214 bus_space_tag_t st = sc->sc_st; 1215 bus_space_handle_t sh = sc->sc_sh; 1216 struct ste_descsoft *ds; 1217 int i, error = 0; 1218 1219 /* 1220 * Cancel any pending I/O. 1221 */ 1222 ste_stop(ifp, 0); 1223 1224 /* 1225 * Reset the chip to a known state. 1226 */ 1227 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1228 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1229 1230 /* 1231 * Initialize the transmit descriptor ring. 1232 */ 1233 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1234 sc->sc_txpending = 0; 1235 sc->sc_txdirty = 0; 1236 sc->sc_txlast = STE_NTXDESC - 1; 1237 1238 /* 1239 * Initialize the receive descriptor and receive job 1240 * descriptor rings. 1241 */ 1242 for (i = 0; i < STE_NRXDESC; i++) { 1243 ds = &sc->sc_rxsoft[i]; 1244 if (ds->ds_mbuf == NULL) { 1245 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1246 printf("%s: unable to allocate or map rx " 1247 "buffer %d, error = %d\n", 1248 device_xname(&sc->sc_dev), i, error); 1249 /* 1250 * XXX Should attempt to run with fewer receive 1251 * XXX buffers instead of just failing. 1252 */ 1253 ste_rxdrain(sc); 1254 goto out; 1255 } 1256 } else 1257 STE_INIT_RXDESC(sc, i); 1258 } 1259 sc->sc_rxptr = 0; 1260 1261 /* Set the station address. */ 1262 for (i = 0; i < ETHER_ADDR_LEN; i++) 1263 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1264 CLLADDR(ifp->if_sadl)[i]); 1265 1266 /* Set up the receive filter. */ 1267 ste_set_filter(sc); 1268 1269 /* 1270 * Give the receive ring to the chip. 1271 */ 1272 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1273 STE_CDRXADDR(sc, sc->sc_rxptr)); 1274 1275 /* 1276 * We defer giving the transmit ring to the chip until we 1277 * transmit the first packet. 1278 */ 1279 1280 /* 1281 * Initialize the Tx auto-poll period. It's OK to make this number 1282 * large (127 is the max) -- we explicitly kick the transmit engine 1283 * when there's actually a packet. We are using auto-polling only 1284 * to make the interface to the transmit engine not suck. 1285 */ 1286 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1287 1288 /* ..and the Rx auto-poll period. */ 1289 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1290 1291 /* Initialize the Tx start threshold. */ 1292 ste_setthresh(sc); 1293 1294 /* Set the FIFO release threshold to 512 bytes. */ 1295 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1296 1297 /* Set maximum packet size for VLAN. */ 1298 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1299 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1300 else 1301 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1302 1303 /* 1304 * Initialize the interrupt mask. 1305 */ 1306 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1307 IE_TxDMAComplete | IE_RxDMAComplete; 1308 1309 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1310 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1311 1312 /* 1313 * Start the receive DMA engine. 1314 */ 1315 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1316 1317 /* 1318 * Initialize MacCtrl0 -- do it before setting the media, 1319 * as setting the media will actually program the register. 1320 */ 1321 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1322 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1323 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1324 1325 /* 1326 * Set the current media. 1327 */ 1328 if ((error = ether_mediachange(ifp)) != 0) 1329 goto out; 1330 1331 /* 1332 * Start the MAC. 1333 */ 1334 bus_space_write_2(st, sh, STE_MacCtrl1, 1335 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1336 1337 /* 1338 * Start the one second MII clock. 1339 */ 1340 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1341 1342 /* 1343 * ...all done! 1344 */ 1345 ifp->if_flags |= IFF_RUNNING; 1346 ifp->if_flags &= ~IFF_OACTIVE; 1347 1348 out: 1349 if (error) 1350 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1351 return (error); 1352 } 1353 1354 /* 1355 * ste_drain: 1356 * 1357 * Drain the receive queue. 1358 */ 1359 static void 1360 ste_rxdrain(struct ste_softc *sc) 1361 { 1362 struct ste_descsoft *ds; 1363 int i; 1364 1365 for (i = 0; i < STE_NRXDESC; i++) { 1366 ds = &sc->sc_rxsoft[i]; 1367 if (ds->ds_mbuf != NULL) { 1368 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1369 m_freem(ds->ds_mbuf); 1370 ds->ds_mbuf = NULL; 1371 } 1372 } 1373 } 1374 1375 /* 1376 * ste_stop: [ ifnet interface function ] 1377 * 1378 * Stop transmission on the interface. 1379 */ 1380 static void 1381 ste_stop(struct ifnet *ifp, int disable) 1382 { 1383 struct ste_softc *sc = ifp->if_softc; 1384 struct ste_descsoft *ds; 1385 int i; 1386 1387 /* 1388 * Stop the one second clock. 1389 */ 1390 callout_stop(&sc->sc_tick_ch); 1391 1392 /* Down the MII. */ 1393 mii_down(&sc->sc_mii); 1394 1395 /* 1396 * Disable interrupts. 1397 */ 1398 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1399 1400 /* 1401 * Stop receiver, transmitter, and stats update. 1402 */ 1403 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1404 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1405 1406 /* 1407 * Stop the transmit and receive DMA. 1408 */ 1409 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1410 DC_RxDMAHalt | DC_TxDMAHalt); 1411 ste_dmahalt_wait(sc); 1412 1413 /* 1414 * Release any queued transmit buffers. 1415 */ 1416 for (i = 0; i < STE_NTXDESC; i++) { 1417 ds = &sc->sc_txsoft[i]; 1418 if (ds->ds_mbuf != NULL) { 1419 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1420 m_freem(ds->ds_mbuf); 1421 ds->ds_mbuf = NULL; 1422 } 1423 } 1424 1425 /* 1426 * Mark the interface down and cancel the watchdog timer. 1427 */ 1428 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1429 ifp->if_timer = 0; 1430 1431 if (disable) 1432 ste_rxdrain(sc); 1433 } 1434 1435 static int 1436 ste_eeprom_wait(struct ste_softc *sc) 1437 { 1438 int i; 1439 1440 for (i = 0; i < STE_TIMEOUT; i++) { 1441 delay(1000); 1442 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1443 EC_EepromBusy) == 0) 1444 return (0); 1445 } 1446 return (1); 1447 } 1448 1449 /* 1450 * ste_read_eeprom: 1451 * 1452 * Read data from the serial EEPROM. 1453 */ 1454 static void 1455 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1456 { 1457 1458 if (ste_eeprom_wait(sc)) 1459 printf("%s: EEPROM failed to come ready\n", 1460 device_xname(&sc->sc_dev)); 1461 1462 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1463 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1464 if (ste_eeprom_wait(sc)) 1465 printf("%s: EEPROM read timed out\n", 1466 device_xname(&sc->sc_dev)); 1467 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1468 } 1469 1470 /* 1471 * ste_add_rxbuf: 1472 * 1473 * Add a receive buffer to the indicated descriptor. 1474 */ 1475 static int 1476 ste_add_rxbuf(struct ste_softc *sc, int idx) 1477 { 1478 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1479 struct mbuf *m; 1480 int error; 1481 1482 MGETHDR(m, M_DONTWAIT, MT_DATA); 1483 if (m == NULL) 1484 return (ENOBUFS); 1485 1486 MCLGET(m, M_DONTWAIT); 1487 if ((m->m_flags & M_EXT) == 0) { 1488 m_freem(m); 1489 return (ENOBUFS); 1490 } 1491 1492 if (ds->ds_mbuf != NULL) 1493 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1494 1495 ds->ds_mbuf = m; 1496 1497 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1498 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1499 BUS_DMA_READ|BUS_DMA_NOWAIT); 1500 if (error) { 1501 printf("%s: can't load rx DMA map %d, error = %d\n", 1502 device_xname(&sc->sc_dev), idx, error); 1503 panic("ste_add_rxbuf"); /* XXX */ 1504 } 1505 1506 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1507 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1508 1509 STE_INIT_RXDESC(sc, idx); 1510 1511 return (0); 1512 } 1513 1514 /* 1515 * ste_set_filter: 1516 * 1517 * Set up the receive filter. 1518 */ 1519 static void 1520 ste_set_filter(struct ste_softc *sc) 1521 { 1522 struct ethercom *ec = &sc->sc_ethercom; 1523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1524 struct ether_multi *enm; 1525 struct ether_multistep step; 1526 uint32_t crc; 1527 uint16_t mchash[4]; 1528 1529 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1530 if (ifp->if_flags & IFF_BROADCAST) 1531 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1532 1533 if (ifp->if_flags & IFF_PROMISC) { 1534 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1535 goto allmulti; 1536 } 1537 1538 /* 1539 * Set up the multicast address filter by passing all multicast 1540 * addresses through a CRC generator, and then using the low-order 1541 * 6 bits as an index into the 64 bit multicast hash table. The 1542 * high order bits select the register, while the rest of the bits 1543 * select the bit within the register. 1544 */ 1545 1546 memset(mchash, 0, sizeof(mchash)); 1547 1548 ETHER_FIRST_MULTI(step, ec, enm); 1549 if (enm == NULL) 1550 goto done; 1551 1552 while (enm != NULL) { 1553 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1554 /* 1555 * We must listen to a range of multicast addresses. 1556 * For now, just accept all multicasts, rather than 1557 * trying to set only those filter bits needed to match 1558 * the range. (At this time, the only use of address 1559 * ranges is for IP multicast routing, for which the 1560 * range is big enough to require all bits set.) 1561 */ 1562 goto allmulti; 1563 } 1564 1565 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1566 1567 /* Just want the 6 least significant bits. */ 1568 crc &= 0x3f; 1569 1570 /* Set the corresponding bit in the hash table. */ 1571 mchash[crc >> 4] |= 1 << (crc & 0xf); 1572 1573 ETHER_NEXT_MULTI(step, enm); 1574 } 1575 1576 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1577 1578 ifp->if_flags &= ~IFF_ALLMULTI; 1579 goto done; 1580 1581 allmulti: 1582 ifp->if_flags |= IFF_ALLMULTI; 1583 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1584 1585 done: 1586 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1587 /* 1588 * Program the multicast hash table. 1589 */ 1590 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1591 mchash[0]); 1592 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1593 mchash[1]); 1594 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1595 mchash[2]); 1596 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1597 mchash[3]); 1598 } 1599 1600 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1601 sc->sc_ReceiveMode); 1602 } 1603 1604 /* 1605 * ste_mii_readreg: [mii interface function] 1606 * 1607 * Read a PHY register on the MII of the ST-201. 1608 */ 1609 static int 1610 ste_mii_readreg(device_t self, int phy, int reg) 1611 { 1612 1613 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1614 } 1615 1616 /* 1617 * ste_mii_writereg: [mii interface function] 1618 * 1619 * Write a PHY register on the MII of the ST-201. 1620 */ 1621 static void 1622 ste_mii_writereg(device_t self, int phy, int reg, int val) 1623 { 1624 1625 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1626 } 1627 1628 /* 1629 * ste_mii_statchg: [mii interface function] 1630 * 1631 * Callback from MII layer when media changes. 1632 */ 1633 static void 1634 ste_mii_statchg(device_t self) 1635 { 1636 struct ste_softc *sc = device_private(self); 1637 1638 if (sc->sc_mii.mii_media_active & IFM_FDX) 1639 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1640 else 1641 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1642 1643 /* XXX 802.1x flow-control? */ 1644 1645 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1646 } 1647 1648 /* 1649 * ste_mii_bitbang_read: [mii bit-bang interface function] 1650 * 1651 * Read the MII serial port for the MII bit-bang module. 1652 */ 1653 static uint32_t 1654 ste_mii_bitbang_read(device_t self) 1655 { 1656 struct ste_softc *sc = device_private(self); 1657 1658 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1659 } 1660 1661 /* 1662 * ste_mii_bitbang_write: [mii big-bang interface function] 1663 * 1664 * Write the MII serial port for the MII bit-bang module. 1665 */ 1666 static void 1667 ste_mii_bitbang_write(device_t self, uint32_t val) 1668 { 1669 struct ste_softc *sc = device_private(self); 1670 1671 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1672 } 1673