1 /* $NetBSD: if_ste.c,v 1.40 2010/01/19 22:07:01 pooka Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.40 2010/01/19 22:07:01 pooka Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/mii/mii_bitbang.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_stereg.h> 74 75 /* 76 * Transmit descriptor list size. 77 */ 78 #define STE_NTXDESC 256 79 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 80 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 81 82 /* 83 * Receive descriptor list size. 84 */ 85 #define STE_NRXDESC 128 86 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 87 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 88 89 /* 90 * Control structures are DMA'd to the ST-201 chip. We allocate them in 91 * a single clump that maps to a single DMA segment to make several things 92 * easier. 93 */ 94 struct ste_control_data { 95 /* 96 * The transmit descriptors. 97 */ 98 struct ste_tfd scd_txdescs[STE_NTXDESC]; 99 100 /* 101 * The receive descriptors. 102 */ 103 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 104 }; 105 106 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 107 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 108 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 109 110 /* 111 * Software state for transmit and receive jobs. 112 */ 113 struct ste_descsoft { 114 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 115 bus_dmamap_t ds_dmamap; /* our DMA map */ 116 }; 117 118 /* 119 * Software state per device. 120 */ 121 struct ste_softc { 122 struct device sc_dev; /* generic device information */ 123 bus_space_tag_t sc_st; /* bus space tag */ 124 bus_space_handle_t sc_sh; /* bus space handle */ 125 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 126 struct ethercom sc_ethercom; /* ethernet common data */ 127 128 void *sc_ih; /* interrupt cookie */ 129 130 struct mii_data sc_mii; /* MII/media information */ 131 132 callout_t sc_tick_ch; /* tick callout */ 133 134 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 135 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 136 137 /* 138 * Software state for transmit and receive descriptors. 139 */ 140 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 141 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 142 143 /* 144 * Control data structures. 145 */ 146 struct ste_control_data *sc_control_data; 147 #define sc_txdescs sc_control_data->scd_txdescs 148 #define sc_rxdescs sc_control_data->scd_rxdescs 149 150 int sc_txpending; /* number of Tx requests pending */ 151 int sc_txdirty; /* first dirty Tx descriptor */ 152 int sc_txlast; /* last used Tx descriptor */ 153 154 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 155 156 int sc_txthresh; /* Tx threshold */ 157 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 158 uint16_t sc_IntEnable; /* prototype IntEnable register */ 159 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 160 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 161 }; 162 163 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 164 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 165 166 #define STE_CDTXSYNC(sc, x, ops) \ 167 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 168 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 169 170 #define STE_CDRXSYNC(sc, x, ops) \ 171 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 172 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 173 174 #define STE_INIT_RXDESC(sc, x) \ 175 do { \ 176 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 177 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 178 struct mbuf *__m = __ds->ds_mbuf; \ 179 \ 180 /* \ 181 * Note: We scoot the packet forward 2 bytes in the buffer \ 182 * so that the payload after the Ethernet header is aligned \ 183 * to a 4-byte boundary. \ 184 */ \ 185 __m->m_data = __m->m_ext.ext_buf + 2; \ 186 __rfd->rfd_frag.frag_addr = \ 187 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 188 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 189 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 190 __rfd->rfd_status = 0; \ 191 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 192 } while (/*CONSTCOND*/0) 193 194 #define STE_TIMEOUT 1000 195 196 static void ste_start(struct ifnet *); 197 static void ste_watchdog(struct ifnet *); 198 static int ste_ioctl(struct ifnet *, u_long, void *); 199 static int ste_init(struct ifnet *); 200 static void ste_stop(struct ifnet *, int); 201 202 static bool ste_shutdown(device_t, int); 203 204 static void ste_reset(struct ste_softc *, u_int32_t); 205 static void ste_setthresh(struct ste_softc *); 206 static void ste_txrestart(struct ste_softc *, u_int8_t); 207 static void ste_rxdrain(struct ste_softc *); 208 static int ste_add_rxbuf(struct ste_softc *, int); 209 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 210 static void ste_tick(void *); 211 212 static void ste_stats_update(struct ste_softc *); 213 214 static void ste_set_filter(struct ste_softc *); 215 216 static int ste_intr(void *); 217 static void ste_txintr(struct ste_softc *); 218 static void ste_rxintr(struct ste_softc *); 219 220 static int ste_mii_readreg(device_t, int, int); 221 static void ste_mii_writereg(device_t, int, int, int); 222 static void ste_mii_statchg(device_t); 223 224 static int ste_match(device_t, cfdata_t, void *); 225 static void ste_attach(device_t, device_t, void *); 226 227 int ste_copy_small = 0; 228 229 CFATTACH_DECL(ste, sizeof(struct ste_softc), 230 ste_match, ste_attach, NULL, NULL); 231 232 static uint32_t ste_mii_bitbang_read(device_t); 233 static void ste_mii_bitbang_write(device_t, uint32_t); 234 235 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 236 ste_mii_bitbang_read, 237 ste_mii_bitbang_write, 238 { 239 PC_MgmtData, /* MII_BIT_MDO */ 240 PC_MgmtData, /* MII_BIT_MDI */ 241 PC_MgmtClk, /* MII_BIT_MDC */ 242 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 243 0, /* MII_BIT_DIR_PHY_HOST */ 244 } 245 }; 246 247 /* 248 * Devices supported by this driver. 249 */ 250 static const struct ste_product { 251 pci_vendor_id_t ste_vendor; 252 pci_product_id_t ste_product; 253 const char *ste_name; 254 } ste_products[] = { 255 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 256 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 257 258 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 259 "Sundance ST-201 10/100 Ethernet" }, 260 261 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 262 "D-Link DL-1002 10/100 Ethernet" }, 263 264 { 0, 0, 265 NULL }, 266 }; 267 268 static const struct ste_product * 269 ste_lookup(const struct pci_attach_args *pa) 270 { 271 const struct ste_product *sp; 272 273 for (sp = ste_products; sp->ste_name != NULL; sp++) { 274 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 275 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 276 return (sp); 277 } 278 return (NULL); 279 } 280 281 static int 282 ste_match(device_t parent, cfdata_t cf, void *aux) 283 { 284 struct pci_attach_args *pa = aux; 285 286 if (ste_lookup(pa) != NULL) 287 return (1); 288 289 return (0); 290 } 291 292 static void 293 ste_attach(device_t parent, device_t self, void *aux) 294 { 295 struct ste_softc *sc = device_private(self); 296 struct pci_attach_args *pa = aux; 297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 298 pci_chipset_tag_t pc = pa->pa_pc; 299 pci_intr_handle_t ih; 300 const char *intrstr = NULL; 301 bus_space_tag_t iot, memt; 302 bus_space_handle_t ioh, memh; 303 bus_dma_segment_t seg; 304 int ioh_valid, memh_valid; 305 int i, rseg, error; 306 const struct ste_product *sp; 307 uint8_t enaddr[ETHER_ADDR_LEN]; 308 uint16_t myea[ETHER_ADDR_LEN / 2]; 309 310 callout_init(&sc->sc_tick_ch, 0); 311 312 sp = ste_lookup(pa); 313 if (sp == NULL) { 314 printf("\n"); 315 panic("ste_attach: impossible"); 316 } 317 318 printf(": %s\n", sp->ste_name); 319 320 /* 321 * Map the device. 322 */ 323 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 324 PCI_MAPREG_TYPE_IO, 0, 325 &iot, &ioh, NULL, NULL) == 0); 326 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 327 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 328 &memt, &memh, NULL, NULL) == 0); 329 330 if (memh_valid) { 331 sc->sc_st = memt; 332 sc->sc_sh = memh; 333 } else if (ioh_valid) { 334 sc->sc_st = iot; 335 sc->sc_sh = ioh; 336 } else { 337 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 338 return; 339 } 340 341 sc->sc_dmat = pa->pa_dmat; 342 343 /* Enable bus mastering. */ 344 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 345 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 346 PCI_COMMAND_MASTER_ENABLE); 347 348 /* power up chip */ 349 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 350 NULL)) && error != EOPNOTSUPP) { 351 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 352 error); 353 return; 354 } 355 356 /* 357 * Map and establish our interrupt. 358 */ 359 if (pci_intr_map(pa, &ih)) { 360 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 361 return; 362 } 363 intrstr = pci_intr_string(pc, ih); 364 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 365 if (sc->sc_ih == NULL) { 366 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 367 if (intrstr != NULL) 368 aprint_error(" at %s", intrstr); 369 aprint_error("\n"); 370 return; 371 } 372 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 373 374 /* 375 * Allocate the control data structures, and create and load the 376 * DMA map for it. 377 */ 378 if ((error = bus_dmamem_alloc(sc->sc_dmat, 379 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 380 0)) != 0) { 381 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 382 error); 383 goto fail_0; 384 } 385 386 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 387 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 388 BUS_DMA_COHERENT)) != 0) { 389 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 390 error); 391 goto fail_1; 392 } 393 394 if ((error = bus_dmamap_create(sc->sc_dmat, 395 sizeof(struct ste_control_data), 1, 396 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 397 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 398 "error = %d\n", error); 399 goto fail_2; 400 } 401 402 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 403 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 404 0)) != 0) { 405 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 406 error); 407 goto fail_3; 408 } 409 410 /* 411 * Create the transmit buffer DMA maps. 412 */ 413 for (i = 0; i < STE_NTXDESC; i++) { 414 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 415 STE_NTXFRAGS, MCLBYTES, 0, 0, 416 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 417 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 418 "error = %d\n", i, error); 419 goto fail_4; 420 } 421 } 422 423 /* 424 * Create the receive buffer DMA maps. 425 */ 426 for (i = 0; i < STE_NRXDESC; i++) { 427 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 428 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 429 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 430 "error = %d\n", i, error); 431 goto fail_5; 432 } 433 sc->sc_rxsoft[i].ds_mbuf = NULL; 434 } 435 436 /* 437 * Reset the chip to a known state. 438 */ 439 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 440 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 441 442 /* 443 * Read the Ethernet address from the EEPROM. 444 */ 445 for (i = 0; i < 3; i++) { 446 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 447 myea[i] = le16toh(myea[i]); 448 } 449 memcpy(enaddr, myea, sizeof(enaddr)); 450 451 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 452 ether_sprintf(enaddr)); 453 454 /* 455 * Initialize our media structures and probe the MII. 456 */ 457 sc->sc_mii.mii_ifp = ifp; 458 sc->sc_mii.mii_readreg = ste_mii_readreg; 459 sc->sc_mii.mii_writereg = ste_mii_writereg; 460 sc->sc_mii.mii_statchg = ste_mii_statchg; 461 sc->sc_ethercom.ec_mii = &sc->sc_mii; 462 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 463 ether_mediastatus); 464 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 465 MII_OFFSET_ANY, 0); 466 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 467 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 468 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 469 } else 470 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 471 472 ifp = &sc->sc_ethercom.ec_if; 473 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 474 ifp->if_softc = sc; 475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 476 ifp->if_ioctl = ste_ioctl; 477 ifp->if_start = ste_start; 478 ifp->if_watchdog = ste_watchdog; 479 ifp->if_init = ste_init; 480 ifp->if_stop = ste_stop; 481 IFQ_SET_READY(&ifp->if_snd); 482 483 /* 484 * Default the transmit threshold to 128 bytes. 485 */ 486 sc->sc_txthresh = 128; 487 488 /* 489 * Disable MWI if the PCI layer tells us to. 490 */ 491 sc->sc_DMACtrl = 0; 492 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 493 sc->sc_DMACtrl |= DC_MWIDisable; 494 495 /* 496 * We can support 802.1Q VLAN-sized frames. 497 */ 498 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 499 500 /* 501 * Attach the interface. 502 */ 503 if_attach(ifp); 504 ether_ifattach(ifp, enaddr); 505 506 /* 507 * Make sure the interface is shutdown during reboot. 508 */ 509 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 510 pmf_class_network_register(self, ifp); 511 else 512 aprint_error_dev(self, "couldn't establish power handler\n"); 513 514 return; 515 516 /* 517 * Free any resources we've allocated during the failed attach 518 * attempt. Do this in reverse order and fall through. 519 */ 520 fail_5: 521 for (i = 0; i < STE_NRXDESC; i++) { 522 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 523 bus_dmamap_destroy(sc->sc_dmat, 524 sc->sc_rxsoft[i].ds_dmamap); 525 } 526 fail_4: 527 for (i = 0; i < STE_NTXDESC; i++) { 528 if (sc->sc_txsoft[i].ds_dmamap != NULL) 529 bus_dmamap_destroy(sc->sc_dmat, 530 sc->sc_txsoft[i].ds_dmamap); 531 } 532 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 533 fail_3: 534 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 535 fail_2: 536 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 537 sizeof(struct ste_control_data)); 538 fail_1: 539 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 540 fail_0: 541 return; 542 } 543 544 /* 545 * ste_shutdown: 546 * 547 * Make sure the interface is stopped at reboot time. 548 */ 549 static bool 550 ste_shutdown(device_t self, int howto) 551 { 552 struct ste_softc *sc; 553 554 sc = device_private(self); 555 ste_stop(&sc->sc_ethercom.ec_if, 1); 556 557 return true; 558 } 559 560 static void 561 ste_dmahalt_wait(struct ste_softc *sc) 562 { 563 int i; 564 565 for (i = 0; i < STE_TIMEOUT; i++) { 566 delay(2); 567 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 568 DC_DMAHaltBusy) == 0) 569 break; 570 } 571 572 if (i == STE_TIMEOUT) 573 printf("%s: DMA halt timed out\n", device_xname(&sc->sc_dev)); 574 } 575 576 /* 577 * ste_start: [ifnet interface function] 578 * 579 * Start packet transmission on the interface. 580 */ 581 static void 582 ste_start(struct ifnet *ifp) 583 { 584 struct ste_softc *sc = ifp->if_softc; 585 struct mbuf *m0, *m; 586 struct ste_descsoft *ds; 587 struct ste_tfd *tfd; 588 bus_dmamap_t dmamap; 589 int error, olasttx, nexttx, opending, seg, totlen; 590 591 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 592 return; 593 594 /* 595 * Remember the previous number of pending transmissions 596 * and the current last descriptor in the list. 597 */ 598 opending = sc->sc_txpending; 599 olasttx = sc->sc_txlast; 600 601 /* 602 * Loop through the send queue, setting up transmit descriptors 603 * until we drain the queue, or use up all available transmit 604 * descriptors. 605 */ 606 while (sc->sc_txpending < STE_NTXDESC) { 607 /* 608 * Grab a packet off the queue. 609 */ 610 IFQ_POLL(&ifp->if_snd, m0); 611 if (m0 == NULL) 612 break; 613 m = NULL; 614 615 /* 616 * Get the last and next available transmit descriptor. 617 */ 618 nexttx = STE_NEXTTX(sc->sc_txlast); 619 tfd = &sc->sc_txdescs[nexttx]; 620 ds = &sc->sc_txsoft[nexttx]; 621 622 dmamap = ds->ds_dmamap; 623 624 /* 625 * Load the DMA map. If this fails, the packet either 626 * didn't fit in the alloted number of segments, or we 627 * were short on resources. In this case, we'll copy 628 * and try again. 629 */ 630 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 631 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 632 MGETHDR(m, M_DONTWAIT, MT_DATA); 633 if (m == NULL) { 634 printf("%s: unable to allocate Tx mbuf\n", 635 device_xname(&sc->sc_dev)); 636 break; 637 } 638 if (m0->m_pkthdr.len > MHLEN) { 639 MCLGET(m, M_DONTWAIT); 640 if ((m->m_flags & M_EXT) == 0) { 641 printf("%s: unable to allocate Tx " 642 "cluster\n", device_xname(&sc->sc_dev)); 643 m_freem(m); 644 break; 645 } 646 } 647 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 648 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 649 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 650 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 651 if (error) { 652 printf("%s: unable to load Tx buffer, " 653 "error = %d\n", device_xname(&sc->sc_dev), error); 654 break; 655 } 656 } 657 658 IFQ_DEQUEUE(&ifp->if_snd, m0); 659 if (m != NULL) { 660 m_freem(m0); 661 m0 = m; 662 } 663 664 /* 665 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 666 */ 667 668 /* Sync the DMA map. */ 669 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 /* Initialize the fragment list. */ 673 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 674 tfd->tfd_frags[seg].frag_addr = 675 htole32(dmamap->dm_segs[seg].ds_addr); 676 tfd->tfd_frags[seg].frag_len = 677 htole32(dmamap->dm_segs[seg].ds_len); 678 totlen += dmamap->dm_segs[seg].ds_len; 679 } 680 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 681 682 /* Initialize the descriptor. */ 683 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 684 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 685 686 /* Sync the descriptor. */ 687 STE_CDTXSYNC(sc, nexttx, 688 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 689 690 /* 691 * Store a pointer to the packet so we can free it later, 692 * and remember what txdirty will be once the packet is 693 * done. 694 */ 695 ds->ds_mbuf = m0; 696 697 /* Advance the tx pointer. */ 698 sc->sc_txpending++; 699 sc->sc_txlast = nexttx; 700 701 /* 702 * Pass the packet to any BPF listeners. 703 */ 704 if (ifp->if_bpf) 705 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 706 } 707 708 if (sc->sc_txpending == STE_NTXDESC) { 709 /* No more slots left; notify upper layer. */ 710 ifp->if_flags |= IFF_OACTIVE; 711 } 712 713 if (sc->sc_txpending != opending) { 714 /* 715 * We enqueued packets. If the transmitter was idle, 716 * reset the txdirty pointer. 717 */ 718 if (opending == 0) 719 sc->sc_txdirty = STE_NEXTTX(olasttx); 720 721 /* 722 * Cause a descriptor interrupt to happen on the 723 * last packet we enqueued, and also cause the 724 * DMA engine to wait after is has finished processing 725 * it. 726 */ 727 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 728 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 729 htole32(TFD_TxDMAIndicate); 730 STE_CDTXSYNC(sc, sc->sc_txlast, 731 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 732 733 /* 734 * Link up the new chain of descriptors to the 735 * last. 736 */ 737 sc->sc_txdescs[olasttx].tfd_next = 738 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 739 STE_CDTXSYNC(sc, olasttx, 740 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 741 742 /* 743 * Kick the transmit DMA logic. Note that since we're 744 * using auto-polling, reading the Tx desc pointer will 745 * give it the nudge it needs to get going. 746 */ 747 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 748 STE_TxDMAListPtr) == 0) { 749 bus_space_write_4(sc->sc_st, sc->sc_sh, 750 STE_DMACtrl, DC_TxDMAHalt); 751 ste_dmahalt_wait(sc); 752 bus_space_write_4(sc->sc_st, sc->sc_sh, 753 STE_TxDMAListPtr, 754 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 755 bus_space_write_4(sc->sc_st, sc->sc_sh, 756 STE_DMACtrl, DC_TxDMAResume); 757 } 758 759 /* Set a watchdog timer in case the chip flakes out. */ 760 ifp->if_timer = 5; 761 } 762 } 763 764 /* 765 * ste_watchdog: [ifnet interface function] 766 * 767 * Watchdog timer handler. 768 */ 769 static void 770 ste_watchdog(struct ifnet *ifp) 771 { 772 struct ste_softc *sc = ifp->if_softc; 773 774 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 775 ifp->if_oerrors++; 776 777 ste_txintr(sc); 778 ste_rxintr(sc); 779 (void) ste_init(ifp); 780 781 /* Try to get more packets going. */ 782 ste_start(ifp); 783 } 784 785 /* 786 * ste_ioctl: [ifnet interface function] 787 * 788 * Handle control requests from the operator. 789 */ 790 static int 791 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 792 { 793 struct ste_softc *sc = ifp->if_softc; 794 int s, error; 795 796 s = splnet(); 797 798 error = ether_ioctl(ifp, cmd, data); 799 if (error == ENETRESET) { 800 /* 801 * Multicast list has changed; set the hardware filter 802 * accordingly. 803 */ 804 if (ifp->if_flags & IFF_RUNNING) 805 ste_set_filter(sc); 806 error = 0; 807 } 808 809 /* Try to get more packets going. */ 810 ste_start(ifp); 811 812 splx(s); 813 return (error); 814 } 815 816 /* 817 * ste_intr: 818 * 819 * Interrupt service routine. 820 */ 821 static int 822 ste_intr(void *arg) 823 { 824 struct ste_softc *sc = arg; 825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 826 uint16_t isr; 827 uint8_t txstat; 828 int wantinit; 829 830 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 831 IS_InterruptStatus) == 0) 832 return (0); 833 834 for (wantinit = 0; wantinit == 0;) { 835 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 836 if ((isr & sc->sc_IntEnable) == 0) 837 break; 838 839 /* Receive interrupts. */ 840 if (isr & IE_RxDMAComplete) 841 ste_rxintr(sc); 842 843 /* Transmit interrupts. */ 844 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 845 ste_txintr(sc); 846 847 /* Statistics overflow. */ 848 if (isr & IE_UpdateStats) 849 ste_stats_update(sc); 850 851 /* Transmission errors. */ 852 if (isr & IE_TxComplete) { 853 for (;;) { 854 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 855 STE_TxStatus); 856 if ((txstat & TS_TxComplete) == 0) 857 break; 858 if (txstat & TS_TxUnderrun) { 859 sc->sc_txthresh += 32; 860 if (sc->sc_txthresh > 0x1ffc) 861 sc->sc_txthresh = 0x1ffc; 862 printf("%s: transmit underrun, new " 863 "threshold: %d bytes\n", 864 device_xname(&sc->sc_dev), 865 sc->sc_txthresh); 866 ste_reset(sc, AC_TxReset | AC_DMA | 867 AC_FIFO | AC_Network); 868 ste_setthresh(sc); 869 bus_space_write_1(sc->sc_st, sc->sc_sh, 870 STE_TxDMAPollPeriod, 127); 871 ste_txrestart(sc, 872 bus_space_read_1(sc->sc_st, 873 sc->sc_sh, STE_TxFrameId)); 874 } 875 if (txstat & TS_TxReleaseError) { 876 printf("%s: Tx FIFO release error\n", 877 device_xname(&sc->sc_dev)); 878 wantinit = 1; 879 } 880 if (txstat & TS_MaxCollisions) { 881 printf("%s: excessive collisions\n", 882 device_xname(&sc->sc_dev)); 883 wantinit = 1; 884 } 885 if (txstat & TS_TxStatusOverflow) { 886 printf("%s: status overflow\n", 887 device_xname(&sc->sc_dev)); 888 wantinit = 1; 889 } 890 bus_space_write_2(sc->sc_st, sc->sc_sh, 891 STE_TxStatus, 0); 892 } 893 } 894 895 /* Host interface errors. */ 896 if (isr & IE_HostError) { 897 printf("%s: Host interface error\n", 898 device_xname(&sc->sc_dev)); 899 wantinit = 1; 900 } 901 } 902 903 if (wantinit) 904 ste_init(ifp); 905 906 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 907 sc->sc_IntEnable); 908 909 /* Try to get more packets going. */ 910 ste_start(ifp); 911 912 return (1); 913 } 914 915 /* 916 * ste_txintr: 917 * 918 * Helper; handle transmit interrupts. 919 */ 920 static void 921 ste_txintr(struct ste_softc *sc) 922 { 923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 924 struct ste_descsoft *ds; 925 uint32_t control; 926 int i; 927 928 ifp->if_flags &= ~IFF_OACTIVE; 929 930 /* 931 * Go through our Tx list and free mbufs for those 932 * frames which have been transmitted. 933 */ 934 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 935 i = STE_NEXTTX(i), sc->sc_txpending--) { 936 ds = &sc->sc_txsoft[i]; 937 938 STE_CDTXSYNC(sc, i, 939 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 940 941 control = le32toh(sc->sc_txdescs[i].tfd_control); 942 if ((control & TFD_TxDMAComplete) == 0) 943 break; 944 945 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 946 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 947 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 948 m_freem(ds->ds_mbuf); 949 ds->ds_mbuf = NULL; 950 } 951 952 /* Update the dirty transmit buffer pointer. */ 953 sc->sc_txdirty = i; 954 955 /* 956 * If there are no more pending transmissions, cancel the watchdog 957 * timer. 958 */ 959 if (sc->sc_txpending == 0) 960 ifp->if_timer = 0; 961 } 962 963 /* 964 * ste_rxintr: 965 * 966 * Helper; handle receive interrupts. 967 */ 968 static void 969 ste_rxintr(struct ste_softc *sc) 970 { 971 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 972 struct ste_descsoft *ds; 973 struct mbuf *m; 974 uint32_t status; 975 int i, len; 976 977 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 978 ds = &sc->sc_rxsoft[i]; 979 980 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 981 982 status = le32toh(sc->sc_rxdescs[i].rfd_status); 983 984 if ((status & RFD_RxDMAComplete) == 0) 985 break; 986 987 /* 988 * If the packet had an error, simply recycle the 989 * buffer. Note, we count the error later in the 990 * periodic stats update. 991 */ 992 if (status & RFD_RxFrameError) { 993 STE_INIT_RXDESC(sc, i); 994 continue; 995 } 996 997 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 998 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 999 1000 /* 1001 * No errors; receive the packet. Note, we have 1002 * configured the chip to not include the CRC at 1003 * the end of the packet. 1004 */ 1005 len = RFD_RxDMAFrameLen(status); 1006 1007 /* 1008 * If the packet is small enough to fit in a 1009 * single header mbuf, allocate one and copy 1010 * the data into it. This greatly reduces 1011 * memory consumption when we receive lots 1012 * of small packets. 1013 * 1014 * Otherwise, we add a new buffer to the receive 1015 * chain. If this fails, we drop the packet and 1016 * recycle the old buffer. 1017 */ 1018 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1019 MGETHDR(m, M_DONTWAIT, MT_DATA); 1020 if (m == NULL) 1021 goto dropit; 1022 m->m_data += 2; 1023 memcpy(mtod(m, void *), 1024 mtod(ds->ds_mbuf, void *), len); 1025 STE_INIT_RXDESC(sc, i); 1026 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1027 ds->ds_dmamap->dm_mapsize, 1028 BUS_DMASYNC_PREREAD); 1029 } else { 1030 m = ds->ds_mbuf; 1031 if (ste_add_rxbuf(sc, i) != 0) { 1032 dropit: 1033 ifp->if_ierrors++; 1034 STE_INIT_RXDESC(sc, i); 1035 bus_dmamap_sync(sc->sc_dmat, 1036 ds->ds_dmamap, 0, 1037 ds->ds_dmamap->dm_mapsize, 1038 BUS_DMASYNC_PREREAD); 1039 continue; 1040 } 1041 } 1042 1043 m->m_pkthdr.rcvif = ifp; 1044 m->m_pkthdr.len = m->m_len = len; 1045 1046 /* 1047 * Pass this up to any BPF listeners, but only 1048 * pass if up the stack if it's for us. 1049 */ 1050 if (ifp->if_bpf) 1051 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1052 1053 /* Pass it on. */ 1054 (*ifp->if_input)(ifp, m); 1055 } 1056 1057 /* Update the receive pointer. */ 1058 sc->sc_rxptr = i; 1059 } 1060 1061 /* 1062 * ste_tick: 1063 * 1064 * One second timer, used to tick the MII. 1065 */ 1066 static void 1067 ste_tick(void *arg) 1068 { 1069 struct ste_softc *sc = arg; 1070 int s; 1071 1072 s = splnet(); 1073 mii_tick(&sc->sc_mii); 1074 ste_stats_update(sc); 1075 splx(s); 1076 1077 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1078 } 1079 1080 /* 1081 * ste_stats_update: 1082 * 1083 * Read the ST-201 statistics counters. 1084 */ 1085 static void 1086 ste_stats_update(struct ste_softc *sc) 1087 { 1088 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1089 bus_space_tag_t st = sc->sc_st; 1090 bus_space_handle_t sh = sc->sc_sh; 1091 1092 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1093 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1094 1095 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1096 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1097 1098 ifp->if_opackets += 1099 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1100 ifp->if_ipackets += 1101 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1102 1103 ifp->if_collisions += 1104 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1105 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1106 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1107 1108 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1109 1110 ifp->if_ierrors += 1111 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1112 1113 ifp->if_oerrors += 1114 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1115 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1116 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1117 1118 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1119 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1120 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1121 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1122 } 1123 1124 /* 1125 * ste_reset: 1126 * 1127 * Perform a soft reset on the ST-201. 1128 */ 1129 static void 1130 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1131 { 1132 uint32_t ac; 1133 int i; 1134 1135 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1136 1137 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1138 1139 delay(50000); 1140 1141 for (i = 0; i < STE_TIMEOUT; i++) { 1142 delay(1000); 1143 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1144 AC_ResetBusy) == 0) 1145 break; 1146 } 1147 1148 if (i == STE_TIMEOUT) 1149 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1150 1151 delay(1000); 1152 } 1153 1154 /* 1155 * ste_setthresh: 1156 * 1157 * set the various transmit threshold registers 1158 */ 1159 static void 1160 ste_setthresh(struct ste_softc *sc) 1161 { 1162 /* set the TX threhold */ 1163 bus_space_write_2(sc->sc_st, sc->sc_sh, 1164 STE_TxStartThresh, sc->sc_txthresh); 1165 /* Urgent threshold: set to sc_txthresh / 2 */ 1166 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1167 sc->sc_txthresh >> 6); 1168 /* Burst threshold: use default value (256 bytes) */ 1169 } 1170 1171 /* 1172 * restart TX at the given frame ID in the transmitter ring 1173 */ 1174 static void 1175 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1176 { 1177 u_int32_t control; 1178 1179 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1180 control = le32toh(sc->sc_txdescs[id].tfd_control); 1181 control &= ~TFD_TxDMAComplete; 1182 sc->sc_txdescs[id].tfd_control = htole32(control); 1183 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1184 1185 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1186 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1187 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1188 ste_dmahalt_wait(sc); 1189 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1190 STE_CDTXADDR(sc, id)); 1191 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1192 } 1193 1194 /* 1195 * ste_init: [ ifnet interface function ] 1196 * 1197 * Initialize the interface. Must be called at splnet(). 1198 */ 1199 static int 1200 ste_init(struct ifnet *ifp) 1201 { 1202 struct ste_softc *sc = ifp->if_softc; 1203 bus_space_tag_t st = sc->sc_st; 1204 bus_space_handle_t sh = sc->sc_sh; 1205 struct ste_descsoft *ds; 1206 int i, error = 0; 1207 1208 /* 1209 * Cancel any pending I/O. 1210 */ 1211 ste_stop(ifp, 0); 1212 1213 /* 1214 * Reset the chip to a known state. 1215 */ 1216 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1217 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1218 1219 /* 1220 * Initialize the transmit descriptor ring. 1221 */ 1222 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1223 sc->sc_txpending = 0; 1224 sc->sc_txdirty = 0; 1225 sc->sc_txlast = STE_NTXDESC - 1; 1226 1227 /* 1228 * Initialize the receive descriptor and receive job 1229 * descriptor rings. 1230 */ 1231 for (i = 0; i < STE_NRXDESC; i++) { 1232 ds = &sc->sc_rxsoft[i]; 1233 if (ds->ds_mbuf == NULL) { 1234 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1235 printf("%s: unable to allocate or map rx " 1236 "buffer %d, error = %d\n", 1237 device_xname(&sc->sc_dev), i, error); 1238 /* 1239 * XXX Should attempt to run with fewer receive 1240 * XXX buffers instead of just failing. 1241 */ 1242 ste_rxdrain(sc); 1243 goto out; 1244 } 1245 } else 1246 STE_INIT_RXDESC(sc, i); 1247 } 1248 sc->sc_rxptr = 0; 1249 1250 /* Set the station address. */ 1251 for (i = 0; i < ETHER_ADDR_LEN; i++) 1252 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1253 CLLADDR(ifp->if_sadl)[i]); 1254 1255 /* Set up the receive filter. */ 1256 ste_set_filter(sc); 1257 1258 /* 1259 * Give the receive ring to the chip. 1260 */ 1261 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1262 STE_CDRXADDR(sc, sc->sc_rxptr)); 1263 1264 /* 1265 * We defer giving the transmit ring to the chip until we 1266 * transmit the first packet. 1267 */ 1268 1269 /* 1270 * Initialize the Tx auto-poll period. It's OK to make this number 1271 * large (127 is the max) -- we explicitly kick the transmit engine 1272 * when there's actually a packet. We are using auto-polling only 1273 * to make the interface to the transmit engine not suck. 1274 */ 1275 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1276 1277 /* ..and the Rx auto-poll period. */ 1278 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1279 1280 /* Initialize the Tx start threshold. */ 1281 ste_setthresh(sc); 1282 1283 /* Set the FIFO release threshold to 512 bytes. */ 1284 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1285 1286 /* Set maximum packet size for VLAN. */ 1287 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1288 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1289 else 1290 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1291 1292 /* 1293 * Initialize the interrupt mask. 1294 */ 1295 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1296 IE_TxDMAComplete | IE_RxDMAComplete; 1297 1298 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1299 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1300 1301 /* 1302 * Start the receive DMA engine. 1303 */ 1304 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1305 1306 /* 1307 * Initialize MacCtrl0 -- do it before setting the media, 1308 * as setting the media will actually program the register. 1309 */ 1310 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1311 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1312 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1313 1314 /* 1315 * Set the current media. 1316 */ 1317 if ((error = ether_mediachange(ifp)) != 0) 1318 goto out; 1319 1320 /* 1321 * Start the MAC. 1322 */ 1323 bus_space_write_2(st, sh, STE_MacCtrl1, 1324 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1325 1326 /* 1327 * Start the one second MII clock. 1328 */ 1329 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1330 1331 /* 1332 * ...all done! 1333 */ 1334 ifp->if_flags |= IFF_RUNNING; 1335 ifp->if_flags &= ~IFF_OACTIVE; 1336 1337 out: 1338 if (error) 1339 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1340 return (error); 1341 } 1342 1343 /* 1344 * ste_drain: 1345 * 1346 * Drain the receive queue. 1347 */ 1348 static void 1349 ste_rxdrain(struct ste_softc *sc) 1350 { 1351 struct ste_descsoft *ds; 1352 int i; 1353 1354 for (i = 0; i < STE_NRXDESC; i++) { 1355 ds = &sc->sc_rxsoft[i]; 1356 if (ds->ds_mbuf != NULL) { 1357 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1358 m_freem(ds->ds_mbuf); 1359 ds->ds_mbuf = NULL; 1360 } 1361 } 1362 } 1363 1364 /* 1365 * ste_stop: [ ifnet interface function ] 1366 * 1367 * Stop transmission on the interface. 1368 */ 1369 static void 1370 ste_stop(struct ifnet *ifp, int disable) 1371 { 1372 struct ste_softc *sc = ifp->if_softc; 1373 struct ste_descsoft *ds; 1374 int i; 1375 1376 /* 1377 * Stop the one second clock. 1378 */ 1379 callout_stop(&sc->sc_tick_ch); 1380 1381 /* Down the MII. */ 1382 mii_down(&sc->sc_mii); 1383 1384 /* 1385 * Disable interrupts. 1386 */ 1387 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1388 1389 /* 1390 * Stop receiver, transmitter, and stats update. 1391 */ 1392 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1393 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1394 1395 /* 1396 * Stop the transmit and receive DMA. 1397 */ 1398 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1399 DC_RxDMAHalt | DC_TxDMAHalt); 1400 ste_dmahalt_wait(sc); 1401 1402 /* 1403 * Release any queued transmit buffers. 1404 */ 1405 for (i = 0; i < STE_NTXDESC; i++) { 1406 ds = &sc->sc_txsoft[i]; 1407 if (ds->ds_mbuf != NULL) { 1408 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1409 m_freem(ds->ds_mbuf); 1410 ds->ds_mbuf = NULL; 1411 } 1412 } 1413 1414 /* 1415 * Mark the interface down and cancel the watchdog timer. 1416 */ 1417 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1418 ifp->if_timer = 0; 1419 1420 if (disable) 1421 ste_rxdrain(sc); 1422 } 1423 1424 static int 1425 ste_eeprom_wait(struct ste_softc *sc) 1426 { 1427 int i; 1428 1429 for (i = 0; i < STE_TIMEOUT; i++) { 1430 delay(1000); 1431 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1432 EC_EepromBusy) == 0) 1433 return (0); 1434 } 1435 return (1); 1436 } 1437 1438 /* 1439 * ste_read_eeprom: 1440 * 1441 * Read data from the serial EEPROM. 1442 */ 1443 static void 1444 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1445 { 1446 1447 if (ste_eeprom_wait(sc)) 1448 printf("%s: EEPROM failed to come ready\n", 1449 device_xname(&sc->sc_dev)); 1450 1451 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1452 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1453 if (ste_eeprom_wait(sc)) 1454 printf("%s: EEPROM read timed out\n", 1455 device_xname(&sc->sc_dev)); 1456 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1457 } 1458 1459 /* 1460 * ste_add_rxbuf: 1461 * 1462 * Add a receive buffer to the indicated descriptor. 1463 */ 1464 static int 1465 ste_add_rxbuf(struct ste_softc *sc, int idx) 1466 { 1467 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1468 struct mbuf *m; 1469 int error; 1470 1471 MGETHDR(m, M_DONTWAIT, MT_DATA); 1472 if (m == NULL) 1473 return (ENOBUFS); 1474 1475 MCLGET(m, M_DONTWAIT); 1476 if ((m->m_flags & M_EXT) == 0) { 1477 m_freem(m); 1478 return (ENOBUFS); 1479 } 1480 1481 if (ds->ds_mbuf != NULL) 1482 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1483 1484 ds->ds_mbuf = m; 1485 1486 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1487 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1488 BUS_DMA_READ|BUS_DMA_NOWAIT); 1489 if (error) { 1490 printf("%s: can't load rx DMA map %d, error = %d\n", 1491 device_xname(&sc->sc_dev), idx, error); 1492 panic("ste_add_rxbuf"); /* XXX */ 1493 } 1494 1495 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1496 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1497 1498 STE_INIT_RXDESC(sc, idx); 1499 1500 return (0); 1501 } 1502 1503 /* 1504 * ste_set_filter: 1505 * 1506 * Set up the receive filter. 1507 */ 1508 static void 1509 ste_set_filter(struct ste_softc *sc) 1510 { 1511 struct ethercom *ec = &sc->sc_ethercom; 1512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1513 struct ether_multi *enm; 1514 struct ether_multistep step; 1515 uint32_t crc; 1516 uint16_t mchash[4]; 1517 1518 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1519 if (ifp->if_flags & IFF_BROADCAST) 1520 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1521 1522 if (ifp->if_flags & IFF_PROMISC) { 1523 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1524 goto allmulti; 1525 } 1526 1527 /* 1528 * Set up the multicast address filter by passing all multicast 1529 * addresses through a CRC generator, and then using the low-order 1530 * 6 bits as an index into the 64 bit multicast hash table. The 1531 * high order bits select the register, while the rest of the bits 1532 * select the bit within the register. 1533 */ 1534 1535 memset(mchash, 0, sizeof(mchash)); 1536 1537 ETHER_FIRST_MULTI(step, ec, enm); 1538 if (enm == NULL) 1539 goto done; 1540 1541 while (enm != NULL) { 1542 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1543 /* 1544 * We must listen to a range of multicast addresses. 1545 * For now, just accept all multicasts, rather than 1546 * trying to set only those filter bits needed to match 1547 * the range. (At this time, the only use of address 1548 * ranges is for IP multicast routing, for which the 1549 * range is big enough to require all bits set.) 1550 */ 1551 goto allmulti; 1552 } 1553 1554 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1555 1556 /* Just want the 6 least significant bits. */ 1557 crc &= 0x3f; 1558 1559 /* Set the corresponding bit in the hash table. */ 1560 mchash[crc >> 4] |= 1 << (crc & 0xf); 1561 1562 ETHER_NEXT_MULTI(step, enm); 1563 } 1564 1565 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1566 1567 ifp->if_flags &= ~IFF_ALLMULTI; 1568 goto done; 1569 1570 allmulti: 1571 ifp->if_flags |= IFF_ALLMULTI; 1572 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1573 1574 done: 1575 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1576 /* 1577 * Program the multicast hash table. 1578 */ 1579 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1580 mchash[0]); 1581 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1582 mchash[1]); 1583 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1584 mchash[2]); 1585 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1586 mchash[3]); 1587 } 1588 1589 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1590 sc->sc_ReceiveMode); 1591 } 1592 1593 /* 1594 * ste_mii_readreg: [mii interface function] 1595 * 1596 * Read a PHY register on the MII of the ST-201. 1597 */ 1598 static int 1599 ste_mii_readreg(device_t self, int phy, int reg) 1600 { 1601 1602 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1603 } 1604 1605 /* 1606 * ste_mii_writereg: [mii interface function] 1607 * 1608 * Write a PHY register on the MII of the ST-201. 1609 */ 1610 static void 1611 ste_mii_writereg(device_t self, int phy, int reg, int val) 1612 { 1613 1614 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1615 } 1616 1617 /* 1618 * ste_mii_statchg: [mii interface function] 1619 * 1620 * Callback from MII layer when media changes. 1621 */ 1622 static void 1623 ste_mii_statchg(device_t self) 1624 { 1625 struct ste_softc *sc = device_private(self); 1626 1627 if (sc->sc_mii.mii_media_active & IFM_FDX) 1628 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1629 else 1630 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1631 1632 /* XXX 802.1x flow-control? */ 1633 1634 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1635 } 1636 1637 /* 1638 * ste_mii_bitbang_read: [mii bit-bang interface function] 1639 * 1640 * Read the MII serial port for the MII bit-bang module. 1641 */ 1642 static uint32_t 1643 ste_mii_bitbang_read(device_t self) 1644 { 1645 struct ste_softc *sc = device_private(self); 1646 1647 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1648 } 1649 1650 /* 1651 * ste_mii_bitbang_write: [mii big-bang interface function] 1652 * 1653 * Write the MII serial port for the MII bit-bang module. 1654 */ 1655 static void 1656 ste_mii_bitbang_write(device_t self, uint32_t val) 1657 { 1658 struct ste_softc *sc = device_private(self); 1659 1660 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1661 } 1662