1 /* $NetBSD: if_ste.c,v 1.6 2001/07/23 17:26:50 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include "bpfilter.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/callout.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 #include <sys/queue.h> 57 58 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 59 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_ether.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <machine/bus.h> 70 #include <machine/intr.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/mii/mii_bitbang.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_stereg.h> 81 82 /* 83 * Transmit descriptor list size. 84 */ 85 #define STE_NTXDESC 256 86 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 87 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 88 89 /* 90 * Receive descriptor list size. 91 */ 92 #define STE_NRXDESC 128 93 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 94 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 95 96 /* 97 * Control structures are DMA'd to the ST-201 chip. We allocate them in 98 * a single clump that maps to a single DMA segment to make several things 99 * easier. 100 */ 101 struct ste_control_data { 102 /* 103 * The transmit descriptors. 104 */ 105 struct ste_tfd scd_txdescs[STE_NTXDESC]; 106 107 /* 108 * The receive descriptors. 109 */ 110 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 111 }; 112 113 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 114 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 115 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 116 117 /* 118 * Software state for transmit and receive jobs. 119 */ 120 struct ste_descsoft { 121 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 122 bus_dmamap_t ds_dmamap; /* our DMA map */ 123 }; 124 125 /* 126 * Software state per device. 127 */ 128 struct ste_softc { 129 struct device sc_dev; /* generic device information */ 130 bus_space_tag_t sc_st; /* bus space tag */ 131 bus_space_handle_t sc_sh; /* bus space handle */ 132 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 133 struct ethercom sc_ethercom; /* ethernet common data */ 134 void *sc_sdhook; /* shutdown hook */ 135 136 void *sc_ih; /* interrupt cookie */ 137 138 struct mii_data sc_mii; /* MII/media information */ 139 140 struct callout sc_tick_ch; /* tick callout */ 141 142 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 143 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 144 145 /* 146 * Software state for transmit and receive descriptors. 147 */ 148 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 149 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 150 151 /* 152 * Control data structures. 153 */ 154 struct ste_control_data *sc_control_data; 155 #define sc_txdescs sc_control_data->scd_txdescs 156 #define sc_rxdescs sc_control_data->scd_rxdescs 157 158 int sc_txpending; /* number of Tx requests pending */ 159 int sc_txdirty; /* first dirty Tx descriptor */ 160 int sc_txlast; /* last used Tx descriptor */ 161 162 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 163 164 int sc_txthresh; /* Tx threshold */ 165 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 166 uint16_t sc_IntEnable; /* prototype IntEnable register */ 167 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 168 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 169 }; 170 171 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 172 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 173 174 #define STE_CDTXSYNC(sc, x, ops) \ 175 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 176 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 177 178 #define STE_CDRXSYNC(sc, x, ops) \ 179 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 180 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 181 182 #define STE_INIT_RXDESC(sc, x) \ 183 do { \ 184 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 185 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 186 struct mbuf *__m = __ds->ds_mbuf; \ 187 \ 188 /* \ 189 * Note: We scoot the packet forward 2 bytes in the buffer \ 190 * so that the payload after the Ethernet header is aligned \ 191 * to a 4-byte boundary. \ 192 */ \ 193 __m->m_data = __m->m_ext.ext_buf + 2; \ 194 __rfd->rfd_frag.frag_addr = \ 195 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 196 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 197 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 198 __rfd->rfd_status = 0; \ 199 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 200 } while (/*CONSTCOND*/0) 201 202 #define STE_TIMEOUT 1000 203 204 void ste_start(struct ifnet *); 205 void ste_watchdog(struct ifnet *); 206 int ste_ioctl(struct ifnet *, u_long, caddr_t); 207 int ste_init(struct ifnet *); 208 void ste_stop(struct ifnet *, int); 209 210 void ste_shutdown(void *); 211 212 void ste_reset(struct ste_softc *); 213 void ste_rxdrain(struct ste_softc *); 214 int ste_add_rxbuf(struct ste_softc *, int); 215 void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 216 void ste_tick(void *); 217 218 void ste_stats_update(struct ste_softc *); 219 220 void ste_set_filter(struct ste_softc *); 221 222 int ste_intr(void *); 223 void ste_txintr(struct ste_softc *); 224 void ste_rxintr(struct ste_softc *); 225 226 int ste_mii_readreg(struct device *, int, int); 227 void ste_mii_writereg(struct device *, int, int, int); 228 void ste_mii_statchg(struct device *); 229 230 int ste_mediachange(struct ifnet *); 231 void ste_mediastatus(struct ifnet *, struct ifmediareq *); 232 233 int ste_match(struct device *, struct cfdata *, void *); 234 void ste_attach(struct device *, struct device *, void *); 235 236 int ste_copy_small = 0; 237 238 struct cfattach ste_ca = { 239 sizeof(struct ste_softc), ste_match, ste_attach, 240 }; 241 242 uint32_t ste_mii_bitbang_read(struct device *); 243 void ste_mii_bitbang_write(struct device *, uint32_t); 244 245 const struct mii_bitbang_ops ste_mii_bitbang_ops = { 246 ste_mii_bitbang_read, 247 ste_mii_bitbang_write, 248 { 249 PC_MgmtData, /* MII_BIT_MDO */ 250 PC_MgmtData, /* MII_BIT_MDI */ 251 PC_MgmtClk, /* MII_BIT_MDC */ 252 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 253 0, /* MII_BIT_DIR_PHY_HOST */ 254 } 255 }; 256 257 /* 258 * Devices supported by this driver. 259 */ 260 const struct ste_product { 261 pci_vendor_id_t ste_vendor; 262 pci_product_id_t ste_product; 263 const char *ste_name; 264 } ste_products[] = { 265 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 266 "Sundance ST-201 10/100 Ethernet" }, 267 268 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 269 "D-Link DL-1002 10/100 Ethernet" }, 270 271 { 0, 0, 272 NULL }, 273 }; 274 275 static const struct ste_product * 276 ste_lookup(const struct pci_attach_args *pa) 277 { 278 const struct ste_product *sp; 279 280 for (sp = ste_products; sp->ste_name != NULL; sp++) { 281 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 282 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 283 return (sp); 284 } 285 return (NULL); 286 } 287 288 int 289 ste_match(struct device *parent, struct cfdata *cf, void *aux) 290 { 291 struct pci_attach_args *pa = aux; 292 293 if (ste_lookup(pa) != NULL) 294 return (1); 295 296 return (0); 297 } 298 299 void 300 ste_attach(struct device *parent, struct device *self, void *aux) 301 { 302 struct ste_softc *sc = (struct ste_softc *) self; 303 struct pci_attach_args *pa = aux; 304 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 305 pci_chipset_tag_t pc = pa->pa_pc; 306 pci_intr_handle_t ih; 307 const char *intrstr = NULL; 308 bus_space_tag_t iot, memt; 309 bus_space_handle_t ioh, memh; 310 bus_dma_segment_t seg; 311 int ioh_valid, memh_valid; 312 int i, rseg, error; 313 const struct ste_product *sp; 314 pcireg_t pmode; 315 uint8_t enaddr[ETHER_ADDR_LEN]; 316 uint16_t myea[ETHER_ADDR_LEN / 2]; 317 int pmreg; 318 319 callout_init(&sc->sc_tick_ch); 320 321 sp = ste_lookup(pa); 322 if (sp == NULL) { 323 printf("\n"); 324 panic("ste_attach: impossible"); 325 } 326 327 printf(": %s\n", sp->ste_name); 328 329 /* 330 * Map the device. 331 */ 332 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 333 PCI_MAPREG_TYPE_IO, 0, 334 &iot, &ioh, NULL, NULL) == 0); 335 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 336 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 337 &memt, &memh, NULL, NULL) == 0); 338 339 if (memh_valid) { 340 sc->sc_st = memt; 341 sc->sc_sh = memh; 342 } else if (ioh_valid) { 343 sc->sc_st = iot; 344 sc->sc_sh = ioh; 345 } else { 346 printf("%s: unable to map device registers\n", 347 sc->sc_dev.dv_xname); 348 return; 349 } 350 351 sc->sc_dmat = pa->pa_dmat; 352 353 /* Enable bus mastering. */ 354 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 355 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 356 PCI_COMMAND_MASTER_ENABLE); 357 358 /* Get it out of power save mode if needed. */ 359 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 360 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 361 if (pmode == 3) { 362 /* 363 * The card has lost all configuration data in 364 * this state, so punt. 365 */ 366 printf("%s: unable to wake up from power state D3\n", 367 sc->sc_dev.dv_xname); 368 return; 369 } 370 if (pmode != 0) { 371 printf("%s: waking up from power state D%d\n", 372 sc->sc_dev.dv_xname, pmode); 373 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 374 } 375 } 376 377 /* 378 * Map and establish our interrupt. 379 */ 380 if (pci_intr_map(pa, &ih)) { 381 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 382 return; 383 } 384 intrstr = pci_intr_string(pc, ih); 385 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 386 if (sc->sc_ih == NULL) { 387 printf("%s: unable to establish interrupt", 388 sc->sc_dev.dv_xname); 389 if (intrstr != NULL) 390 printf(" at %s", intrstr); 391 printf("\n"); 392 return; 393 } 394 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 395 396 /* 397 * Allocate the control data structures, and create and load the 398 * DMA map for it. 399 */ 400 if ((error = bus_dmamem_alloc(sc->sc_dmat, 401 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 402 0)) != 0) { 403 printf("%s: unable to allocate control data, error = %d\n", 404 sc->sc_dev.dv_xname, error); 405 goto fail_0; 406 } 407 408 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 409 sizeof(struct ste_control_data), (caddr_t *)&sc->sc_control_data, 410 BUS_DMA_COHERENT)) != 0) { 411 printf("%s: unable to map control data, error = %d\n", 412 sc->sc_dev.dv_xname, error); 413 goto fail_1; 414 } 415 416 if ((error = bus_dmamap_create(sc->sc_dmat, 417 sizeof(struct ste_control_data), 1, 418 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 419 printf("%s: unable to create control data DMA map, " 420 "error = %d\n", sc->sc_dev.dv_xname, error); 421 goto fail_2; 422 } 423 424 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 425 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 426 0)) != 0) { 427 printf("%s: unable to load control data DMA map, error = %d\n", 428 sc->sc_dev.dv_xname, error); 429 goto fail_3; 430 } 431 432 /* 433 * Create the transmit buffer DMA maps. 434 */ 435 for (i = 0; i < STE_NTXDESC; i++) { 436 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 437 STE_NTXFRAGS, MCLBYTES, 0, 0, 438 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 439 printf("%s: unable to create tx DMA map %d, " 440 "error = %d\n", sc->sc_dev.dv_xname, i, error); 441 goto fail_4; 442 } 443 } 444 445 /* 446 * Create the receive buffer DMA maps. 447 */ 448 for (i = 0; i < STE_NRXDESC; i++) { 449 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 450 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 451 printf("%s: unable to create rx DMA map %d, " 452 "error = %d\n", sc->sc_dev.dv_xname, i, error); 453 goto fail_5; 454 } 455 sc->sc_rxsoft[i].ds_mbuf = NULL; 456 } 457 458 /* 459 * Reset the chip to a known state. 460 */ 461 ste_reset(sc); 462 463 /* 464 * Read the Ethernet address from the EEPROM. 465 */ 466 for (i = 0; i < 3; i++) { 467 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 468 myea[i] = le16toh(myea[i]); 469 } 470 memcpy(enaddr, myea, sizeof(enaddr)); 471 472 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 473 ether_sprintf(enaddr)); 474 475 /* 476 * Initialize our media structures and probe the MII. 477 */ 478 sc->sc_mii.mii_ifp = ifp; 479 sc->sc_mii.mii_readreg = ste_mii_readreg; 480 sc->sc_mii.mii_writereg = ste_mii_writereg; 481 sc->sc_mii.mii_statchg = ste_mii_statchg; 482 ifmedia_init(&sc->sc_mii.mii_media, 0, ste_mediachange, 483 ste_mediastatus); 484 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 485 MII_OFFSET_ANY, 0); 486 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 487 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 488 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 489 } else 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 491 492 ifp = &sc->sc_ethercom.ec_if; 493 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 494 ifp->if_softc = sc; 495 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 496 ifp->if_ioctl = ste_ioctl; 497 ifp->if_start = ste_start; 498 ifp->if_watchdog = ste_watchdog; 499 ifp->if_init = ste_init; 500 ifp->if_stop = ste_stop; 501 IFQ_SET_READY(&ifp->if_snd); 502 503 /* 504 * Default the transmit threshold to 128 bytes. 505 */ 506 sc->sc_txthresh = 128; 507 508 /* 509 * Disable MWI if the PCI layer tells us to. 510 */ 511 sc->sc_DMACtrl = 0; 512 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 513 sc->sc_DMACtrl |= DC_MWIDisable; 514 515 /* 516 * We can support 802.1Q VLAN-sized frames. 517 */ 518 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 519 520 /* 521 * Attach the interface. 522 */ 523 if_attach(ifp); 524 ether_ifattach(ifp, enaddr); 525 526 /* 527 * Make sure the interface is shutdown during reboot. 528 */ 529 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 530 if (sc->sc_sdhook == NULL) 531 printf("%s: WARNING: unable to establish shutdown hook\n", 532 sc->sc_dev.dv_xname); 533 return; 534 535 /* 536 * Free any resources we've allocated during the failed attach 537 * attempt. Do this in reverse order and fall through. 538 */ 539 fail_5: 540 for (i = 0; i < STE_NRXDESC; i++) { 541 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 542 bus_dmamap_destroy(sc->sc_dmat, 543 sc->sc_rxsoft[i].ds_dmamap); 544 } 545 fail_4: 546 for (i = 0; i < STE_NTXDESC; i++) { 547 if (sc->sc_txsoft[i].ds_dmamap != NULL) 548 bus_dmamap_destroy(sc->sc_dmat, 549 sc->sc_txsoft[i].ds_dmamap); 550 } 551 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 552 fail_3: 553 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 554 fail_2: 555 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 556 sizeof(struct ste_control_data)); 557 fail_1: 558 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 559 fail_0: 560 return; 561 } 562 563 /* 564 * ste_shutdown: 565 * 566 * Make sure the interface is stopped at reboot time. 567 */ 568 void 569 ste_shutdown(void *arg) 570 { 571 struct ste_softc *sc = arg; 572 573 ste_stop(&sc->sc_ethercom.ec_if, 1); 574 } 575 576 static void 577 ste_dmahalt_wait(struct ste_softc *sc) 578 { 579 int i; 580 581 for (i = 0; i < STE_TIMEOUT; i++) { 582 delay(2); 583 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 584 DC_DMAHaltBusy) == 0) 585 break; 586 } 587 588 if (i == STE_TIMEOUT) 589 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 590 } 591 592 /* 593 * ste_start: [ifnet interface function] 594 * 595 * Start packet transmission on the interface. 596 */ 597 void 598 ste_start(struct ifnet *ifp) 599 { 600 struct ste_softc *sc = ifp->if_softc; 601 struct mbuf *m0, *m; 602 struct ste_descsoft *ds; 603 struct ste_tfd *tfd; 604 bus_dmamap_t dmamap; 605 int error, olasttx, nexttx, opending, seg, totlen; 606 607 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 608 return; 609 610 /* 611 * Remember the previous number of pending transmissions 612 * and the current last descriptor in the list. 613 */ 614 opending = sc->sc_txpending; 615 olasttx = sc->sc_txlast; 616 617 /* 618 * Loop through the send queue, setting up transmit descriptors 619 * until we drain the queue, or use up all available transmit 620 * descriptors. 621 */ 622 while (sc->sc_txpending < STE_NTXDESC) { 623 /* 624 * Grab a packet off the queue. 625 */ 626 IFQ_POLL(&ifp->if_snd, m0); 627 if (m0 == NULL) 628 break; 629 m = NULL; 630 631 /* 632 * Get the last and next available transmit descriptor. 633 */ 634 nexttx = STE_NEXTTX(sc->sc_txlast); 635 tfd = &sc->sc_txdescs[nexttx]; 636 ds = &sc->sc_txsoft[nexttx]; 637 638 dmamap = ds->ds_dmamap; 639 640 /* 641 * Load the DMA map. If this fails, the packet either 642 * didn't fit in the alloted number of segments, or we 643 * were short on resources. In this case, we'll copy 644 * and try again. 645 */ 646 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 647 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 648 MGETHDR(m, M_DONTWAIT, MT_DATA); 649 if (m == NULL) { 650 printf("%s: unable to allocate Tx mbuf\n", 651 sc->sc_dev.dv_xname); 652 break; 653 } 654 if (m0->m_pkthdr.len > MHLEN) { 655 MCLGET(m, M_DONTWAIT); 656 if ((m->m_flags & M_EXT) == 0) { 657 printf("%s: unable to allocate Tx " 658 "cluster\n", sc->sc_dev.dv_xname); 659 m_freem(m); 660 break; 661 } 662 } 663 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 664 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 665 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 666 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 667 if (error) { 668 printf("%s: unable to load Tx buffer, " 669 "error = %d\n", sc->sc_dev.dv_xname, error); 670 break; 671 } 672 } 673 674 IFQ_DEQUEUE(&ifp->if_snd, m0); 675 if (m != NULL) { 676 m_freem(m0); 677 m0 = m; 678 } 679 680 /* 681 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 682 */ 683 684 /* Sync the DMA map. */ 685 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 686 BUS_DMASYNC_PREWRITE); 687 688 /* Initialize the fragment list. */ 689 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 690 tfd->tfd_frags[seg].frag_addr = 691 htole32(dmamap->dm_segs[seg].ds_addr); 692 tfd->tfd_frags[seg].frag_len = 693 htole32(dmamap->dm_segs[seg].ds_len); 694 totlen += dmamap->dm_segs[seg].ds_len; 695 } 696 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 697 698 /* Initialize the descriptor. */ 699 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 700 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 701 702 /* Sync the descriptor. */ 703 STE_CDTXSYNC(sc, nexttx, 704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 705 706 /* 707 * Store a pointer to the packet so we can free it later, 708 * and remember what txdirty will be once the packet is 709 * done. 710 */ 711 ds->ds_mbuf = m0; 712 713 /* Advance the tx pointer. */ 714 sc->sc_txpending++; 715 sc->sc_txlast = nexttx; 716 717 #if NBPFILTER > 0 718 /* 719 * Pass the packet to any BPF listeners. 720 */ 721 if (ifp->if_bpf) 722 bpf_mtap(ifp->if_bpf, m0); 723 #endif /* NBPFILTER > 0 */ 724 } 725 726 if (sc->sc_txpending == STE_NTXDESC) { 727 /* No more slots left; notify upper layer. */ 728 ifp->if_flags |= IFF_OACTIVE; 729 } 730 731 if (sc->sc_txpending != opending) { 732 /* 733 * We enqueued packets. If the transmitter was idle, 734 * reset the txdirty pointer. 735 */ 736 if (opending == 0) 737 sc->sc_txdirty = STE_NEXTTX(olasttx); 738 739 /* 740 * Cause a descriptor interrupt to happen on the 741 * last packet we enqueued, and also cause the 742 * DMA engine to wait after is has finished processing 743 * it. 744 */ 745 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 746 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 747 htole32(TFD_TxDMAIndicate); 748 STE_CDTXSYNC(sc, sc->sc_txlast, 749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 750 751 /* 752 * Link up the new chain of descriptors to the 753 * last. 754 */ 755 sc->sc_txdescs[olasttx].tfd_next = 756 STE_CDTXADDR(sc, STE_NEXTTX(olasttx)); 757 STE_CDTXSYNC(sc, olasttx, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 /* 761 * Kick the transmit DMA logic. Note that since we're 762 * using auto-polling, reading the Tx desc pointer will 763 * give it the nudge it needs to get going. 764 */ 765 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 766 STE_TxDMAListPtr) == 0) { 767 bus_space_write_4(sc->sc_st, sc->sc_sh, 768 STE_DMACtrl, DC_TxDMAHalt); 769 ste_dmahalt_wait(sc); 770 bus_space_write_4(sc->sc_st, sc->sc_sh, 771 STE_TxDMAListPtr, 772 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 773 bus_space_write_4(sc->sc_st, sc->sc_sh, 774 STE_DMACtrl, DC_TxDMAResume); 775 } 776 777 /* Set a watchdog timer in case the chip flakes out. */ 778 ifp->if_timer = 5; 779 } 780 } 781 782 /* 783 * ste_watchdog: [ifnet interface function] 784 * 785 * Watchdog timer handler. 786 */ 787 void 788 ste_watchdog(struct ifnet *ifp) 789 { 790 struct ste_softc *sc = ifp->if_softc; 791 792 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 793 ifp->if_oerrors++; 794 795 (void) ste_init(ifp); 796 797 /* Try to get more packets going. */ 798 ste_start(ifp); 799 } 800 801 /* 802 * ste_ioctl: [ifnet interface function] 803 * 804 * Handle control requests from the operator. 805 */ 806 int 807 ste_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 808 { 809 struct ste_softc *sc = ifp->if_softc; 810 struct ifreq *ifr = (struct ifreq *)data; 811 int s, error; 812 813 s = splnet(); 814 815 switch (cmd) { 816 case SIOCSIFMEDIA: 817 case SIOCGIFMEDIA: 818 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 819 break; 820 821 default: 822 error = ether_ioctl(ifp, cmd, data); 823 if (error == ENETRESET) { 824 /* 825 * Multicast list has changed; set the hardware filter 826 * accordingly. 827 */ 828 ste_set_filter(sc); 829 error = 0; 830 } 831 break; 832 } 833 834 /* Try to get more packets going. */ 835 ste_start(ifp); 836 837 splx(s); 838 return (error); 839 } 840 841 /* 842 * ste_intr: 843 * 844 * Interrupt service routine. 845 */ 846 int 847 ste_intr(void *arg) 848 { 849 struct ste_softc *sc = arg; 850 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 851 uint16_t isr; 852 uint8_t txstat; 853 int wantinit; 854 855 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 856 IS_InterruptStatus) == 0) 857 return (0); 858 859 for (wantinit = 0; wantinit == 0;) { 860 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 861 if ((isr & sc->sc_IntEnable) == 0) 862 break; 863 864 /* Receive interrupts. */ 865 if (isr & IE_RxDMAComplete) 866 ste_rxintr(sc); 867 868 /* Transmit interrupts. */ 869 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 870 ste_txintr(sc); 871 872 /* Statistics overflow. */ 873 if (isr & IE_UpdateStats) 874 ste_stats_update(sc); 875 876 /* Transmission errors. */ 877 if (isr & IE_TxComplete) { 878 for (;;) { 879 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 880 STE_TxStatus); 881 if ((txstat & TS_TxComplete) == 0) 882 break; 883 if (txstat & TS_TxUnderrun) { 884 sc->sc_txthresh += 32; 885 if (sc->sc_txthresh > 0x1ffc) 886 sc->sc_txthresh = 0x1ffc; 887 printf("%s: transmit underrun, new " 888 "threshold: %d bytes\n", 889 sc->sc_dev.dv_xname, 890 sc->sc_txthresh); 891 } 892 if (txstat & TS_TxReleaseError) 893 printf("%s: Tx FIFO release error\n", 894 sc->sc_dev.dv_xname); 895 if (txstat & TS_MaxCollisions) 896 printf("%s: excessive collisions\n", 897 sc->sc_dev.dv_xname); 898 bus_space_write_2(sc->sc_st, sc->sc_sh, 899 STE_TxStatus, 0); 900 } 901 wantinit = 1; 902 } 903 904 /* Host interface errors. */ 905 if (isr & IE_HostError) { 906 printf("%s: Host interface error\n", 907 sc->sc_dev.dv_xname); 908 wantinit = 1; 909 } 910 } 911 912 if (wantinit) 913 ste_init(ifp); 914 915 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 916 sc->sc_IntEnable); 917 918 /* Try to get more packets going. */ 919 ste_start(ifp); 920 921 return (1); 922 } 923 924 /* 925 * ste_txintr: 926 * 927 * Helper; handle transmit interrupts. 928 */ 929 void 930 ste_txintr(struct ste_softc *sc) 931 { 932 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 933 struct ste_descsoft *ds; 934 uint32_t control; 935 int i; 936 937 ifp->if_flags &= ~IFF_OACTIVE; 938 939 /* 940 * Go through our Tx list and free mbufs for those 941 * frames which have been transmitted. 942 */ 943 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 944 i = STE_NEXTTX(i), sc->sc_txpending--) { 945 ds = &sc->sc_txsoft[i]; 946 947 STE_CDTXSYNC(sc, i, 948 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 949 950 control = le32toh(sc->sc_txdescs[i].tfd_control); 951 if ((control & TFD_TxDMAComplete) == 0) 952 break; 953 954 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 955 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 956 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 957 m_freem(ds->ds_mbuf); 958 ds->ds_mbuf = NULL; 959 } 960 961 /* Update the dirty transmit buffer pointer. */ 962 sc->sc_txdirty = i; 963 964 /* 965 * If there are no more pending transmissions, cancel the watchdog 966 * timer. 967 */ 968 if (sc->sc_txpending == 0) 969 ifp->if_timer = 0; 970 } 971 972 /* 973 * ste_rxintr: 974 * 975 * Helper; handle receive interrupts. 976 */ 977 void 978 ste_rxintr(struct ste_softc *sc) 979 { 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 struct ste_descsoft *ds; 982 struct mbuf *m; 983 uint32_t status; 984 int i, len; 985 986 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 987 ds = &sc->sc_rxsoft[i]; 988 989 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 990 991 status = le32toh(sc->sc_rxdescs[i].rfd_status); 992 993 if ((status & RFD_RxDMAComplete) == 0) 994 break; 995 996 /* 997 * If the packet had an error, simply recycle the 998 * buffer. Note, we count the error later in the 999 * periodic stats update. 1000 */ 1001 if (status & RFD_RxFrameError) { 1002 STE_INIT_RXDESC(sc, i); 1003 continue; 1004 } 1005 1006 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1007 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1008 1009 /* 1010 * No errors; receive the packet. Note, we have 1011 * configured the chip to not include the CRC at 1012 * the end of the packet. 1013 */ 1014 len = RFD_RxDMAFrameLen(status); 1015 1016 /* 1017 * If the packet is small enough to fit in a 1018 * single header mbuf, allocate one and copy 1019 * the data into it. This greatly reduces 1020 * memory consumption when we receive lots 1021 * of small packets. 1022 * 1023 * Otherwise, we add a new buffer to the receive 1024 * chain. If this fails, we drop the packet and 1025 * recycle the old buffer. 1026 */ 1027 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1028 MGETHDR(m, M_DONTWAIT, MT_DATA); 1029 if (m == NULL) 1030 goto dropit; 1031 m->m_data += 2; 1032 memcpy(mtod(m, caddr_t), 1033 mtod(ds->ds_mbuf, caddr_t), len); 1034 STE_INIT_RXDESC(sc, i); 1035 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1036 ds->ds_dmamap->dm_mapsize, 1037 BUS_DMASYNC_PREREAD); 1038 } else { 1039 m = ds->ds_mbuf; 1040 if (ste_add_rxbuf(sc, i) != 0) { 1041 dropit: 1042 ifp->if_ierrors++; 1043 STE_INIT_RXDESC(sc, i); 1044 bus_dmamap_sync(sc->sc_dmat, 1045 ds->ds_dmamap, 0, 1046 ds->ds_dmamap->dm_mapsize, 1047 BUS_DMASYNC_PREREAD); 1048 continue; 1049 } 1050 } 1051 1052 m->m_pkthdr.rcvif = ifp; 1053 m->m_pkthdr.len = m->m_len = len; 1054 1055 #if NBPFILTER > 0 1056 /* 1057 * Pass this up to any BPF listeners, but only 1058 * pass if up the stack if it's for us. 1059 */ 1060 if (ifp->if_bpf) 1061 bpf_mtap(ifp->if_bpf, m); 1062 #endif /* NBPFILTER > 0 */ 1063 1064 /* Pass it on. */ 1065 (*ifp->if_input)(ifp, m); 1066 } 1067 1068 /* Update the receive pointer. */ 1069 sc->sc_rxptr = i; 1070 } 1071 1072 /* 1073 * ste_tick: 1074 * 1075 * One second timer, used to tick the MII. 1076 */ 1077 void 1078 ste_tick(void *arg) 1079 { 1080 struct ste_softc *sc = arg; 1081 int s; 1082 1083 s = splnet(); 1084 mii_tick(&sc->sc_mii); 1085 ste_stats_update(sc); 1086 splx(s); 1087 1088 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1089 } 1090 1091 /* 1092 * ste_stats_update: 1093 * 1094 * Read the ST-201 statistics counters. 1095 */ 1096 void 1097 ste_stats_update(struct ste_softc *sc) 1098 { 1099 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1100 bus_space_tag_t st = sc->sc_st; 1101 bus_space_handle_t sh = sc->sc_sh; 1102 1103 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1104 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1105 1106 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1107 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1108 1109 ifp->if_opackets += 1110 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1111 ifp->if_ipackets += 1112 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1113 1114 (void) bus_space_read_2(st, sh, STE_CarrierSenseErrors); 1115 1116 ifp->if_collisions += 1117 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1118 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1119 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1120 1121 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1122 1123 ifp->if_ierrors += 1124 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1125 1126 ifp->if_oerrors += 1127 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1128 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls); 1129 1130 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1131 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1132 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1133 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1134 } 1135 1136 /* 1137 * ste_reset: 1138 * 1139 * Perform a soft reset on the ST-201. 1140 */ 1141 void 1142 ste_reset(struct ste_softc *sc) 1143 { 1144 uint32_t ac; 1145 int i; 1146 1147 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1148 1149 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, 1150 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1151 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1152 AC_RstOut); 1153 1154 delay(50000); 1155 1156 for (i = 0; i < STE_TIMEOUT; i++) { 1157 delay(1000); 1158 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1159 AC_ResetBusy) == 0) 1160 break; 1161 } 1162 1163 if (i == STE_TIMEOUT) 1164 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1165 1166 delay(1000); 1167 } 1168 1169 /* 1170 * ste_init: [ ifnet interface function ] 1171 * 1172 * Initialize the interface. Must be called at splnet(). 1173 */ 1174 int 1175 ste_init(struct ifnet *ifp) 1176 { 1177 struct ste_softc *sc = ifp->if_softc; 1178 bus_space_tag_t st = sc->sc_st; 1179 bus_space_handle_t sh = sc->sc_sh; 1180 struct ste_descsoft *ds; 1181 int i, error = 0; 1182 1183 /* 1184 * Cancel any pending I/O. 1185 */ 1186 ste_stop(ifp, 0); 1187 1188 /* 1189 * Reset the chip to a known state. 1190 */ 1191 ste_reset(sc); 1192 1193 /* 1194 * Initialize the transmit descriptor ring. 1195 */ 1196 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1197 sc->sc_txpending = 0; 1198 sc->sc_txdirty = 0; 1199 sc->sc_txlast = STE_NTXDESC - 1; 1200 1201 /* 1202 * Initialize the receive descriptor and receive job 1203 * descriptor rings. 1204 */ 1205 for (i = 0; i < STE_NRXDESC; i++) { 1206 ds = &sc->sc_rxsoft[i]; 1207 if (ds->ds_mbuf == NULL) { 1208 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1209 printf("%s: unable to allocate or map rx " 1210 "buffer %d, error = %d\n", 1211 sc->sc_dev.dv_xname, i, error); 1212 /* 1213 * XXX Should attempt to run with fewer receive 1214 * XXX buffers instead of just failing. 1215 */ 1216 ste_rxdrain(sc); 1217 goto out; 1218 } 1219 } else 1220 STE_INIT_RXDESC(sc, i); 1221 } 1222 sc->sc_rxptr = 0; 1223 1224 /* Set the station address. */ 1225 for (i = 0; i < ETHER_ADDR_LEN; i++) 1226 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1227 LLADDR(ifp->if_sadl)[i]); 1228 1229 /* Set up the receive filter. */ 1230 ste_set_filter(sc); 1231 1232 /* 1233 * Give the receive ring to the chip. 1234 */ 1235 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1236 STE_CDRXADDR(sc, sc->sc_rxptr)); 1237 1238 /* 1239 * We defer giving the transmit ring to the chip until we 1240 * transmit the first packet. 1241 */ 1242 1243 /* 1244 * Initialize the Tx auto-poll period. It's OK to make this number 1245 * large (127 is the max) -- we explicitly kick the transmit engine 1246 * when there's actually a packet. We are using auto-polling only 1247 * to make the interface to the transmit engine not suck. 1248 */ 1249 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1250 1251 /* ..and the Rx auto-poll period. */ 1252 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1253 1254 /* Initialize the Tx start threshold. */ 1255 bus_space_write_2(st, sh, STE_TxStartThresh, sc->sc_txthresh); 1256 1257 /* Set the FIFO release threshold to 512 bytes. */ 1258 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1259 1260 /* 1261 * Initialize the interrupt mask. 1262 */ 1263 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1264 IE_TxDMAComplete | IE_RxDMAComplete; 1265 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1266 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1267 1268 /* 1269 * Start the receive DMA engine. 1270 */ 1271 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1272 1273 /* 1274 * Initialize MacCtrl0 -- do it before setting the media, 1275 * as setting the media will actually program the register. 1276 */ 1277 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1278 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1279 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1280 1281 /* 1282 * Set the current media. 1283 */ 1284 mii_mediachg(&sc->sc_mii); 1285 1286 /* 1287 * Start the MAC. 1288 */ 1289 bus_space_write_2(st, sh, STE_MacCtrl1, 1290 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1291 1292 /* 1293 * Start the one second MII clock. 1294 */ 1295 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1296 1297 /* 1298 * ...all done! 1299 */ 1300 ifp->if_flags |= IFF_RUNNING; 1301 ifp->if_flags &= ~IFF_OACTIVE; 1302 1303 out: 1304 if (error) 1305 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1306 return (error); 1307 } 1308 1309 /* 1310 * ste_drain: 1311 * 1312 * Drain the receive queue. 1313 */ 1314 void 1315 ste_rxdrain(struct ste_softc *sc) 1316 { 1317 struct ste_descsoft *ds; 1318 int i; 1319 1320 for (i = 0; i < STE_NRXDESC; i++) { 1321 ds = &sc->sc_rxsoft[i]; 1322 if (ds->ds_mbuf != NULL) { 1323 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1324 m_freem(ds->ds_mbuf); 1325 ds->ds_mbuf = NULL; 1326 } 1327 } 1328 } 1329 1330 /* 1331 * ste_stop: [ ifnet interface function ] 1332 * 1333 * Stop transmission on the interface. 1334 */ 1335 void 1336 ste_stop(struct ifnet *ifp, int disable) 1337 { 1338 struct ste_softc *sc = ifp->if_softc; 1339 struct ste_descsoft *ds; 1340 int i; 1341 1342 /* 1343 * Stop the one second clock. 1344 */ 1345 callout_stop(&sc->sc_tick_ch); 1346 1347 /* Down the MII. */ 1348 mii_down(&sc->sc_mii); 1349 1350 /* 1351 * Disable interrupts. 1352 */ 1353 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1354 1355 /* 1356 * Stop receiver, transmitter, and stats update. 1357 */ 1358 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1359 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1360 1361 /* 1362 * Stop the transmit and receive DMA. 1363 */ 1364 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1365 DC_RxDMAHalt | DC_TxDMAHalt); 1366 ste_dmahalt_wait(sc); 1367 1368 /* 1369 * Release any queued transmit buffers. 1370 */ 1371 for (i = 0; i < STE_NTXDESC; i++) { 1372 ds = &sc->sc_txsoft[i]; 1373 if (ds->ds_mbuf != NULL) { 1374 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1375 m_freem(ds->ds_mbuf); 1376 ds->ds_mbuf = NULL; 1377 } 1378 } 1379 1380 if (disable) 1381 ste_rxdrain(sc); 1382 1383 /* 1384 * Mark the interface down and cancel the watchdog timer. 1385 */ 1386 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1387 ifp->if_timer = 0; 1388 } 1389 1390 static int 1391 ste_eeprom_wait(struct ste_softc *sc) 1392 { 1393 int i; 1394 1395 for (i = 0; i < STE_TIMEOUT; i++) { 1396 delay(1000); 1397 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1398 EC_EepromBusy) == 0) 1399 return (0); 1400 } 1401 return (1); 1402 } 1403 1404 /* 1405 * ste_read_eeprom: 1406 * 1407 * Read data from the serial EEPROM. 1408 */ 1409 void 1410 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1411 { 1412 1413 if (ste_eeprom_wait(sc)) 1414 printf("%s: EEPROM failed to come ready\n", 1415 sc->sc_dev.dv_xname); 1416 1417 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1418 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1419 if (ste_eeprom_wait(sc)) 1420 printf("%s: EEPROM read timed out\n", 1421 sc->sc_dev.dv_xname); 1422 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1423 } 1424 1425 /* 1426 * ste_add_rxbuf: 1427 * 1428 * Add a receive buffer to the indicated descriptor. 1429 */ 1430 int 1431 ste_add_rxbuf(struct ste_softc *sc, int idx) 1432 { 1433 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1434 struct mbuf *m; 1435 int error; 1436 1437 MGETHDR(m, M_DONTWAIT, MT_DATA); 1438 if (m == NULL) 1439 return (ENOBUFS); 1440 1441 MCLGET(m, M_DONTWAIT); 1442 if ((m->m_flags & M_EXT) == 0) { 1443 m_freem(m); 1444 return (ENOBUFS); 1445 } 1446 1447 if (ds->ds_mbuf != NULL) 1448 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1449 1450 ds->ds_mbuf = m; 1451 1452 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1453 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1454 BUS_DMA_READ|BUS_DMA_NOWAIT); 1455 if (error) { 1456 printf("%s: can't load rx DMA map %d, error = %d\n", 1457 sc->sc_dev.dv_xname, idx, error); 1458 panic("ste_add_rxbuf"); /* XXX */ 1459 } 1460 1461 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1462 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1463 1464 STE_INIT_RXDESC(sc, idx); 1465 1466 return (0); 1467 } 1468 1469 /* 1470 * ste_set_filter: 1471 * 1472 * Set up the receive filter. 1473 */ 1474 void 1475 ste_set_filter(struct ste_softc *sc) 1476 { 1477 struct ethercom *ec = &sc->sc_ethercom; 1478 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1479 struct ether_multi *enm; 1480 struct ether_multistep step; 1481 uint32_t crc; 1482 uint16_t mchash[4]; 1483 1484 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1485 if (ifp->if_flags & IFF_BROADCAST) 1486 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1487 1488 if (ifp->if_flags & IFF_PROMISC) { 1489 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1490 goto allmulti; 1491 } 1492 1493 /* 1494 * Set up the multicast address filter by passing all multicast 1495 * addresses through a CRC generator, and then using the low-order 1496 * 6 bits as an index into the 64 bit multicast hash table. The 1497 * high order bits select the register, while the rest of the bits 1498 * select the bit within the register. 1499 */ 1500 1501 memset(mchash, 0, sizeof(mchash)); 1502 1503 ETHER_FIRST_MULTI(step, ec, enm); 1504 if (enm == NULL) 1505 goto done; 1506 1507 while (enm != NULL) { 1508 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1509 /* 1510 * We must listen to a range of multicast addresses. 1511 * For now, just accept all multicasts, rather than 1512 * trying to set only those filter bits needed to match 1513 * the range. (At this time, the only use of address 1514 * ranges is for IP multicast routing, for which the 1515 * range is big enough to require all bits set.) 1516 */ 1517 goto allmulti; 1518 } 1519 1520 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1521 1522 /* Just want the 6 least significant bits. */ 1523 crc &= 0x3f; 1524 1525 /* Set the corresponding bit in the hash table. */ 1526 mchash[crc >> 4] |= 1 << (crc & 0xf); 1527 1528 ETHER_NEXT_MULTI(step, enm); 1529 } 1530 1531 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1532 1533 ifp->if_flags &= ~IFF_ALLMULTI; 1534 goto done; 1535 1536 allmulti: 1537 ifp->if_flags |= IFF_ALLMULTI; 1538 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1539 1540 done: 1541 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1542 /* 1543 * Program the multicast hash table. 1544 */ 1545 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1546 mchash[0]); 1547 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1548 mchash[1]); 1549 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1550 mchash[2]); 1551 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1552 mchash[3]); 1553 } 1554 1555 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1556 sc->sc_ReceiveMode); 1557 } 1558 1559 /* 1560 * ste_mii_readreg: [mii interface function] 1561 * 1562 * Read a PHY register on the MII of the ST-201. 1563 */ 1564 int 1565 ste_mii_readreg(struct device *self, int phy, int reg) 1566 { 1567 1568 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1569 } 1570 1571 /* 1572 * ste_mii_writereg: [mii interface function] 1573 * 1574 * Write a PHY register on the MII of the ST-201. 1575 */ 1576 void 1577 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1578 { 1579 1580 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1581 } 1582 1583 /* 1584 * ste_mii_statchg: [mii interface function] 1585 * 1586 * Callback from MII layer when media changes. 1587 */ 1588 void 1589 ste_mii_statchg(struct device *self) 1590 { 1591 struct ste_softc *sc = (struct ste_softc *) self; 1592 1593 if (sc->sc_mii.mii_media_active & IFM_FDX) 1594 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1595 else 1596 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1597 1598 /* XXX 802.1x flow-control? */ 1599 1600 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1601 } 1602 1603 /* 1604 * ste_mii_bitbang_read: [mii bit-bang interface function] 1605 * 1606 * Read the MII serial port for the MII bit-bang module. 1607 */ 1608 uint32_t 1609 ste_mii_bitbang_read(struct device *self) 1610 { 1611 struct ste_softc *sc = (void *) self; 1612 1613 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1614 } 1615 1616 /* 1617 * ste_mii_bitbang_write: [mii big-bang interface function] 1618 * 1619 * Write the MII serial port for the MII bit-bang module. 1620 */ 1621 void 1622 ste_mii_bitbang_write(struct device *self, uint32_t val) 1623 { 1624 struct ste_softc *sc = (void *) self; 1625 1626 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1627 } 1628 1629 /* 1630 * ste_mediastatus: [ifmedia interface function] 1631 * 1632 * Get the current interface media status. 1633 */ 1634 void 1635 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1636 { 1637 struct ste_softc *sc = ifp->if_softc; 1638 1639 mii_pollstat(&sc->sc_mii); 1640 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1641 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1642 } 1643 1644 /* 1645 * ste_mediachange: [ifmedia interface function] 1646 * 1647 * Set hardware to newly-selected media. 1648 */ 1649 int 1650 ste_mediachange(struct ifnet *ifp) 1651 { 1652 struct ste_softc *sc = ifp->if_softc; 1653 1654 if (ifp->if_flags & IFF_UP) 1655 mii_mediachg(&sc->sc_mii); 1656 return (0); 1657 } 1658