1 /* $NetBSD: if_ste.c,v 1.39 2009/11/26 15:17:10 njoly Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.39 2009/11/26 15:17:10 njoly Exp $"); 39 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 #include <dev/mii/mii_bitbang.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_stereg.h> 77 78 /* 79 * Transmit descriptor list size. 80 */ 81 #define STE_NTXDESC 256 82 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 83 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 84 85 /* 86 * Receive descriptor list size. 87 */ 88 #define STE_NRXDESC 128 89 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 90 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 91 92 /* 93 * Control structures are DMA'd to the ST-201 chip. We allocate them in 94 * a single clump that maps to a single DMA segment to make several things 95 * easier. 96 */ 97 struct ste_control_data { 98 /* 99 * The transmit descriptors. 100 */ 101 struct ste_tfd scd_txdescs[STE_NTXDESC]; 102 103 /* 104 * The receive descriptors. 105 */ 106 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 107 }; 108 109 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 110 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 111 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 112 113 /* 114 * Software state for transmit and receive jobs. 115 */ 116 struct ste_descsoft { 117 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t ds_dmamap; /* our DMA map */ 119 }; 120 121 /* 122 * Software state per device. 123 */ 124 struct ste_softc { 125 struct device sc_dev; /* generic device information */ 126 bus_space_tag_t sc_st; /* bus space tag */ 127 bus_space_handle_t sc_sh; /* bus space handle */ 128 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 129 struct ethercom sc_ethercom; /* ethernet common data */ 130 131 void *sc_ih; /* interrupt cookie */ 132 133 struct mii_data sc_mii; /* MII/media information */ 134 135 callout_t sc_tick_ch; /* tick callout */ 136 137 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 138 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 139 140 /* 141 * Software state for transmit and receive descriptors. 142 */ 143 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 144 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 145 146 /* 147 * Control data structures. 148 */ 149 struct ste_control_data *sc_control_data; 150 #define sc_txdescs sc_control_data->scd_txdescs 151 #define sc_rxdescs sc_control_data->scd_rxdescs 152 153 int sc_txpending; /* number of Tx requests pending */ 154 int sc_txdirty; /* first dirty Tx descriptor */ 155 int sc_txlast; /* last used Tx descriptor */ 156 157 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 158 159 int sc_txthresh; /* Tx threshold */ 160 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 161 uint16_t sc_IntEnable; /* prototype IntEnable register */ 162 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 163 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 164 }; 165 166 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 167 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 168 169 #define STE_CDTXSYNC(sc, x, ops) \ 170 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 171 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 172 173 #define STE_CDRXSYNC(sc, x, ops) \ 174 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 175 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 176 177 #define STE_INIT_RXDESC(sc, x) \ 178 do { \ 179 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 180 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 181 struct mbuf *__m = __ds->ds_mbuf; \ 182 \ 183 /* \ 184 * Note: We scoot the packet forward 2 bytes in the buffer \ 185 * so that the payload after the Ethernet header is aligned \ 186 * to a 4-byte boundary. \ 187 */ \ 188 __m->m_data = __m->m_ext.ext_buf + 2; \ 189 __rfd->rfd_frag.frag_addr = \ 190 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 191 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 192 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 193 __rfd->rfd_status = 0; \ 194 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 195 } while (/*CONSTCOND*/0) 196 197 #define STE_TIMEOUT 1000 198 199 static void ste_start(struct ifnet *); 200 static void ste_watchdog(struct ifnet *); 201 static int ste_ioctl(struct ifnet *, u_long, void *); 202 static int ste_init(struct ifnet *); 203 static void ste_stop(struct ifnet *, int); 204 205 static bool ste_shutdown(device_t, int); 206 207 static void ste_reset(struct ste_softc *, u_int32_t); 208 static void ste_setthresh(struct ste_softc *); 209 static void ste_txrestart(struct ste_softc *, u_int8_t); 210 static void ste_rxdrain(struct ste_softc *); 211 static int ste_add_rxbuf(struct ste_softc *, int); 212 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 213 static void ste_tick(void *); 214 215 static void ste_stats_update(struct ste_softc *); 216 217 static void ste_set_filter(struct ste_softc *); 218 219 static int ste_intr(void *); 220 static void ste_txintr(struct ste_softc *); 221 static void ste_rxintr(struct ste_softc *); 222 223 static int ste_mii_readreg(device_t, int, int); 224 static void ste_mii_writereg(device_t, int, int, int); 225 static void ste_mii_statchg(device_t); 226 227 static int ste_match(device_t, cfdata_t, void *); 228 static void ste_attach(device_t, device_t, void *); 229 230 int ste_copy_small = 0; 231 232 CFATTACH_DECL(ste, sizeof(struct ste_softc), 233 ste_match, ste_attach, NULL, NULL); 234 235 static uint32_t ste_mii_bitbang_read(device_t); 236 static void ste_mii_bitbang_write(device_t, uint32_t); 237 238 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 239 ste_mii_bitbang_read, 240 ste_mii_bitbang_write, 241 { 242 PC_MgmtData, /* MII_BIT_MDO */ 243 PC_MgmtData, /* MII_BIT_MDI */ 244 PC_MgmtClk, /* MII_BIT_MDC */ 245 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 246 0, /* MII_BIT_DIR_PHY_HOST */ 247 } 248 }; 249 250 /* 251 * Devices supported by this driver. 252 */ 253 static const struct ste_product { 254 pci_vendor_id_t ste_vendor; 255 pci_product_id_t ste_product; 256 const char *ste_name; 257 } ste_products[] = { 258 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 259 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 260 261 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 262 "Sundance ST-201 10/100 Ethernet" }, 263 264 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 265 "D-Link DL-1002 10/100 Ethernet" }, 266 267 { 0, 0, 268 NULL }, 269 }; 270 271 static const struct ste_product * 272 ste_lookup(const struct pci_attach_args *pa) 273 { 274 const struct ste_product *sp; 275 276 for (sp = ste_products; sp->ste_name != NULL; sp++) { 277 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 278 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 279 return (sp); 280 } 281 return (NULL); 282 } 283 284 static int 285 ste_match(device_t parent, cfdata_t cf, void *aux) 286 { 287 struct pci_attach_args *pa = aux; 288 289 if (ste_lookup(pa) != NULL) 290 return (1); 291 292 return (0); 293 } 294 295 static void 296 ste_attach(device_t parent, device_t self, void *aux) 297 { 298 struct ste_softc *sc = device_private(self); 299 struct pci_attach_args *pa = aux; 300 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 301 pci_chipset_tag_t pc = pa->pa_pc; 302 pci_intr_handle_t ih; 303 const char *intrstr = NULL; 304 bus_space_tag_t iot, memt; 305 bus_space_handle_t ioh, memh; 306 bus_dma_segment_t seg; 307 int ioh_valid, memh_valid; 308 int i, rseg, error; 309 const struct ste_product *sp; 310 uint8_t enaddr[ETHER_ADDR_LEN]; 311 uint16_t myea[ETHER_ADDR_LEN / 2]; 312 313 callout_init(&sc->sc_tick_ch, 0); 314 315 sp = ste_lookup(pa); 316 if (sp == NULL) { 317 printf("\n"); 318 panic("ste_attach: impossible"); 319 } 320 321 printf(": %s\n", sp->ste_name); 322 323 /* 324 * Map the device. 325 */ 326 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 327 PCI_MAPREG_TYPE_IO, 0, 328 &iot, &ioh, NULL, NULL) == 0); 329 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 330 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 331 &memt, &memh, NULL, NULL) == 0); 332 333 if (memh_valid) { 334 sc->sc_st = memt; 335 sc->sc_sh = memh; 336 } else if (ioh_valid) { 337 sc->sc_st = iot; 338 sc->sc_sh = ioh; 339 } else { 340 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 341 return; 342 } 343 344 sc->sc_dmat = pa->pa_dmat; 345 346 /* Enable bus mastering. */ 347 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 348 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 349 PCI_COMMAND_MASTER_ENABLE); 350 351 /* power up chip */ 352 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 353 NULL)) && error != EOPNOTSUPP) { 354 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 355 error); 356 return; 357 } 358 359 /* 360 * Map and establish our interrupt. 361 */ 362 if (pci_intr_map(pa, &ih)) { 363 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 364 return; 365 } 366 intrstr = pci_intr_string(pc, ih); 367 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 368 if (sc->sc_ih == NULL) { 369 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 370 if (intrstr != NULL) 371 aprint_error(" at %s", intrstr); 372 aprint_error("\n"); 373 return; 374 } 375 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 376 377 /* 378 * Allocate the control data structures, and create and load the 379 * DMA map for it. 380 */ 381 if ((error = bus_dmamem_alloc(sc->sc_dmat, 382 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 383 0)) != 0) { 384 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 385 error); 386 goto fail_0; 387 } 388 389 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 390 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 391 BUS_DMA_COHERENT)) != 0) { 392 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 393 error); 394 goto fail_1; 395 } 396 397 if ((error = bus_dmamap_create(sc->sc_dmat, 398 sizeof(struct ste_control_data), 1, 399 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 400 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 401 "error = %d\n", error); 402 goto fail_2; 403 } 404 405 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 406 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 407 0)) != 0) { 408 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 409 error); 410 goto fail_3; 411 } 412 413 /* 414 * Create the transmit buffer DMA maps. 415 */ 416 for (i = 0; i < STE_NTXDESC; i++) { 417 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 418 STE_NTXFRAGS, MCLBYTES, 0, 0, 419 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 420 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 421 "error = %d\n", i, error); 422 goto fail_4; 423 } 424 } 425 426 /* 427 * Create the receive buffer DMA maps. 428 */ 429 for (i = 0; i < STE_NRXDESC; i++) { 430 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 431 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 432 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 433 "error = %d\n", i, error); 434 goto fail_5; 435 } 436 sc->sc_rxsoft[i].ds_mbuf = NULL; 437 } 438 439 /* 440 * Reset the chip to a known state. 441 */ 442 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 443 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 444 445 /* 446 * Read the Ethernet address from the EEPROM. 447 */ 448 for (i = 0; i < 3; i++) { 449 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 450 myea[i] = le16toh(myea[i]); 451 } 452 memcpy(enaddr, myea, sizeof(enaddr)); 453 454 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 455 ether_sprintf(enaddr)); 456 457 /* 458 * Initialize our media structures and probe the MII. 459 */ 460 sc->sc_mii.mii_ifp = ifp; 461 sc->sc_mii.mii_readreg = ste_mii_readreg; 462 sc->sc_mii.mii_writereg = ste_mii_writereg; 463 sc->sc_mii.mii_statchg = ste_mii_statchg; 464 sc->sc_ethercom.ec_mii = &sc->sc_mii; 465 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 466 ether_mediastatus); 467 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 468 MII_OFFSET_ANY, 0); 469 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 470 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 471 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 472 } else 473 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 474 475 ifp = &sc->sc_ethercom.ec_if; 476 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 477 ifp->if_softc = sc; 478 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 479 ifp->if_ioctl = ste_ioctl; 480 ifp->if_start = ste_start; 481 ifp->if_watchdog = ste_watchdog; 482 ifp->if_init = ste_init; 483 ifp->if_stop = ste_stop; 484 IFQ_SET_READY(&ifp->if_snd); 485 486 /* 487 * Default the transmit threshold to 128 bytes. 488 */ 489 sc->sc_txthresh = 128; 490 491 /* 492 * Disable MWI if the PCI layer tells us to. 493 */ 494 sc->sc_DMACtrl = 0; 495 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 496 sc->sc_DMACtrl |= DC_MWIDisable; 497 498 /* 499 * We can support 802.1Q VLAN-sized frames. 500 */ 501 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 502 503 /* 504 * Attach the interface. 505 */ 506 if_attach(ifp); 507 ether_ifattach(ifp, enaddr); 508 509 /* 510 * Make sure the interface is shutdown during reboot. 511 */ 512 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 513 pmf_class_network_register(self, ifp); 514 else 515 aprint_error_dev(self, "couldn't establish power handler\n"); 516 517 return; 518 519 /* 520 * Free any resources we've allocated during the failed attach 521 * attempt. Do this in reverse order and fall through. 522 */ 523 fail_5: 524 for (i = 0; i < STE_NRXDESC; i++) { 525 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 526 bus_dmamap_destroy(sc->sc_dmat, 527 sc->sc_rxsoft[i].ds_dmamap); 528 } 529 fail_4: 530 for (i = 0; i < STE_NTXDESC; i++) { 531 if (sc->sc_txsoft[i].ds_dmamap != NULL) 532 bus_dmamap_destroy(sc->sc_dmat, 533 sc->sc_txsoft[i].ds_dmamap); 534 } 535 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 536 fail_3: 537 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 538 fail_2: 539 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 540 sizeof(struct ste_control_data)); 541 fail_1: 542 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 543 fail_0: 544 return; 545 } 546 547 /* 548 * ste_shutdown: 549 * 550 * Make sure the interface is stopped at reboot time. 551 */ 552 static bool 553 ste_shutdown(device_t self, int howto) 554 { 555 struct ste_softc *sc; 556 557 sc = device_private(self); 558 ste_stop(&sc->sc_ethercom.ec_if, 1); 559 560 return true; 561 } 562 563 static void 564 ste_dmahalt_wait(struct ste_softc *sc) 565 { 566 int i; 567 568 for (i = 0; i < STE_TIMEOUT; i++) { 569 delay(2); 570 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 571 DC_DMAHaltBusy) == 0) 572 break; 573 } 574 575 if (i == STE_TIMEOUT) 576 printf("%s: DMA halt timed out\n", device_xname(&sc->sc_dev)); 577 } 578 579 /* 580 * ste_start: [ifnet interface function] 581 * 582 * Start packet transmission on the interface. 583 */ 584 static void 585 ste_start(struct ifnet *ifp) 586 { 587 struct ste_softc *sc = ifp->if_softc; 588 struct mbuf *m0, *m; 589 struct ste_descsoft *ds; 590 struct ste_tfd *tfd; 591 bus_dmamap_t dmamap; 592 int error, olasttx, nexttx, opending, seg, totlen; 593 594 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 595 return; 596 597 /* 598 * Remember the previous number of pending transmissions 599 * and the current last descriptor in the list. 600 */ 601 opending = sc->sc_txpending; 602 olasttx = sc->sc_txlast; 603 604 /* 605 * Loop through the send queue, setting up transmit descriptors 606 * until we drain the queue, or use up all available transmit 607 * descriptors. 608 */ 609 while (sc->sc_txpending < STE_NTXDESC) { 610 /* 611 * Grab a packet off the queue. 612 */ 613 IFQ_POLL(&ifp->if_snd, m0); 614 if (m0 == NULL) 615 break; 616 m = NULL; 617 618 /* 619 * Get the last and next available transmit descriptor. 620 */ 621 nexttx = STE_NEXTTX(sc->sc_txlast); 622 tfd = &sc->sc_txdescs[nexttx]; 623 ds = &sc->sc_txsoft[nexttx]; 624 625 dmamap = ds->ds_dmamap; 626 627 /* 628 * Load the DMA map. If this fails, the packet either 629 * didn't fit in the alloted number of segments, or we 630 * were short on resources. In this case, we'll copy 631 * and try again. 632 */ 633 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 634 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 635 MGETHDR(m, M_DONTWAIT, MT_DATA); 636 if (m == NULL) { 637 printf("%s: unable to allocate Tx mbuf\n", 638 device_xname(&sc->sc_dev)); 639 break; 640 } 641 if (m0->m_pkthdr.len > MHLEN) { 642 MCLGET(m, M_DONTWAIT); 643 if ((m->m_flags & M_EXT) == 0) { 644 printf("%s: unable to allocate Tx " 645 "cluster\n", device_xname(&sc->sc_dev)); 646 m_freem(m); 647 break; 648 } 649 } 650 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 651 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 652 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 653 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 654 if (error) { 655 printf("%s: unable to load Tx buffer, " 656 "error = %d\n", device_xname(&sc->sc_dev), error); 657 break; 658 } 659 } 660 661 IFQ_DEQUEUE(&ifp->if_snd, m0); 662 if (m != NULL) { 663 m_freem(m0); 664 m0 = m; 665 } 666 667 /* 668 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 669 */ 670 671 /* Sync the DMA map. */ 672 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 673 BUS_DMASYNC_PREWRITE); 674 675 /* Initialize the fragment list. */ 676 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 677 tfd->tfd_frags[seg].frag_addr = 678 htole32(dmamap->dm_segs[seg].ds_addr); 679 tfd->tfd_frags[seg].frag_len = 680 htole32(dmamap->dm_segs[seg].ds_len); 681 totlen += dmamap->dm_segs[seg].ds_len; 682 } 683 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 684 685 /* Initialize the descriptor. */ 686 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 687 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 688 689 /* Sync the descriptor. */ 690 STE_CDTXSYNC(sc, nexttx, 691 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 692 693 /* 694 * Store a pointer to the packet so we can free it later, 695 * and remember what txdirty will be once the packet is 696 * done. 697 */ 698 ds->ds_mbuf = m0; 699 700 /* Advance the tx pointer. */ 701 sc->sc_txpending++; 702 sc->sc_txlast = nexttx; 703 704 #if NBPFILTER > 0 705 /* 706 * Pass the packet to any BPF listeners. 707 */ 708 if (ifp->if_bpf) 709 bpf_mtap(ifp->if_bpf, m0); 710 #endif /* NBPFILTER > 0 */ 711 } 712 713 if (sc->sc_txpending == STE_NTXDESC) { 714 /* No more slots left; notify upper layer. */ 715 ifp->if_flags |= IFF_OACTIVE; 716 } 717 718 if (sc->sc_txpending != opending) { 719 /* 720 * We enqueued packets. If the transmitter was idle, 721 * reset the txdirty pointer. 722 */ 723 if (opending == 0) 724 sc->sc_txdirty = STE_NEXTTX(olasttx); 725 726 /* 727 * Cause a descriptor interrupt to happen on the 728 * last packet we enqueued, and also cause the 729 * DMA engine to wait after is has finished processing 730 * it. 731 */ 732 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 733 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 734 htole32(TFD_TxDMAIndicate); 735 STE_CDTXSYNC(sc, sc->sc_txlast, 736 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 737 738 /* 739 * Link up the new chain of descriptors to the 740 * last. 741 */ 742 sc->sc_txdescs[olasttx].tfd_next = 743 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 744 STE_CDTXSYNC(sc, olasttx, 745 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 746 747 /* 748 * Kick the transmit DMA logic. Note that since we're 749 * using auto-polling, reading the Tx desc pointer will 750 * give it the nudge it needs to get going. 751 */ 752 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 753 STE_TxDMAListPtr) == 0) { 754 bus_space_write_4(sc->sc_st, sc->sc_sh, 755 STE_DMACtrl, DC_TxDMAHalt); 756 ste_dmahalt_wait(sc); 757 bus_space_write_4(sc->sc_st, sc->sc_sh, 758 STE_TxDMAListPtr, 759 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 760 bus_space_write_4(sc->sc_st, sc->sc_sh, 761 STE_DMACtrl, DC_TxDMAResume); 762 } 763 764 /* Set a watchdog timer in case the chip flakes out. */ 765 ifp->if_timer = 5; 766 } 767 } 768 769 /* 770 * ste_watchdog: [ifnet interface function] 771 * 772 * Watchdog timer handler. 773 */ 774 static void 775 ste_watchdog(struct ifnet *ifp) 776 { 777 struct ste_softc *sc = ifp->if_softc; 778 779 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 780 ifp->if_oerrors++; 781 782 ste_txintr(sc); 783 ste_rxintr(sc); 784 (void) ste_init(ifp); 785 786 /* Try to get more packets going. */ 787 ste_start(ifp); 788 } 789 790 /* 791 * ste_ioctl: [ifnet interface function] 792 * 793 * Handle control requests from the operator. 794 */ 795 static int 796 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 797 { 798 struct ste_softc *sc = ifp->if_softc; 799 int s, error; 800 801 s = splnet(); 802 803 error = ether_ioctl(ifp, cmd, data); 804 if (error == ENETRESET) { 805 /* 806 * Multicast list has changed; set the hardware filter 807 * accordingly. 808 */ 809 if (ifp->if_flags & IFF_RUNNING) 810 ste_set_filter(sc); 811 error = 0; 812 } 813 814 /* Try to get more packets going. */ 815 ste_start(ifp); 816 817 splx(s); 818 return (error); 819 } 820 821 /* 822 * ste_intr: 823 * 824 * Interrupt service routine. 825 */ 826 static int 827 ste_intr(void *arg) 828 { 829 struct ste_softc *sc = arg; 830 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 831 uint16_t isr; 832 uint8_t txstat; 833 int wantinit; 834 835 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 836 IS_InterruptStatus) == 0) 837 return (0); 838 839 for (wantinit = 0; wantinit == 0;) { 840 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 841 if ((isr & sc->sc_IntEnable) == 0) 842 break; 843 844 /* Receive interrupts. */ 845 if (isr & IE_RxDMAComplete) 846 ste_rxintr(sc); 847 848 /* Transmit interrupts. */ 849 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 850 ste_txintr(sc); 851 852 /* Statistics overflow. */ 853 if (isr & IE_UpdateStats) 854 ste_stats_update(sc); 855 856 /* Transmission errors. */ 857 if (isr & IE_TxComplete) { 858 for (;;) { 859 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 860 STE_TxStatus); 861 if ((txstat & TS_TxComplete) == 0) 862 break; 863 if (txstat & TS_TxUnderrun) { 864 sc->sc_txthresh += 32; 865 if (sc->sc_txthresh > 0x1ffc) 866 sc->sc_txthresh = 0x1ffc; 867 printf("%s: transmit underrun, new " 868 "threshold: %d bytes\n", 869 device_xname(&sc->sc_dev), 870 sc->sc_txthresh); 871 ste_reset(sc, AC_TxReset | AC_DMA | 872 AC_FIFO | AC_Network); 873 ste_setthresh(sc); 874 bus_space_write_1(sc->sc_st, sc->sc_sh, 875 STE_TxDMAPollPeriod, 127); 876 ste_txrestart(sc, 877 bus_space_read_1(sc->sc_st, 878 sc->sc_sh, STE_TxFrameId)); 879 } 880 if (txstat & TS_TxReleaseError) { 881 printf("%s: Tx FIFO release error\n", 882 device_xname(&sc->sc_dev)); 883 wantinit = 1; 884 } 885 if (txstat & TS_MaxCollisions) { 886 printf("%s: excessive collisions\n", 887 device_xname(&sc->sc_dev)); 888 wantinit = 1; 889 } 890 if (txstat & TS_TxStatusOverflow) { 891 printf("%s: status overflow\n", 892 device_xname(&sc->sc_dev)); 893 wantinit = 1; 894 } 895 bus_space_write_2(sc->sc_st, sc->sc_sh, 896 STE_TxStatus, 0); 897 } 898 } 899 900 /* Host interface errors. */ 901 if (isr & IE_HostError) { 902 printf("%s: Host interface error\n", 903 device_xname(&sc->sc_dev)); 904 wantinit = 1; 905 } 906 } 907 908 if (wantinit) 909 ste_init(ifp); 910 911 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 912 sc->sc_IntEnable); 913 914 /* Try to get more packets going. */ 915 ste_start(ifp); 916 917 return (1); 918 } 919 920 /* 921 * ste_txintr: 922 * 923 * Helper; handle transmit interrupts. 924 */ 925 static void 926 ste_txintr(struct ste_softc *sc) 927 { 928 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 929 struct ste_descsoft *ds; 930 uint32_t control; 931 int i; 932 933 ifp->if_flags &= ~IFF_OACTIVE; 934 935 /* 936 * Go through our Tx list and free mbufs for those 937 * frames which have been transmitted. 938 */ 939 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 940 i = STE_NEXTTX(i), sc->sc_txpending--) { 941 ds = &sc->sc_txsoft[i]; 942 943 STE_CDTXSYNC(sc, i, 944 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 945 946 control = le32toh(sc->sc_txdescs[i].tfd_control); 947 if ((control & TFD_TxDMAComplete) == 0) 948 break; 949 950 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 951 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 952 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 953 m_freem(ds->ds_mbuf); 954 ds->ds_mbuf = NULL; 955 } 956 957 /* Update the dirty transmit buffer pointer. */ 958 sc->sc_txdirty = i; 959 960 /* 961 * If there are no more pending transmissions, cancel the watchdog 962 * timer. 963 */ 964 if (sc->sc_txpending == 0) 965 ifp->if_timer = 0; 966 } 967 968 /* 969 * ste_rxintr: 970 * 971 * Helper; handle receive interrupts. 972 */ 973 static void 974 ste_rxintr(struct ste_softc *sc) 975 { 976 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 977 struct ste_descsoft *ds; 978 struct mbuf *m; 979 uint32_t status; 980 int i, len; 981 982 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 983 ds = &sc->sc_rxsoft[i]; 984 985 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 986 987 status = le32toh(sc->sc_rxdescs[i].rfd_status); 988 989 if ((status & RFD_RxDMAComplete) == 0) 990 break; 991 992 /* 993 * If the packet had an error, simply recycle the 994 * buffer. Note, we count the error later in the 995 * periodic stats update. 996 */ 997 if (status & RFD_RxFrameError) { 998 STE_INIT_RXDESC(sc, i); 999 continue; 1000 } 1001 1002 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1003 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1004 1005 /* 1006 * No errors; receive the packet. Note, we have 1007 * configured the chip to not include the CRC at 1008 * the end of the packet. 1009 */ 1010 len = RFD_RxDMAFrameLen(status); 1011 1012 /* 1013 * If the packet is small enough to fit in a 1014 * single header mbuf, allocate one and copy 1015 * the data into it. This greatly reduces 1016 * memory consumption when we receive lots 1017 * of small packets. 1018 * 1019 * Otherwise, we add a new buffer to the receive 1020 * chain. If this fails, we drop the packet and 1021 * recycle the old buffer. 1022 */ 1023 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1024 MGETHDR(m, M_DONTWAIT, MT_DATA); 1025 if (m == NULL) 1026 goto dropit; 1027 m->m_data += 2; 1028 memcpy(mtod(m, void *), 1029 mtod(ds->ds_mbuf, void *), len); 1030 STE_INIT_RXDESC(sc, i); 1031 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1032 ds->ds_dmamap->dm_mapsize, 1033 BUS_DMASYNC_PREREAD); 1034 } else { 1035 m = ds->ds_mbuf; 1036 if (ste_add_rxbuf(sc, i) != 0) { 1037 dropit: 1038 ifp->if_ierrors++; 1039 STE_INIT_RXDESC(sc, i); 1040 bus_dmamap_sync(sc->sc_dmat, 1041 ds->ds_dmamap, 0, 1042 ds->ds_dmamap->dm_mapsize, 1043 BUS_DMASYNC_PREREAD); 1044 continue; 1045 } 1046 } 1047 1048 m->m_pkthdr.rcvif = ifp; 1049 m->m_pkthdr.len = m->m_len = len; 1050 1051 #if NBPFILTER > 0 1052 /* 1053 * Pass this up to any BPF listeners, but only 1054 * pass if up the stack if it's for us. 1055 */ 1056 if (ifp->if_bpf) 1057 bpf_mtap(ifp->if_bpf, m); 1058 #endif /* NBPFILTER > 0 */ 1059 1060 /* Pass it on. */ 1061 (*ifp->if_input)(ifp, m); 1062 } 1063 1064 /* Update the receive pointer. */ 1065 sc->sc_rxptr = i; 1066 } 1067 1068 /* 1069 * ste_tick: 1070 * 1071 * One second timer, used to tick the MII. 1072 */ 1073 static void 1074 ste_tick(void *arg) 1075 { 1076 struct ste_softc *sc = arg; 1077 int s; 1078 1079 s = splnet(); 1080 mii_tick(&sc->sc_mii); 1081 ste_stats_update(sc); 1082 splx(s); 1083 1084 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1085 } 1086 1087 /* 1088 * ste_stats_update: 1089 * 1090 * Read the ST-201 statistics counters. 1091 */ 1092 static void 1093 ste_stats_update(struct ste_softc *sc) 1094 { 1095 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1096 bus_space_tag_t st = sc->sc_st; 1097 bus_space_handle_t sh = sc->sc_sh; 1098 1099 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1100 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1101 1102 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1103 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1104 1105 ifp->if_opackets += 1106 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1107 ifp->if_ipackets += 1108 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1109 1110 ifp->if_collisions += 1111 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1112 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1113 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1114 1115 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1116 1117 ifp->if_ierrors += 1118 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1119 1120 ifp->if_oerrors += 1121 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1122 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1123 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1124 1125 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1126 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1127 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1128 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1129 } 1130 1131 /* 1132 * ste_reset: 1133 * 1134 * Perform a soft reset on the ST-201. 1135 */ 1136 static void 1137 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1138 { 1139 uint32_t ac; 1140 int i; 1141 1142 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1143 1144 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1145 1146 delay(50000); 1147 1148 for (i = 0; i < STE_TIMEOUT; i++) { 1149 delay(1000); 1150 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1151 AC_ResetBusy) == 0) 1152 break; 1153 } 1154 1155 if (i == STE_TIMEOUT) 1156 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1157 1158 delay(1000); 1159 } 1160 1161 /* 1162 * ste_setthresh: 1163 * 1164 * set the various transmit threshold registers 1165 */ 1166 static void 1167 ste_setthresh(struct ste_softc *sc) 1168 { 1169 /* set the TX threhold */ 1170 bus_space_write_2(sc->sc_st, sc->sc_sh, 1171 STE_TxStartThresh, sc->sc_txthresh); 1172 /* Urgent threshold: set to sc_txthresh / 2 */ 1173 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1174 sc->sc_txthresh >> 6); 1175 /* Burst threshold: use default value (256 bytes) */ 1176 } 1177 1178 /* 1179 * restart TX at the given frame ID in the transmitter ring 1180 */ 1181 static void 1182 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1183 { 1184 u_int32_t control; 1185 1186 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1187 control = le32toh(sc->sc_txdescs[id].tfd_control); 1188 control &= ~TFD_TxDMAComplete; 1189 sc->sc_txdescs[id].tfd_control = htole32(control); 1190 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1191 1192 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1193 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1194 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1195 ste_dmahalt_wait(sc); 1196 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1197 STE_CDTXADDR(sc, id)); 1198 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1199 } 1200 1201 /* 1202 * ste_init: [ ifnet interface function ] 1203 * 1204 * Initialize the interface. Must be called at splnet(). 1205 */ 1206 static int 1207 ste_init(struct ifnet *ifp) 1208 { 1209 struct ste_softc *sc = ifp->if_softc; 1210 bus_space_tag_t st = sc->sc_st; 1211 bus_space_handle_t sh = sc->sc_sh; 1212 struct ste_descsoft *ds; 1213 int i, error = 0; 1214 1215 /* 1216 * Cancel any pending I/O. 1217 */ 1218 ste_stop(ifp, 0); 1219 1220 /* 1221 * Reset the chip to a known state. 1222 */ 1223 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1224 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1225 1226 /* 1227 * Initialize the transmit descriptor ring. 1228 */ 1229 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1230 sc->sc_txpending = 0; 1231 sc->sc_txdirty = 0; 1232 sc->sc_txlast = STE_NTXDESC - 1; 1233 1234 /* 1235 * Initialize the receive descriptor and receive job 1236 * descriptor rings. 1237 */ 1238 for (i = 0; i < STE_NRXDESC; i++) { 1239 ds = &sc->sc_rxsoft[i]; 1240 if (ds->ds_mbuf == NULL) { 1241 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1242 printf("%s: unable to allocate or map rx " 1243 "buffer %d, error = %d\n", 1244 device_xname(&sc->sc_dev), i, error); 1245 /* 1246 * XXX Should attempt to run with fewer receive 1247 * XXX buffers instead of just failing. 1248 */ 1249 ste_rxdrain(sc); 1250 goto out; 1251 } 1252 } else 1253 STE_INIT_RXDESC(sc, i); 1254 } 1255 sc->sc_rxptr = 0; 1256 1257 /* Set the station address. */ 1258 for (i = 0; i < ETHER_ADDR_LEN; i++) 1259 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1260 CLLADDR(ifp->if_sadl)[i]); 1261 1262 /* Set up the receive filter. */ 1263 ste_set_filter(sc); 1264 1265 /* 1266 * Give the receive ring to the chip. 1267 */ 1268 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1269 STE_CDRXADDR(sc, sc->sc_rxptr)); 1270 1271 /* 1272 * We defer giving the transmit ring to the chip until we 1273 * transmit the first packet. 1274 */ 1275 1276 /* 1277 * Initialize the Tx auto-poll period. It's OK to make this number 1278 * large (127 is the max) -- we explicitly kick the transmit engine 1279 * when there's actually a packet. We are using auto-polling only 1280 * to make the interface to the transmit engine not suck. 1281 */ 1282 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1283 1284 /* ..and the Rx auto-poll period. */ 1285 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1286 1287 /* Initialize the Tx start threshold. */ 1288 ste_setthresh(sc); 1289 1290 /* Set the FIFO release threshold to 512 bytes. */ 1291 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1292 1293 /* Set maximum packet size for VLAN. */ 1294 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1295 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1296 else 1297 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1298 1299 /* 1300 * Initialize the interrupt mask. 1301 */ 1302 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1303 IE_TxDMAComplete | IE_RxDMAComplete; 1304 1305 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1306 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1307 1308 /* 1309 * Start the receive DMA engine. 1310 */ 1311 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1312 1313 /* 1314 * Initialize MacCtrl0 -- do it before setting the media, 1315 * as setting the media will actually program the register. 1316 */ 1317 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1318 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1319 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1320 1321 /* 1322 * Set the current media. 1323 */ 1324 if ((error = ether_mediachange(ifp)) != 0) 1325 goto out; 1326 1327 /* 1328 * Start the MAC. 1329 */ 1330 bus_space_write_2(st, sh, STE_MacCtrl1, 1331 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1332 1333 /* 1334 * Start the one second MII clock. 1335 */ 1336 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1337 1338 /* 1339 * ...all done! 1340 */ 1341 ifp->if_flags |= IFF_RUNNING; 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 1344 out: 1345 if (error) 1346 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1347 return (error); 1348 } 1349 1350 /* 1351 * ste_drain: 1352 * 1353 * Drain the receive queue. 1354 */ 1355 static void 1356 ste_rxdrain(struct ste_softc *sc) 1357 { 1358 struct ste_descsoft *ds; 1359 int i; 1360 1361 for (i = 0; i < STE_NRXDESC; i++) { 1362 ds = &sc->sc_rxsoft[i]; 1363 if (ds->ds_mbuf != NULL) { 1364 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1365 m_freem(ds->ds_mbuf); 1366 ds->ds_mbuf = NULL; 1367 } 1368 } 1369 } 1370 1371 /* 1372 * ste_stop: [ ifnet interface function ] 1373 * 1374 * Stop transmission on the interface. 1375 */ 1376 static void 1377 ste_stop(struct ifnet *ifp, int disable) 1378 { 1379 struct ste_softc *sc = ifp->if_softc; 1380 struct ste_descsoft *ds; 1381 int i; 1382 1383 /* 1384 * Stop the one second clock. 1385 */ 1386 callout_stop(&sc->sc_tick_ch); 1387 1388 /* Down the MII. */ 1389 mii_down(&sc->sc_mii); 1390 1391 /* 1392 * Disable interrupts. 1393 */ 1394 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1395 1396 /* 1397 * Stop receiver, transmitter, and stats update. 1398 */ 1399 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1400 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1401 1402 /* 1403 * Stop the transmit and receive DMA. 1404 */ 1405 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1406 DC_RxDMAHalt | DC_TxDMAHalt); 1407 ste_dmahalt_wait(sc); 1408 1409 /* 1410 * Release any queued transmit buffers. 1411 */ 1412 for (i = 0; i < STE_NTXDESC; i++) { 1413 ds = &sc->sc_txsoft[i]; 1414 if (ds->ds_mbuf != NULL) { 1415 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1416 m_freem(ds->ds_mbuf); 1417 ds->ds_mbuf = NULL; 1418 } 1419 } 1420 1421 /* 1422 * Mark the interface down and cancel the watchdog timer. 1423 */ 1424 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1425 ifp->if_timer = 0; 1426 1427 if (disable) 1428 ste_rxdrain(sc); 1429 } 1430 1431 static int 1432 ste_eeprom_wait(struct ste_softc *sc) 1433 { 1434 int i; 1435 1436 for (i = 0; i < STE_TIMEOUT; i++) { 1437 delay(1000); 1438 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1439 EC_EepromBusy) == 0) 1440 return (0); 1441 } 1442 return (1); 1443 } 1444 1445 /* 1446 * ste_read_eeprom: 1447 * 1448 * Read data from the serial EEPROM. 1449 */ 1450 static void 1451 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1452 { 1453 1454 if (ste_eeprom_wait(sc)) 1455 printf("%s: EEPROM failed to come ready\n", 1456 device_xname(&sc->sc_dev)); 1457 1458 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1459 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1460 if (ste_eeprom_wait(sc)) 1461 printf("%s: EEPROM read timed out\n", 1462 device_xname(&sc->sc_dev)); 1463 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1464 } 1465 1466 /* 1467 * ste_add_rxbuf: 1468 * 1469 * Add a receive buffer to the indicated descriptor. 1470 */ 1471 static int 1472 ste_add_rxbuf(struct ste_softc *sc, int idx) 1473 { 1474 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1475 struct mbuf *m; 1476 int error; 1477 1478 MGETHDR(m, M_DONTWAIT, MT_DATA); 1479 if (m == NULL) 1480 return (ENOBUFS); 1481 1482 MCLGET(m, M_DONTWAIT); 1483 if ((m->m_flags & M_EXT) == 0) { 1484 m_freem(m); 1485 return (ENOBUFS); 1486 } 1487 1488 if (ds->ds_mbuf != NULL) 1489 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1490 1491 ds->ds_mbuf = m; 1492 1493 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1494 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1495 BUS_DMA_READ|BUS_DMA_NOWAIT); 1496 if (error) { 1497 printf("%s: can't load rx DMA map %d, error = %d\n", 1498 device_xname(&sc->sc_dev), idx, error); 1499 panic("ste_add_rxbuf"); /* XXX */ 1500 } 1501 1502 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1503 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1504 1505 STE_INIT_RXDESC(sc, idx); 1506 1507 return (0); 1508 } 1509 1510 /* 1511 * ste_set_filter: 1512 * 1513 * Set up the receive filter. 1514 */ 1515 static void 1516 ste_set_filter(struct ste_softc *sc) 1517 { 1518 struct ethercom *ec = &sc->sc_ethercom; 1519 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1520 struct ether_multi *enm; 1521 struct ether_multistep step; 1522 uint32_t crc; 1523 uint16_t mchash[4]; 1524 1525 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1526 if (ifp->if_flags & IFF_BROADCAST) 1527 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1528 1529 if (ifp->if_flags & IFF_PROMISC) { 1530 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1531 goto allmulti; 1532 } 1533 1534 /* 1535 * Set up the multicast address filter by passing all multicast 1536 * addresses through a CRC generator, and then using the low-order 1537 * 6 bits as an index into the 64 bit multicast hash table. The 1538 * high order bits select the register, while the rest of the bits 1539 * select the bit within the register. 1540 */ 1541 1542 memset(mchash, 0, sizeof(mchash)); 1543 1544 ETHER_FIRST_MULTI(step, ec, enm); 1545 if (enm == NULL) 1546 goto done; 1547 1548 while (enm != NULL) { 1549 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1550 /* 1551 * We must listen to a range of multicast addresses. 1552 * For now, just accept all multicasts, rather than 1553 * trying to set only those filter bits needed to match 1554 * the range. (At this time, the only use of address 1555 * ranges is for IP multicast routing, for which the 1556 * range is big enough to require all bits set.) 1557 */ 1558 goto allmulti; 1559 } 1560 1561 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1562 1563 /* Just want the 6 least significant bits. */ 1564 crc &= 0x3f; 1565 1566 /* Set the corresponding bit in the hash table. */ 1567 mchash[crc >> 4] |= 1 << (crc & 0xf); 1568 1569 ETHER_NEXT_MULTI(step, enm); 1570 } 1571 1572 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1573 1574 ifp->if_flags &= ~IFF_ALLMULTI; 1575 goto done; 1576 1577 allmulti: 1578 ifp->if_flags |= IFF_ALLMULTI; 1579 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1580 1581 done: 1582 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1583 /* 1584 * Program the multicast hash table. 1585 */ 1586 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1587 mchash[0]); 1588 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1589 mchash[1]); 1590 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1591 mchash[2]); 1592 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1593 mchash[3]); 1594 } 1595 1596 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1597 sc->sc_ReceiveMode); 1598 } 1599 1600 /* 1601 * ste_mii_readreg: [mii interface function] 1602 * 1603 * Read a PHY register on the MII of the ST-201. 1604 */ 1605 static int 1606 ste_mii_readreg(device_t self, int phy, int reg) 1607 { 1608 1609 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1610 } 1611 1612 /* 1613 * ste_mii_writereg: [mii interface function] 1614 * 1615 * Write a PHY register on the MII of the ST-201. 1616 */ 1617 static void 1618 ste_mii_writereg(device_t self, int phy, int reg, int val) 1619 { 1620 1621 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1622 } 1623 1624 /* 1625 * ste_mii_statchg: [mii interface function] 1626 * 1627 * Callback from MII layer when media changes. 1628 */ 1629 static void 1630 ste_mii_statchg(device_t self) 1631 { 1632 struct ste_softc *sc = device_private(self); 1633 1634 if (sc->sc_mii.mii_media_active & IFM_FDX) 1635 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1636 else 1637 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1638 1639 /* XXX 802.1x flow-control? */ 1640 1641 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1642 } 1643 1644 /* 1645 * ste_mii_bitbang_read: [mii bit-bang interface function] 1646 * 1647 * Read the MII serial port for the MII bit-bang module. 1648 */ 1649 static uint32_t 1650 ste_mii_bitbang_read(device_t self) 1651 { 1652 struct ste_softc *sc = device_private(self); 1653 1654 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1655 } 1656 1657 /* 1658 * ste_mii_bitbang_write: [mii big-bang interface function] 1659 * 1660 * Write the MII serial port for the MII bit-bang module. 1661 */ 1662 static void 1663 ste_mii_bitbang_write(device_t self, uint32_t val) 1664 { 1665 struct ste_softc *sc = device_private(self); 1666 1667 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1668 } 1669