1 /* $NetBSD: if_ste.c,v 1.11 2002/06/05 16:27:29 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.11 2002/06/05 16:27:29 bouyer Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 struct callout sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 void ste_start(struct ifnet *); 208 void ste_watchdog(struct ifnet *); 209 int ste_ioctl(struct ifnet *, u_long, caddr_t); 210 int ste_init(struct ifnet *); 211 void ste_stop(struct ifnet *, int); 212 213 void ste_shutdown(void *); 214 215 void ste_reset(struct ste_softc *, u_int32_t); 216 void ste_setthresh(struct ste_softc *); 217 void ste_txrestart(struct ste_softc *, u_int8_t); 218 void ste_rxdrain(struct ste_softc *); 219 int ste_add_rxbuf(struct ste_softc *, int); 220 void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 221 void ste_tick(void *); 222 223 void ste_stats_update(struct ste_softc *); 224 225 void ste_set_filter(struct ste_softc *); 226 227 int ste_intr(void *); 228 void ste_txintr(struct ste_softc *); 229 void ste_rxintr(struct ste_softc *); 230 231 int ste_mii_readreg(struct device *, int, int); 232 void ste_mii_writereg(struct device *, int, int, int); 233 void ste_mii_statchg(struct device *); 234 235 int ste_mediachange(struct ifnet *); 236 void ste_mediastatus(struct ifnet *, struct ifmediareq *); 237 238 int ste_match(struct device *, struct cfdata *, void *); 239 void ste_attach(struct device *, struct device *, void *); 240 241 int ste_copy_small = 0; 242 243 struct cfattach ste_ca = { 244 sizeof(struct ste_softc), ste_match, ste_attach, 245 }; 246 247 uint32_t ste_mii_bitbang_read(struct device *); 248 void ste_mii_bitbang_write(struct device *, uint32_t); 249 250 const struct mii_bitbang_ops ste_mii_bitbang_ops = { 251 ste_mii_bitbang_read, 252 ste_mii_bitbang_write, 253 { 254 PC_MgmtData, /* MII_BIT_MDO */ 255 PC_MgmtData, /* MII_BIT_MDI */ 256 PC_MgmtClk, /* MII_BIT_MDC */ 257 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 258 0, /* MII_BIT_DIR_PHY_HOST */ 259 } 260 }; 261 262 /* 263 * Devices supported by this driver. 264 */ 265 const struct ste_product { 266 pci_vendor_id_t ste_vendor; 267 pci_product_id_t ste_product; 268 const char *ste_name; 269 } ste_products[] = { 270 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 271 "Sundance ST-201 10/100 Ethernet" }, 272 273 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 274 "D-Link DL-1002 10/100 Ethernet" }, 275 276 { 0, 0, 277 NULL }, 278 }; 279 280 static const struct ste_product * 281 ste_lookup(const struct pci_attach_args *pa) 282 { 283 const struct ste_product *sp; 284 285 for (sp = ste_products; sp->ste_name != NULL; sp++) { 286 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 287 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 288 return (sp); 289 } 290 return (NULL); 291 } 292 293 int 294 ste_match(struct device *parent, struct cfdata *cf, void *aux) 295 { 296 struct pci_attach_args *pa = aux; 297 298 if (ste_lookup(pa) != NULL) 299 return (1); 300 301 return (0); 302 } 303 304 void 305 ste_attach(struct device *parent, struct device *self, void *aux) 306 { 307 struct ste_softc *sc = (struct ste_softc *) self; 308 struct pci_attach_args *pa = aux; 309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 310 pci_chipset_tag_t pc = pa->pa_pc; 311 pci_intr_handle_t ih; 312 const char *intrstr = NULL; 313 bus_space_tag_t iot, memt; 314 bus_space_handle_t ioh, memh; 315 bus_dma_segment_t seg; 316 int ioh_valid, memh_valid; 317 int i, rseg, error; 318 const struct ste_product *sp; 319 pcireg_t pmode; 320 uint8_t enaddr[ETHER_ADDR_LEN]; 321 uint16_t myea[ETHER_ADDR_LEN / 2]; 322 int pmreg; 323 324 callout_init(&sc->sc_tick_ch); 325 326 sp = ste_lookup(pa); 327 if (sp == NULL) { 328 printf("\n"); 329 panic("ste_attach: impossible"); 330 } 331 332 printf(": %s\n", sp->ste_name); 333 334 /* 335 * Map the device. 336 */ 337 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 338 PCI_MAPREG_TYPE_IO, 0, 339 &iot, &ioh, NULL, NULL) == 0); 340 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 341 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 342 &memt, &memh, NULL, NULL) == 0); 343 344 if (memh_valid) { 345 sc->sc_st = memt; 346 sc->sc_sh = memh; 347 } else if (ioh_valid) { 348 sc->sc_st = iot; 349 sc->sc_sh = ioh; 350 } else { 351 printf("%s: unable to map device registers\n", 352 sc->sc_dev.dv_xname); 353 return; 354 } 355 356 sc->sc_dmat = pa->pa_dmat; 357 358 /* Enable bus mastering. */ 359 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 360 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 361 PCI_COMMAND_MASTER_ENABLE); 362 363 /* Get it out of power save mode if needed. */ 364 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 365 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 366 if (pmode == 3) { 367 /* 368 * The card has lost all configuration data in 369 * this state, so punt. 370 */ 371 printf("%s: unable to wake up from power state D3\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } 375 if (pmode != 0) { 376 printf("%s: waking up from power state D%d\n", 377 sc->sc_dev.dv_xname, pmode); 378 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 379 } 380 } 381 382 /* 383 * Map and establish our interrupt. 384 */ 385 if (pci_intr_map(pa, &ih)) { 386 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 387 return; 388 } 389 intrstr = pci_intr_string(pc, ih); 390 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 391 if (sc->sc_ih == NULL) { 392 printf("%s: unable to establish interrupt", 393 sc->sc_dev.dv_xname); 394 if (intrstr != NULL) 395 printf(" at %s", intrstr); 396 printf("\n"); 397 return; 398 } 399 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 400 401 /* 402 * Allocate the control data structures, and create and load the 403 * DMA map for it. 404 */ 405 if ((error = bus_dmamem_alloc(sc->sc_dmat, 406 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 407 0)) != 0) { 408 printf("%s: unable to allocate control data, error = %d\n", 409 sc->sc_dev.dv_xname, error); 410 goto fail_0; 411 } 412 413 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 414 sizeof(struct ste_control_data), (caddr_t *)&sc->sc_control_data, 415 BUS_DMA_COHERENT)) != 0) { 416 printf("%s: unable to map control data, error = %d\n", 417 sc->sc_dev.dv_xname, error); 418 goto fail_1; 419 } 420 421 if ((error = bus_dmamap_create(sc->sc_dmat, 422 sizeof(struct ste_control_data), 1, 423 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 424 printf("%s: unable to create control data DMA map, " 425 "error = %d\n", sc->sc_dev.dv_xname, error); 426 goto fail_2; 427 } 428 429 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 430 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 431 0)) != 0) { 432 printf("%s: unable to load control data DMA map, error = %d\n", 433 sc->sc_dev.dv_xname, error); 434 goto fail_3; 435 } 436 437 /* 438 * Create the transmit buffer DMA maps. 439 */ 440 for (i = 0; i < STE_NTXDESC; i++) { 441 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 442 STE_NTXFRAGS, MCLBYTES, 0, 0, 443 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 444 printf("%s: unable to create tx DMA map %d, " 445 "error = %d\n", sc->sc_dev.dv_xname, i, error); 446 goto fail_4; 447 } 448 } 449 450 /* 451 * Create the receive buffer DMA maps. 452 */ 453 for (i = 0; i < STE_NRXDESC; i++) { 454 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 455 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 456 printf("%s: unable to create rx DMA map %d, " 457 "error = %d\n", sc->sc_dev.dv_xname, i, error); 458 goto fail_5; 459 } 460 sc->sc_rxsoft[i].ds_mbuf = NULL; 461 } 462 463 /* 464 * Reset the chip to a known state. 465 */ 466 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 467 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 468 469 /* 470 * Read the Ethernet address from the EEPROM. 471 */ 472 for (i = 0; i < 3; i++) { 473 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 474 myea[i] = le16toh(myea[i]); 475 } 476 memcpy(enaddr, myea, sizeof(enaddr)); 477 478 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 479 ether_sprintf(enaddr)); 480 481 /* 482 * Initialize our media structures and probe the MII. 483 */ 484 sc->sc_mii.mii_ifp = ifp; 485 sc->sc_mii.mii_readreg = ste_mii_readreg; 486 sc->sc_mii.mii_writereg = ste_mii_writereg; 487 sc->sc_mii.mii_statchg = ste_mii_statchg; 488 ifmedia_init(&sc->sc_mii.mii_media, 0, ste_mediachange, 489 ste_mediastatus); 490 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 491 MII_OFFSET_ANY, 0); 492 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 493 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 495 } else 496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 497 498 ifp = &sc->sc_ethercom.ec_if; 499 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 500 ifp->if_softc = sc; 501 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 502 ifp->if_ioctl = ste_ioctl; 503 ifp->if_start = ste_start; 504 ifp->if_watchdog = ste_watchdog; 505 ifp->if_init = ste_init; 506 ifp->if_stop = ste_stop; 507 IFQ_SET_READY(&ifp->if_snd); 508 509 /* 510 * Default the transmit threshold to 128 bytes. 511 */ 512 sc->sc_txthresh = 128; 513 514 /* 515 * Disable MWI if the PCI layer tells us to. 516 */ 517 sc->sc_DMACtrl = 0; 518 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 519 sc->sc_DMACtrl |= DC_MWIDisable; 520 521 /* 522 * We can support 802.1Q VLAN-sized frames. 523 */ 524 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 525 526 /* 527 * Attach the interface. 528 */ 529 if_attach(ifp); 530 ether_ifattach(ifp, enaddr); 531 532 /* 533 * Make sure the interface is shutdown during reboot. 534 */ 535 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 536 if (sc->sc_sdhook == NULL) 537 printf("%s: WARNING: unable to establish shutdown hook\n", 538 sc->sc_dev.dv_xname); 539 return; 540 541 /* 542 * Free any resources we've allocated during the failed attach 543 * attempt. Do this in reverse order and fall through. 544 */ 545 fail_5: 546 for (i = 0; i < STE_NRXDESC; i++) { 547 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 548 bus_dmamap_destroy(sc->sc_dmat, 549 sc->sc_rxsoft[i].ds_dmamap); 550 } 551 fail_4: 552 for (i = 0; i < STE_NTXDESC; i++) { 553 if (sc->sc_txsoft[i].ds_dmamap != NULL) 554 bus_dmamap_destroy(sc->sc_dmat, 555 sc->sc_txsoft[i].ds_dmamap); 556 } 557 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 558 fail_3: 559 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 560 fail_2: 561 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 562 sizeof(struct ste_control_data)); 563 fail_1: 564 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 565 fail_0: 566 return; 567 } 568 569 /* 570 * ste_shutdown: 571 * 572 * Make sure the interface is stopped at reboot time. 573 */ 574 void 575 ste_shutdown(void *arg) 576 { 577 struct ste_softc *sc = arg; 578 579 ste_stop(&sc->sc_ethercom.ec_if, 1); 580 } 581 582 static void 583 ste_dmahalt_wait(struct ste_softc *sc) 584 { 585 int i; 586 587 for (i = 0; i < STE_TIMEOUT; i++) { 588 delay(2); 589 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 590 DC_DMAHaltBusy) == 0) 591 break; 592 } 593 594 if (i == STE_TIMEOUT) 595 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 596 } 597 598 /* 599 * ste_start: [ifnet interface function] 600 * 601 * Start packet transmission on the interface. 602 */ 603 void 604 ste_start(struct ifnet *ifp) 605 { 606 struct ste_softc *sc = ifp->if_softc; 607 struct mbuf *m0, *m; 608 struct ste_descsoft *ds; 609 struct ste_tfd *tfd; 610 bus_dmamap_t dmamap; 611 int error, olasttx, nexttx, opending, seg, totlen; 612 613 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 614 return; 615 616 /* 617 * Remember the previous number of pending transmissions 618 * and the current last descriptor in the list. 619 */ 620 opending = sc->sc_txpending; 621 olasttx = sc->sc_txlast; 622 623 /* 624 * Loop through the send queue, setting up transmit descriptors 625 * until we drain the queue, or use up all available transmit 626 * descriptors. 627 */ 628 while (sc->sc_txpending < STE_NTXDESC) { 629 /* 630 * Grab a packet off the queue. 631 */ 632 IFQ_POLL(&ifp->if_snd, m0); 633 if (m0 == NULL) 634 break; 635 m = NULL; 636 637 /* 638 * Get the last and next available transmit descriptor. 639 */ 640 nexttx = STE_NEXTTX(sc->sc_txlast); 641 tfd = &sc->sc_txdescs[nexttx]; 642 ds = &sc->sc_txsoft[nexttx]; 643 644 dmamap = ds->ds_dmamap; 645 646 /* 647 * Load the DMA map. If this fails, the packet either 648 * didn't fit in the alloted number of segments, or we 649 * were short on resources. In this case, we'll copy 650 * and try again. 651 */ 652 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 653 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 654 MGETHDR(m, M_DONTWAIT, MT_DATA); 655 if (m == NULL) { 656 printf("%s: unable to allocate Tx mbuf\n", 657 sc->sc_dev.dv_xname); 658 break; 659 } 660 if (m0->m_pkthdr.len > MHLEN) { 661 MCLGET(m, M_DONTWAIT); 662 if ((m->m_flags & M_EXT) == 0) { 663 printf("%s: unable to allocate Tx " 664 "cluster\n", sc->sc_dev.dv_xname); 665 m_freem(m); 666 break; 667 } 668 } 669 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 670 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 671 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 672 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 673 if (error) { 674 printf("%s: unable to load Tx buffer, " 675 "error = %d\n", sc->sc_dev.dv_xname, error); 676 break; 677 } 678 } 679 680 IFQ_DEQUEUE(&ifp->if_snd, m0); 681 if (m != NULL) { 682 m_freem(m0); 683 m0 = m; 684 } 685 686 /* 687 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 688 */ 689 690 /* Sync the DMA map. */ 691 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 692 BUS_DMASYNC_PREWRITE); 693 694 /* Initialize the fragment list. */ 695 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 696 tfd->tfd_frags[seg].frag_addr = 697 htole32(dmamap->dm_segs[seg].ds_addr); 698 tfd->tfd_frags[seg].frag_len = 699 htole32(dmamap->dm_segs[seg].ds_len); 700 totlen += dmamap->dm_segs[seg].ds_len; 701 } 702 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 703 704 /* Initialize the descriptor. */ 705 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 706 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 707 708 /* Sync the descriptor. */ 709 STE_CDTXSYNC(sc, nexttx, 710 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 711 712 /* 713 * Store a pointer to the packet so we can free it later, 714 * and remember what txdirty will be once the packet is 715 * done. 716 */ 717 ds->ds_mbuf = m0; 718 719 /* Advance the tx pointer. */ 720 sc->sc_txpending++; 721 sc->sc_txlast = nexttx; 722 723 #if NBPFILTER > 0 724 /* 725 * Pass the packet to any BPF listeners. 726 */ 727 if (ifp->if_bpf) 728 bpf_mtap(ifp->if_bpf, m0); 729 #endif /* NBPFILTER > 0 */ 730 } 731 732 if (sc->sc_txpending == STE_NTXDESC) { 733 /* No more slots left; notify upper layer. */ 734 ifp->if_flags |= IFF_OACTIVE; 735 } 736 737 if (sc->sc_txpending != opending) { 738 /* 739 * We enqueued packets. If the transmitter was idle, 740 * reset the txdirty pointer. 741 */ 742 if (opending == 0) 743 sc->sc_txdirty = STE_NEXTTX(olasttx); 744 745 /* 746 * Cause a descriptor interrupt to happen on the 747 * last packet we enqueued, and also cause the 748 * DMA engine to wait after is has finished processing 749 * it. 750 */ 751 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 752 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 753 htole32(TFD_TxDMAIndicate); 754 STE_CDTXSYNC(sc, sc->sc_txlast, 755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 756 757 /* 758 * Link up the new chain of descriptors to the 759 * last. 760 */ 761 sc->sc_txdescs[olasttx].tfd_next = 762 STE_CDTXADDR(sc, STE_NEXTTX(olasttx)); 763 STE_CDTXSYNC(sc, olasttx, 764 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 765 766 /* 767 * Kick the transmit DMA logic. Note that since we're 768 * using auto-polling, reading the Tx desc pointer will 769 * give it the nudge it needs to get going. 770 */ 771 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 772 STE_TxDMAListPtr) == 0) { 773 bus_space_write_4(sc->sc_st, sc->sc_sh, 774 STE_DMACtrl, DC_TxDMAHalt); 775 ste_dmahalt_wait(sc); 776 bus_space_write_4(sc->sc_st, sc->sc_sh, 777 STE_TxDMAListPtr, 778 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 779 bus_space_write_4(sc->sc_st, sc->sc_sh, 780 STE_DMACtrl, DC_TxDMAResume); 781 } 782 783 /* Set a watchdog timer in case the chip flakes out. */ 784 ifp->if_timer = 5; 785 } 786 } 787 788 /* 789 * ste_watchdog: [ifnet interface function] 790 * 791 * Watchdog timer handler. 792 */ 793 void 794 ste_watchdog(struct ifnet *ifp) 795 { 796 struct ste_softc *sc = ifp->if_softc; 797 798 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 799 ifp->if_oerrors++; 800 801 (void) ste_init(ifp); 802 803 /* Try to get more packets going. */ 804 ste_start(ifp); 805 } 806 807 /* 808 * ste_ioctl: [ifnet interface function] 809 * 810 * Handle control requests from the operator. 811 */ 812 int 813 ste_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 814 { 815 struct ste_softc *sc = ifp->if_softc; 816 struct ifreq *ifr = (struct ifreq *)data; 817 int s, error; 818 819 s = splnet(); 820 821 switch (cmd) { 822 case SIOCSIFMEDIA: 823 case SIOCGIFMEDIA: 824 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 825 break; 826 827 default: 828 error = ether_ioctl(ifp, cmd, data); 829 if (error == ENETRESET) { 830 /* 831 * Multicast list has changed; set the hardware filter 832 * accordingly. 833 */ 834 ste_set_filter(sc); 835 error = 0; 836 } 837 break; 838 } 839 840 /* Try to get more packets going. */ 841 ste_start(ifp); 842 843 splx(s); 844 return (error); 845 } 846 847 /* 848 * ste_intr: 849 * 850 * Interrupt service routine. 851 */ 852 int 853 ste_intr(void *arg) 854 { 855 struct ste_softc *sc = arg; 856 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 857 uint16_t isr; 858 uint8_t txstat; 859 int wantinit; 860 861 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 862 IS_InterruptStatus) == 0) 863 return (0); 864 865 for (wantinit = 0; wantinit == 0;) { 866 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 867 if ((isr & sc->sc_IntEnable) == 0) 868 break; 869 870 /* Receive interrupts. */ 871 if (isr & IE_RxDMAComplete) 872 ste_rxintr(sc); 873 874 /* Transmit interrupts. */ 875 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 876 ste_txintr(sc); 877 878 /* Statistics overflow. */ 879 if (isr & IE_UpdateStats) 880 ste_stats_update(sc); 881 882 /* Transmission errors. */ 883 if (isr & IE_TxComplete) { 884 for (;;) { 885 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 886 STE_TxStatus); 887 if ((txstat & TS_TxComplete) == 0) 888 break; 889 if (txstat & TS_TxUnderrun) { 890 sc->sc_txthresh += 32; 891 if (sc->sc_txthresh > 0x1ffc) 892 sc->sc_txthresh = 0x1ffc; 893 printf("%s: transmit underrun, new " 894 "threshold: %d bytes\n", 895 sc->sc_dev.dv_xname, 896 sc->sc_txthresh); 897 ste_reset(sc, AC_TxReset | AC_DMA | 898 AC_FIFO | AC_Network); 899 ste_setthresh(sc); 900 bus_space_write_1(sc->sc_st, sc->sc_sh, 901 STE_TxDMAPollPeriod, 127); 902 ste_txrestart(sc, 903 bus_space_read_1(sc->sc_st, 904 sc->sc_sh, STE_TxFrameId)); 905 } 906 if (txstat & TS_TxReleaseError) { 907 printf("%s: Tx FIFO release error\n", 908 sc->sc_dev.dv_xname); 909 wantinit = 1; 910 } 911 if (txstat & TS_MaxCollisions) { 912 printf("%s: excessive collisions\n", 913 sc->sc_dev.dv_xname); 914 wantinit = 1; 915 } 916 if (txstat & TS_TxStatusOverflow) { 917 printf("%s: status overflow\n", 918 sc->sc_dev.dv_xname); 919 wantinit = 1; 920 } 921 bus_space_write_2(sc->sc_st, sc->sc_sh, 922 STE_TxStatus, 0); 923 } 924 } 925 926 /* Host interface errors. */ 927 if (isr & IE_HostError) { 928 printf("%s: Host interface error\n", 929 sc->sc_dev.dv_xname); 930 wantinit = 1; 931 } 932 } 933 934 if (wantinit) 935 ste_init(ifp); 936 937 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 938 sc->sc_IntEnable); 939 940 /* Try to get more packets going. */ 941 ste_start(ifp); 942 943 return (1); 944 } 945 946 /* 947 * ste_txintr: 948 * 949 * Helper; handle transmit interrupts. 950 */ 951 void 952 ste_txintr(struct ste_softc *sc) 953 { 954 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 955 struct ste_descsoft *ds; 956 uint32_t control; 957 int i; 958 959 ifp->if_flags &= ~IFF_OACTIVE; 960 961 /* 962 * Go through our Tx list and free mbufs for those 963 * frames which have been transmitted. 964 */ 965 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 966 i = STE_NEXTTX(i), sc->sc_txpending--) { 967 ds = &sc->sc_txsoft[i]; 968 969 STE_CDTXSYNC(sc, i, 970 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 971 972 control = le32toh(sc->sc_txdescs[i].tfd_control); 973 if ((control & TFD_TxDMAComplete) == 0) 974 break; 975 976 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 977 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 978 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 979 m_freem(ds->ds_mbuf); 980 ds->ds_mbuf = NULL; 981 } 982 983 /* Update the dirty transmit buffer pointer. */ 984 sc->sc_txdirty = i; 985 986 /* 987 * If there are no more pending transmissions, cancel the watchdog 988 * timer. 989 */ 990 if (sc->sc_txpending == 0) 991 ifp->if_timer = 0; 992 } 993 994 /* 995 * ste_rxintr: 996 * 997 * Helper; handle receive interrupts. 998 */ 999 void 1000 ste_rxintr(struct ste_softc *sc) 1001 { 1002 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1003 struct ste_descsoft *ds; 1004 struct mbuf *m; 1005 uint32_t status; 1006 int i, len; 1007 1008 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 1009 ds = &sc->sc_rxsoft[i]; 1010 1011 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1012 1013 status = le32toh(sc->sc_rxdescs[i].rfd_status); 1014 1015 if ((status & RFD_RxDMAComplete) == 0) 1016 break; 1017 1018 /* 1019 * If the packet had an error, simply recycle the 1020 * buffer. Note, we count the error later in the 1021 * periodic stats update. 1022 */ 1023 if (status & RFD_RxFrameError) { 1024 STE_INIT_RXDESC(sc, i); 1025 continue; 1026 } 1027 1028 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1029 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1030 1031 /* 1032 * No errors; receive the packet. Note, we have 1033 * configured the chip to not include the CRC at 1034 * the end of the packet. 1035 */ 1036 len = RFD_RxDMAFrameLen(status); 1037 1038 /* 1039 * If the packet is small enough to fit in a 1040 * single header mbuf, allocate one and copy 1041 * the data into it. This greatly reduces 1042 * memory consumption when we receive lots 1043 * of small packets. 1044 * 1045 * Otherwise, we add a new buffer to the receive 1046 * chain. If this fails, we drop the packet and 1047 * recycle the old buffer. 1048 */ 1049 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1050 MGETHDR(m, M_DONTWAIT, MT_DATA); 1051 if (m == NULL) 1052 goto dropit; 1053 m->m_data += 2; 1054 memcpy(mtod(m, caddr_t), 1055 mtod(ds->ds_mbuf, caddr_t), len); 1056 STE_INIT_RXDESC(sc, i); 1057 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1058 ds->ds_dmamap->dm_mapsize, 1059 BUS_DMASYNC_PREREAD); 1060 } else { 1061 m = ds->ds_mbuf; 1062 if (ste_add_rxbuf(sc, i) != 0) { 1063 dropit: 1064 ifp->if_ierrors++; 1065 STE_INIT_RXDESC(sc, i); 1066 bus_dmamap_sync(sc->sc_dmat, 1067 ds->ds_dmamap, 0, 1068 ds->ds_dmamap->dm_mapsize, 1069 BUS_DMASYNC_PREREAD); 1070 continue; 1071 } 1072 } 1073 1074 m->m_pkthdr.rcvif = ifp; 1075 m->m_pkthdr.len = m->m_len = len; 1076 1077 #if NBPFILTER > 0 1078 /* 1079 * Pass this up to any BPF listeners, but only 1080 * pass if up the stack if it's for us. 1081 */ 1082 if (ifp->if_bpf) 1083 bpf_mtap(ifp->if_bpf, m); 1084 #endif /* NBPFILTER > 0 */ 1085 1086 /* Pass it on. */ 1087 (*ifp->if_input)(ifp, m); 1088 } 1089 1090 /* Update the receive pointer. */ 1091 sc->sc_rxptr = i; 1092 } 1093 1094 /* 1095 * ste_tick: 1096 * 1097 * One second timer, used to tick the MII. 1098 */ 1099 void 1100 ste_tick(void *arg) 1101 { 1102 struct ste_softc *sc = arg; 1103 int s; 1104 1105 s = splnet(); 1106 mii_tick(&sc->sc_mii); 1107 ste_stats_update(sc); 1108 splx(s); 1109 1110 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1111 } 1112 1113 /* 1114 * ste_stats_update: 1115 * 1116 * Read the ST-201 statistics counters. 1117 */ 1118 void 1119 ste_stats_update(struct ste_softc *sc) 1120 { 1121 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1122 bus_space_tag_t st = sc->sc_st; 1123 bus_space_handle_t sh = sc->sc_sh; 1124 1125 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1126 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1127 1128 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1129 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1130 1131 ifp->if_opackets += 1132 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1133 ifp->if_ipackets += 1134 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1135 1136 ifp->if_collisions += 1137 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1138 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1139 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1140 1141 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1142 1143 ifp->if_ierrors += 1144 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1145 1146 ifp->if_oerrors += 1147 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1148 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1149 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1150 1151 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1152 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1153 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1154 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1155 } 1156 1157 /* 1158 * ste_reset: 1159 * 1160 * Perform a soft reset on the ST-201. 1161 */ 1162 void 1163 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1164 { 1165 uint32_t ac; 1166 int i; 1167 1168 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1169 1170 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1171 1172 delay(50000); 1173 1174 for (i = 0; i < STE_TIMEOUT; i++) { 1175 delay(1000); 1176 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1177 AC_ResetBusy) == 0) 1178 break; 1179 } 1180 1181 if (i == STE_TIMEOUT) 1182 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1183 1184 delay(1000); 1185 } 1186 1187 /* 1188 * ste_setthresh: 1189 * 1190 * set the various transmit threshold registers 1191 */ 1192 void 1193 ste_setthresh(struct ste_softc *sc) 1194 { 1195 /* set the TX threhold */ 1196 bus_space_write_2(sc->sc_st, sc->sc_sh, 1197 STE_TxStartThresh, sc->sc_txthresh); 1198 /* Urgent threshold: set to sc_txthresh / 2 */ 1199 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1200 sc->sc_txthresh >> 6); 1201 /* Burst threshold: use default value (256 bytes) */ 1202 } 1203 1204 /* 1205 * restart TX at the given frame ID in the transmitter ring 1206 */ 1207 1208 void 1209 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1210 { 1211 u_int32_t control; 1212 1213 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1214 control = le32toh(sc->sc_txdescs[id].tfd_control); 1215 control &= ~TFD_TxDMAComplete; 1216 sc->sc_txdescs[id].tfd_control = htole32(control); 1217 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1218 1219 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1220 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1221 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1222 ste_dmahalt_wait(sc); 1223 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1224 STE_CDTXADDR(sc, id)); 1225 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1226 } 1227 1228 /* 1229 * ste_init: [ ifnet interface function ] 1230 * 1231 * Initialize the interface. Must be called at splnet(). 1232 */ 1233 int 1234 ste_init(struct ifnet *ifp) 1235 { 1236 struct ste_softc *sc = ifp->if_softc; 1237 bus_space_tag_t st = sc->sc_st; 1238 bus_space_handle_t sh = sc->sc_sh; 1239 struct ste_descsoft *ds; 1240 int i, error = 0; 1241 1242 /* 1243 * Cancel any pending I/O. 1244 */ 1245 ste_stop(ifp, 0); 1246 1247 /* 1248 * Reset the chip to a known state. 1249 */ 1250 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1251 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1252 1253 /* 1254 * Initialize the transmit descriptor ring. 1255 */ 1256 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1257 sc->sc_txpending = 0; 1258 sc->sc_txdirty = 0; 1259 sc->sc_txlast = STE_NTXDESC - 1; 1260 1261 /* 1262 * Initialize the receive descriptor and receive job 1263 * descriptor rings. 1264 */ 1265 for (i = 0; i < STE_NRXDESC; i++) { 1266 ds = &sc->sc_rxsoft[i]; 1267 if (ds->ds_mbuf == NULL) { 1268 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1269 printf("%s: unable to allocate or map rx " 1270 "buffer %d, error = %d\n", 1271 sc->sc_dev.dv_xname, i, error); 1272 /* 1273 * XXX Should attempt to run with fewer receive 1274 * XXX buffers instead of just failing. 1275 */ 1276 ste_rxdrain(sc); 1277 goto out; 1278 } 1279 } else 1280 STE_INIT_RXDESC(sc, i); 1281 } 1282 sc->sc_rxptr = 0; 1283 1284 /* Set the station address. */ 1285 for (i = 0; i < ETHER_ADDR_LEN; i++) 1286 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1287 LLADDR(ifp->if_sadl)[i]); 1288 1289 /* Set up the receive filter. */ 1290 ste_set_filter(sc); 1291 1292 /* 1293 * Give the receive ring to the chip. 1294 */ 1295 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1296 STE_CDRXADDR(sc, sc->sc_rxptr)); 1297 1298 /* 1299 * We defer giving the transmit ring to the chip until we 1300 * transmit the first packet. 1301 */ 1302 1303 /* 1304 * Initialize the Tx auto-poll period. It's OK to make this number 1305 * large (127 is the max) -- we explicitly kick the transmit engine 1306 * when there's actually a packet. We are using auto-polling only 1307 * to make the interface to the transmit engine not suck. 1308 */ 1309 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1310 1311 /* ..and the Rx auto-poll period. */ 1312 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1313 1314 /* Initialize the Tx start threshold. */ 1315 ste_setthresh(sc); 1316 1317 /* Set the FIFO release threshold to 512 bytes. */ 1318 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1319 1320 /* 1321 * Initialize the interrupt mask. 1322 */ 1323 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1324 IE_TxDMAComplete | IE_RxDMAComplete; 1325 1326 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1327 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1328 1329 /* 1330 * Start the receive DMA engine. 1331 */ 1332 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1333 1334 /* 1335 * Initialize MacCtrl0 -- do it before setting the media, 1336 * as setting the media will actually program the register. 1337 */ 1338 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1339 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1340 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1341 1342 /* 1343 * Set the current media. 1344 */ 1345 mii_mediachg(&sc->sc_mii); 1346 1347 /* 1348 * Start the MAC. 1349 */ 1350 bus_space_write_2(st, sh, STE_MacCtrl1, 1351 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1352 1353 /* 1354 * Start the one second MII clock. 1355 */ 1356 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1357 1358 /* 1359 * ...all done! 1360 */ 1361 ifp->if_flags |= IFF_RUNNING; 1362 ifp->if_flags &= ~IFF_OACTIVE; 1363 1364 out: 1365 if (error) 1366 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1367 return (error); 1368 } 1369 1370 /* 1371 * ste_drain: 1372 * 1373 * Drain the receive queue. 1374 */ 1375 void 1376 ste_rxdrain(struct ste_softc *sc) 1377 { 1378 struct ste_descsoft *ds; 1379 int i; 1380 1381 for (i = 0; i < STE_NRXDESC; i++) { 1382 ds = &sc->sc_rxsoft[i]; 1383 if (ds->ds_mbuf != NULL) { 1384 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1385 m_freem(ds->ds_mbuf); 1386 ds->ds_mbuf = NULL; 1387 } 1388 } 1389 } 1390 1391 /* 1392 * ste_stop: [ ifnet interface function ] 1393 * 1394 * Stop transmission on the interface. 1395 */ 1396 void 1397 ste_stop(struct ifnet *ifp, int disable) 1398 { 1399 struct ste_softc *sc = ifp->if_softc; 1400 struct ste_descsoft *ds; 1401 int i; 1402 1403 /* 1404 * Stop the one second clock. 1405 */ 1406 callout_stop(&sc->sc_tick_ch); 1407 1408 /* Down the MII. */ 1409 mii_down(&sc->sc_mii); 1410 1411 /* 1412 * Disable interrupts. 1413 */ 1414 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1415 1416 /* 1417 * Stop receiver, transmitter, and stats update. 1418 */ 1419 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1420 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1421 1422 /* 1423 * Stop the transmit and receive DMA. 1424 */ 1425 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1426 DC_RxDMAHalt | DC_TxDMAHalt); 1427 ste_dmahalt_wait(sc); 1428 1429 /* 1430 * Release any queued transmit buffers. 1431 */ 1432 for (i = 0; i < STE_NTXDESC; i++) { 1433 ds = &sc->sc_txsoft[i]; 1434 if (ds->ds_mbuf != NULL) { 1435 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1436 m_freem(ds->ds_mbuf); 1437 ds->ds_mbuf = NULL; 1438 } 1439 } 1440 1441 if (disable) 1442 ste_rxdrain(sc); 1443 1444 /* 1445 * Mark the interface down and cancel the watchdog timer. 1446 */ 1447 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1448 ifp->if_timer = 0; 1449 } 1450 1451 static int 1452 ste_eeprom_wait(struct ste_softc *sc) 1453 { 1454 int i; 1455 1456 for (i = 0; i < STE_TIMEOUT; i++) { 1457 delay(1000); 1458 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1459 EC_EepromBusy) == 0) 1460 return (0); 1461 } 1462 return (1); 1463 } 1464 1465 /* 1466 * ste_read_eeprom: 1467 * 1468 * Read data from the serial EEPROM. 1469 */ 1470 void 1471 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1472 { 1473 1474 if (ste_eeprom_wait(sc)) 1475 printf("%s: EEPROM failed to come ready\n", 1476 sc->sc_dev.dv_xname); 1477 1478 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1479 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1480 if (ste_eeprom_wait(sc)) 1481 printf("%s: EEPROM read timed out\n", 1482 sc->sc_dev.dv_xname); 1483 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1484 } 1485 1486 /* 1487 * ste_add_rxbuf: 1488 * 1489 * Add a receive buffer to the indicated descriptor. 1490 */ 1491 int 1492 ste_add_rxbuf(struct ste_softc *sc, int idx) 1493 { 1494 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1495 struct mbuf *m; 1496 int error; 1497 1498 MGETHDR(m, M_DONTWAIT, MT_DATA); 1499 if (m == NULL) 1500 return (ENOBUFS); 1501 1502 MCLGET(m, M_DONTWAIT); 1503 if ((m->m_flags & M_EXT) == 0) { 1504 m_freem(m); 1505 return (ENOBUFS); 1506 } 1507 1508 if (ds->ds_mbuf != NULL) 1509 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1510 1511 ds->ds_mbuf = m; 1512 1513 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1514 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1515 BUS_DMA_READ|BUS_DMA_NOWAIT); 1516 if (error) { 1517 printf("%s: can't load rx DMA map %d, error = %d\n", 1518 sc->sc_dev.dv_xname, idx, error); 1519 panic("ste_add_rxbuf"); /* XXX */ 1520 } 1521 1522 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1523 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1524 1525 STE_INIT_RXDESC(sc, idx); 1526 1527 return (0); 1528 } 1529 1530 /* 1531 * ste_set_filter: 1532 * 1533 * Set up the receive filter. 1534 */ 1535 void 1536 ste_set_filter(struct ste_softc *sc) 1537 { 1538 struct ethercom *ec = &sc->sc_ethercom; 1539 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1540 struct ether_multi *enm; 1541 struct ether_multistep step; 1542 uint32_t crc; 1543 uint16_t mchash[4]; 1544 1545 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1546 if (ifp->if_flags & IFF_BROADCAST) 1547 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1548 1549 if (ifp->if_flags & IFF_PROMISC) { 1550 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1551 goto allmulti; 1552 } 1553 1554 /* 1555 * Set up the multicast address filter by passing all multicast 1556 * addresses through a CRC generator, and then using the low-order 1557 * 6 bits as an index into the 64 bit multicast hash table. The 1558 * high order bits select the register, while the rest of the bits 1559 * select the bit within the register. 1560 */ 1561 1562 memset(mchash, 0, sizeof(mchash)); 1563 1564 ETHER_FIRST_MULTI(step, ec, enm); 1565 if (enm == NULL) 1566 goto done; 1567 1568 while (enm != NULL) { 1569 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1570 /* 1571 * We must listen to a range of multicast addresses. 1572 * For now, just accept all multicasts, rather than 1573 * trying to set only those filter bits needed to match 1574 * the range. (At this time, the only use of address 1575 * ranges is for IP multicast routing, for which the 1576 * range is big enough to require all bits set.) 1577 */ 1578 goto allmulti; 1579 } 1580 1581 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1582 1583 /* Just want the 6 least significant bits. */ 1584 crc &= 0x3f; 1585 1586 /* Set the corresponding bit in the hash table. */ 1587 mchash[crc >> 4] |= 1 << (crc & 0xf); 1588 1589 ETHER_NEXT_MULTI(step, enm); 1590 } 1591 1592 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1593 1594 ifp->if_flags &= ~IFF_ALLMULTI; 1595 goto done; 1596 1597 allmulti: 1598 ifp->if_flags |= IFF_ALLMULTI; 1599 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1600 1601 done: 1602 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1603 /* 1604 * Program the multicast hash table. 1605 */ 1606 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1607 mchash[0]); 1608 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1609 mchash[1]); 1610 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1611 mchash[2]); 1612 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1613 mchash[3]); 1614 } 1615 1616 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1617 sc->sc_ReceiveMode); 1618 } 1619 1620 /* 1621 * ste_mii_readreg: [mii interface function] 1622 * 1623 * Read a PHY register on the MII of the ST-201. 1624 */ 1625 int 1626 ste_mii_readreg(struct device *self, int phy, int reg) 1627 { 1628 1629 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1630 } 1631 1632 /* 1633 * ste_mii_writereg: [mii interface function] 1634 * 1635 * Write a PHY register on the MII of the ST-201. 1636 */ 1637 void 1638 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1639 { 1640 1641 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1642 } 1643 1644 /* 1645 * ste_mii_statchg: [mii interface function] 1646 * 1647 * Callback from MII layer when media changes. 1648 */ 1649 void 1650 ste_mii_statchg(struct device *self) 1651 { 1652 struct ste_softc *sc = (struct ste_softc *) self; 1653 1654 if (sc->sc_mii.mii_media_active & IFM_FDX) 1655 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1656 else 1657 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1658 1659 /* XXX 802.1x flow-control? */ 1660 1661 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1662 } 1663 1664 /* 1665 * ste_mii_bitbang_read: [mii bit-bang interface function] 1666 * 1667 * Read the MII serial port for the MII bit-bang module. 1668 */ 1669 uint32_t 1670 ste_mii_bitbang_read(struct device *self) 1671 { 1672 struct ste_softc *sc = (void *) self; 1673 1674 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1675 } 1676 1677 /* 1678 * ste_mii_bitbang_write: [mii big-bang interface function] 1679 * 1680 * Write the MII serial port for the MII bit-bang module. 1681 */ 1682 void 1683 ste_mii_bitbang_write(struct device *self, uint32_t val) 1684 { 1685 struct ste_softc *sc = (void *) self; 1686 1687 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1688 } 1689 1690 /* 1691 * ste_mediastatus: [ifmedia interface function] 1692 * 1693 * Get the current interface media status. 1694 */ 1695 void 1696 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1697 { 1698 struct ste_softc *sc = ifp->if_softc; 1699 1700 mii_pollstat(&sc->sc_mii); 1701 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1702 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1703 } 1704 1705 /* 1706 * ste_mediachange: [ifmedia interface function] 1707 * 1708 * Set hardware to newly-selected media. 1709 */ 1710 int 1711 ste_mediachange(struct ifnet *ifp) 1712 { 1713 struct ste_softc *sc = ifp->if_softc; 1714 1715 if (ifp->if_flags & IFF_UP) 1716 mii_mediachg(&sc->sc_mii); 1717 return (0); 1718 } 1719