1 /* $NetBSD: if_sk.c,v 1.7 2004/01/28 17:07:21 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul@ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_calchash(caddr_t); 209 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 #define SK_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 229 230 #define SK_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 232 233 #define SK_WIN_SETBIT_4(sc, reg, x) \ 234 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 235 236 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 237 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 238 239 #define SK_WIN_SETBIT_2(sc, reg, x) \ 240 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 241 242 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 243 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 244 245 /* supported device vendors */ 246 static const struct sk_product { 247 pci_vendor_id_t sk_vendor; 248 pci_product_id_t sk_product; 249 } sk_products[] = { 250 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 251 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 252 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, }, 253 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 254 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 255 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 256 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 257 { 0, 0, } 258 }; 259 260 static inline u_int32_t 261 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_4(sc, reg); 268 #endif 269 } 270 271 static inline u_int16_t 272 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_2(sc, reg); 279 #endif 280 } 281 282 static inline u_int8_t 283 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 288 #else 289 return CSR_READ_1(sc, reg); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_4(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_2(sc, reg, x); 312 #endif 313 } 314 315 static inline void 316 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 317 { 318 #ifdef SK_USEIOSPACE 319 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 320 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 321 #else 322 CSR_WRITE_1(sc, reg, x); 323 #endif 324 } 325 326 /* 327 * The VPD EEPROM contains Vital Product Data, as suggested in 328 * the PCI 2.1 specification. The VPD data is separared into areas 329 * denoted by resource IDs. The SysKonnect VPD contains an ID string 330 * resource (the name of the adapter), a read-only area resource 331 * containing various key/data fields and a read/write area which 332 * can be used to store asset management information or log messages. 333 * We read the ID string and read-only into buffers attached to 334 * the controller softc structure for later use. At the moment, 335 * we only use the ID string during sk_attach(). 336 */ 337 u_int8_t 338 sk_vpd_readbyte(struct sk_softc *sc, int addr) 339 { 340 int i; 341 342 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 343 for (i = 0; i < SK_TIMEOUT; i++) { 344 DELAY(1); 345 if (sk_win_read_2(sc, 346 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 347 break; 348 } 349 350 if (i == SK_TIMEOUT) 351 return(0); 352 353 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 354 } 355 356 void 357 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 358 { 359 int i; 360 u_int8_t *ptr; 361 362 ptr = (u_int8_t *)res; 363 for (i = 0; i < sizeof(struct vpd_res); i++) 364 ptr[i] = sk_vpd_readbyte(sc, i + addr); 365 } 366 367 void 368 sk_vpd_read(struct sk_softc *sc) 369 { 370 int pos = 0, i; 371 struct vpd_res res; 372 373 if (sc->sk_vpd_prodname != NULL) 374 free(sc->sk_vpd_prodname, M_DEVBUF); 375 if (sc->sk_vpd_readonly != NULL) 376 free(sc->sk_vpd_readonly, M_DEVBUF); 377 sc->sk_vpd_prodname = NULL; 378 sc->sk_vpd_readonly = NULL; 379 380 sk_vpd_read_res(sc, &res, pos); 381 382 if (res.vr_id != VPD_RES_ID) { 383 printf("%s: bad VPD resource id: expected %x got %x\n", 384 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 385 return; 386 } 387 388 pos += sizeof(res); 389 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 390 if (sc->sk_vpd_prodname == NULL) 391 panic("sk_vpd_read"); 392 for (i = 0; i < res.vr_len; i++) 393 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 394 sc->sk_vpd_prodname[i] = '\0'; 395 pos += i; 396 397 sk_vpd_read_res(sc, &res, pos); 398 399 if (res.vr_id != VPD_RES_READ) { 400 printf("%s: bad VPD resource id: expected %x got %x\n", 401 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 402 return; 403 } 404 405 pos += sizeof(res); 406 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 407 if (sc->sk_vpd_readonly == NULL) 408 panic("sk_vpd_read"); 409 for (i = 0; i < res.vr_len + 1; i++) 410 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 411 } 412 413 int 414 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 415 { 416 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 417 int i; 418 419 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 420 421 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 422 return(0); 423 424 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 425 SK_XM_READ_2(sc_if, XM_PHY_DATA); 426 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 427 for (i = 0; i < SK_TIMEOUT; i++) { 428 DELAY(1); 429 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 430 XM_MMUCMD_PHYDATARDY) 431 break; 432 } 433 434 if (i == SK_TIMEOUT) { 435 printf("%s: phy failed to come ready\n", 436 sc_if->sk_dev.dv_xname); 437 return(0); 438 } 439 } 440 DELAY(1); 441 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 442 } 443 444 void 445 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 446 { 447 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 448 int i; 449 450 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 451 452 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 455 break; 456 } 457 458 if (i == SK_TIMEOUT) { 459 printf("%s: phy failed to come ready\n", 460 sc_if->sk_dev.dv_xname); 461 return; 462 } 463 464 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 465 for (i = 0; i < SK_TIMEOUT; i++) { 466 DELAY(1); 467 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 468 break; 469 } 470 471 if (i == SK_TIMEOUT) 472 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 473 } 474 475 void 476 sk_xmac_miibus_statchg(struct device *dev) 477 { 478 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 479 struct mii_data *mii = &sc_if->sk_mii; 480 481 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 482 483 /* 484 * If this is a GMII PHY, manually set the XMAC's 485 * duplex mode accordingly. 486 */ 487 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 488 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 489 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 490 } else { 491 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 492 } 493 } 494 } 495 496 int 497 sk_marv_miibus_readreg(dev, phy, reg) 498 struct device *dev; 499 int phy, reg; 500 { 501 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 502 u_int16_t val; 503 int i; 504 505 if (phy != 0 || 506 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 507 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 508 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 509 phy, reg)); 510 return(0); 511 } 512 513 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 514 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 515 516 for (i = 0; i < SK_TIMEOUT; i++) { 517 DELAY(1); 518 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 519 if (val & YU_SMICR_READ_VALID) 520 break; 521 } 522 523 if (i == SK_TIMEOUT) { 524 printf("%s: phy failed to come ready\n", 525 sc_if->sk_dev.dv_xname); 526 return 0; 527 } 528 529 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 530 SK_TIMEOUT)); 531 532 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 533 534 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 535 phy, reg, val)); 536 537 return val; 538 } 539 540 void 541 sk_marv_miibus_writereg(dev, phy, reg, val) 542 struct device *dev; 543 int phy, reg, val; 544 { 545 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 546 int i; 547 548 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 549 phy, reg, val)); 550 551 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 552 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 553 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 554 555 for (i = 0; i < SK_TIMEOUT; i++) { 556 DELAY(1); 557 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 558 break; 559 } 560 } 561 562 void 563 sk_marv_miibus_statchg(dev) 564 struct device *dev; 565 { 566 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 567 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 568 } 569 570 #define SK_BITS 6 571 #define SK_POLY 0xEDB88320 572 573 u_int32_t 574 sk_calchash(caddr_t addr) 575 { 576 u_int32_t crc; 577 578 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 579 crc = ~crc & ((1<< SK_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 581 return (crc); 582 } 583 584 void 585 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 586 { 587 int base = XM_RXFILT_ENTRY(slot); 588 589 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 590 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 591 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 592 } 593 594 void 595 sk_setmulti(struct sk_if_softc *sc_if) 596 { 597 struct sk_softc *sc = sc_if->sk_softc; 598 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 599 u_int32_t hashes[2] = { 0, 0 }; 600 int h, i; 601 struct ethercom *ec = &sc_if->sk_ethercom; 602 struct ether_multi *enm; 603 struct ether_multistep step; 604 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 605 606 /* First, zot all the existing filters. */ 607 switch(sc->sk_type) { 608 case SK_GENESIS: 609 for (i = 1; i < XM_RXFILT_MAX; i++) 610 sk_setfilt(sc_if, (caddr_t)&dummy, i); 611 612 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 613 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 614 break; 615 case SK_YUKON: 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 620 break; 621 } 622 623 /* Now program new ones. */ 624 allmulti: 625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 626 hashes[0] = 0xFFFFFFFF; 627 hashes[1] = 0xFFFFFFFF; 628 } else { 629 i = 1; 630 /* First find the tail of the list. */ 631 ETHER_FIRST_MULTI(step, ec, enm); 632 while (enm != NULL) { 633 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 634 ETHER_ADDR_LEN)) { 635 ifp->if_flags |= IFF_ALLMULTI; 636 goto allmulti; 637 } 638 DPRINTFN(2,("multicast address %s\n", 639 ether_sprintf(enm->enm_addrlo))); 640 /* 641 * Program the first XM_RXFILT_MAX multicast groups 642 * into the perfect filter. For all others, 643 * use the hash table. 644 */ 645 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 646 sk_setfilt(sc_if, enm->enm_addrlo, i); 647 i++; 648 } 649 else { 650 h = sk_calchash(enm->enm_addrlo); 651 if (h < 32) 652 hashes[0] |= (1 << h); 653 else 654 hashes[1] |= (1 << (h - 32)); 655 } 656 657 ETHER_NEXT_MULTI(step, enm); 658 } 659 } 660 661 switch(sc->sk_type) { 662 case SK_GENESIS: 663 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 664 XM_MODE_RX_USE_PERFECT); 665 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 666 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 667 break; 668 case SK_YUKON: 669 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 670 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 671 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 672 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 673 break; 674 } 675 } 676 677 int 678 sk_init_rx_ring(struct sk_if_softc *sc_if) 679 { 680 struct sk_chain_data *cd = &sc_if->sk_cdata; 681 struct sk_ring_data *rd = sc_if->sk_rdata; 682 int i; 683 684 bzero((char *)rd->sk_rx_ring, 685 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 686 687 for (i = 0; i < SK_RX_RING_CNT; i++) { 688 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 689 if (i == (SK_RX_RING_CNT - 1)) { 690 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 691 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 692 } else { 693 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 694 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 695 } 696 } 697 698 for (i = 0; i < SK_RX_RING_CNT; i++) { 699 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 700 printf("%s: failed alloc of %dth mbuf\n", 701 sc_if->sk_dev.dv_xname, i); 702 return(ENOBUFS); 703 } 704 } 705 sc_if->sk_cdata.sk_rx_prod = 0; 706 sc_if->sk_cdata.sk_rx_cons = 0; 707 708 return(0); 709 } 710 711 int 712 sk_init_tx_ring(struct sk_if_softc *sc_if) 713 { 714 struct sk_chain_data *cd = &sc_if->sk_cdata; 715 struct sk_ring_data *rd = sc_if->sk_rdata; 716 int i; 717 718 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 719 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 720 721 for (i = 0; i < SK_TX_RING_CNT; i++) { 722 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 723 if (i == (SK_TX_RING_CNT - 1)) { 724 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 725 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 726 } else { 727 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 728 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 729 } 730 } 731 732 sc_if->sk_cdata.sk_tx_prod = 0; 733 sc_if->sk_cdata.sk_tx_cons = 0; 734 sc_if->sk_cdata.sk_tx_cnt = 0; 735 736 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 737 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 738 739 return (0); 740 } 741 742 int 743 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 744 bus_dmamap_t dmamap) 745 { 746 struct sk_softc *sc = sc_if->sk_softc; 747 struct mbuf *m_new = NULL; 748 struct sk_chain *c; 749 struct sk_rx_desc *r; 750 751 if (dmamap == NULL) { 752 /* if (m) panic() */ 753 754 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 755 0, BUS_DMA_NOWAIT, &dmamap)) { 756 printf("%s: can't create recv map\n", 757 sc_if->sk_dev.dv_xname); 758 return(ENOMEM); 759 } 760 } else if (m == NULL) 761 bus_dmamap_unload(sc->sc_dmatag, dmamap); 762 763 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 764 765 if (m == NULL) { 766 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 767 if (m_new == NULL) { 768 printf("%s: no memory for rx list -- " 769 "packet dropped!\n", sc_if->sk_dev.dv_xname); 770 return(ENOBUFS); 771 } 772 773 /* Allocate the jumbo buffer */ 774 MCLGET(m_new, M_DONTWAIT); 775 if (!(m_new->m_flags & M_EXT)) { 776 m_freem(m_new); 777 return (ENOBUFS); 778 } 779 780 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 781 782 m_adj(m_new, ETHER_ALIGN); 783 784 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 785 BUS_DMA_NOWAIT)) 786 return(ENOBUFS); 787 } else { 788 /* 789 * We're re-using a previously allocated mbuf; 790 * be sure to re-init pointers and lengths to 791 * default values. 792 */ 793 m_new = m; 794 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 795 m_adj(m_new, ETHER_ALIGN); 796 m_new->m_data = m_new->m_ext.ext_buf; 797 } 798 799 c = &sc_if->sk_cdata.sk_rx_chain[i]; 800 r = c->sk_desc; 801 c->sk_mbuf = m_new; 802 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 803 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 804 805 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 806 807 return(0); 808 } 809 810 /* 811 * Set media options. 812 */ 813 int 814 sk_ifmedia_upd(struct ifnet *ifp) 815 { 816 struct sk_if_softc *sc_if = ifp->if_softc; 817 818 (void) sk_init(ifp); 819 mii_mediachg(&sc_if->sk_mii); 820 return(0); 821 } 822 823 /* 824 * Report current media status. 825 */ 826 void 827 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 828 { 829 struct sk_if_softc *sc_if = ifp->if_softc; 830 831 mii_pollstat(&sc_if->sk_mii); 832 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 833 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 834 } 835 836 int 837 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 838 { 839 struct sk_if_softc *sc_if = ifp->if_softc; 840 struct sk_softc *sc = sc_if->sk_softc; 841 struct ifreq *ifr = (struct ifreq *) data; 842 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 843 struct mii_data *mii; 844 int s, error = 0; 845 846 /* DPRINTFN(2, ("sk_ioctl\n")); */ 847 848 s = splnet(); 849 850 switch(command) { 851 852 case SIOCSIFFLAGS: 853 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 854 if (ifp->if_flags & IFF_UP) { 855 if (ifp->if_flags & IFF_RUNNING && 856 ifp->if_flags & IFF_PROMISC && 857 !(sc_if->sk_if_flags & IFF_PROMISC)) { 858 switch(sc->sk_type) { 859 case SK_GENESIS: 860 SK_XM_SETBIT_4(sc_if, XM_MODE, 861 XM_MODE_RX_PROMISC); 862 break; 863 case SK_YUKON: 864 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 865 YU_RCR_UFLEN | YU_RCR_MUFLEN); 866 break; 867 } 868 sk_setmulti(sc_if); 869 } else if (ifp->if_flags & IFF_RUNNING && 870 !(ifp->if_flags & IFF_PROMISC) && 871 sc_if->sk_if_flags & IFF_PROMISC) { 872 switch(sc->sk_type) { 873 case SK_GENESIS: 874 SK_XM_CLRBIT_4(sc_if, XM_MODE, 875 XM_MODE_RX_PROMISC); 876 break; 877 case SK_YUKON: 878 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 879 YU_RCR_UFLEN | YU_RCR_MUFLEN); 880 break; 881 } 882 883 sk_setmulti(sc_if); 884 } else 885 (void) sk_init(ifp); 886 } else { 887 if (ifp->if_flags & IFF_RUNNING) 888 sk_stop(ifp,0); 889 } 890 sc_if->sk_if_flags = ifp->if_flags; 891 error = 0; 892 break; 893 894 case SIOCGIFMEDIA: 895 case SIOCSIFMEDIA: 896 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 897 mii = &sc_if->sk_mii; 898 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 899 break; 900 default: 901 DPRINTFN(2, ("sk_ioctl ETHER\n")); 902 error = ether_ioctl(ifp, command, data); 903 904 if ( error == ENETRESET) { 905 sk_setmulti(sc_if); 906 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 907 error = 0; 908 } else if ( error ) { 909 splx(s); 910 return error; 911 } 912 break; 913 } 914 915 splx(s); 916 return(error); 917 } 918 919 /* 920 * Lookup: Check the PCI vendor and device, and return a pointer to 921 * The structure if the IDs match against our list. 922 */ 923 924 static const struct sk_product * 925 sk_lookup(const struct pci_attach_args *pa) 926 { 927 const struct sk_product *psk; 928 929 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 930 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 931 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 932 return (psk); 933 } 934 return (NULL); 935 } 936 937 /* 938 * Probe for a SysKonnect GEnesis chip. 939 */ 940 941 int 942 skc_probe(struct device *parent, struct cfdata *match, void *aux) 943 { 944 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 945 const struct sk_product *psk; 946 947 if ((psk = sk_lookup(pa))) { 948 return(1); 949 } 950 return(0); 951 } 952 953 /* 954 * Force the GEnesis into reset, then bring it out of reset. 955 */ 956 void sk_reset(struct sk_softc *sc) 957 { 958 DPRINTFN(2, ("sk_reset\n")); 959 960 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 961 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 962 if (sc->sk_type == SK_YUKON) 963 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 964 965 DELAY(1000); 966 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 967 DELAY(2); 968 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 969 if (sc->sk_type == SK_YUKON) 970 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 971 972 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 973 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 974 CSR_READ_2(sc, SK_LINK_CTRL))); 975 976 if (sc->sk_type == SK_GENESIS) { 977 /* Configure packet arbiter */ 978 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 979 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 980 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 981 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 982 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 983 } 984 985 /* Enable RAM interface */ 986 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 987 988 /* 989 * Configure interrupt moderation. The moderation timer 990 * defers interrupts specified in the interrupt moderation 991 * timer mask based on the timeout specified in the interrupt 992 * moderation timer init register. Each bit in the timer 993 * register represents 18.825ns, so to specify a timeout in 994 * microseconds, we have to multiply by 54. 995 */ 996 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 997 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 998 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 999 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1000 } 1001 1002 int 1003 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1004 { 1005 struct skc_attach_args *sa = aux; 1006 1007 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1008 return(0); 1009 1010 return (1); 1011 } 1012 1013 /* 1014 * Each XMAC chip is attached as a separate logical IP interface. 1015 * Single port cards will have only one logical interface of course. 1016 */ 1017 void 1018 sk_attach(struct device *parent, struct device *self, void *aux) 1019 { 1020 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1021 struct sk_softc *sc = (struct sk_softc *)parent; 1022 struct skc_attach_args *sa = aux; 1023 struct sk_txmap_entry *entry; 1024 struct ifnet *ifp; 1025 bus_dma_segment_t seg; 1026 bus_dmamap_t dmamap; 1027 caddr_t kva; 1028 int i, rseg; 1029 1030 sc_if->sk_port = sa->skc_port; 1031 sc_if->sk_softc = sc; 1032 sc->sk_if[sa->skc_port] = sc_if; 1033 1034 if (sa->skc_port == SK_PORT_A) 1035 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1036 if (sa->skc_port == SK_PORT_B) 1037 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1038 1039 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1040 1041 /* 1042 * Get station address for this interface. Note that 1043 * dual port cards actually come with three station 1044 * addresses: one for each port, plus an extra. The 1045 * extra one is used by the SysKonnect driver software 1046 * as a 'virtual' station address for when both ports 1047 * are operating in failover mode. Currently we don't 1048 * use this extra address. 1049 */ 1050 for (i = 0; i < ETHER_ADDR_LEN; i++) 1051 sc_if->sk_enaddr[i] = 1052 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1053 1054 1055 aprint_normal(": Ethernet address %s\n", 1056 ether_sprintf(sc_if->sk_enaddr)); 1057 1058 /* 1059 * Set up RAM buffer addresses. The NIC will have a certain 1060 * amount of SRAM on it, somewhere between 512K and 2MB. We 1061 * need to divide this up a) between the transmitter and 1062 * receiver and b) between the two XMACs, if this is a 1063 * dual port NIC. Our algotithm is to divide up the memory 1064 * evenly so that everyone gets a fair share. 1065 */ 1066 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1067 u_int32_t chunk, val; 1068 1069 chunk = sc->sk_ramsize / 2; 1070 val = sc->sk_rboff / sizeof(u_int64_t); 1071 sc_if->sk_rx_ramstart = val; 1072 val += (chunk / sizeof(u_int64_t)); 1073 sc_if->sk_rx_ramend = val - 1; 1074 sc_if->sk_tx_ramstart = val; 1075 val += (chunk / sizeof(u_int64_t)); 1076 sc_if->sk_tx_ramend = val - 1; 1077 } else { 1078 u_int32_t chunk, val; 1079 1080 chunk = sc->sk_ramsize / 4; 1081 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1082 sizeof(u_int64_t); 1083 sc_if->sk_rx_ramstart = val; 1084 val += (chunk / sizeof(u_int64_t)); 1085 sc_if->sk_rx_ramend = val - 1; 1086 sc_if->sk_tx_ramstart = val; 1087 val += (chunk / sizeof(u_int64_t)); 1088 sc_if->sk_tx_ramend = val - 1; 1089 } 1090 1091 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1092 " tx_ramstart=%#x tx_ramend=%#x\n", 1093 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1094 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1095 1096 /* Read and save PHY type and set PHY address */ 1097 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1098 switch (sc_if->sk_phytype) { 1099 case SK_PHYTYPE_XMAC: 1100 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1101 break; 1102 case SK_PHYTYPE_BCOM: 1103 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1104 break; 1105 case SK_PHYTYPE_MARV_COPPER: 1106 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1107 break; 1108 default: 1109 aprint_error("%s: unsupported PHY type: %d\n", 1110 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1111 return; 1112 } 1113 1114 /* Allocate the descriptor queues. */ 1115 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1116 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1117 aprint_error("%s: can't alloc rx buffers\n", 1118 sc->sk_dev.dv_xname); 1119 goto fail; 1120 } 1121 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1122 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1123 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1124 sc_if->sk_dev.dv_xname, 1125 (u_long) sizeof(struct sk_ring_data)); 1126 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1127 goto fail; 1128 } 1129 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1130 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1131 &sc_if->sk_ring_map)) { 1132 aprint_error("%s: can't create dma map\n", 1133 sc_if->sk_dev.dv_xname); 1134 bus_dmamem_unmap(sc->sc_dmatag, kva, 1135 sizeof(struct sk_ring_data)); 1136 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1137 goto fail; 1138 } 1139 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1140 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1141 aprint_error("%s: can't load dma map\n", 1142 sc_if->sk_dev.dv_xname); 1143 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1144 bus_dmamem_unmap(sc->sc_dmatag, kva, 1145 sizeof(struct sk_ring_data)); 1146 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1147 goto fail; 1148 } 1149 1150 for (i = 0; i < SK_RX_RING_CNT; i++) 1151 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1152 1153 SLIST_INIT(&sc_if->sk_txmap_listhead); 1154 for (i = 0; i < SK_TX_RING_CNT; i++) { 1155 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1156 1157 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1158 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1159 aprint_error("%s: Can't create TX dmamap\n", 1160 sc_if->sk_dev.dv_xname); 1161 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1162 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1163 bus_dmamem_unmap(sc->sc_dmatag, kva, 1164 sizeof(struct sk_ring_data)); 1165 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1166 goto fail; 1167 } 1168 1169 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1170 if (!entry) { 1171 aprint_error("%s: Can't alloc txmap entry\n", 1172 sc_if->sk_dev.dv_xname); 1173 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1174 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1175 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1176 bus_dmamem_unmap(sc->sc_dmatag, kva, 1177 sizeof(struct sk_ring_data)); 1178 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1179 goto fail; 1180 } 1181 entry->dmamap = dmamap; 1182 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 1183 } 1184 1185 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1186 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1187 1188 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1189 XXX TLS support in this driver, so we don't enable it. */ 1190 1191 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1192 1193 ifp = &sc_if->sk_ethercom.ec_if; 1194 ifp->if_softc = sc_if; 1195 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1196 ifp->if_ioctl = sk_ioctl; 1197 ifp->if_start = sk_start; 1198 ifp->if_stop = sk_stop; 1199 ifp->if_init = sk_init; 1200 ifp->if_watchdog = sk_watchdog; 1201 ifp->if_capabilities = 0; 1202 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1203 IFQ_SET_READY(&ifp->if_snd); 1204 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1205 1206 /* 1207 * Do miibus setup. 1208 */ 1209 switch (sc->sk_type) { 1210 case SK_GENESIS: 1211 sk_init_xmac(sc_if); 1212 break; 1213 case SK_YUKON: 1214 sk_init_yukon(sc_if); 1215 break; 1216 default: 1217 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1218 sc->sk_type); 1219 } 1220 1221 DPRINTFN(2, ("sk_attach: 1\n")); 1222 1223 sc_if->sk_mii.mii_ifp = ifp; 1224 switch (sc->sk_type) { 1225 case SK_GENESIS: 1226 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1227 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1228 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1229 break; 1230 case SK_YUKON: 1231 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1232 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1233 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1234 break; 1235 } 1236 1237 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1238 sk_ifmedia_upd, sk_ifmedia_sts); 1239 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, 0); 1241 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1242 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1243 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1244 0, NULL); 1245 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1246 } 1247 else 1248 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1249 1250 callout_init(&sc_if->sk_tick_ch); 1251 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1252 1253 DPRINTFN(2, ("sk_attach: 1\n")); 1254 1255 /* 1256 * Call MI attach routines. 1257 */ 1258 if_attach(ifp); 1259 1260 ether_ifattach(ifp, sc_if->sk_enaddr); 1261 1262 #if NRND > 0 1263 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1264 RND_TYPE_NET, 0); 1265 #endif 1266 1267 DPRINTFN(2, ("sk_attach: end\n")); 1268 1269 return; 1270 1271 fail: 1272 sc->sk_if[sa->skc_port] = NULL; 1273 } 1274 1275 int 1276 skcprint(void *aux, const char *pnp) 1277 { 1278 struct skc_attach_args *sa = aux; 1279 1280 if (pnp) 1281 aprint_normal("sk port %c at %s", 1282 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1283 else 1284 aprint_normal(" port %c", 1285 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1286 return (UNCONF); 1287 } 1288 1289 /* 1290 * Attach the interface. Allocate softc structures, do ifmedia 1291 * setup and ethernet/BPF attach. 1292 */ 1293 void 1294 skc_attach(struct device *parent, struct device *self, void *aux) 1295 { 1296 struct sk_softc *sc = (struct sk_softc *)self; 1297 struct pci_attach_args *pa = aux; 1298 struct skc_attach_args skca; 1299 pci_chipset_tag_t pc = pa->pa_pc; 1300 pcireg_t memtype; 1301 pci_intr_handle_t ih; 1302 const char *intrstr = NULL; 1303 bus_addr_t iobase; 1304 bus_size_t iosize; 1305 int s; 1306 u_int32_t command; 1307 1308 DPRINTFN(2, ("begin skc_attach\n")); 1309 1310 s = splnet(); 1311 1312 /* 1313 * Handle power management nonsense. 1314 */ 1315 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1316 1317 if (command == 0x01) { 1318 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1319 if (command & SK_PSTATE_MASK) { 1320 u_int32_t iobase, membase, irq; 1321 1322 /* Save important PCI config data. */ 1323 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1324 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1325 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1326 1327 /* Reset the power state. */ 1328 aprint_normal("%s chip is in D%d power mode " 1329 "-- setting to D0\n", sc->sk_dev.dv_xname, 1330 command & SK_PSTATE_MASK); 1331 command &= 0xFFFFFFFC; 1332 pci_conf_write(pc, pa->pa_tag, 1333 SK_PCI_PWRMGMTCTRL, command); 1334 1335 /* Restore PCI config data. */ 1336 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1337 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1338 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1339 } 1340 } 1341 1342 /* 1343 * Map control/status registers. 1344 */ 1345 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1346 command |= PCI_COMMAND_IO_ENABLE | 1347 PCI_COMMAND_MEM_ENABLE | 1348 PCI_COMMAND_MASTER_ENABLE; 1349 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1350 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1351 1352 switch (PCI_PRODUCT(pa->pa_id)) { 1353 case PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE: 1354 sc->sk_type = SK_GENESIS; 1355 break; 1356 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1357 case PCI_PRODUCT_3COM_3C940: 1358 case PCI_PRODUCT_DLINK_DGE530T: 1359 case PCI_PRODUCT_LINKSYS_EG1032: 1360 case PCI_PRODUCT_LINKSYS_EG1064: 1361 sc->sk_type = SK_YUKON; 1362 break; 1363 default: 1364 aprint_error(": unknown device!\n"); 1365 goto fail; 1366 } 1367 1368 #ifdef SK_USEIOSPACE 1369 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1370 aprint_error(": failed to enable I/O ports!\n"); 1371 goto fail; 1372 } 1373 /* 1374 * Map control/status registers. 1375 */ 1376 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1377 &iobase, &iosize)) { 1378 aprint_error(": can't find i/o space\n"); 1379 goto fail; 1380 } 1381 #else 1382 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1383 aprint_error(": failed to enable memory mapping!\n"); 1384 goto fail; 1385 } 1386 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1387 switch (memtype) { 1388 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1389 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1390 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1391 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1392 &iobase, &iosize) == 0) 1393 break; 1394 default: 1395 aprint_error("%s: can't find mem space\n", 1396 sc->sk_dev.dv_xname); 1397 return; 1398 } 1399 1400 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1401 #endif 1402 sc->sc_dmatag = pa->pa_dmat; 1403 1404 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1405 1406 /* Allocate interrupt */ 1407 if (pci_intr_map(pa, &ih)) { 1408 aprint_error(": couldn't map interrupt\n"); 1409 goto fail; 1410 } 1411 1412 intrstr = pci_intr_string(pc, ih); 1413 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1414 if (sc->sk_intrhand == NULL) { 1415 aprint_error(": couldn't establish interrupt"); 1416 if (intrstr != NULL) 1417 aprint_normal(" at %s", intrstr); 1418 goto fail; 1419 } 1420 aprint_normal(": %s\n", intrstr); 1421 1422 /* Reset the adapter. */ 1423 sk_reset(sc); 1424 1425 /* Read and save vital product data from EEPROM. */ 1426 sk_vpd_read(sc); 1427 1428 if (sc->sk_type == SK_GENESIS) { 1429 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1430 /* Read and save RAM size and RAMbuffer offset */ 1431 switch(val) { 1432 case SK_RAMSIZE_512K_64: 1433 sc->sk_ramsize = 0x80000; 1434 sc->sk_rboff = SK_RBOFF_0; 1435 break; 1436 case SK_RAMSIZE_1024K_64: 1437 sc->sk_ramsize = 0x100000; 1438 sc->sk_rboff = SK_RBOFF_80000; 1439 break; 1440 case SK_RAMSIZE_1024K_128: 1441 sc->sk_ramsize = 0x100000; 1442 sc->sk_rboff = SK_RBOFF_0; 1443 break; 1444 case SK_RAMSIZE_2048K_128: 1445 sc->sk_ramsize = 0x200000; 1446 sc->sk_rboff = SK_RBOFF_0; 1447 break; 1448 default: 1449 aprint_error("%s: unknown ram size: %d\n", 1450 sc->sk_dev.dv_xname, val); 1451 goto fail; 1452 break; 1453 } 1454 1455 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1456 sc->sk_ramsize, sc->sk_ramsize / 1024, 1457 sc->sk_rboff)); 1458 } else { 1459 sc->sk_ramsize = 0x20000; 1460 sc->sk_rboff = SK_RBOFF_0; 1461 1462 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1463 sc->sk_ramsize / 1024, sc->sk_ramsize, 1464 sc->sk_rboff)); 1465 } 1466 1467 /* Read and save physical media type */ 1468 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1469 case SK_PMD_1000BASESX: 1470 sc->sk_pmd = IFM_1000_SX; 1471 break; 1472 case SK_PMD_1000BASELX: 1473 sc->sk_pmd = IFM_1000_LX; 1474 break; 1475 case SK_PMD_1000BASECX: 1476 sc->sk_pmd = IFM_1000_CX; 1477 break; 1478 case SK_PMD_1000BASETX: 1479 sc->sk_pmd = IFM_1000_T; 1480 break; 1481 default: 1482 aprint_error("%s: unknown media type: 0x%x\n", 1483 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1484 goto fail; 1485 } 1486 1487 /* Announce the product name. */ 1488 aprint_normal("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1489 1490 skca.skc_port = SK_PORT_A; 1491 (void)config_found(&sc->sk_dev, &skca, skcprint); 1492 1493 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1494 skca.skc_port = SK_PORT_B; 1495 (void)config_found(&sc->sk_dev, &skca, skcprint); 1496 } 1497 1498 /* Turn on the 'driver is loaded' LED. */ 1499 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1500 1501 fail: 1502 splx(s); 1503 } 1504 1505 int 1506 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1507 { 1508 struct sk_softc *sc = sc_if->sk_softc; 1509 struct sk_tx_desc *f = NULL; 1510 u_int32_t frag, cur, cnt = 0; 1511 int i; 1512 struct sk_txmap_entry *entry; 1513 bus_dmamap_t txmap; 1514 1515 DPRINTFN(3, ("sk_encap\n")); 1516 1517 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1518 if (entry == NULL) { 1519 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1520 return ENOBUFS; 1521 } 1522 txmap = entry->dmamap; 1523 1524 cur = frag = *txidx; 1525 1526 #ifdef SK_DEBUG 1527 if (skdebug >= 3) 1528 sk_dump_mbuf(m_head); 1529 #endif 1530 1531 /* 1532 * Start packing the mbufs in this chain into 1533 * the fragment pointers. Stop when we run out 1534 * of fragments or hit the end of the mbuf chain. 1535 */ 1536 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1537 BUS_DMA_NOWAIT)) { 1538 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1539 return(ENOBUFS); 1540 } 1541 1542 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1543 1544 /* Sync the DMA map. */ 1545 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1546 BUS_DMASYNC_PREWRITE); 1547 1548 for (i = 0; i < txmap->dm_nsegs; i++) { 1549 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1550 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1551 return(ENOBUFS); 1552 } 1553 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1554 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1555 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1556 if (cnt == 0) 1557 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1558 else 1559 f->sk_ctl |= SK_TXCTL_OWN; 1560 1561 cur = frag; 1562 SK_INC(frag, SK_TX_RING_CNT); 1563 cnt++; 1564 } 1565 1566 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1567 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1568 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1569 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1570 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1571 1572 /* Sync descriptors before handing to chip */ 1573 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1574 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1575 1576 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1577 1578 /* Sync first descriptor to hand it off */ 1579 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1580 1581 sc_if->sk_cdata.sk_tx_cnt += cnt; 1582 1583 #ifdef SK_DEBUG 1584 if (skdebug >= 3) { 1585 struct sk_tx_desc *desc; 1586 u_int32_t idx; 1587 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1588 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1589 sk_dump_txdesc(desc, idx); 1590 } 1591 } 1592 #endif 1593 1594 *txidx = frag; 1595 1596 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1597 1598 return(0); 1599 } 1600 1601 void 1602 sk_start(struct ifnet *ifp) 1603 { 1604 struct sk_if_softc *sc_if = ifp->if_softc; 1605 struct sk_softc *sc = sc_if->sk_softc; 1606 struct mbuf *m_head = NULL; 1607 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1608 int pkts = 0; 1609 1610 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1611 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1612 1613 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1614 1615 IFQ_POLL(&ifp->if_snd, m_head); 1616 if (m_head == NULL) 1617 break; 1618 1619 /* 1620 * Pack the data into the transmit ring. If we 1621 * don't have room, set the OACTIVE flag and wait 1622 * for the NIC to drain the ring. 1623 */ 1624 if (sk_encap(sc_if, m_head, &idx)) { 1625 ifp->if_flags |= IFF_OACTIVE; 1626 break; 1627 } 1628 1629 /* now we are committed to transmit the packet */ 1630 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1631 pkts++; 1632 1633 /* 1634 * If there's a BPF listener, bounce a copy of this frame 1635 * to him. 1636 */ 1637 #if NBPFILTER > 0 1638 if (ifp->if_bpf) 1639 bpf_mtap(ifp->if_bpf, m_head); 1640 #endif 1641 } 1642 if (pkts == 0) 1643 return; 1644 1645 /* Transmit */ 1646 sc_if->sk_cdata.sk_tx_prod = idx; 1647 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1648 1649 /* Set a timeout in case the chip goes out to lunch. */ 1650 ifp->if_timer = 5; 1651 } 1652 1653 1654 void 1655 sk_watchdog(struct ifnet *ifp) 1656 { 1657 struct sk_if_softc *sc_if = ifp->if_softc; 1658 1659 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1660 (void) sk_init(ifp); 1661 } 1662 1663 void 1664 sk_shutdown(void * v) 1665 { 1666 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1667 struct sk_softc *sc = sc_if->sk_softc; 1668 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1669 1670 DPRINTFN(2, ("sk_shutdown\n")); 1671 sk_stop(ifp,1); 1672 1673 /* Turn off the 'driver is loaded' LED. */ 1674 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1675 1676 /* 1677 * Reset the GEnesis controller. Doing this should also 1678 * assert the resets on the attached XMAC(s). 1679 */ 1680 sk_reset(sc); 1681 } 1682 1683 void 1684 sk_rxeof(struct sk_if_softc *sc_if) 1685 { 1686 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1687 struct mbuf *m; 1688 struct sk_chain *cur_rx; 1689 struct sk_rx_desc *cur_desc; 1690 int i, cur, total_len = 0; 1691 u_int32_t rxstat; 1692 bus_dmamap_t dmamap; 1693 1694 i = sc_if->sk_cdata.sk_rx_prod; 1695 1696 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1697 1698 for (;;) { 1699 cur = i; 1700 1701 /* Sync the descriptor */ 1702 SK_CDRXSYNC(sc_if, cur, 1703 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1704 1705 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1706 /* Invalidate the descriptor -- it's not ready yet */ 1707 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1708 sc_if->sk_cdata.sk_rx_prod = i; 1709 break; 1710 } 1711 1712 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1713 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1714 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1715 1716 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1717 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1718 1719 rxstat = cur_desc->sk_xmac_rxstat; 1720 m = cur_rx->sk_mbuf; 1721 cur_rx->sk_mbuf = NULL; 1722 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1723 1724 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1725 1726 SK_INC(i, SK_RX_RING_CNT); 1727 1728 if (rxstat & XM_RXSTAT_ERRFRAME) { 1729 ifp->if_ierrors++; 1730 sk_newbuf(sc_if, cur, m, dmamap); 1731 continue; 1732 } 1733 1734 /* 1735 * Try to allocate a new jumbo buffer. If that 1736 * fails, copy the packet to mbufs and put the 1737 * jumbo buffer back in the ring so it can be 1738 * re-used. If allocating mbufs fails, then we 1739 * have to drop the packet. 1740 */ 1741 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1742 struct mbuf *m0; 1743 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1744 total_len + ETHER_ALIGN, 0, ifp, NULL); 1745 sk_newbuf(sc_if, cur, m, dmamap); 1746 if (m0 == NULL) { 1747 printf("%s: no receive buffers " 1748 "available -- packet dropped!\n", 1749 sc_if->sk_dev.dv_xname); 1750 ifp->if_ierrors++; 1751 continue; 1752 } 1753 m_adj(m0, ETHER_ALIGN); 1754 m = m0; 1755 } else { 1756 m->m_pkthdr.rcvif = ifp; 1757 m->m_pkthdr.len = m->m_len = total_len; 1758 } 1759 1760 ifp->if_ipackets++; 1761 1762 #if NBPFILTER > 0 1763 if (ifp->if_bpf) 1764 bpf_mtap(ifp->if_bpf, m); 1765 #endif 1766 /* pass it on. */ 1767 (*ifp->if_input)(ifp, m); 1768 } 1769 } 1770 1771 void 1772 sk_txeof(struct sk_if_softc *sc_if) 1773 { 1774 struct sk_softc *sc = sc_if->sk_softc; 1775 struct sk_tx_desc *cur_tx = NULL; 1776 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1777 u_int32_t idx; 1778 struct sk_txmap_entry *entry; 1779 1780 DPRINTFN(3, ("sk_txeof\n")); 1781 1782 /* 1783 * Go through our tx ring and free mbufs for those 1784 * frames that have been sent. 1785 */ 1786 idx = sc_if->sk_cdata.sk_tx_cons; 1787 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1788 SK_CDTXSYNC(sc_if, idx, 1, 1789 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1790 1791 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1792 #ifdef SK_DEBUG 1793 if (skdebug >= 3) 1794 sk_dump_txdesc(cur_tx, idx); 1795 #endif 1796 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1797 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1798 break; 1799 } 1800 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1801 ifp->if_opackets++; 1802 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1803 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1804 1805 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1806 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1807 1808 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1809 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1810 1811 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1812 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1813 link); 1814 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1815 } 1816 sc_if->sk_cdata.sk_tx_cnt--; 1817 SK_INC(idx, SK_TX_RING_CNT); 1818 } 1819 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1820 ifp->if_timer = 0; 1821 1822 sc_if->sk_cdata.sk_tx_cons = idx; 1823 1824 if (cur_tx != NULL) 1825 ifp->if_flags &= ~IFF_OACTIVE; 1826 } 1827 1828 void 1829 sk_tick(void *xsc_if) 1830 { 1831 struct sk_if_softc *sc_if = xsc_if; 1832 struct mii_data *mii = &sc_if->sk_mii; 1833 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1834 int i; 1835 1836 DPRINTFN(3, ("sk_tick\n")); 1837 1838 if (!(ifp->if_flags & IFF_UP)) 1839 return; 1840 1841 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1842 sk_intr_bcom(sc_if); 1843 return; 1844 } 1845 1846 /* 1847 * According to SysKonnect, the correct way to verify that 1848 * the link has come back up is to poll bit 0 of the GPIO 1849 * register three times. This pin has the signal from the 1850 * link sync pin connected to it; if we read the same link 1851 * state 3 times in a row, we know the link is up. 1852 */ 1853 for (i = 0; i < 3; i++) { 1854 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1855 break; 1856 } 1857 1858 if (i != 3) { 1859 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1860 return; 1861 } 1862 1863 /* Turn the GP0 interrupt back on. */ 1864 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1865 SK_XM_READ_2(sc_if, XM_ISR); 1866 mii_tick(mii); 1867 mii_pollstat(mii); 1868 callout_stop(&sc_if->sk_tick_ch); 1869 } 1870 1871 void 1872 sk_intr_bcom(struct sk_if_softc *sc_if) 1873 { 1874 struct mii_data *mii = &sc_if->sk_mii; 1875 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1876 int status; 1877 1878 1879 DPRINTFN(3, ("sk_intr_bcom\n")); 1880 1881 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1882 1883 /* 1884 * Read the PHY interrupt register to make sure 1885 * we clear any pending interrupts. 1886 */ 1887 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1888 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1889 1890 if (!(ifp->if_flags & IFF_RUNNING)) { 1891 sk_init_xmac(sc_if); 1892 return; 1893 } 1894 1895 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1896 int lstat; 1897 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1898 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1899 1900 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1901 mii_mediachg(mii); 1902 /* Turn off the link LED. */ 1903 SK_IF_WRITE_1(sc_if, 0, 1904 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1905 sc_if->sk_link = 0; 1906 } else if (status & BRGPHY_ISR_LNK_CHG) { 1907 sk_xmac_miibus_writereg((struct device *)sc_if, 1908 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1909 mii_tick(mii); 1910 sc_if->sk_link = 1; 1911 /* Turn on the link LED. */ 1912 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1913 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1914 SK_LINKLED_BLINK_OFF); 1915 mii_pollstat(mii); 1916 } else { 1917 mii_tick(mii); 1918 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 1919 } 1920 } 1921 1922 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1923 } 1924 1925 void 1926 sk_intr_xmac(struct sk_if_softc *sc_if) 1927 { 1928 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1929 1930 DPRINTFN(3, ("sk_intr_xmac\n")); 1931 1932 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1933 if (status & XM_ISR_GP0_SET) { 1934 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1935 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1936 } 1937 1938 if (status & XM_ISR_AUTONEG_DONE) { 1939 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1940 } 1941 } 1942 1943 if (status & XM_IMR_TX_UNDERRUN) 1944 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1945 1946 if (status & XM_IMR_RX_OVERRUN) 1947 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1948 } 1949 1950 void 1951 sk_intr_yukon(sc_if) 1952 struct sk_if_softc *sc_if; 1953 { 1954 int status; 1955 1956 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1957 1958 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 1959 } 1960 1961 int 1962 sk_intr(void *xsc) 1963 { 1964 struct sk_softc *sc = xsc; 1965 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1966 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1967 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1968 u_int32_t status; 1969 int claimed = 0; 1970 1971 if (sc_if0 != NULL) 1972 ifp0 = &sc_if0->sk_ethercom.ec_if; 1973 if (sc_if1 != NULL) 1974 ifp1 = &sc_if1->sk_ethercom.ec_if; 1975 1976 for (;;) { 1977 status = CSR_READ_4(sc, SK_ISSR); 1978 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 1979 1980 if (!(status & sc->sk_intrmask)) 1981 break; 1982 1983 claimed = 1; 1984 1985 /* Handle receive interrupts first. */ 1986 if (status & SK_ISR_RX1_EOF) { 1987 sk_rxeof(sc_if0); 1988 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1989 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1990 } 1991 if (status & SK_ISR_RX2_EOF) { 1992 sk_rxeof(sc_if1); 1993 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1994 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1995 } 1996 1997 /* Then transmit interrupts. */ 1998 if (status & SK_ISR_TX1_S_EOF) { 1999 sk_txeof(sc_if0); 2000 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2001 SK_TXBMU_CLR_IRQ_EOF); 2002 } 2003 if (status & SK_ISR_TX2_S_EOF) { 2004 sk_txeof(sc_if1); 2005 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2006 SK_TXBMU_CLR_IRQ_EOF); 2007 } 2008 2009 /* Then MAC interrupts. */ 2010 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2011 if (sc->sk_type == SK_GENESIS) 2012 sk_intr_xmac(sc_if0); 2013 else 2014 sk_intr_yukon(sc_if0); 2015 } 2016 2017 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2018 if (sc->sk_type == SK_GENESIS) 2019 sk_intr_xmac(sc_if1); 2020 else 2021 sk_intr_yukon(sc_if1); 2022 2023 } 2024 2025 if (status & SK_ISR_EXTERNAL_REG) { 2026 if (ifp0 != NULL && 2027 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2028 sk_intr_bcom(sc_if0); 2029 2030 if (ifp1 != NULL && 2031 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2032 sk_intr_bcom(sc_if1); 2033 } 2034 } 2035 2036 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2037 2038 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2039 sk_start(ifp0); 2040 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2041 sk_start(ifp1); 2042 2043 return (claimed); 2044 } 2045 2046 void 2047 sk_init_xmac(struct sk_if_softc *sc_if) 2048 { 2049 struct sk_softc *sc = sc_if->sk_softc; 2050 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2051 static const struct sk_bcom_hack bhack[] = { 2052 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2053 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2054 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2055 { 0, 0 } }; 2056 2057 DPRINTFN(1, ("sk_init_xmac\n")); 2058 2059 /* Unreset the XMAC. */ 2060 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2061 DELAY(1000); 2062 2063 /* Reset the XMAC's internal state. */ 2064 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2065 2066 /* Save the XMAC II revision */ 2067 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2068 2069 /* 2070 * Perform additional initialization for external PHYs, 2071 * namely for the 1000baseTX cards that use the XMAC's 2072 * GMII mode. 2073 */ 2074 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2075 int i = 0; 2076 u_int32_t val; 2077 2078 /* Take PHY out of reset. */ 2079 val = sk_win_read_4(sc, SK_GPIO); 2080 if (sc_if->sk_port == SK_PORT_A) 2081 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2082 else 2083 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2084 sk_win_write_4(sc, SK_GPIO, val); 2085 2086 /* Enable GMII mode on the XMAC. */ 2087 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2088 2089 sk_xmac_miibus_writereg((struct device *)sc_if, 2090 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2091 DELAY(10000); 2092 sk_xmac_miibus_writereg((struct device *)sc_if, 2093 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2094 2095 /* 2096 * Early versions of the BCM5400 apparently have 2097 * a bug that requires them to have their reserved 2098 * registers initialized to some magic values. I don't 2099 * know what the numbers do, I'm just the messenger. 2100 */ 2101 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2102 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2103 while(bhack[i].reg) { 2104 sk_xmac_miibus_writereg((struct device *)sc_if, 2105 SK_PHYADDR_BCOM, bhack[i].reg, 2106 bhack[i].val); 2107 i++; 2108 } 2109 } 2110 } 2111 2112 /* Set station address */ 2113 SK_XM_WRITE_2(sc_if, XM_PAR0, 2114 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2115 SK_XM_WRITE_2(sc_if, XM_PAR1, 2116 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2117 SK_XM_WRITE_2(sc_if, XM_PAR2, 2118 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2119 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2120 2121 if (ifp->if_flags & IFF_PROMISC) { 2122 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2123 } else { 2124 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2125 } 2126 2127 if (ifp->if_flags & IFF_BROADCAST) { 2128 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2129 } else { 2130 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2131 } 2132 2133 /* We don't need the FCS appended to the packet. */ 2134 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2135 2136 /* We want short frames padded to 60 bytes. */ 2137 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2138 2139 /* 2140 * Enable the reception of all error frames. This is is 2141 * a necessary evil due to the design of the XMAC. The 2142 * XMAC's receive FIFO is only 8K in size, however jumbo 2143 * frames can be up to 9000 bytes in length. When bad 2144 * frame filtering is enabled, the XMAC's RX FIFO operates 2145 * in 'store and forward' mode. For this to work, the 2146 * entire frame has to fit into the FIFO, but that means 2147 * that jumbo frames larger than 8192 bytes will be 2148 * truncated. Disabling all bad frame filtering causes 2149 * the RX FIFO to operate in streaming mode, in which 2150 * case the XMAC will start transfering frames out of the 2151 * RX FIFO as soon as the FIFO threshold is reached. 2152 */ 2153 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2154 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2155 XM_MODE_RX_INRANGELEN); 2156 2157 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2158 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2159 else 2160 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2161 2162 /* 2163 * Bump up the transmit threshold. This helps hold off transmit 2164 * underruns when we're blasting traffic from both ports at once. 2165 */ 2166 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2167 2168 /* Set multicast filter */ 2169 sk_setmulti(sc_if); 2170 2171 /* Clear and enable interrupts */ 2172 SK_XM_READ_2(sc_if, XM_ISR); 2173 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2174 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2175 else 2176 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2177 2178 /* Configure MAC arbiter */ 2179 switch(sc_if->sk_xmac_rev) { 2180 case XM_XMAC_REV_B2: 2181 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2182 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2183 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2184 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2185 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2186 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2187 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2188 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2189 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2190 break; 2191 case XM_XMAC_REV_C1: 2192 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2193 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2194 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2195 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2196 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2197 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2198 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2199 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2200 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2201 break; 2202 default: 2203 break; 2204 } 2205 sk_win_write_2(sc, SK_MACARB_CTL, 2206 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2207 2208 sc_if->sk_link = 1; 2209 } 2210 2211 void sk_init_yukon(sc_if) 2212 struct sk_if_softc *sc_if; 2213 { 2214 u_int32_t /*mac, */phy; 2215 u_int16_t reg; 2216 int i; 2217 2218 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2219 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2220 2221 /* GMAC and GPHY Reset */ 2222 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2223 2224 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2225 2226 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2227 DELAY(1000); 2228 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2229 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2230 DELAY(1000); 2231 2232 2233 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2234 2235 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2236 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2237 2238 switch(sc_if->sk_softc->sk_pmd) { 2239 case IFM_1000_SX: 2240 case IFM_1000_LX: 2241 phy |= SK_GPHY_FIBER; 2242 break; 2243 2244 case IFM_1000_CX: 2245 case IFM_1000_T: 2246 phy |= SK_GPHY_COPPER; 2247 break; 2248 } 2249 2250 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2251 2252 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2253 DELAY(1000); 2254 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2255 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2256 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2257 2258 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2259 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2260 2261 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2262 2263 /* unused read of the interrupt source register */ 2264 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2265 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2266 2267 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2268 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2269 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2270 2271 /* MIB Counter Clear Mode set */ 2272 reg |= YU_PAR_MIB_CLR; 2273 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2274 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2275 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2276 2277 /* MIB Counter Clear Mode clear */ 2278 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2279 reg &= ~YU_PAR_MIB_CLR; 2280 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2281 2282 /* receive control reg */ 2283 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2284 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2285 YU_RCR_CRCR); 2286 2287 /* transmit parameter register */ 2288 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2289 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2290 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2291 2292 /* serial mode register */ 2293 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2294 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2295 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2296 2297 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2298 /* Setup Yukon's address */ 2299 for (i = 0; i < 3; i++) { 2300 /* Write Source Address 1 (unicast filter) */ 2301 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2302 sc_if->sk_enaddr[i * 2] | 2303 sc_if->sk_enaddr[i * 2 + 1] << 8); 2304 } 2305 2306 for (i = 0; i < 3; i++) { 2307 reg = sk_win_read_2(sc_if->sk_softc, 2308 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2309 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2310 } 2311 2312 /* clear all Multicast filter hash registers */ 2313 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2314 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2315 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2316 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2317 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2318 2319 /* enable interrupt mask for counter overflows */ 2320 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2321 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2322 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2323 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2324 2325 /* Configure RX MAC FIFO */ 2326 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2328 2329 /* Configure TX MAC FIFO */ 2330 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2331 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2332 2333 DPRINTFN(6, ("sk_init_yukon: end\n")); 2334 } 2335 2336 /* 2337 * Note that to properly initialize any part of the GEnesis chip, 2338 * you first have to take it out of reset mode. 2339 */ 2340 int 2341 sk_init(struct ifnet *ifp) 2342 { 2343 struct sk_if_softc *sc_if = ifp->if_softc; 2344 struct sk_softc *sc = sc_if->sk_softc; 2345 struct mii_data *mii = &sc_if->sk_mii; 2346 int s; 2347 2348 DPRINTFN(1, ("sk_init\n")); 2349 2350 s = splnet(); 2351 2352 /* Cancel pending I/O and free all RX/TX buffers. */ 2353 sk_stop(ifp,0); 2354 2355 if (sc->sk_type == SK_GENESIS) { 2356 /* Configure LINK_SYNC LED */ 2357 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2358 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2359 SK_LINKLED_LINKSYNC_ON); 2360 2361 /* Configure RX LED */ 2362 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2363 SK_RXLEDCTL_COUNTER_START); 2364 2365 /* Configure TX LED */ 2366 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2367 SK_TXLEDCTL_COUNTER_START); 2368 } 2369 2370 /* Configure I2C registers */ 2371 2372 /* Configure XMAC(s) */ 2373 switch (sc->sk_type) { 2374 case SK_GENESIS: 2375 sk_init_xmac(sc_if); 2376 break; 2377 case SK_YUKON: 2378 sk_init_yukon(sc_if); 2379 break; 2380 } 2381 mii_mediachg(mii); 2382 2383 if (sc->sk_type == SK_GENESIS) { 2384 /* Configure MAC FIFOs */ 2385 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2386 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2387 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2388 2389 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2390 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2391 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2392 } 2393 2394 /* Configure transmit arbiter(s) */ 2395 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2396 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2397 2398 /* Configure RAMbuffers */ 2399 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2400 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2401 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2402 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2403 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2404 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2405 2406 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2407 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2408 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2409 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2410 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2411 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2412 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2413 2414 /* Configure BMUs */ 2415 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2416 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2417 SK_RX_RING_ADDR(sc_if, 0)); 2418 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2419 2420 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2421 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2422 SK_TX_RING_ADDR(sc_if, 0)); 2423 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2424 2425 /* Init descriptors */ 2426 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2427 printf("%s: initialization failed: no " 2428 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2429 sk_stop(ifp,0); 2430 splx(s); 2431 return(ENOBUFS); 2432 } 2433 2434 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2435 printf("%s: initialization failed: no " 2436 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2437 sk_stop(ifp,0); 2438 splx(s); 2439 return(ENOBUFS); 2440 } 2441 2442 /* Configure interrupt handling */ 2443 CSR_READ_4(sc, SK_ISSR); 2444 if (sc_if->sk_port == SK_PORT_A) 2445 sc->sk_intrmask |= SK_INTRS1; 2446 else 2447 sc->sk_intrmask |= SK_INTRS2; 2448 2449 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2450 2451 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2452 2453 /* Start BMUs. */ 2454 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2455 2456 if (sc->sk_type == SK_GENESIS) { 2457 /* Enable XMACs TX and RX state machines */ 2458 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2459 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2460 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2461 } 2462 2463 if (sc->sk_type == SK_YUKON) { 2464 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2465 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2466 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2467 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2468 } 2469 2470 2471 ifp->if_flags |= IFF_RUNNING; 2472 ifp->if_flags &= ~IFF_OACTIVE; 2473 2474 splx(s); 2475 return(0); 2476 } 2477 2478 void 2479 sk_stop(struct ifnet *ifp, int disable) 2480 { 2481 struct sk_if_softc *sc_if = ifp->if_softc; 2482 struct sk_softc *sc = sc_if->sk_softc; 2483 int i; 2484 2485 DPRINTFN(1, ("sk_stop\n")); 2486 2487 callout_stop(&sc_if->sk_tick_ch); 2488 2489 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2490 u_int32_t val; 2491 2492 /* Put PHY back into reset. */ 2493 val = sk_win_read_4(sc, SK_GPIO); 2494 if (sc_if->sk_port == SK_PORT_A) { 2495 val |= SK_GPIO_DIR0; 2496 val &= ~SK_GPIO_DAT0; 2497 } else { 2498 val |= SK_GPIO_DIR2; 2499 val &= ~SK_GPIO_DAT2; 2500 } 2501 sk_win_write_4(sc, SK_GPIO, val); 2502 } 2503 2504 /* Turn off various components of this interface. */ 2505 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2506 switch (sc->sk_type) { 2507 case SK_GENESIS: 2508 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2509 SK_TXMACCTL_XMAC_RESET); 2510 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2511 break; 2512 case SK_YUKON: 2513 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2514 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2515 break; 2516 } 2517 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2518 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2519 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2520 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2521 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2522 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2523 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2524 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2525 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2526 2527 /* Disable interrupts */ 2528 if (sc_if->sk_port == SK_PORT_A) 2529 sc->sk_intrmask &= ~SK_INTRS1; 2530 else 2531 sc->sk_intrmask &= ~SK_INTRS2; 2532 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2533 2534 SK_XM_READ_2(sc_if, XM_ISR); 2535 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2536 2537 /* Free RX and TX mbufs still in the queues. */ 2538 for (i = 0; i < SK_RX_RING_CNT; i++) { 2539 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2540 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2541 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2542 } 2543 } 2544 2545 for (i = 0; i < SK_TX_RING_CNT; i++) { 2546 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2547 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2548 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2549 } 2550 } 2551 2552 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2553 } 2554 2555 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2556 2557 /* 2558 struct cfdriver skc_cd = { 2559 0, "skc", DV_DULL 2560 }; 2561 */ 2562 2563 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2564 2565 /* 2566 struct cfdriver sk_cd = { 2567 0, "sk", DV_IFNET 2568 }; 2569 */ 2570 2571 #ifdef SK_DEBUG 2572 void 2573 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2574 { 2575 #define DESC_PRINT(X) \ 2576 if (desc->X) \ 2577 printf("txdesc[%d]." #X "=%#x\n", \ 2578 idx, desc->X); 2579 2580 DESC_PRINT(sk_ctl); 2581 DESC_PRINT(sk_next); 2582 DESC_PRINT(sk_data_lo); 2583 DESC_PRINT(sk_data_hi); 2584 DESC_PRINT(sk_xmac_txstat); 2585 DESC_PRINT(sk_rsvd0); 2586 DESC_PRINT(sk_csum_startval); 2587 DESC_PRINT(sk_csum_startpos); 2588 DESC_PRINT(sk_csum_writepos); 2589 DESC_PRINT(sk_rsvd1); 2590 #undef PRINT 2591 } 2592 2593 void 2594 sk_dump_bytes(const char *data, int len) 2595 { 2596 int c, i, j; 2597 2598 for (i = 0; i < len; i += 16) { 2599 printf("%08x ", i); 2600 c = len - i; 2601 if (c > 16) c = 16; 2602 2603 for (j = 0; j < c; j++) { 2604 printf("%02x ", data[i + j] & 0xff); 2605 if ((j & 0xf) == 7 && j > 0) 2606 printf(" "); 2607 } 2608 2609 for (; j < 16; j++) 2610 printf(" "); 2611 printf(" "); 2612 2613 for (j = 0; j < c; j++) { 2614 int ch = data[i + j] & 0xff; 2615 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2616 } 2617 2618 printf("\n"); 2619 2620 if (c < 16) 2621 break; 2622 } 2623 } 2624 2625 void 2626 sk_dump_mbuf(struct mbuf *m) 2627 { 2628 int count = m->m_pkthdr.len; 2629 2630 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2631 2632 while (count > 0 && m) { 2633 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2634 m, m->m_data, m->m_len); 2635 sk_dump_bytes(mtod(m, char *), m->m_len); 2636 2637 count -= m->m_len; 2638 m = m->m_next; 2639 } 2640 } 2641 #endif 2642