1 /* $NetBSD: if_sipreg.h,v 1.2 2000/01/31 18:36:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_PCI_IF_SIPREG_H_ 33 #define _DEV_PCI_IF_SIPREG_H_ 34 35 /* 36 * Register description for the Silicon Integrated Systems SiS 900 37 * and SiS 7016 10/100 PCI Ethernet controller. 38 * 39 * Written by Jason R. Thorpe for Network Computer, Inc. 40 */ 41 42 /* 43 * Transmit FIFO size. Used to compute the transmit drain threshold. 44 * 45 * The transmit FIFO is arranged as a 512 32-bit memory array. 46 */ 47 #define SIP_TXFIFO_SIZE (512 * 4) 48 49 /* 50 * The SiS900 uses a single descriptor format for both transmit 51 * and receive descriptor chains. 52 */ 53 struct sip_desc { 54 u_int32_t sipd_link; /* link to next descriptor */ 55 u_int32_t sipd_cmdsts; /* command/status word */ 56 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 57 }; 58 59 /* 60 * CMDSTS bits common to transmit and receive. 61 */ 62 #define CMDSTS_OWN 0x80000000 /* owned by consumer */ 63 #define CMDSTS_MORE 0x40000000 /* more descriptors */ 64 #define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */ 65 #define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */ 66 #define CMDSTS_OK 0x08000000 /* packet ok */ 67 #define CMDSTS_SIZE_MASK 0x000007ff /* packet size */ 68 69 #define CMDSTS_SIZE(x) ((x) & CMDSTS_SIZE_MASK) 70 71 /* 72 * CMDSTS bits for transmit. 73 */ 74 #define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */ 75 #define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */ 76 #define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */ 77 #define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */ 78 #define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */ 79 #define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */ 80 #define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */ 81 #define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */ 82 83 #define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16) 84 85 /* 86 * CMDSTS bits for receive. 87 */ 88 #define CMDSTS_Rx_RXA 0x04000000 /* receive abort */ 89 #define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */ 90 #define CMDSTS_Rx_DEST 0x01800000 /* destination class */ 91 #define CMDSTS_Rx_LONG 0x00400000 /* packet too long */ 92 #define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */ 93 #define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */ 94 #define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */ 95 #define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */ 96 #define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */ 97 #define CMDSTS_Rx_COL 0x00010000 /* collision activity */ 98 99 #define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */ 100 #define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */ 101 #define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */ 102 #define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */ 103 104 /* 105 * PCI Configuration space registers. 106 */ 107 #define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00) 108 109 #define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04) 110 111 #define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */ 112 113 #define SIP_PCI_CFGPMC 0x40 /* power management cap. */ 114 115 #define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */ 116 117 /* 118 * MAC Operation Registers 119 */ 120 #define SIP_CR 0x00 /* command register */ 121 #define CR_RST 0x00000100 /* software reset */ 122 #define CR_SWI 0x00000080 /* software interrupt */ 123 #define CR_RXR 0x00000020 /* receiver reset */ 124 #define CR_TXR 0x00000010 /* transmit reset */ 125 #define CR_RXD 0x00000008 /* receiver disable */ 126 #define CR_RXE 0x00000004 /* receiver enable */ 127 #define CR_TXD 0x00000002 /* transmit disable */ 128 #define CR_TXE 0x00000001 /* transmit enable */ 129 130 #define SIP_CFG 0x04 /* configuration register */ 131 #define CFG_REQALG 0x00000080 /* PCI bus request alg. */ 132 #define CFG_SB 0x00000040 /* single backoff */ 133 #define CFG_POW 0x00000020 /* program out of window timer */ 134 #define CFG_EXD 0x00000010 /* excessive defferal timer disable */ 135 #define CFG_PESEL 0x00000008 /* parity error detection action */ 136 #define CFG_BEM 0x00000001 /* big-endian mode */ 137 138 #define SIP_EROMAR 0x08 /* EEPROM access register */ 139 #define EROMAR_EECS 0x00000008 /* chip select */ 140 #define EROMAR_EESK 0x00000004 /* clock */ 141 #define EROMAR_EEDO 0x00000002 /* data out */ 142 #define EROMAR_EEDI 0x00000001 /* data in */ 143 144 #define SIP_PTSCR 0x0c /* PCI test control register */ 145 #define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */ 146 #define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */ 147 #define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */ 148 #define PTSCR_BMTEN 0x00000200 /* bus master test enable */ 149 #define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */ 150 #define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */ 151 #define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */ 152 #define PTSCR_SRAMADR 0x0000001f /* status RAM address */ 153 154 #define SIP_ISR 0x10 /* interrupt status register */ 155 #define ISR_WAKEEVT 0x10000000 /* wake up event */ 156 #define ISR_PAUSE_END 0x08000000 /* end of transmission pause */ 157 #define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */ 158 #define ISR_TXRCMP 0x02000000 /* transmit reset complete */ 159 #define ISR_RXRCMP 0x01000000 /* receive reset complete */ 160 #define ISR_DPERR 0x00800000 /* detected parity error */ 161 #define ISR_SSERR 0x00400000 /* signalled system error */ 162 #define ISR_RMABT 0x00200000 /* received master abort */ 163 #define ISR_RTABT 0x00100000 /* received target abort */ 164 #define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */ 165 #define ISR_HIBERR 0x00008000 /* high bits error set */ 166 #define ISR_SWI 0x00001000 /* software interrupt */ 167 #define ISR_TXURN 0x00000400 /* Tx underrun */ 168 #define ISR_TXIDLE 0x00000200 /* Tx idle */ 169 #define ISR_TXERR 0x00000100 /* Tx error */ 170 #define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */ 171 #define ISR_TXOK 0x00000040 /* Tx okay */ 172 #define ISR_RXORN 0x00000020 /* Rx overrun */ 173 #define ISR_RXIDLE 0x00000010 /* Rx idle */ 174 #define ISR_RXEARLY 0x00000008 /* Rx early */ 175 #define ISR_RXERR 0x00000004 /* Rx error */ 176 #define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */ 177 #define ISR_RXOK 0x00000001 /* Rx okay */ 178 179 #define SIP_IMR 0x14 /* interrupt mask register */ 180 /* See bits in SIP_ISR */ 181 182 #define SIP_IER 0x18 /* interrupt enable register */ 183 #define IER_IE 0x00000001 /* master interrupt enable */ 184 185 #define SIP_ENPHY 0x1c /* enhanced PHY access register */ 186 #define ENPHY_PHYDATA 0xffff0000 /* PHY data */ 187 #define ENPHY_DATA_SHIFT 16 188 #define ENPHY_PHYADDR 0x0000f800 /* PHY number (7016 only) */ 189 #define ENPHY_PHYADDR_SHIFT 11 190 #define ENPHY_REGADDR 0x000007c0 /* PHY register */ 191 #define ENPHY_REGADDR_SHIFT 6 192 #define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */ 193 #define ENPHY_ACCESS 0x00000010 /* PHY access enable */ 194 195 #define SIP_TXDP 0x20 /* transmit descriptor pointer reg */ 196 197 #define SIP_TXCFG 0x24 /* transmit configuration register */ 198 #define TXCFG_CSI 0x80000000 /* carrier sense ignore */ 199 #define TXCFG_HBI 0x40000000 /* heartbeat ignore */ 200 #define TXCFG_MLB 0x20000000 /* MAC loopback */ 201 #define TXCFG_ATP 0x10000000 /* automatic transmit padding */ 202 #define TXCFG_MXDMA 0x00700000 /* max DMA burst size */ 203 #define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 204 #define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 205 #define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 206 #define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 207 #define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 208 #define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 209 #define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 210 #define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 211 #define TXCFG_FLTH 0x00003f00 /* Tx fill threshold */ 212 #define TXCFG_FLTH_SHIFT 8 213 #define TXCFG_DRTH 0x0000003f /* Tx drain threshold */ 214 215 #define SIP_RXDP 0x30 /* receive desciptor pointer reg */ 216 217 #define SIP_RXCFG 0x34 /* receive configuration register */ 218 #define RXCFG_AEP 0x80000000 /* accept error packets */ 219 #define RXCFG_ARP 0x40000000 /* accept runt packets */ 220 #define RXCFG_ATX 0x10000000 /* accept transmit packets */ 221 #define RXCFG_AJAB 0x08000000 /* accept jabber packets */ 222 #define RXCFG_MXDMA 0x00700000 /* max DMA burst size */ 223 #define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 224 #define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 225 #define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 226 #define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 227 #define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 228 #define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 229 #define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 230 #define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 231 #define RXCFG_DRTH 0x0000003e 232 #define RXCFG_DRTH_SHIFT 1 233 234 #define SIP_FLOWCTL 0x38 /* flow control register */ 235 #define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */ 236 #define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */ 237 238 #define SIP_RFCR 0x48 /* receive filter control register */ 239 #define RFCR_RFEN 0x80000000 /* Rx filter enable */ 240 #define RFCR_AAB 0x40000000 /* accept all broadcast */ 241 #define RFCR_AAM 0x20000000 /* accept all multicast */ 242 #define RFCR_AAP 0x10000000 /* accept all physical */ 243 #define RFCR_RFADDR 0x000f0000 /* Rx filter address */ 244 #define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */ 245 #define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */ 246 #define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */ 247 #define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */ 248 #define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */ 249 #define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */ 250 #define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */ 251 #define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */ 252 #define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */ 253 #define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */ 254 #define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */ 255 256 #define SIP_RFDR 0x4c /* receive filter data register */ 257 #define RFDR_DATA 0x0000ffff /* data bits */ 258 259 #define SIP_PMCTL 0xb0 /* power management control register */ 260 #define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */ 261 #define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */ 262 #define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */ 263 #define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */ 264 #define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */ 265 #define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */ 266 #define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */ 267 #define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */ 268 #define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */ 269 #define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */ 270 #define PMCTL_LINKON 0x00000002 /* link on monitor enable */ 271 #define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */ 272 273 #define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */ 274 #define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */ 275 #define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */ 276 #define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */ 277 #define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */ 278 #define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */ 279 #define PMEVT_ONEVT 0x00000002 /* link on event */ 280 #define PMEVT_LOSSEVT 0x00000001 /* link loss event */ 281 282 #define SIP_WAKECRC 0xbc /* wake-up frame CRC register */ 283 284 #define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */ 285 #define SIP_WAKEMASK1 0xc4 286 #define SIP_WAKEMASK2 0xc8 287 #define SIP_WAKEMASK3 0xcc 288 #define SIP_WAKEMASK4 0xe0 289 #define SIP_WASKMASK5 0xe4 290 #define SIP_WAKEMASK6 0xe8 291 #define SIP_WAKEMASK7 0xec 292 293 /* 294 * Serial EEPROM opcodes, including the start bit. 295 */ 296 #define SIP_EEPROM_OPC_ERASE 0x04 297 #define SIP_EEPROM_OPC_WRITE 0x05 298 #define SIP_EEPROM_OPC_READ 0x06 299 300 /* 301 * Serial EEPROM address map (byte address). 302 */ 303 #define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */ 304 #define SIP_EEPROM_MASK 0x02 /* `enable' mask */ 305 #define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */ 306 #define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */ 307 #define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */ 308 #define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */ 309 #define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */ 310 #define SIP_EEPROM_reserved 0x0e /* reserved */ 311 #define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */ 312 #define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */ 313 #define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */ 314 #define SIP_EEPROM_CHECKSUM 0x16 /* checksum */ 315 316 #endif /* _DEV_PCI_IF_SIPREG_H_ */ 317