1 /* $NetBSD: if_sip.c,v 1.193 2024/07/05 04:31:51 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.193 2024/07/05 04:31:51 rin Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/ioctl.h> 85 #include <sys/errno.h> 86 #include <sys/device.h> 87 #include <sys/queue.h> 88 #include <sys/rndsource.h> 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/if_ether.h> 94 #include <net/bpf.h> 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 #include <machine/endian.h> 99 100 #include <dev/mii/mii.h> 101 #include <dev/mii/miivar.h> 102 #include <dev/mii/mii_bitbang.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/pci/if_sipreg.h> 109 110 /* 111 * Transmit descriptor list size. This is arbitrary, but allocate 112 * enough descriptors for 128 pending transmissions, and 8 segments 113 * per packet (64 for DP83820 for jumbo frames). 114 * 115 * This MUST work out to a power of 2. 116 */ 117 #define GSIP_NTXSEGS_ALLOC 16 118 #define SIP_NTXSEGS_ALLOC 8 119 120 #define SIP_TXQUEUELEN 256 121 #define MAX_SIP_NTXDESC \ 122 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 123 124 /* 125 * Receive descriptor list size. We have one Rx buffer per incoming 126 * packet, so this logic is a little simpler. 127 * 128 * Actually, on the DP83820, we allow the packet to consume more than 129 * one buffer, in order to support jumbo Ethernet frames. In that 130 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 131 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 132 * so we'd better be quick about handling receive interrupts. 133 */ 134 #define GSIP_NRXDESC 256 135 #define SIP_NRXDESC 128 136 137 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 138 139 /* 140 * Set this to 1 to force-disable using the 64-bit data path 141 * on DP83820. 142 */ 143 static int gsip_disable_data64 = 0; 144 145 /* 146 * Control structures are DMA'd to the SiS900 chip. We allocate them in 147 * a single clump that maps to a single DMA segment to make several things 148 * easier. 149 */ 150 struct sip_control_data { 151 /* 152 * The transmit descriptors. 153 */ 154 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 155 156 /* 157 * The receive descriptors. 158 */ 159 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 160 }; 161 162 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 163 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 164 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 165 166 /* 167 * Software state for transmit jobs. 168 */ 169 struct sip_txsoft { 170 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 171 bus_dmamap_t txs_dmamap; /* our DMA map */ 172 int txs_firstdesc; /* first descriptor in packet */ 173 int txs_lastdesc; /* last descriptor in packet */ 174 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 175 }; 176 177 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 178 179 /* 180 * Software state for receive jobs. 181 */ 182 struct sip_rxsoft { 183 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t rxs_dmamap; /* our DMA map */ 185 }; 186 187 enum sip_attach_stage { 188 SIP_ATTACH_FIN = 0 189 , SIP_ATTACH_CREATE_RXMAP 190 , SIP_ATTACH_CREATE_TXMAP 191 , SIP_ATTACH_LOAD_MAP 192 , SIP_ATTACH_CREATE_MAP 193 , SIP_ATTACH_MAP_MEM 194 , SIP_ATTACH_ALLOC_MEM 195 , SIP_ATTACH_INTR 196 , SIP_ATTACH_MAP 197 }; 198 199 /* 200 * Software state per device. 201 */ 202 struct sip_softc { 203 device_t sc_dev; /* generic device information */ 204 device_suspensor_t sc_suspensor; 205 pmf_qual_t sc_qual; 206 207 bus_space_tag_t sc_st; /* bus space tag */ 208 bus_space_handle_t sc_sh; /* bus space handle */ 209 bus_size_t sc_sz; /* bus space size */ 210 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 211 pci_chipset_tag_t sc_pc; 212 bus_dma_segment_t sc_seg; 213 struct ethercom sc_ethercom; /* ethernet common data */ 214 215 const struct sip_product *sc_model; /* which model are we? */ 216 bool sc_gigabit; /* 1: 83820, 0: other */ 217 bool sc_dma64; /* using 64-bit DMA addresses */ 218 int sc_rev; /* chip revision */ 219 220 unsigned int sc_bufptr_idx; 221 unsigned int sc_cmdsts_idx; 222 unsigned int sc_extsts_idx; /* DP83820 only */ 223 224 void *sc_ih; /* interrupt cookie */ 225 226 struct mii_data sc_mii; /* MII/media information */ 227 228 callout_t sc_tick_ch; /* tick callout */ 229 230 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 231 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 232 233 /* 234 * Software state for transmit and receive descriptors. 235 */ 236 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 237 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 238 239 /* 240 * Control data structures. 241 */ 242 struct sip_control_data *sc_control_data; 243 #define sc_txdescs sc_control_data->scd_txdescs 244 #define sc_rxdescs sc_control_data->scd_rxdescs 245 246 #ifdef SIP_EVENT_COUNTERS 247 /* 248 * Event counters. 249 */ 250 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 251 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 252 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 253 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 254 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 255 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 256 struct evcnt sc_ev_rxpause; /* PAUSE received */ 257 /* DP83820 only */ 258 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 259 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 260 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 261 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 262 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 263 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 264 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 265 #endif /* SIP_EVENT_COUNTERS */ 266 267 uint32_t sc_txcfg; /* prototype TXCFG register */ 268 uint32_t sc_rxcfg; /* prototype RXCFG register */ 269 uint32_t sc_imr; /* prototype IMR register */ 270 uint32_t sc_rfcr; /* prototype RFCR register */ 271 272 uint32_t sc_cfg; /* prototype CFG register */ 273 274 uint32_t sc_gpior; /* prototype GPIOR register */ 275 276 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 277 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 278 279 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 280 281 int sc_flowflags; /* 802.3x flow control flags */ 282 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 283 int sc_paused; /* paused indication */ 284 285 int sc_txfree; /* number of free Tx descriptors */ 286 int sc_txnext; /* next ready Tx descriptor */ 287 int sc_txwin; /* Tx descriptors since last intr */ 288 289 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 290 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 291 292 /* values of interface state at last init */ 293 struct { 294 /* if_capenable */ 295 uint64_t if_capenable; 296 /* ec_capenable */ 297 int ec_capenable; 298 /* VLAN_ATTACHED */ 299 int is_vlan; 300 } sc_prev; 301 302 u_short sc_if_flags; 303 304 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 305 int sc_rxdiscard; 306 int sc_rxlen; 307 struct mbuf *sc_rxhead; 308 struct mbuf *sc_rxtail; 309 struct mbuf **sc_rxtailp; 310 311 int sc_ntxdesc; 312 int sc_ntxdesc_mask; 313 314 int sc_nrxdesc_mask; 315 316 const struct sip_parm { 317 const struct sip_regs { 318 int r_rxcfg; 319 int r_txcfg; 320 } p_regs; 321 322 const struct sip_bits { 323 uint32_t b_txcfg_mxdma_8; 324 uint32_t b_txcfg_mxdma_16; 325 uint32_t b_txcfg_mxdma_32; 326 uint32_t b_txcfg_mxdma_64; 327 uint32_t b_txcfg_mxdma_128; 328 uint32_t b_txcfg_mxdma_256; 329 uint32_t b_txcfg_mxdma_512; 330 uint32_t b_txcfg_flth_mask; 331 uint32_t b_txcfg_drth_mask; 332 333 uint32_t b_rxcfg_mxdma_8; 334 uint32_t b_rxcfg_mxdma_16; 335 uint32_t b_rxcfg_mxdma_32; 336 uint32_t b_rxcfg_mxdma_64; 337 uint32_t b_rxcfg_mxdma_128; 338 uint32_t b_rxcfg_mxdma_256; 339 uint32_t b_rxcfg_mxdma_512; 340 341 uint32_t b_isr_txrcmp; 342 uint32_t b_isr_rxrcmp; 343 uint32_t b_isr_dperr; 344 uint32_t b_isr_sserr; 345 uint32_t b_isr_rmabt; 346 uint32_t b_isr_rtabt; 347 348 uint32_t b_cmdsts_size_mask; 349 } p_bits; 350 int p_filtmem; 351 int p_rxbuf_len; 352 bus_size_t p_tx_dmamap_size; 353 int p_ntxsegs; 354 int p_ntxsegs_alloc; 355 int p_nrxdesc; 356 } *sc_parm; 357 358 void (*sc_rxintr)(struct sip_softc *); 359 360 krndsource_t rnd_source; /* random source */ 361 }; 362 363 #define sc_bits sc_parm->p_bits 364 #define sc_regs sc_parm->p_regs 365 366 static const struct sip_parm sip_parm = { 367 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 368 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 369 , .p_tx_dmamap_size = MCLBYTES 370 , .p_ntxsegs = 16 371 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 372 , .p_nrxdesc = SIP_NRXDESC 373 , .p_bits = { 374 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 375 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 376 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 377 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 378 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 379 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 380 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 381 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 382 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 383 384 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 385 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 386 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 387 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 388 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 389 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 390 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 391 392 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 393 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 394 , .b_isr_dperr = 0x00800000 /* detected parity error */ 395 , .b_isr_sserr = 0x00400000 /* signalled system error */ 396 , .b_isr_rmabt = 0x00200000 /* received master abort */ 397 , .b_isr_rtabt = 0x00100000 /* received target abort */ 398 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 399 } 400 , .p_regs = { 401 .r_rxcfg = OTHER_SIP_RXCFG, 402 .r_txcfg = OTHER_SIP_TXCFG 403 } 404 }, gsip_parm = { 405 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 406 , .p_rxbuf_len = MCLBYTES - 8 407 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 408 , .p_ntxsegs = 64 409 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 410 , .p_nrxdesc = GSIP_NRXDESC 411 , .p_bits = { 412 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 413 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 414 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 415 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 416 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 417 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 418 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 419 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 420 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 421 422 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 423 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 424 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 425 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 426 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 427 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 428 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 429 430 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 431 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 432 , .b_isr_dperr = 0x00100000 /* detected parity error */ 433 , .b_isr_sserr = 0x00080000 /* signalled system error */ 434 , .b_isr_rmabt = 0x00040000 /* received master abort */ 435 , .b_isr_rtabt = 0x00020000 /* received target abort */ 436 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 437 } 438 , .p_regs = { 439 .r_rxcfg = DP83820_SIP_RXCFG, 440 .r_txcfg = DP83820_SIP_TXCFG 441 } 442 }; 443 444 static inline int 445 sip_nexttx(const struct sip_softc *sc, int x) 446 { 447 return (x + 1) & sc->sc_ntxdesc_mask; 448 } 449 450 static inline int 451 sip_nextrx(const struct sip_softc *sc, int x) 452 { 453 return (x + 1) & sc->sc_nrxdesc_mask; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_reset(struct sip_softc *sc) 459 { 460 sc->sc_rxtailp = &sc->sc_rxhead; 461 *sc->sc_rxtailp = NULL; 462 sc->sc_rxlen = 0; 463 } 464 465 /* 83820 only */ 466 static inline void 467 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 468 { 469 *sc->sc_rxtailp = sc->sc_rxtail = m; 470 sc->sc_rxtailp = &m->m_next; 471 } 472 473 #ifdef SIP_EVENT_COUNTERS 474 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 475 #else 476 #define SIP_EVCNT_INCR(ev) /* nothing */ 477 #endif 478 479 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 480 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 481 482 static inline void 483 sip_set_rxdp(struct sip_softc *sc, bus_addr_t addr) 484 { 485 if (sc->sc_gigabit) 486 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP_HI, 487 BUS_ADDR_HI32(addr)); 488 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP, BUS_ADDR_LO32(addr)); 489 } 490 491 static inline void 492 sip_set_txdp(struct sip_softc *sc, bus_addr_t addr) 493 { 494 if (sc->sc_gigabit) 495 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP_HI, 496 BUS_ADDR_HI32(addr)); 497 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, BUS_ADDR_LO32(addr)); 498 } 499 500 static inline void 501 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 502 { 503 int x, n; 504 505 x = x0; 506 n = n0; 507 508 /* If it will wrap around, sync to the end of the ring. */ 509 if (x + n > sc->sc_ntxdesc) { 510 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 511 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 512 (sc->sc_ntxdesc - x), ops); 513 n -= (sc->sc_ntxdesc - x); 514 x = 0; 515 } 516 517 /* Now sync whatever is left. */ 518 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 519 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 520 } 521 522 static inline void 523 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 524 { 525 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 526 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 527 } 528 529 static void 530 sip_init_txring(struct sip_softc *sc) 531 { 532 struct sip_desc *sipd; 533 bus_addr_t next_desc; 534 int i; 535 536 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 537 for (i = 0; i < sc->sc_ntxdesc; i++) { 538 sipd = &sc->sc_txdescs[i]; 539 next_desc = SIP_CDTXADDR(sc, sip_nexttx(sc, i)); 540 if (sc->sc_dma64) { 541 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 542 htole32(BUS_ADDR_LO32(next_desc)); 543 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 544 htole32(BUS_ADDR_HI32(next_desc)); 545 } else { 546 /* SIP_DESC_LINK == GSIP_DESC_LINK */ 547 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 548 } 549 } 550 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 552 sc->sc_txfree = sc->sc_ntxdesc; 553 sc->sc_txnext = 0; 554 sc->sc_txwin = 0; 555 } 556 557 static inline void 558 sip_init_txdesc(struct sip_softc *sc, int x, bus_addr_t bufptr, uint32_t cmdsts) 559 { 560 struct sip_desc *sipd = &sc->sc_txdescs[x]; 561 562 if (sc->sc_dma64) { 563 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 564 htole32(BUS_ADDR_LO32(bufptr)); 565 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 566 htole32(BUS_ADDR_HI32(bufptr)); 567 } else { 568 sipd->sipd_words[sc->sc_bufptr_idx] = htole32(bufptr); 569 } 570 sipd->sipd_words[sc->sc_extsts_idx] = 0; 571 sipd->sipd_words[sc->sc_cmdsts_idx] = htole32(cmdsts); 572 /* sip_cdtxsync() will be done later. */ 573 } 574 575 static inline void 576 sip_init_rxdesc(struct sip_softc *sc, int x) 577 { 578 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 579 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 580 const bus_addr_t next_desc = SIP_CDRXADDR(sc, sip_nextrx(sc, x)); 581 582 if (sc->sc_dma64) { 583 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 584 htole32(BUS_ADDR_LO32(next_desc)); 585 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 586 htole32(BUS_ADDR_HI32(next_desc)); 587 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 588 htole32(BUS_ADDR_LO32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 589 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 590 htole32(BUS_ADDR_HI32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 591 } else { 592 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 593 sipd->sipd_words[sc->sc_bufptr_idx] = 594 htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 595 } 596 sipd->sipd_words[sc->sc_extsts_idx] = 0; 597 sip_cdrxsync(sc, x, BUS_DMASYNC_PREWRITE); 598 sipd->sipd_words[sc->sc_cmdsts_idx] = 599 htole32(CMDSTS_INTR | (sc->sc_parm->p_rxbuf_len & 600 sc->sc_bits.b_cmdsts_size_mask)); 601 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 602 } 603 604 #define SIP_CHIP_VERS(sc, v, p, r) \ 605 ((sc)->sc_model->sip_vendor == (v) && \ 606 (sc)->sc_model->sip_product == (p) && \ 607 (sc)->sc_rev == (r)) 608 609 #define SIP_CHIP_MODEL(sc, v, p) \ 610 ((sc)->sc_model->sip_vendor == (v) && \ 611 (sc)->sc_model->sip_product == (p)) 612 613 #define SIP_SIS900_REV(sc, rev) \ 614 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 615 616 #define SIP_TIMEOUT 1000 617 618 static int sip_ifflags_cb(struct ethercom *); 619 static void sipcom_start(struct ifnet *); 620 static void sipcom_watchdog(struct ifnet *); 621 static int sipcom_ioctl(struct ifnet *, u_long, void *); 622 static int sipcom_init(struct ifnet *); 623 static void sipcom_stop(struct ifnet *, int); 624 625 static bool sipcom_reset(struct sip_softc *); 626 static void sipcom_rxdrain(struct sip_softc *); 627 static int sipcom_add_rxbuf(struct sip_softc *, int); 628 static void sipcom_read_eeprom(struct sip_softc *, int, int, 629 uint16_t *); 630 static void sipcom_tick(void *); 631 632 static void sipcom_sis900_set_filter(struct sip_softc *); 633 static void sipcom_dp83815_set_filter(struct sip_softc *); 634 635 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 636 const struct pci_attach_args *, uint8_t *); 637 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 638 static void sipcom_sis900_read_macaddr(struct sip_softc *, 639 const struct pci_attach_args *, uint8_t *); 640 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 641 const struct pci_attach_args *, uint8_t *); 642 643 static int sipcom_intr(void *); 644 static void sipcom_txintr(struct sip_softc *); 645 static void sip_rxintr(struct sip_softc *); 646 static void gsip_rxintr(struct sip_softc *); 647 648 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 649 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 650 static void sipcom_dp83820_mii_statchg(struct ifnet *); 651 652 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 653 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 654 static void sipcom_sis900_mii_statchg(struct ifnet *); 655 656 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 657 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 658 static void sipcom_dp83815_mii_statchg(struct ifnet *); 659 660 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 661 662 static int sipcom_match(device_t, cfdata_t, void *); 663 static void sipcom_attach(device_t, device_t, void *); 664 static void sipcom_do_detach(device_t, enum sip_attach_stage); 665 static int sipcom_detach(device_t, int); 666 static bool sipcom_resume(device_t, const pmf_qual_t *); 667 static bool sipcom_suspend(device_t, const pmf_qual_t *); 668 669 int gsip_copy_small = 0; 670 int sip_copy_small = 0; 671 672 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 673 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 674 DVF_DETACH_SHUTDOWN); 675 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 676 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 677 DVF_DETACH_SHUTDOWN); 678 679 /* 680 * Descriptions of the variants of the SiS900. 681 */ 682 struct sip_variant { 683 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 684 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 685 void (*sipv_mii_statchg)(struct ifnet *); 686 void (*sipv_set_filter)(struct sip_softc *); 687 void (*sipv_read_macaddr)(struct sip_softc *, 688 const struct pci_attach_args *, uint8_t *); 689 }; 690 691 static uint32_t sipcom_mii_bitbang_read(device_t); 692 static void sipcom_mii_bitbang_write(device_t, uint32_t); 693 694 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 695 sipcom_mii_bitbang_read, 696 sipcom_mii_bitbang_write, 697 { 698 EROMAR_MDIO, /* MII_BIT_MDO */ 699 EROMAR_MDIO, /* MII_BIT_MDI */ 700 EROMAR_MDC, /* MII_BIT_MDC */ 701 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 702 0, /* MII_BIT_DIR_PHY_HOST */ 703 } 704 }; 705 706 static const struct sip_variant sipcom_variant_dp83820 = { 707 sipcom_dp83820_mii_readreg, 708 sipcom_dp83820_mii_writereg, 709 sipcom_dp83820_mii_statchg, 710 sipcom_dp83815_set_filter, 711 sipcom_dp83820_read_macaddr, 712 }; 713 714 static const struct sip_variant sipcom_variant_sis900 = { 715 sipcom_sis900_mii_readreg, 716 sipcom_sis900_mii_writereg, 717 sipcom_sis900_mii_statchg, 718 sipcom_sis900_set_filter, 719 sipcom_sis900_read_macaddr, 720 }; 721 722 static const struct sip_variant sipcom_variant_dp83815 = { 723 sipcom_dp83815_mii_readreg, 724 sipcom_dp83815_mii_writereg, 725 sipcom_dp83815_mii_statchg, 726 sipcom_dp83815_set_filter, 727 sipcom_dp83815_read_macaddr, 728 }; 729 730 731 /* 732 * Devices supported by this driver. 733 */ 734 static const struct sip_product { 735 pci_vendor_id_t sip_vendor; 736 pci_product_id_t sip_product; 737 const char *sip_name; 738 const struct sip_variant *sip_variant; 739 bool sip_gigabit; 740 } sipcom_products[] = { 741 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 742 "NatSemi DP83820 Gigabit Ethernet", 743 &sipcom_variant_dp83820, true }, 744 745 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 746 "SiS 900 10/100 Ethernet", 747 &sipcom_variant_sis900, false }, 748 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 749 "SiS 7016 10/100 Ethernet", 750 &sipcom_variant_sis900, false }, 751 752 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 753 "NatSemi DP83815 10/100 Ethernet", 754 &sipcom_variant_dp83815, false }, 755 756 { 0, 0, 757 NULL, 758 NULL, false }, 759 }; 760 761 static const struct sip_product * 762 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 763 { 764 const struct sip_product *sip; 765 766 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 767 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 768 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 769 sip->sip_gigabit == gigabit) 770 return sip; 771 } 772 return NULL; 773 } 774 775 /* 776 * I really hate stupid hardware vendors. There's a bit in the EEPROM 777 * which indicates if the card can do 64-bit data transfers. Unfortunately, 778 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 779 * which means we try to use 64-bit data transfers on those cards if we 780 * happen to be plugged into a 32-bit slot. 781 * 782 * What we do is use this table of cards known to be 64-bit cards. If 783 * you have a 64-bit card who's subsystem ID is not listed in this table, 784 * send the output of "pcictl dump ..." of the device to me so that your 785 * card will use the 64-bit data path when plugged into a 64-bit slot. 786 * 787 * -- Jason R. Thorpe <thorpej@NetBSD.org> 788 * June 30, 2002 789 */ 790 static int 791 sipcom_check_64bit(const struct pci_attach_args *pa) 792 { 793 static const struct { 794 pci_vendor_id_t c64_vendor; 795 pci_product_id_t c64_product; 796 } card64[] = { 797 /* Asante GigaNIX */ 798 { 0x128a, 0x0002 }, 799 800 /* Accton EN1407-T, Planex GN-1000TE */ 801 { 0x1113, 0x1407 }, 802 803 /* Netgear GA621 */ 804 { 0x1385, 0x621a }, 805 806 /* Netgear GA622 */ 807 { 0x1385, 0x622a }, 808 809 /* SMC EZ Card 1000 (9462TX) */ 810 { 0x10b8, 0x9462 }, 811 812 { 0, 0} 813 }; 814 pcireg_t subsys; 815 int i; 816 817 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 818 819 for (i = 0; card64[i].c64_vendor != 0; i++) { 820 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 821 PCI_PRODUCT(subsys) == card64[i].c64_product) 822 return 1; 823 } 824 825 return 0; 826 } 827 828 static int 829 sipcom_match(device_t parent, cfdata_t cf, void *aux) 830 { 831 struct pci_attach_args *pa = aux; 832 833 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 834 return 1; 835 836 return 0; 837 } 838 839 static void 840 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 841 { 842 uint32_t reg; 843 int i; 844 845 /* 846 * Cause the chip to load configuration data from the EEPROM. 847 */ 848 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 849 for (i = 0; i < 10000; i++) { 850 delay(10); 851 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 852 PTSCR_EELOAD_EN) == 0) 853 break; 854 } 855 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 856 PTSCR_EELOAD_EN) { 857 printf("%s: timeout loading configuration from EEPROM\n", 858 device_xname(sc->sc_dev)); 859 return; 860 } 861 862 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 863 864 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 865 if (reg & CFG_PCI64_DET) { 866 const char *using64 = NULL; 867 868 if (reg & CFG_DATA64_EN) { 869 /* 870 * Check to see if this card is 64-bit. If so, 871 * enable 64-bit data transfers. 872 * 873 * We can't trust the DATA64_EN bit in the EEPROM, 874 * because vendors of 32-bit cards fail to clear 875 * that bit in many cases (yet the card still detects 876 * that it's in a 64-bit slot because I guess they 877 * wired up ACK64# and REQ64#). 878 */ 879 if (gsip_disable_data64) 880 using64 = "force-disabled"; 881 else if (sipcom_check_64bit(pa)) { 882 sc->sc_cfg |= CFG_DATA64_EN; 883 using64 = "enabled"; 884 } else 885 using64 = "disabled (32-bit card)"; 886 } else { 887 using64 = "disabled in EEPROM"; 888 } 889 printf("%s: 64-bit slot detected, 64-bit transfers %s\n", 890 device_xname(sc->sc_dev), using64); 891 } 892 893 /* 894 * The T64ADDR bit is loaded by the chip from the EEPROM and 895 * is read-only. 896 */ 897 if (reg & CFG_T64ADDR) 898 sc->sc_cfg |= CFG_T64ADDR; 899 900 /* 901 * We can use 64-bit DMA addressing regardless of what 902 * sort of slot we're in. 903 */ 904 if (pci_dma64_available(pa)) { 905 sc->sc_dmat = pa->pa_dmat64; 906 sc->sc_cfg |= CFG_M64ADDR; 907 sc->sc_dma64 = true; 908 } 909 910 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 911 const char *sep = ""; 912 printf("%s: using ", device_xname(sc->sc_dev)); 913 if (reg & CFG_EXT_125) { 914 sc->sc_cfg |= CFG_EXT_125; 915 printf("%sexternal 125MHz clock", sep); 916 sep = ", "; 917 } 918 if (reg & CFG_TBI_EN) { 919 sc->sc_cfg |= CFG_TBI_EN; 920 printf("%sten-bit interface", sep); 921 sep = ", "; 922 } 923 printf("\n"); 924 } 925 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 926 (reg & CFG_MRM_DIS) != 0) 927 sc->sc_cfg |= CFG_MRM_DIS; 928 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 929 (reg & CFG_MWI_DIS) != 0) 930 sc->sc_cfg |= CFG_MWI_DIS; 931 932 /* 933 * Use the extended descriptor format on the DP83820. This 934 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 935 * checksumming. 936 */ 937 sc->sc_cfg |= CFG_EXTSTS_EN; 938 } 939 940 static int 941 sipcom_detach(device_t self, int flags) 942 { 943 int s; 944 945 s = splnet(); 946 sipcom_do_detach(self, SIP_ATTACH_FIN); 947 splx(s); 948 949 return 0; 950 } 951 952 static void 953 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 954 { 955 int i; 956 struct sip_softc *sc = device_private(self); 957 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 958 959 /* 960 * Free any resources we've allocated during attach. 961 * Do this in reverse order and fall through. 962 */ 963 switch (stage) { 964 case SIP_ATTACH_FIN: 965 sipcom_stop(ifp, 1); 966 pmf_device_deregister(self); 967 #ifdef SIP_EVENT_COUNTERS 968 /* 969 * Attach event counters. 970 */ 971 evcnt_detach(&sc->sc_ev_txforceintr); 972 evcnt_detach(&sc->sc_ev_txdstall); 973 evcnt_detach(&sc->sc_ev_hiberr); 974 evcnt_detach(&sc->sc_ev_rxintr); 975 evcnt_detach(&sc->sc_ev_txiintr); 976 evcnt_detach(&sc->sc_ev_txdintr); 977 if (!sc->sc_gigabit) { 978 evcnt_detach(&sc->sc_ev_rxpause); 979 } else { 980 evcnt_detach(&sc->sc_ev_txudpsum); 981 evcnt_detach(&sc->sc_ev_txtcpsum); 982 evcnt_detach(&sc->sc_ev_txipsum); 983 evcnt_detach(&sc->sc_ev_rxudpsum); 984 evcnt_detach(&sc->sc_ev_rxtcpsum); 985 evcnt_detach(&sc->sc_ev_rxipsum); 986 evcnt_detach(&sc->sc_ev_txpause); 987 evcnt_detach(&sc->sc_ev_rxpause); 988 } 989 #endif /* SIP_EVENT_COUNTERS */ 990 991 rnd_detach_source(&sc->rnd_source); 992 993 ether_ifdetach(ifp); 994 if_detach(ifp); 995 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 996 ifmedia_fini(&sc->sc_mii.mii_media); 997 998 /*FALLTHROUGH*/ 999 case SIP_ATTACH_CREATE_RXMAP: 1000 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1001 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1002 bus_dmamap_destroy(sc->sc_dmat, 1003 sc->sc_rxsoft[i].rxs_dmamap); 1004 } 1005 /*FALLTHROUGH*/ 1006 case SIP_ATTACH_CREATE_TXMAP: 1007 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1008 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1009 bus_dmamap_destroy(sc->sc_dmat, 1010 sc->sc_txsoft[i].txs_dmamap); 1011 } 1012 /*FALLTHROUGH*/ 1013 case SIP_ATTACH_LOAD_MAP: 1014 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1015 /*FALLTHROUGH*/ 1016 case SIP_ATTACH_CREATE_MAP: 1017 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1018 /*FALLTHROUGH*/ 1019 case SIP_ATTACH_MAP_MEM: 1020 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1021 sizeof(struct sip_control_data)); 1022 /*FALLTHROUGH*/ 1023 case SIP_ATTACH_ALLOC_MEM: 1024 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 1025 /* FALLTHROUGH*/ 1026 case SIP_ATTACH_INTR: 1027 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1028 /* FALLTHROUGH*/ 1029 case SIP_ATTACH_MAP: 1030 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1031 break; 1032 default: 1033 break; 1034 } 1035 return; 1036 } 1037 1038 static bool 1039 sipcom_resume(device_t self, const pmf_qual_t *qual) 1040 { 1041 struct sip_softc *sc = device_private(self); 1042 1043 return sipcom_reset(sc); 1044 } 1045 1046 static bool 1047 sipcom_suspend(device_t self, const pmf_qual_t *qual) 1048 { 1049 struct sip_softc *sc = device_private(self); 1050 1051 sipcom_rxdrain(sc); 1052 return true; 1053 } 1054 1055 static void 1056 sipcom_attach(device_t parent, device_t self, void *aux) 1057 { 1058 struct sip_softc *sc = device_private(self); 1059 struct pci_attach_args *pa = aux; 1060 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1061 struct mii_data * const mii = &sc->sc_mii; 1062 pci_chipset_tag_t pc = pa->pa_pc; 1063 pci_intr_handle_t ih; 1064 const char *intrstr = NULL; 1065 bus_space_tag_t iot, memt; 1066 bus_space_handle_t ioh, memh; 1067 bus_size_t iosz, memsz; 1068 int ioh_valid, memh_valid; 1069 int i, rseg, error; 1070 const struct sip_product *sip; 1071 uint8_t enaddr[ETHER_ADDR_LEN]; 1072 pcireg_t csr; 1073 pcireg_t memtype; 1074 bus_size_t tx_dmamap_size; 1075 int ntxsegs_alloc; 1076 cfdata_t cf = device_cfdata(self); 1077 char intrbuf[PCI_INTRSTR_LEN]; 1078 1079 callout_init(&sc->sc_tick_ch, 0); 1080 callout_setfunc(&sc->sc_tick_ch, sipcom_tick, sc); 1081 1082 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1083 if (sip == NULL) { 1084 aprint_error("\n"); 1085 panic("%s: impossible", __func__); 1086 } 1087 sc->sc_dev = self; 1088 sc->sc_gigabit = sip->sip_gigabit; 1089 sc->sc_dma64 = false; 1090 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1091 sc->sc_pc = pc; 1092 1093 if (sc->sc_gigabit) { 1094 if (sc->sc_dma64) { 1095 sc->sc_bufptr_idx = GSIP64_DESC_BUFPTR_LO; 1096 sc->sc_cmdsts_idx = GSIP64_DESC_CMDSTS; 1097 sc->sc_extsts_idx = GSIP64_DESC_EXTSTS; 1098 } else { 1099 sc->sc_bufptr_idx = GSIP_DESC_BUFPTR; 1100 sc->sc_cmdsts_idx = GSIP_DESC_CMDSTS; 1101 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1102 } 1103 sc->sc_rxintr = gsip_rxintr; 1104 sc->sc_parm = &gsip_parm; 1105 } else { 1106 sc->sc_rxintr = sip_rxintr; 1107 sc->sc_parm = &sip_parm; 1108 sc->sc_bufptr_idx = SIP_DESC_BUFPTR; 1109 sc->sc_cmdsts_idx = SIP_DESC_CMDSTS; 1110 /* 1111 * EXTSTS doesn't really exist on non-GigE parts, 1112 * but we initialize the index for simplicity later. 1113 */ 1114 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1115 } 1116 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1117 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1118 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1119 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1120 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1121 1122 sc->sc_rev = PCI_REVISION(pa->pa_class); 1123 1124 aprint_naive("\n"); 1125 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1126 1127 sc->sc_model = sip; 1128 1129 /* 1130 * XXX Work-around broken PXE firmware on some boards. 1131 * 1132 * The DP83815 shares an address decoder with the MEM BAR 1133 * and the ROM BAR. Make sure the ROM BAR is disabled, 1134 * so that memory mapped access works. 1135 */ 1136 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1137 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1138 ~PCI_MAPREG_ROM_ENABLE); 1139 1140 /* 1141 * Map the device. 1142 */ 1143 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1144 PCI_MAPREG_TYPE_IO, 0, 1145 &iot, &ioh, NULL, &iosz) == 0); 1146 if (sc->sc_gigabit) { 1147 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1148 switch (memtype) { 1149 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1150 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1151 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1152 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1153 break; 1154 default: 1155 memh_valid = 0; 1156 } 1157 } else { 1158 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1159 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1160 &memt, &memh, NULL, &memsz) == 0); 1161 } 1162 1163 if (memh_valid) { 1164 sc->sc_st = memt; 1165 sc->sc_sh = memh; 1166 sc->sc_sz = memsz; 1167 } else if (ioh_valid) { 1168 sc->sc_st = iot; 1169 sc->sc_sh = ioh; 1170 sc->sc_sz = iosz; 1171 } else { 1172 aprint_error_dev(self, "unable to map device registers\n"); 1173 return; 1174 } 1175 1176 sc->sc_dmat = pa->pa_dmat; 1177 1178 /* 1179 * Make sure bus mastering is enabled. Also make sure 1180 * Write/Invalidate is enabled if we're allowed to use it. 1181 */ 1182 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1183 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1184 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1185 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1186 csr | PCI_COMMAND_MASTER_ENABLE); 1187 1188 /* Power up chip */ 1189 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1190 if (error != 0 && error != EOPNOTSUPP) { 1191 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1192 return; 1193 } 1194 1195 /* 1196 * Map and establish our interrupt. 1197 */ 1198 if (pci_intr_map(pa, &ih)) { 1199 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1200 return; 1201 } 1202 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1203 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1204 device_xname(self)); 1205 if (sc->sc_ih == NULL) { 1206 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1207 if (intrstr != NULL) 1208 aprint_error(" at %s", intrstr); 1209 aprint_error("\n"); 1210 sipcom_do_detach(self, SIP_ATTACH_MAP); 1211 return; 1212 } 1213 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1214 1215 SIMPLEQ_INIT(&sc->sc_txfreeq); 1216 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1217 1218 /* 1219 * Allocate the control data structures, and create and load the 1220 * DMA map for it. 1221 */ 1222 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1223 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1224 &rseg, 0)) != 0) { 1225 aprint_error_dev(sc->sc_dev, 1226 "unable to allocate control data, error = %d\n", error); 1227 sipcom_do_detach(self, SIP_ATTACH_INTR); 1228 return; 1229 } 1230 1231 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1232 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1233 BUS_DMA_COHERENT)) != 0) { 1234 aprint_error_dev(sc->sc_dev, 1235 "unable to map control data, error = %d\n", error); 1236 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1237 } 1238 1239 if ((error = bus_dmamap_create(sc->sc_dmat, 1240 sizeof(struct sip_control_data), 1, 1241 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1242 aprint_error_dev(self, "unable to create control data DMA map" 1243 ", error = %d\n", error); 1244 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1245 } 1246 1247 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1248 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1249 0)) != 0) { 1250 aprint_error_dev(self, "unable to load control data DMA map" 1251 ", error = %d\n", error); 1252 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1253 } 1254 1255 /* 1256 * Create the transmit buffer DMA maps. 1257 */ 1258 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1259 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1260 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1261 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1262 aprint_error_dev(self, "unable to create tx DMA map %d" 1263 ", error = %d\n", i, error); 1264 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1265 } 1266 } 1267 1268 /* 1269 * Create the receive buffer DMA maps. 1270 */ 1271 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1272 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1273 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1274 aprint_error_dev(self, "unable to create rx DMA map %d" 1275 ", error = %d\n", i, error); 1276 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1277 } 1278 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1279 } 1280 1281 /* 1282 * Reset the chip to a known state. 1283 */ 1284 sipcom_reset(sc); 1285 1286 /* 1287 * Read the Ethernet address from the EEPROM. This might 1288 * also fetch other stuff from the EEPROM and stash it 1289 * in the softc. 1290 */ 1291 sc->sc_cfg = 0; 1292 if (!sc->sc_gigabit) { 1293 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1294 SIP_SIS900_REV(sc, SIS_REV_900B)) 1295 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1296 1297 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1298 SIP_SIS900_REV(sc, SIS_REV_960) || 1299 SIP_SIS900_REV(sc, SIS_REV_900B)) 1300 sc->sc_cfg |= 1301 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1302 CFG_EDBMASTEN); 1303 } 1304 1305 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1306 1307 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1308 1309 /* 1310 * Initialize the configuration register: aggressive PCI 1311 * bus request algorithm, default backoff, default OW timer, 1312 * default parity error detection. 1313 * 1314 * NOTE: "Big endian mode" is useless on the SiS900 and 1315 * friends -- it affects packet data, not descriptors. 1316 */ 1317 if (sc->sc_gigabit) 1318 sipcom_dp83820_attach(sc, pa); 1319 1320 /* 1321 * Initialize our media structures and probe the MII. 1322 */ 1323 mii->mii_ifp = ifp; 1324 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1325 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1326 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1327 sc->sc_ethercom.ec_mii = mii; 1328 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1329 sipcom_mediastatus); 1330 1331 /* 1332 * XXX We cannot handle flow control on the DP83815. 1333 */ 1334 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1335 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1336 MII_OFFSET_ANY, 0); 1337 else 1338 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1339 MII_OFFSET_ANY, MIIF_DOPAUSE); 1340 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1341 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1342 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1343 } else 1344 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1345 1346 ifp = &sc->sc_ethercom.ec_if; 1347 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1348 ifp->if_softc = sc; 1349 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1350 sc->sc_if_flags = ifp->if_flags; 1351 ifp->if_ioctl = sipcom_ioctl; 1352 ifp->if_start = sipcom_start; 1353 ifp->if_watchdog = sipcom_watchdog; 1354 ifp->if_init = sipcom_init; 1355 ifp->if_stop = sipcom_stop; 1356 IFQ_SET_READY(&ifp->if_snd); 1357 1358 /* 1359 * We can support 802.1Q VLAN-sized frames. 1360 */ 1361 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1362 1363 if (sc->sc_gigabit) { 1364 /* 1365 * And the DP83820 can do VLAN tagging in hardware, and 1366 * support the jumbo Ethernet MTU. 1367 */ 1368 sc->sc_ethercom.ec_capabilities |= 1369 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1370 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1371 1372 /* 1373 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1374 * in hardware. 1375 */ 1376 ifp->if_capabilities |= 1377 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1378 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1379 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1380 } 1381 1382 /* 1383 * Attach the interface. 1384 */ 1385 if_attach(ifp); 1386 if_deferred_start_init(ifp, NULL); 1387 ether_ifattach(ifp, enaddr); 1388 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1389 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1390 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1391 sc->sc_prev.if_capenable = ifp->if_capenable; 1392 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1393 RND_TYPE_NET, RND_FLAG_DEFAULT); 1394 1395 /* 1396 * The number of bytes that must be available in 1397 * the Tx FIFO before the bus master can DMA more 1398 * data into the FIFO. 1399 */ 1400 sc->sc_tx_fill_thresh = 64 / 32; 1401 1402 /* 1403 * Start at a drain threshold of 512 bytes. We will 1404 * increase it if a DMA underrun occurs. 1405 * 1406 * XXX The minimum value of this variable should be 1407 * tuned. We may be able to improve performance 1408 * by starting with a lower value. That, however, 1409 * may trash the first few outgoing packets if the 1410 * PCI bus is saturated. 1411 */ 1412 if (sc->sc_gigabit) 1413 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1414 else 1415 sc->sc_tx_drain_thresh = 1504 / 32; 1416 1417 /* 1418 * Initialize the Rx FIFO drain threshold. 1419 * 1420 * This is in units of 8 bytes. 1421 * 1422 * We should never set this value lower than 2; 14 bytes are 1423 * required to filter the packet. 1424 */ 1425 sc->sc_rx_drain_thresh = 128 / 8; 1426 1427 #ifdef SIP_EVENT_COUNTERS 1428 /* 1429 * Attach event counters. 1430 */ 1431 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1432 NULL, device_xname(sc->sc_dev), "txdstall"); 1433 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1434 NULL, device_xname(sc->sc_dev), "txforceintr"); 1435 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1436 NULL, device_xname(sc->sc_dev), "txdintr"); 1437 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1438 NULL, device_xname(sc->sc_dev), "txiintr"); 1439 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1440 NULL, device_xname(sc->sc_dev), "rxintr"); 1441 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1442 NULL, device_xname(sc->sc_dev), "hiberr"); 1443 if (!sc->sc_gigabit) { 1444 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1445 NULL, device_xname(sc->sc_dev), "rxpause"); 1446 } else { 1447 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1448 NULL, device_xname(sc->sc_dev), "rxpause"); 1449 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1450 NULL, device_xname(sc->sc_dev), "txpause"); 1451 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1452 NULL, device_xname(sc->sc_dev), "rxipsum"); 1453 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1454 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1455 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1456 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1457 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1458 NULL, device_xname(sc->sc_dev), "txipsum"); 1459 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1460 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1461 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1462 NULL, device_xname(sc->sc_dev), "txudpsum"); 1463 } 1464 #endif /* SIP_EVENT_COUNTERS */ 1465 1466 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1467 pmf_class_network_register(self, ifp); 1468 else 1469 aprint_error_dev(self, "couldn't establish power handler\n"); 1470 } 1471 1472 static inline void 1473 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1474 uint64_t capenable) 1475 { 1476 uint32_t extsts = 0; 1477 #ifdef DEBUG 1478 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1479 #endif 1480 /* 1481 * If VLANs are enabled and the packet has a VLAN tag, set 1482 * up the descriptor to encapsulate the packet for us. 1483 * 1484 * This apparently has to be on the last descriptor of 1485 * the packet. 1486 */ 1487 1488 /* 1489 * Byte swapping is tricky. We need to provide the tag 1490 * in a network byte order. On a big-endian machine, 1491 * the byteorder is correct, but we need to swap it 1492 * anyway, because this will be undone by the outside 1493 * htole32(). That's why there must be an 1494 * unconditional swap instead of htons() inside. 1495 */ 1496 if (vlan_has_tag(m0)) { 1497 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |= 1498 htole32(EXTSTS_VPKT | 1499 (bswap16(vlan_get_tag(m0)) & 1500 EXTSTS_VTCI)); 1501 } 1502 1503 /* 1504 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1505 * checksumming, set up the descriptor to do this work 1506 * for us. 1507 * 1508 * This apparently has to be on the first descriptor of 1509 * the packet. 1510 * 1511 * Byte-swap constants so the compiler can optimize. 1512 */ 1513 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1514 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1515 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1516 extsts |= htole32(EXTSTS_IPPKT); 1517 } 1518 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1519 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1520 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1521 extsts |= htole32(EXTSTS_TCPPKT); 1522 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1523 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1524 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1525 extsts |= htole32(EXTSTS_UDPPKT); 1526 } 1527 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts; 1528 } 1529 1530 /* 1531 * sip_start: [ifnet interface function] 1532 * 1533 * Start packet transmission on the interface. 1534 */ 1535 static void 1536 sipcom_start(struct ifnet *ifp) 1537 { 1538 struct sip_softc *sc = ifp->if_softc; 1539 struct mbuf *m0; 1540 struct mbuf *m; 1541 struct sip_txsoft *txs; 1542 bus_dmamap_t dmamap; 1543 int error, nexttx, lasttx, seg; 1544 int ofree = sc->sc_txfree; 1545 uint32_t cmdsts; 1546 #if 0 1547 int firsttx = sc->sc_txnext; 1548 #endif 1549 1550 /* 1551 * If we've been told to pause, don't transmit any more packets. 1552 */ 1553 if (!sc->sc_gigabit && sc->sc_paused) 1554 return; 1555 1556 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1557 return; 1558 1559 /* 1560 * Loop through the send queue, setting up transmit descriptors 1561 * until we drain the queue, or use up all available transmit 1562 * descriptors. 1563 */ 1564 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL) { 1565 /* 1566 * Grab a packet off the queue. 1567 */ 1568 IFQ_POLL(&ifp->if_snd, m0); 1569 if (m0 == NULL) 1570 break; 1571 m = NULL; 1572 1573 dmamap = txs->txs_dmamap; 1574 1575 /* 1576 * Load the DMA map. If this fails, the packet either 1577 * didn't fit in the allotted number of segments, or we 1578 * were short on resources. 1579 */ 1580 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1581 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1582 /* In the non-gigabit case, we'll copy and try again. */ 1583 if (error != 0 && !sc->sc_gigabit) { 1584 MGETHDR(m, M_DONTWAIT, MT_DATA); 1585 if (m == NULL) { 1586 printf("%s: unable to allocate Tx mbuf\n", 1587 device_xname(sc->sc_dev)); 1588 break; 1589 } 1590 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1591 if (m0->m_pkthdr.len > MHLEN) { 1592 MCLGET(m, M_DONTWAIT); 1593 if ((m->m_flags & M_EXT) == 0) { 1594 printf("%s: unable to allocate Tx " 1595 "cluster\n", 1596 device_xname(sc->sc_dev)); 1597 m_freem(m); 1598 break; 1599 } 1600 } 1601 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1602 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1603 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1604 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1605 if (error) { 1606 printf("%s: unable to load Tx buffer, error = " 1607 "%d\n", device_xname(sc->sc_dev), error); 1608 break; 1609 } 1610 } else if (error == EFBIG) { 1611 /* 1612 * For the too-many-segments case, we simply 1613 * report an error and drop the packet, 1614 * since we can't sanely copy a jumbo packet 1615 * to a single buffer. 1616 */ 1617 printf("%s: Tx packet consumes too many DMA segments, " 1618 "dropping...\n", device_xname(sc->sc_dev)); 1619 IFQ_DEQUEUE(&ifp->if_snd, m0); 1620 m_freem(m0); 1621 continue; 1622 } else if (error != 0) { 1623 /* 1624 * Short on resources, just stop for now. 1625 */ 1626 break; 1627 } 1628 1629 /* 1630 * Ensure we have enough descriptors free to describe 1631 * the packet. Note, we always reserve one descriptor 1632 * at the end of the ring as a termination point, to 1633 * prevent wrap-around. 1634 */ 1635 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1636 /* 1637 * Not enough free descriptors to transmit this 1638 * packet. 1639 */ 1640 bus_dmamap_unload(sc->sc_dmat, dmamap); 1641 m_freem(m); 1642 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1643 break; 1644 } 1645 1646 IFQ_DEQUEUE(&ifp->if_snd, m0); 1647 if (m != NULL) { 1648 m_freem(m0); 1649 m0 = m; 1650 } 1651 1652 /* 1653 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1654 */ 1655 1656 /* Sync the DMA map. */ 1657 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1658 BUS_DMASYNC_PREWRITE); 1659 1660 /* 1661 * Initialize the transmit descriptors. 1662 */ 1663 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1664 seg < dmamap->dm_nsegs; 1665 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1666 /* 1667 * If this is the first descriptor we're 1668 * enqueueing, don't set the OWN bit just 1669 * yet. That could cause a race condition. 1670 * We'll do it below. 1671 */ 1672 1673 cmdsts = dmamap->dm_segs[seg].ds_len; 1674 if (nexttx != sc->sc_txnext) 1675 cmdsts |= CMDSTS_OWN; 1676 if (seg < dmamap->dm_nsegs - 1) 1677 cmdsts |= CMDSTS_MORE; 1678 sip_init_txdesc(sc, nexttx, 1679 dmamap->dm_segs[seg].ds_addr, cmdsts); 1680 lasttx = nexttx; 1681 } 1682 1683 /* 1684 * If we're in the interrupt delay window, delay the 1685 * interrupt. 1686 */ 1687 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1688 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1689 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |= 1690 htole32(CMDSTS_INTR); 1691 sc->sc_txwin = 0; 1692 } 1693 1694 if (sc->sc_gigabit) 1695 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1696 1697 /* Sync the descriptors we're using. */ 1698 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1700 1701 /* 1702 * The entire packet is set up. Give the first descriptor 1703 * to the chip now. 1704 */ 1705 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |= 1706 htole32(CMDSTS_OWN); 1707 sip_cdtxsync(sc, sc->sc_txnext, 1, 1708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1709 1710 /* 1711 * Store a pointer to the packet so we can free it later, 1712 * and remember what txdirty will be once the packet is 1713 * done. 1714 */ 1715 txs->txs_mbuf = m0; 1716 txs->txs_firstdesc = sc->sc_txnext; 1717 txs->txs_lastdesc = lasttx; 1718 1719 /* Advance the tx pointer. */ 1720 sc->sc_txfree -= dmamap->dm_nsegs; 1721 sc->sc_txnext = nexttx; 1722 1723 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1724 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1725 1726 /* Pass the packet to any BPF listeners. */ 1727 bpf_mtap(ifp, m0, BPF_D_OUT); 1728 } 1729 1730 if (sc->sc_txfree != ofree) { 1731 /* 1732 * Start the transmit process. Note, the manual says 1733 * that if there are no pending transmissions in the 1734 * chip's internal queue (indicated by TXE being clear), 1735 * then the driver software must set the TXDP to the 1736 * first descriptor to be transmitted. However, if we 1737 * do this, it causes serious performance degradation on 1738 * the DP83820 under load, not setting TXDP doesn't seem 1739 * to adversely affect the SiS 900 or DP83815. 1740 * 1741 * Well, I guess it wouldn't be the first time a manual 1742 * has lied -- and they could be speaking of the NULL- 1743 * terminated descriptor list case, rather than OWN- 1744 * terminated rings. 1745 */ 1746 #if 0 1747 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1748 CR_TXE) == 0) { 1749 sip_set_txdp(sc, SIP_CDTXADDR(sc, firsttx)); 1750 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1751 } 1752 #else 1753 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1754 #endif 1755 1756 /* Set a watchdog timer in case the chip flakes out. */ 1757 /* Gigabit autonegotiation takes 5 seconds. */ 1758 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1759 } 1760 } 1761 1762 /* 1763 * sip_watchdog: [ifnet interface function] 1764 * 1765 * Watchdog timer handler. 1766 */ 1767 static void 1768 sipcom_watchdog(struct ifnet *ifp) 1769 { 1770 struct sip_softc *sc = ifp->if_softc; 1771 1772 /* 1773 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1774 * If we get a timeout, try and sweep up transmit descriptors. 1775 * If we manage to sweep them all up, ignore the lack of 1776 * interrupt. 1777 */ 1778 sipcom_txintr(sc); 1779 1780 if (sc->sc_txfree != sc->sc_ntxdesc) { 1781 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1782 if_statinc(ifp, if_oerrors); 1783 1784 /* Reset the interface. */ 1785 (void) sipcom_init(ifp); 1786 } else if (ifp->if_flags & IFF_DEBUG) 1787 printf("%s: recovered from device timeout\n", 1788 device_xname(sc->sc_dev)); 1789 1790 /* Try to get more packets going. */ 1791 sipcom_start(ifp); 1792 } 1793 1794 /* If the interface is up and running, only modify the receive 1795 * filter when setting promiscuous or debug mode. Otherwise fall 1796 * through to ether_ioctl, which will reset the chip. 1797 */ 1798 static int 1799 sip_ifflags_cb(struct ethercom *ec) 1800 { 1801 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1802 == (sc)->sc_ethercom.ec_capenable) \ 1803 && ((sc)->sc_prev.is_vlan == \ 1804 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1805 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1806 struct ifnet *ifp = &ec->ec_if; 1807 struct sip_softc *sc = ifp->if_softc; 1808 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1809 1810 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1811 !COMPARE_IC(sc, ifp)) 1812 return ENETRESET; 1813 /* Set up the receive filter. */ 1814 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1815 return 0; 1816 } 1817 1818 /* 1819 * sip_ioctl: [ifnet interface function] 1820 * 1821 * Handle control requests from the operator. 1822 */ 1823 static int 1824 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1825 { 1826 struct sip_softc *sc = ifp->if_softc; 1827 struct ifreq *ifr = (struct ifreq *)data; 1828 int s, error; 1829 1830 s = splnet(); 1831 1832 switch (cmd) { 1833 case SIOCSIFMEDIA: 1834 /* Flow control requires full-duplex mode. */ 1835 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1836 (ifr->ifr_media & IFM_FDX) == 0) 1837 ifr->ifr_media &= ~IFM_ETH_FMASK; 1838 1839 /* XXX */ 1840 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1841 ifr->ifr_media &= ~IFM_ETH_FMASK; 1842 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1843 if (sc->sc_gigabit && 1844 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1845 /* We can do both TXPAUSE and RXPAUSE. */ 1846 ifr->ifr_media |= 1847 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1848 } else if (ifr->ifr_media & IFM_FLOW) { 1849 /* 1850 * Both TXPAUSE and RXPAUSE must be set. 1851 * (SiS900 and DP83815 don't have PAUSE_ASYM 1852 * feature.) 1853 * 1854 * XXX Can SiS900 and DP83815 send PAUSE? 1855 */ 1856 ifr->ifr_media |= 1857 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1858 } 1859 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1860 } 1861 /*FALLTHROUGH*/ 1862 default: 1863 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1864 break; 1865 1866 error = 0; 1867 1868 if (cmd == SIOCSIFCAP) 1869 error = if_init(ifp); 1870 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1871 ; 1872 else if (ifp->if_flags & IFF_RUNNING) { 1873 /* 1874 * Multicast list has changed; set the hardware filter 1875 * accordingly. 1876 */ 1877 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1878 } 1879 break; 1880 } 1881 1882 /* Try to get more packets going. */ 1883 sipcom_start(ifp); 1884 1885 sc->sc_if_flags = ifp->if_flags; 1886 splx(s); 1887 return error; 1888 } 1889 1890 /* 1891 * sip_intr: 1892 * 1893 * Interrupt service routine. 1894 */ 1895 static int 1896 sipcom_intr(void *arg) 1897 { 1898 struct sip_softc *sc = arg; 1899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1900 uint32_t isr; 1901 int handled = 0; 1902 1903 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1904 return 0; 1905 1906 /* Disable interrupts. */ 1907 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1908 1909 for (;;) { 1910 /* Reading clears interrupt. */ 1911 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1912 if ((isr & sc->sc_imr) == 0) 1913 break; 1914 1915 rnd_add_uint32(&sc->rnd_source, isr); 1916 1917 handled = 1; 1918 1919 if ((ifp->if_flags & IFF_RUNNING) == 0) 1920 break; 1921 1922 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1923 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1924 1925 /* Grab any new packets. */ 1926 (*sc->sc_rxintr)(sc); 1927 1928 if (isr & ISR_RXORN) { 1929 printf("%s: receive FIFO overrun\n", 1930 device_xname(sc->sc_dev)); 1931 1932 /* XXX adjust rx_drain_thresh? */ 1933 } 1934 1935 if (isr & ISR_RXIDLE) { 1936 printf("%s: receive ring overrun\n", 1937 device_xname(sc->sc_dev)); 1938 1939 /* Get the receive process going again. */ 1940 sip_set_rxdp(sc, 1941 SIP_CDRXADDR(sc, sc->sc_rxptr)); 1942 bus_space_write_4(sc->sc_st, sc->sc_sh, 1943 SIP_CR, CR_RXE); 1944 } 1945 } 1946 1947 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1948 #ifdef SIP_EVENT_COUNTERS 1949 if (isr & ISR_TXDESC) 1950 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1951 else if (isr & ISR_TXIDLE) 1952 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1953 #endif 1954 1955 /* Sweep up transmit descriptors. */ 1956 sipcom_txintr(sc); 1957 1958 if (isr & ISR_TXURN) { 1959 uint32_t thresh; 1960 int txfifo_size = (sc->sc_gigabit) 1961 ? DP83820_SIP_TXFIFO_SIZE 1962 : OTHER_SIP_TXFIFO_SIZE; 1963 1964 printf("%s: transmit FIFO underrun", 1965 device_xname(sc->sc_dev)); 1966 thresh = sc->sc_tx_drain_thresh + 1; 1967 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1968 && (thresh * 32) <= (txfifo_size - 1969 (sc->sc_tx_fill_thresh * 32))) { 1970 printf("; increasing Tx drain " 1971 "threshold to %u bytes\n", 1972 thresh * 32); 1973 sc->sc_tx_drain_thresh = thresh; 1974 (void) sipcom_init(ifp); 1975 } else { 1976 (void) sipcom_init(ifp); 1977 printf("\n"); 1978 } 1979 } 1980 } 1981 1982 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1983 if (isr & ISR_PAUSE_ST) { 1984 sc->sc_paused = 1; 1985 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1986 } 1987 if (isr & ISR_PAUSE_END) { 1988 sc->sc_paused = 0; 1989 } 1990 } 1991 1992 if (isr & ISR_HIBERR) { 1993 int want_init = 0; 1994 1995 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1996 1997 #define PRINTERR(bit, str) \ 1998 do { \ 1999 if ((isr & (bit)) != 0) { \ 2000 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 2001 printf("%s: %s\n", \ 2002 device_xname(sc->sc_dev), str); \ 2003 want_init = 1; \ 2004 } \ 2005 } while (/*CONSTCOND*/0) 2006 2007 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 2008 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 2009 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 2010 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 2011 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 2012 /* 2013 * Ignore: 2014 * Tx reset complete 2015 * Rx reset complete 2016 */ 2017 if (want_init) 2018 (void) sipcom_init(ifp); 2019 #undef PRINTERR 2020 } 2021 } 2022 2023 /* Re-enable interrupts. */ 2024 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 2025 2026 /* Try to get more packets going. */ 2027 if_schedule_deferred_start(ifp); 2028 2029 return handled; 2030 } 2031 2032 /* 2033 * sip_txintr: 2034 * 2035 * Helper; handle transmit interrupts. 2036 */ 2037 static void 2038 sipcom_txintr(struct sip_softc *sc) 2039 { 2040 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2041 struct sip_txsoft *txs; 2042 uint32_t cmdsts; 2043 2044 /* 2045 * Go through our Tx list and free mbufs for those 2046 * frames which have been transmitted. 2047 */ 2048 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2049 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2050 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2051 2052 cmdsts = le32toh(sc->sc_txdescs[ 2053 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2054 if (cmdsts & CMDSTS_OWN) 2055 break; 2056 2057 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2058 2059 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2060 2061 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2062 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2063 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2064 m_freem(txs->txs_mbuf); 2065 txs->txs_mbuf = NULL; 2066 2067 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2068 2069 /* Check for errors and collisions. */ 2070 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2071 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2072 CMDSTS_Tx_EC)) { 2073 if_statinc_ref(ifp, nsr, if_oerrors); 2074 if (cmdsts & CMDSTS_Tx_EC) 2075 if_statadd_ref(ifp, nsr, if_collisions, 16); 2076 if (ifp->if_flags & IFF_DEBUG) { 2077 if (cmdsts & CMDSTS_Tx_ED) 2078 printf("%s: excessive deferral\n", 2079 device_xname(sc->sc_dev)); 2080 if (cmdsts & CMDSTS_Tx_EC) 2081 printf("%s: excessive collisions\n", 2082 device_xname(sc->sc_dev)); 2083 } 2084 } else { 2085 /* Packet was transmitted successfully. */ 2086 if_statinc_ref(ifp, nsr, if_opackets); 2087 if (CMDSTS_COLLISIONS(cmdsts)) 2088 if_statadd_ref(ifp, nsr, if_collisions, 2089 CMDSTS_COLLISIONS(cmdsts)); 2090 } 2091 IF_STAT_PUTREF(ifp); 2092 } 2093 2094 /* 2095 * If there are no more pending transmissions, cancel the watchdog 2096 * timer. 2097 */ 2098 if (txs == NULL) { 2099 ifp->if_timer = 0; 2100 sc->sc_txwin = 0; 2101 } 2102 } 2103 2104 /* 2105 * gsip_rxintr: 2106 * 2107 * Helper; handle receive interrupts on gigabit parts. 2108 */ 2109 static void 2110 gsip_rxintr(struct sip_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2113 struct sip_rxsoft *rxs; 2114 struct mbuf *m; 2115 uint32_t cmdsts, extsts; 2116 int i, len; 2117 2118 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2119 rxs = &sc->sc_rxsoft[i]; 2120 2121 sip_cdrxsync(sc, i, 2122 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2123 2124 cmdsts = 2125 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2126 2127 /* 2128 * NOTE: OWN is set if owned by _consumer_. We're the 2129 * consumer of the receive ring, so if the bit is clear, 2130 * we have processed all of the packets. 2131 */ 2132 if ((cmdsts & CMDSTS_OWN) == 0) { 2133 /* 2134 * We have processed all of the receive buffers. 2135 */ 2136 break; 2137 } 2138 2139 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD); 2140 2141 extsts = 2142 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_extsts_idx]); 2143 len = CMDSTS_SIZE(sc, cmdsts); 2144 2145 if (__predict_false(sc->sc_rxdiscard)) { 2146 sip_init_rxdesc(sc, i); 2147 if ((cmdsts & CMDSTS_MORE) == 0) { 2148 /* Reset our state. */ 2149 sc->sc_rxdiscard = 0; 2150 } 2151 continue; 2152 } 2153 2154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2156 2157 m = rxs->rxs_mbuf; 2158 2159 /* 2160 * Add a new receive buffer to the ring. 2161 */ 2162 if (sipcom_add_rxbuf(sc, i) != 0) { 2163 /* 2164 * Failed, throw away what we've done so 2165 * far, and discard the rest of the packet. 2166 */ 2167 if_statinc(ifp, if_ierrors); 2168 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2169 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2170 sip_init_rxdesc(sc, i); 2171 if (cmdsts & CMDSTS_MORE) 2172 sc->sc_rxdiscard = 1; 2173 m_freem(sc->sc_rxhead); 2174 sip_rxchain_reset(sc); 2175 continue; 2176 } 2177 2178 sip_rxchain_link(sc, m); 2179 2180 m->m_len = len; 2181 2182 /* 2183 * If this is not the end of the packet, keep 2184 * looking. 2185 */ 2186 if (cmdsts & CMDSTS_MORE) { 2187 sc->sc_rxlen += len; 2188 continue; 2189 } 2190 2191 /* 2192 * Okay, we have the entire packet now. The chip includes 2193 * the FCS, so we need to trim it. 2194 */ 2195 m->m_len -= ETHER_CRC_LEN; 2196 2197 *sc->sc_rxtailp = NULL; 2198 len = m->m_len + sc->sc_rxlen; 2199 m = sc->sc_rxhead; 2200 2201 sip_rxchain_reset(sc); 2202 2203 /* If an error occurred, update stats and drop the packet. */ 2204 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_LONG | CMDSTS_Rx_RUNT | 2205 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2206 if_statinc(ifp, if_ierrors); 2207 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2208 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2209 /* Receive overrun handled elsewhere. */ 2210 printf("%s: receive descriptor error\n", 2211 device_xname(sc->sc_dev)); 2212 } 2213 #define PRINTERR(bit, str) \ 2214 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2215 (cmdsts & (bit)) != 0) \ 2216 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2217 PRINTERR(CMDSTS_Rx_LONG, "Too long packet"); 2218 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2219 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2220 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2221 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2222 #undef PRINTERR 2223 m_freem(m); 2224 continue; 2225 } 2226 2227 /* 2228 * If the packet is small enough to fit in a 2229 * single header mbuf, allocate one and copy 2230 * the data into it. This greatly reduces 2231 * memory consumption when we receive lots 2232 * of small packets. 2233 */ 2234 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2235 struct mbuf *nm; 2236 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2237 if (nm == NULL) { 2238 if_statinc(ifp, if_ierrors); 2239 m_freem(m); 2240 continue; 2241 } 2242 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2243 nm->m_data += 2; 2244 nm->m_pkthdr.len = nm->m_len = len; 2245 m_copydata(m, 0, len, mtod(nm, void *)); 2246 m_freem(m); 2247 m = nm; 2248 } 2249 #ifndef __NO_STRICT_ALIGNMENT 2250 else { 2251 /* 2252 * The DP83820's receive buffers must be 4-byte 2253 * aligned. But this means that the data after 2254 * the Ethernet header is misaligned. To compensate, 2255 * we have artificially shortened the buffer size 2256 * in the descriptor, and we do an overlapping copy 2257 * of the data two bytes further in (in the first 2258 * buffer of the chain only). 2259 */ 2260 memmove(mtod(m, char *) + 2, mtod(m, void *), 2261 m->m_len); 2262 m->m_data += 2; 2263 } 2264 #endif /* ! __NO_STRICT_ALIGNMENT */ 2265 2266 /* 2267 * If VLANs are enabled, VLAN packets have been unwrapped 2268 * for us. Associate the tag with the packet. 2269 */ 2270 2271 /* 2272 * Again, byte swapping is tricky. Hardware provided 2273 * the tag in the network byte order, but extsts was 2274 * passed through le32toh() in the meantime. On a 2275 * big-endian machine, we need to swap it again. On a 2276 * little-endian machine, we need to convert from the 2277 * network to host byte order. This means that we must 2278 * swap it in any case, so unconditional swap instead 2279 * of htons() is used. 2280 */ 2281 if ((extsts & EXTSTS_VPKT) != 0) { 2282 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2283 } 2284 2285 /* 2286 * Set the incoming checksum information for the 2287 * packet. 2288 */ 2289 if ((extsts & EXTSTS_IPPKT) != 0) { 2290 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2291 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2292 if (extsts & EXTSTS_Rx_IPERR) 2293 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2294 if (extsts & EXTSTS_TCPPKT) { 2295 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2296 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2297 if (extsts & EXTSTS_Rx_TCPERR) 2298 m->m_pkthdr.csum_flags |= 2299 M_CSUM_TCP_UDP_BAD; 2300 } else if (extsts & EXTSTS_UDPPKT) { 2301 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2302 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2303 if (extsts & EXTSTS_Rx_UDPERR) 2304 m->m_pkthdr.csum_flags |= 2305 M_CSUM_TCP_UDP_BAD; 2306 } 2307 } 2308 2309 m_set_rcvif(m, ifp); 2310 m->m_pkthdr.len = len; 2311 2312 /* Pass it on. */ 2313 if_percpuq_enqueue(ifp->if_percpuq, m); 2314 } 2315 2316 /* Update the receive pointer. */ 2317 sc->sc_rxptr = i; 2318 } 2319 2320 /* 2321 * sip_rxintr: 2322 * 2323 * Helper; handle receive interrupts on 10/100 parts. 2324 */ 2325 static void 2326 sip_rxintr(struct sip_softc *sc) 2327 { 2328 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2329 struct sip_rxsoft *rxs; 2330 struct mbuf *m; 2331 uint32_t cmdsts; 2332 int i, len; 2333 2334 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2335 rxs = &sc->sc_rxsoft[i]; 2336 2337 sip_cdrxsync(sc, i, 2338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2339 2340 cmdsts = 2341 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2342 2343 /* 2344 * NOTE: OWN is set if owned by _consumer_. We're the 2345 * consumer of the receive ring, so if the bit is clear, 2346 * we have processed all of the packets. 2347 */ 2348 if ((cmdsts & CMDSTS_OWN) == 0) { 2349 /* 2350 * We have processed all of the receive buffers. 2351 */ 2352 break; 2353 } 2354 2355 /* If any collisions were seen on the wire, count one. */ 2356 if (cmdsts & CMDSTS_Rx_COL) 2357 if_statinc(ifp, if_collisions); 2358 2359 /* 2360 * If an error occurred, update stats, clear the status 2361 * word, and leave the packet buffer in place. It will 2362 * simply be reused the next time the ring comes around. 2363 */ 2364 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_LONG | CMDSTS_Rx_RUNT | 2365 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2366 if_statinc(ifp, if_ierrors); 2367 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2368 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2369 /* Receive overrun handled elsewhere. */ 2370 printf("%s: receive descriptor error\n", 2371 device_xname(sc->sc_dev)); 2372 } 2373 #define PRINTERR(bit, str) \ 2374 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2375 (cmdsts & (bit)) != 0) \ 2376 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2377 PRINTERR(CMDSTS_Rx_LONG, "Too long packet"); 2378 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2379 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2380 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2381 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2382 #undef PRINTERR 2383 sip_init_rxdesc(sc, i); 2384 continue; 2385 } 2386 2387 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2388 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2389 2390 /* 2391 * No errors; receive the packet. Note, the SiS 900 2392 * includes the CRC with every packet. 2393 */ 2394 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2395 2396 #ifdef __NO_STRICT_ALIGNMENT 2397 /* 2398 * If the packet is small enough to fit in a 2399 * single header mbuf, allocate one and copy 2400 * the data into it. This greatly reduces 2401 * memory consumption when we receive lots 2402 * of small packets. 2403 * 2404 * Otherwise, we add a new buffer to the receive 2405 * chain. If this fails, we drop the packet and 2406 * recycle the old buffer. 2407 */ 2408 if (sip_copy_small != 0 && len <= MHLEN) { 2409 MGETHDR(m, M_DONTWAIT, MT_DATA); 2410 if (m == NULL) 2411 goto dropit; 2412 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2413 memcpy(mtod(m, void *), 2414 mtod(rxs->rxs_mbuf, void *), len); 2415 sip_init_rxdesc(sc, i); 2416 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2417 rxs->rxs_dmamap->dm_mapsize, 2418 BUS_DMASYNC_PREREAD); 2419 } else { 2420 m = rxs->rxs_mbuf; 2421 if (sipcom_add_rxbuf(sc, i) != 0) { 2422 dropit: 2423 if_statinc(ifp, if_ierrors); 2424 sip_init_rxdesc(sc, i); 2425 bus_dmamap_sync(sc->sc_dmat, 2426 rxs->rxs_dmamap, 0, 2427 rxs->rxs_dmamap->dm_mapsize, 2428 BUS_DMASYNC_PREREAD); 2429 continue; 2430 } 2431 } 2432 #else 2433 /* 2434 * The SiS 900's receive buffers must be 4-byte aligned. 2435 * But this means that the data after the Ethernet header 2436 * is misaligned. We must allocate a new buffer and 2437 * copy the data, shifted forward 2 bytes. 2438 */ 2439 MGETHDR(m, M_DONTWAIT, MT_DATA); 2440 if (m == NULL) { 2441 dropit: 2442 if_statinc(ifp, if_ierrors); 2443 sip_init_rxdesc(sc, i); 2444 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2445 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2446 continue; 2447 } 2448 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2449 if (len > (MHLEN - 2)) { 2450 MCLGET(m, M_DONTWAIT); 2451 if ((m->m_flags & M_EXT) == 0) { 2452 m_freem(m); 2453 goto dropit; 2454 } 2455 } 2456 m->m_data += 2; 2457 2458 /* 2459 * Note that we use clusters for incoming frames, so the 2460 * buffer is virtually contiguous. 2461 */ 2462 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2463 2464 /* Allow the receive descriptor to continue using its mbuf. */ 2465 sip_init_rxdesc(sc, i); 2466 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2467 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2468 #endif /* __NO_STRICT_ALIGNMENT */ 2469 2470 m_set_rcvif(m, ifp); 2471 m->m_pkthdr.len = m->m_len = len; 2472 2473 /* Pass it on. */ 2474 if_percpuq_enqueue(ifp->if_percpuq, m); 2475 } 2476 2477 /* Update the receive pointer. */ 2478 sc->sc_rxptr = i; 2479 } 2480 2481 /* 2482 * sip_tick: 2483 * 2484 * One second timer, used to tick the MII. 2485 */ 2486 static void 2487 sipcom_tick(void *arg) 2488 { 2489 struct sip_softc *sc = arg; 2490 int s; 2491 2492 s = splnet(); 2493 #ifdef SIP_EVENT_COUNTERS 2494 if (sc->sc_gigabit) { 2495 /* Read PAUSE related counts from MIB registers. */ 2496 sc->sc_ev_rxpause.ev_count += 2497 bus_space_read_4(sc->sc_st, sc->sc_sh, 2498 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2499 sc->sc_ev_txpause.ev_count += 2500 bus_space_read_4(sc->sc_st, sc->sc_sh, 2501 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2502 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2503 } 2504 #endif /* SIP_EVENT_COUNTERS */ 2505 mii_tick(&sc->sc_mii); 2506 splx(s); 2507 2508 callout_schedule(&sc->sc_tick_ch, hz); 2509 } 2510 2511 /* 2512 * sip_reset: 2513 * 2514 * Perform a soft reset on the SiS 900. 2515 */ 2516 static bool 2517 sipcom_reset(struct sip_softc *sc) 2518 { 2519 bus_space_tag_t st = sc->sc_st; 2520 bus_space_handle_t sh = sc->sc_sh; 2521 int i; 2522 2523 bus_space_write_4(st, sh, SIP_IER, 0); 2524 bus_space_write_4(st, sh, SIP_IMR, 0); 2525 bus_space_write_4(st, sh, SIP_RFCR, 0); 2526 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2527 2528 for (i = 0; i < SIP_TIMEOUT; i++) { 2529 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2530 break; 2531 delay(2); 2532 } 2533 2534 if (i == SIP_TIMEOUT) { 2535 printf("%s: reset failed to complete\n", 2536 device_xname(sc->sc_dev)); 2537 return false; 2538 } 2539 2540 delay(1000); 2541 2542 if (sc->sc_gigabit) { 2543 /* 2544 * Set the general purpose I/O bits. Do it here in case we 2545 * need to have GPIO set up to talk to the media interface. 2546 */ 2547 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2548 delay(1000); 2549 } 2550 return true; 2551 } 2552 2553 static void 2554 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2555 { 2556 uint32_t reg; 2557 bus_space_tag_t st = sc->sc_st; 2558 bus_space_handle_t sh = sc->sc_sh; 2559 /* 2560 * Initialize the VLAN/IP receive control register. 2561 * We enable checksum computation on all incoming 2562 * packets, and do not reject packets w/ bad checksums. 2563 */ 2564 reg = 0; 2565 if (capenable & 2566 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2567 reg |= VRCR_IPEN; 2568 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2569 reg |= VRCR_VTDEN | VRCR_VTREN; 2570 bus_space_write_4(st, sh, SIP_VRCR, reg); 2571 2572 /* 2573 * Initialize the VLAN/IP transmit control register. 2574 * We enable outgoing checksum computation on a 2575 * per-packet basis. 2576 */ 2577 reg = 0; 2578 if (capenable & 2579 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2580 reg |= VTCR_PPCHK; 2581 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2582 reg |= VTCR_VPPTI; 2583 bus_space_write_4(st, sh, SIP_VTCR, reg); 2584 2585 /* 2586 * If we're using VLANs, initialize the VLAN data register. 2587 * To understand why we bswap the VLAN Ethertype, see section 2588 * 4.2.36 of the DP83820 manual. 2589 */ 2590 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2591 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2592 } 2593 2594 /* 2595 * sip_init: [ ifnet interface function ] 2596 * 2597 * Initialize the interface. Must be called at splnet(). 2598 */ 2599 static int 2600 sipcom_init(struct ifnet *ifp) 2601 { 2602 struct sip_softc *sc = ifp->if_softc; 2603 bus_space_tag_t st = sc->sc_st; 2604 bus_space_handle_t sh = sc->sc_sh; 2605 struct sip_txsoft *txs; 2606 struct sip_rxsoft *rxs; 2607 int i, error = 0; 2608 2609 if (device_is_active(sc->sc_dev)) { 2610 /* 2611 * Cancel any pending I/O. 2612 */ 2613 sipcom_stop(ifp, 0); 2614 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2615 !device_is_active(sc->sc_dev)) 2616 return 0; 2617 2618 /* 2619 * Reset the chip to a known state. 2620 */ 2621 if (!sipcom_reset(sc)) 2622 return EBUSY; 2623 2624 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2625 /* 2626 * DP83815 manual, page 78: 2627 * 4.4 Recommended Registers Configuration 2628 * For optimum performance of the DP83815, version noted 2629 * as DP83815CVNG (SRR = 203h), the listed register 2630 * modifications must be followed in sequence... 2631 * 2632 * It's not clear if this should be 302h or 203h because that 2633 * chip name is listed as SRR 302h in the description of the 2634 * SRR register. However, my revision 302h DP83815 on the 2635 * Netgear FA311 purchased in 02/2001 needs these settings 2636 * to avoid tons of errors in AcceptPerfectMatch (non- 2637 * IFF_PROMISC) mode. I do not know if other revisions need 2638 * this set or not. [briggs -- 09 March 2001] 2639 * 2640 * Note that only the low-order 12 bits of 0xe4 are documented 2641 * and that this sets reserved bits in that register. 2642 */ 2643 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2644 2645 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2646 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2647 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2648 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2649 2650 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2651 } 2652 2653 /* Initialize the transmit descriptor ring. */ 2654 sip_init_txring(sc); 2655 2656 /* 2657 * Initialize the transmit job descriptors. 2658 */ 2659 SIMPLEQ_INIT(&sc->sc_txfreeq); 2660 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2661 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2662 txs = &sc->sc_txsoft[i]; 2663 txs->txs_mbuf = NULL; 2664 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2665 } 2666 2667 /* 2668 * Initialize the receive descriptor and receive job 2669 * descriptor rings. 2670 */ 2671 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2672 rxs = &sc->sc_rxsoft[i]; 2673 if (rxs->rxs_mbuf == NULL) { 2674 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2675 printf("%s: unable to allocate or map rx " 2676 "buffer %d, error = %d\n", 2677 device_xname(sc->sc_dev), i, error); 2678 /* 2679 * XXX Should attempt to run with fewer receive 2680 * XXX buffers instead of just failing. 2681 */ 2682 sipcom_rxdrain(sc); 2683 goto out; 2684 } 2685 } else 2686 sip_init_rxdesc(sc, i); 2687 } 2688 sc->sc_rxptr = 0; 2689 sc->sc_rxdiscard = 0; 2690 sip_rxchain_reset(sc); 2691 2692 /* 2693 * Set the configuration register; it's already initialized 2694 * in sip_attach(). 2695 */ 2696 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2697 2698 /* 2699 * Initialize the prototype TXCFG register. 2700 */ 2701 if (sc->sc_gigabit) { 2702 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2703 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2704 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2705 SIP_SIS900_REV(sc, SIS_REV_960) || 2706 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2707 (sc->sc_cfg & CFG_EDBMASTEN)) { 2708 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2709 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2710 } else { 2711 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2712 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2713 } 2714 2715 sc->sc_txcfg |= TXCFG_ATP | 2716 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2717 sc->sc_tx_drain_thresh; 2718 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2719 2720 /* 2721 * Initialize the receive drain threshold if we have never 2722 * done so. 2723 */ 2724 if (sc->sc_rx_drain_thresh == 0) { 2725 /* 2726 * XXX This value should be tuned. This is set to the 2727 * maximum of 248 bytes, and we may be able to improve 2728 * performance by decreasing it (although we should never 2729 * set this value lower than 2; 14 bytes are required to 2730 * filter the packet). 2731 */ 2732 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2733 } 2734 2735 /* 2736 * Initialize the prototype RXCFG register. 2737 */ 2738 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2739 /* 2740 * Accept long packets (including FCS) so we can handle 2741 * 802.1q-tagged frames and jumbo frames properly. 2742 */ 2743 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2744 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2745 sc->sc_rxcfg |= RXCFG_ALP; 2746 2747 /* 2748 * Checksum offloading is disabled if the user selects an MTU 2749 * larger than 8109. (FreeBSD says 8152, but there is empirical 2750 * evidence that >8109 does not work on some boards, such as the 2751 * Planex GN-1000TE). 2752 */ 2753 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2754 (ifp->if_capenable & 2755 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2756 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2757 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2758 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2759 "disabled.\n", device_xname(sc->sc_dev)); 2760 ifp->if_capenable &= 2761 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2762 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2763 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2764 ifp->if_csum_flags_tx = 0; 2765 ifp->if_csum_flags_rx = 0; 2766 } 2767 2768 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2769 2770 if (sc->sc_gigabit) 2771 sipcom_dp83820_init(sc, ifp->if_capenable); 2772 2773 /* 2774 * Give the transmit and receive rings to the chip. 2775 */ 2776 sip_set_txdp(sc, SIP_CDTXADDR(sc, sc->sc_txnext)); 2777 sip_set_rxdp(sc, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2778 2779 /* 2780 * Initialize the interrupt mask. 2781 */ 2782 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2783 sc->sc_bits.b_isr_sserr | 2784 sc->sc_bits.b_isr_rmabt | 2785 sc->sc_bits.b_isr_rtabt | 2786 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2787 ISR_RXIDLE | ISR_RXDESC; 2788 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2789 2790 /* Set up the receive filter. */ 2791 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2792 2793 /* 2794 * Tune sc_rx_flow_thresh. 2795 * XXX "More than 8KB" is too short for jumbo frames. 2796 * XXX TODO: Threshold value should be user-settable. 2797 */ 2798 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2799 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2800 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2801 2802 /* 2803 * Set the current media. Do this after initializing the prototype 2804 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2805 * control. 2806 */ 2807 if ((error = ether_mediachange(ifp)) != 0) 2808 goto out; 2809 2810 /* 2811 * Set the interrupt hold-off timer to 100us. 2812 */ 2813 if (sc->sc_gigabit) 2814 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2815 2816 /* 2817 * Enable interrupts. 2818 */ 2819 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2820 2821 /* 2822 * Start the transmit and receive processes. 2823 */ 2824 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2825 2826 /* 2827 * Start the one second MII clock. 2828 */ 2829 callout_schedule(&sc->sc_tick_ch, hz); 2830 2831 /* 2832 * ...all done! 2833 */ 2834 ifp->if_flags |= IFF_RUNNING; 2835 sc->sc_if_flags = ifp->if_flags; 2836 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2837 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2838 sc->sc_prev.if_capenable = ifp->if_capenable; 2839 2840 out: 2841 if (error) 2842 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2843 return error; 2844 } 2845 2846 /* 2847 * sip_drain: 2848 * 2849 * Drain the receive queue. 2850 */ 2851 static void 2852 sipcom_rxdrain(struct sip_softc *sc) 2853 { 2854 struct sip_rxsoft *rxs; 2855 int i; 2856 2857 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2858 rxs = &sc->sc_rxsoft[i]; 2859 if (rxs->rxs_mbuf != NULL) { 2860 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2861 m_freem(rxs->rxs_mbuf); 2862 rxs->rxs_mbuf = NULL; 2863 } 2864 } 2865 } 2866 2867 /* 2868 * sip_stop: [ ifnet interface function ] 2869 * 2870 * Stop transmission on the interface. 2871 */ 2872 static void 2873 sipcom_stop(struct ifnet *ifp, int disable) 2874 { 2875 struct sip_softc *sc = ifp->if_softc; 2876 bus_space_tag_t st = sc->sc_st; 2877 bus_space_handle_t sh = sc->sc_sh; 2878 struct sip_txsoft *txs; 2879 uint32_t cmdsts = 0; /* DEBUG */ 2880 2881 /* 2882 * Stop the one second clock. 2883 */ 2884 callout_stop(&sc->sc_tick_ch); 2885 2886 /* Down the MII. */ 2887 mii_down(&sc->sc_mii); 2888 2889 if (device_is_active(sc->sc_dev)) { 2890 /* 2891 * Disable interrupts. 2892 */ 2893 bus_space_write_4(st, sh, SIP_IER, 0); 2894 2895 /* 2896 * Stop receiver and transmitter. 2897 */ 2898 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2899 } 2900 2901 /* 2902 * Release any queued transmit buffers. 2903 */ 2904 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2905 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2906 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2907 (sc->sc_txdescs[ 2908 txs->txs_lastdesc].sipd_words[ 2909 sc->sc_cmdsts_idx] & htole32(CMDSTS_INTR)) == 0) 2910 printf("%s: sip_stop: last descriptor does not " 2911 "have INTR bit set\n", device_xname(sc->sc_dev)); 2912 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2913 #ifdef DIAGNOSTIC 2914 if (txs->txs_mbuf == NULL) { 2915 printf("%s: dirty txsoft with no mbuf chain\n", 2916 device_xname(sc->sc_dev)); 2917 panic("sip_stop"); 2918 } 2919 #endif 2920 cmdsts |= /* DEBUG */ 2921 le32toh(sc->sc_txdescs[ 2922 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2923 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2924 m_freem(txs->txs_mbuf); 2925 txs->txs_mbuf = NULL; 2926 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2927 } 2928 2929 /* 2930 * Mark the interface down and cancel the watchdog timer. 2931 */ 2932 ifp->if_flags &= ~IFF_RUNNING; 2933 ifp->if_timer = 0; 2934 2935 if (disable) 2936 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2937 2938 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2939 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2940 printf("%s: sip_stop: no INTR bits set in dirty tx " 2941 "descriptors\n", device_xname(sc->sc_dev)); 2942 } 2943 2944 /* 2945 * sip_read_eeprom: 2946 * 2947 * Read data from the serial EEPROM. 2948 */ 2949 static void 2950 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2951 uint16_t *data) 2952 { 2953 bus_space_tag_t st = sc->sc_st; 2954 bus_space_handle_t sh = sc->sc_sh; 2955 uint16_t reg; 2956 int i, x; 2957 2958 for (i = 0; i < wordcnt; i++) { 2959 /* Send CHIP SELECT. */ 2960 reg = EROMAR_EECS; 2961 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2962 2963 /* Shift in the READ opcode. */ 2964 for (x = 3; x > 0; x--) { 2965 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2966 reg |= EROMAR_EEDI; 2967 else 2968 reg &= ~EROMAR_EEDI; 2969 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2970 bus_space_write_4(st, sh, SIP_EROMAR, 2971 reg | EROMAR_EESK); 2972 delay(4); 2973 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2974 delay(4); 2975 } 2976 2977 /* Shift in address. */ 2978 for (x = 6; x > 0; x--) { 2979 if ((word + i) & (1 << (x - 1))) 2980 reg |= EROMAR_EEDI; 2981 else 2982 reg &= ~EROMAR_EEDI; 2983 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2984 bus_space_write_4(st, sh, SIP_EROMAR, 2985 reg | EROMAR_EESK); 2986 delay(4); 2987 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2988 delay(4); 2989 } 2990 2991 /* Shift out data. */ 2992 reg = EROMAR_EECS; 2993 data[i] = 0; 2994 for (x = 16; x > 0; x--) { 2995 bus_space_write_4(st, sh, SIP_EROMAR, 2996 reg | EROMAR_EESK); 2997 delay(4); 2998 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2999 data[i] |= (1 << (x - 1)); 3000 bus_space_write_4(st, sh, SIP_EROMAR, reg); 3001 delay(4); 3002 } 3003 3004 /* Clear CHIP SELECT. */ 3005 bus_space_write_4(st, sh, SIP_EROMAR, 0); 3006 delay(4); 3007 } 3008 } 3009 3010 /* 3011 * sipcom_add_rxbuf: 3012 * 3013 * Add a receive buffer to the indicated descriptor. 3014 */ 3015 static int 3016 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 3017 { 3018 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3019 struct mbuf *m; 3020 int error; 3021 3022 MGETHDR(m, M_DONTWAIT, MT_DATA); 3023 if (m == NULL) 3024 return ENOBUFS; 3025 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 3026 3027 MCLGET(m, M_DONTWAIT); 3028 if ((m->m_flags & M_EXT) == 0) { 3029 m_freem(m); 3030 return ENOBUFS; 3031 } 3032 3033 /* XXX I don't believe this is necessary. --dyoung */ 3034 if (sc->sc_gigabit) 3035 m->m_len = sc->sc_parm->p_rxbuf_len; 3036 3037 if (rxs->rxs_mbuf != NULL) 3038 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3039 3040 rxs->rxs_mbuf = m; 3041 3042 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3043 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3044 BUS_DMA_READ | BUS_DMA_NOWAIT); 3045 if (error) { 3046 printf("%s: can't load rx DMA map %d, error = %d\n", 3047 device_xname(sc->sc_dev), idx, error); 3048 panic("%s", __func__); /* XXX */ 3049 } 3050 3051 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3052 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3053 3054 sip_init_rxdesc(sc, idx); 3055 3056 return 0; 3057 } 3058 3059 /* 3060 * sip_sis900_set_filter: 3061 * 3062 * Set up the receive filter. 3063 */ 3064 static void 3065 sipcom_sis900_set_filter(struct sip_softc *sc) 3066 { 3067 bus_space_tag_t st = sc->sc_st; 3068 bus_space_handle_t sh = sc->sc_sh; 3069 struct ethercom *ec = &sc->sc_ethercom; 3070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3071 struct ether_multi *enm; 3072 const uint8_t *cp; 3073 struct ether_multistep step; 3074 uint32_t crc, mchash[16]; 3075 3076 /* 3077 * Initialize the prototype RFCR. 3078 */ 3079 sc->sc_rfcr = RFCR_RFEN; 3080 if (ifp->if_flags & IFF_BROADCAST) 3081 sc->sc_rfcr |= RFCR_AAB; 3082 if (ifp->if_flags & IFF_PROMISC) { 3083 sc->sc_rfcr |= RFCR_AAP; 3084 goto allmulti; 3085 } 3086 3087 /* 3088 * Set up the multicast address filter by passing all multicast 3089 * addresses through a CRC generator, and then using the high-order 3090 * 6 bits as an index into the 128 bit multicast hash table (only 3091 * the lower 16 bits of each 32 bit multicast hash register are 3092 * valid). The high order bits select the register, while the 3093 * rest of the bits select the bit within the register. 3094 */ 3095 3096 memset(mchash, 0, sizeof(mchash)); 3097 3098 /* 3099 * SiS900 (at least SiS963) requires us to register the address of 3100 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3101 */ 3102 crc = 0x0ed423f9; 3103 3104 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3105 SIP_SIS900_REV(sc, SIS_REV_960) || 3106 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3107 /* Just want the 8 most significant bits. */ 3108 crc >>= 24; 3109 } else { 3110 /* Just want the 7 most significant bits. */ 3111 crc >>= 25; 3112 } 3113 3114 /* Set the corresponding bit in the hash table. */ 3115 mchash[crc >> 4] |= 1 << (crc & 0xf); 3116 3117 ETHER_LOCK(ec); 3118 ETHER_FIRST_MULTI(step, ec, enm); 3119 while (enm != NULL) { 3120 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3121 /* 3122 * We must listen to a range of multicast addresses. 3123 * For now, just accept all multicasts, rather than 3124 * trying to set only those filter bits needed to match 3125 * the range. (At this time, the only use of address 3126 * ranges is for IP multicast routing, for which the 3127 * range is big enough to require all bits set.) 3128 */ 3129 ETHER_UNLOCK(ec); 3130 goto allmulti; 3131 } 3132 3133 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3134 3135 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3136 SIP_SIS900_REV(sc, SIS_REV_960) || 3137 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3138 /* Just want the 8 most significant bits. */ 3139 crc >>= 24; 3140 } else { 3141 /* Just want the 7 most significant bits. */ 3142 crc >>= 25; 3143 } 3144 3145 /* Set the corresponding bit in the hash table. */ 3146 mchash[crc >> 4] |= 1 << (crc & 0xf); 3147 3148 ETHER_NEXT_MULTI(step, enm); 3149 } 3150 ETHER_UNLOCK(ec); 3151 3152 ifp->if_flags &= ~IFF_ALLMULTI; 3153 goto setit; 3154 3155 allmulti: 3156 ifp->if_flags |= IFF_ALLMULTI; 3157 sc->sc_rfcr |= RFCR_AAM; 3158 3159 setit: 3160 #define FILTER_EMIT(addr, data) \ 3161 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3162 delay(1); \ 3163 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3164 delay(1) 3165 3166 /* 3167 * Disable receive filter, and program the node address. 3168 */ 3169 cp = CLLADDR(ifp->if_sadl); 3170 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3171 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3172 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3173 3174 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3175 /* 3176 * Program the multicast hash table. 3177 */ 3178 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3179 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3180 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3181 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3182 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3183 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3184 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3185 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3186 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3187 SIP_SIS900_REV(sc, SIS_REV_960) || 3188 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3189 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3190 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3191 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3192 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3193 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3194 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3195 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3196 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3197 } 3198 } 3199 #undef FILTER_EMIT 3200 3201 /* 3202 * Re-enable the receiver filter. 3203 */ 3204 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3205 } 3206 3207 /* 3208 * sip_dp83815_set_filter: 3209 * 3210 * Set up the receive filter. 3211 */ 3212 static void 3213 sipcom_dp83815_set_filter(struct sip_softc *sc) 3214 { 3215 bus_space_tag_t st = sc->sc_st; 3216 bus_space_handle_t sh = sc->sc_sh; 3217 struct ethercom *ec = &sc->sc_ethercom; 3218 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3219 struct ether_multi *enm; 3220 const uint8_t *cp; 3221 struct ether_multistep step; 3222 uint32_t crc, hash, slot, bit; 3223 #define MCHASH_NWORDS_83820 128 3224 #define MCHASH_NWORDS_83815 32 3225 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3226 uint16_t mchash[MCHASH_NWORDS]; 3227 int i; 3228 3229 /* 3230 * Initialize the prototype RFCR. 3231 * Enable the receive filter, and accept on 3232 * Perfect (destination address) Match 3233 * If IFF_BROADCAST, also accept all broadcast packets. 3234 * If IFF_PROMISC, accept all unicast packets (and later, set 3235 * IFF_ALLMULTI and accept all multicast, too). 3236 */ 3237 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3238 if (ifp->if_flags & IFF_BROADCAST) 3239 sc->sc_rfcr |= RFCR_AAB; 3240 if (ifp->if_flags & IFF_PROMISC) { 3241 sc->sc_rfcr |= RFCR_AAP; 3242 goto allmulti; 3243 } 3244 3245 /* 3246 * Set up the DP83820/DP83815 multicast address filter by 3247 * passing all multicast addresses through a CRC generator, 3248 * and then using the high-order 11/9 bits as an index into 3249 * the 2048/512 bit multicast hash table. The high-order 3250 * 7/5 bits select the slot, while the low-order 4 bits 3251 * select the bit within the slot. Note that only the low 3252 * 16-bits of each filter word are used, and there are 3253 * 128/32 filter words. 3254 */ 3255 3256 memset(mchash, 0, sizeof(mchash)); 3257 3258 ifp->if_flags &= ~IFF_ALLMULTI; 3259 ETHER_FIRST_MULTI(step, ec, enm); 3260 if (enm == NULL) 3261 goto setit; 3262 while (enm != NULL) { 3263 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3264 /* 3265 * We must listen to a range of multicast addresses. 3266 * For now, just accept all multicasts, rather than 3267 * trying to set only those filter bits needed to match 3268 * the range. (At this time, the only use of address 3269 * ranges is for IP multicast routing, for which the 3270 * range is big enough to require all bits set.) 3271 */ 3272 goto allmulti; 3273 } 3274 3275 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3276 3277 if (sc->sc_gigabit) { 3278 /* Just want the 11 most significant bits. */ 3279 hash = crc >> 21; 3280 } else { 3281 /* Just want the 9 most significant bits. */ 3282 hash = crc >> 23; 3283 } 3284 3285 slot = hash >> 4; 3286 bit = hash & 0xf; 3287 3288 /* Set the corresponding bit in the hash table. */ 3289 mchash[slot] |= 1 << bit; 3290 3291 ETHER_NEXT_MULTI(step, enm); 3292 } 3293 sc->sc_rfcr |= RFCR_MHEN; 3294 goto setit; 3295 3296 allmulti: 3297 ifp->if_flags |= IFF_ALLMULTI; 3298 sc->sc_rfcr |= RFCR_AAM; 3299 3300 setit: 3301 #define FILTER_EMIT(addr, data) \ 3302 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3303 delay(1); \ 3304 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3305 delay(1) 3306 3307 /* 3308 * Disable receive filter, and program the node address. 3309 */ 3310 cp = CLLADDR(ifp->if_sadl); 3311 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3312 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3313 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3314 3315 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3316 int nwords = 3317 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3318 /* 3319 * Program the multicast hash table. 3320 */ 3321 for (i = 0; i < nwords; i++) { 3322 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3323 } 3324 } 3325 #undef FILTER_EMIT 3326 #undef MCHASH_NWORDS 3327 #undef MCHASH_NWORDS_83815 3328 #undef MCHASH_NWORDS_83820 3329 3330 /* 3331 * Re-enable the receiver filter. 3332 */ 3333 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3334 } 3335 3336 /* 3337 * sip_dp83820_mii_readreg: [mii interface function] 3338 * 3339 * Read a PHY register on the MII of the DP83820. 3340 */ 3341 static int 3342 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3343 { 3344 struct sip_softc *sc = device_private(self); 3345 3346 if (sc->sc_cfg & CFG_TBI_EN) { 3347 bus_addr_t tbireg; 3348 3349 if (phy != 0) 3350 return -1; 3351 3352 switch (reg) { 3353 case MII_BMCR: tbireg = SIP_TBICR; break; 3354 case MII_BMSR: tbireg = SIP_TBISR; break; 3355 case MII_ANAR: tbireg = SIP_TANAR; break; 3356 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3357 case MII_ANER: tbireg = SIP_TANER; break; 3358 case MII_EXTSR: 3359 /* 3360 * Don't even bother reading the TESR register. 3361 * The manual documents that the device has 3362 * 1000baseX full/half capability, but the 3363 * register itself seems read back 0 on some 3364 * boards. Just hard-code the result. 3365 */ 3366 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3367 return 0; 3368 3369 default: 3370 return 0; 3371 } 3372 3373 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3374 if (tbireg == SIP_TBISR) { 3375 /* LINK and ACOMP are switched! */ 3376 int sr = *val; 3377 3378 *val = 0; 3379 if (sr & TBISR_MR_LINK_STATUS) 3380 *val |= BMSR_LINK; 3381 if (sr & TBISR_MR_AN_COMPLETE) 3382 *val |= BMSR_ACOMP; 3383 3384 /* 3385 * The manual claims this register reads back 0 3386 * on hard and soft reset. But we want to let 3387 * the gentbi driver know that we support auto- 3388 * negotiation, so hard-code this bit in the 3389 * result. 3390 */ 3391 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3392 } 3393 3394 return 0; 3395 } 3396 3397 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3398 val); 3399 } 3400 3401 /* 3402 * sip_dp83820_mii_writereg: [mii interface function] 3403 * 3404 * Write a PHY register on the MII of the DP83820. 3405 */ 3406 static int 3407 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3408 { 3409 struct sip_softc *sc = device_private(self); 3410 3411 if (sc->sc_cfg & CFG_TBI_EN) { 3412 bus_addr_t tbireg; 3413 3414 if (phy != 0) 3415 return -1; 3416 3417 switch (reg) { 3418 case MII_BMCR: tbireg = SIP_TBICR; break; 3419 case MII_ANAR: tbireg = SIP_TANAR; break; 3420 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3421 default: 3422 return 0; 3423 } 3424 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3426 return 0; 3427 } 3428 3429 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3430 val); 3431 } 3432 3433 /* 3434 * sip_dp83820_mii_statchg: [mii interface function] 3435 * 3436 * Callback from MII layer when media changes. 3437 */ 3438 static void 3439 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3440 { 3441 struct sip_softc *sc = ifp->if_softc; 3442 struct mii_data *mii = &sc->sc_mii; 3443 uint32_t cfg, pcr; 3444 3445 /* 3446 * Get flow control negotiation result. 3447 */ 3448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3450 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3451 mii->mii_media_active &= ~IFM_ETH_FMASK; 3452 } 3453 3454 /* 3455 * Update TXCFG for full-duplex operation. 3456 */ 3457 if ((mii->mii_media_active & IFM_FDX) != 0) 3458 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3459 else 3460 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3461 3462 /* 3463 * Update RXCFG for full-duplex or loopback. 3464 */ 3465 if ((mii->mii_media_active & IFM_FDX) != 0 || 3466 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3467 sc->sc_rxcfg |= RXCFG_ATX; 3468 else 3469 sc->sc_rxcfg &= ~RXCFG_ATX; 3470 3471 /* 3472 * Update CFG for MII/GMII. 3473 */ 3474 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3475 cfg = sc->sc_cfg | CFG_MODE_1000; 3476 else 3477 cfg = sc->sc_cfg; 3478 3479 /* 3480 * 802.3x flow control. 3481 */ 3482 pcr = 0; 3483 if (sc->sc_flowflags & IFM_FLOW) { 3484 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3485 pcr |= sc->sc_rx_flow_thresh; 3486 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3487 pcr |= PCR_PSEN | PCR_PS_MCAST; 3488 } 3489 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3491 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3492 sc->sc_txcfg); 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3494 sc->sc_rxcfg); 3495 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3496 } 3497 3498 /* 3499 * sip_mii_bitbang_read: [mii bit-bang interface function] 3500 * 3501 * Read the MII serial port for the MII bit-bang module. 3502 */ 3503 static uint32_t 3504 sipcom_mii_bitbang_read(device_t self) 3505 { 3506 struct sip_softc *sc = device_private(self); 3507 3508 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3509 } 3510 3511 /* 3512 * sip_mii_bitbang_write: [mii big-bang interface function] 3513 * 3514 * Write the MII serial port for the MII bit-bang module. 3515 */ 3516 static void 3517 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3518 { 3519 struct sip_softc *sc = device_private(self); 3520 3521 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3522 } 3523 3524 /* 3525 * sip_sis900_mii_readreg: [mii interface function] 3526 * 3527 * Read a PHY register on the MII. 3528 */ 3529 static int 3530 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3531 { 3532 struct sip_softc *sc = device_private(self); 3533 uint32_t enphy; 3534 3535 /* 3536 * The PHY of recent SiS chipsets is accessed through bitbang 3537 * operations. 3538 */ 3539 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3540 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3541 phy, reg, val); 3542 3543 #ifndef SIS900_MII_RESTRICT 3544 /* 3545 * The SiS 900 has only an internal PHY on the MII. Only allow 3546 * MII address 0. 3547 */ 3548 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3549 return -1; 3550 #endif 3551 3552 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3553 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3554 ENPHY_RWCMD | ENPHY_ACCESS); 3555 do { 3556 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3557 } while (enphy & ENPHY_ACCESS); 3558 3559 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3560 return 0; 3561 } 3562 3563 /* 3564 * sip_sis900_mii_writereg: [mii interface function] 3565 * 3566 * Write a PHY register on the MII. 3567 */ 3568 static int 3569 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3570 { 3571 struct sip_softc *sc = device_private(self); 3572 uint32_t enphy; 3573 3574 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3575 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3576 phy, reg, val); 3577 } 3578 3579 #ifndef SIS900_MII_RESTRICT 3580 /* 3581 * The SiS 900 has only an internal PHY on the MII. Only allow 3582 * MII address 0. 3583 */ 3584 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3585 return -1; 3586 #endif 3587 3588 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3589 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3590 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3591 do { 3592 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3593 } while (enphy & ENPHY_ACCESS); 3594 3595 return 0; 3596 } 3597 3598 /* 3599 * sip_sis900_mii_statchg: [mii interface function] 3600 * 3601 * Callback from MII layer when media changes. 3602 */ 3603 static void 3604 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3605 { 3606 struct sip_softc *sc = ifp->if_softc; 3607 struct mii_data *mii = &sc->sc_mii; 3608 uint32_t flowctl; 3609 3610 /* 3611 * Get flow control negotiation result. 3612 */ 3613 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3614 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3615 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3616 mii->mii_media_active &= ~IFM_ETH_FMASK; 3617 } 3618 3619 /* 3620 * Update TXCFG for full-duplex operation. 3621 */ 3622 if ((mii->mii_media_active & IFM_FDX) != 0) 3623 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3624 else 3625 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3626 3627 /* 3628 * Update RXCFG for full-duplex or loopback. 3629 */ 3630 if ((mii->mii_media_active & IFM_FDX) != 0 || 3631 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3632 sc->sc_rxcfg |= RXCFG_ATX; 3633 else 3634 sc->sc_rxcfg &= ~RXCFG_ATX; 3635 3636 /* 3637 * Update IMR for use of 802.3x flow control. 3638 */ 3639 if (sc->sc_flowflags & IFM_FLOW) { 3640 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3641 flowctl = FLOWCTL_FLOWEN; 3642 } else { 3643 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3644 flowctl = 0; 3645 } 3646 3647 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3648 sc->sc_txcfg); 3649 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3650 sc->sc_rxcfg); 3651 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3652 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3653 } 3654 3655 /* 3656 * sip_dp83815_mii_readreg: [mii interface function] 3657 * 3658 * Read a PHY register on the MII. 3659 */ 3660 static int 3661 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3662 { 3663 struct sip_softc *sc = device_private(self); 3664 uint32_t data; 3665 3666 /* 3667 * The DP83815 only has an internal PHY. Only allow 3668 * MII address 0. 3669 */ 3670 if (phy != 0) 3671 return -1; 3672 3673 /* 3674 * Apparently, after a reset, the DP83815 can take a while 3675 * to respond. During this recovery period, the BMSR returns 3676 * a value of 0. Catch this -- it's not supposed to happen 3677 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3678 * PHY to come back to life. 3679 * 3680 * This works out because the BMSR is the first register 3681 * read during the PHY probe process. 3682 */ 3683 do { 3684 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3685 } while (reg == MII_BMSR && data == 0); 3686 3687 *val = data & 0xffff; 3688 return 0; 3689 } 3690 3691 /* 3692 * sip_dp83815_mii_writereg: [mii interface function] 3693 * 3694 * Write a PHY register to the MII. 3695 */ 3696 static int 3697 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3698 { 3699 struct sip_softc *sc = device_private(self); 3700 3701 /* 3702 * The DP83815 only has an internal PHY. Only allow 3703 * MII address 0. 3704 */ 3705 if (phy != 0) 3706 return -1; 3707 3708 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3709 3710 return 0; 3711 } 3712 3713 /* 3714 * sip_dp83815_mii_statchg: [mii interface function] 3715 * 3716 * Callback from MII layer when media changes. 3717 */ 3718 static void 3719 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3720 { 3721 struct sip_softc *sc = ifp->if_softc; 3722 3723 /* 3724 * Update TXCFG for full-duplex operation. 3725 */ 3726 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3727 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3728 else 3729 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3730 3731 /* 3732 * Update RXCFG for full-duplex or loopback. 3733 */ 3734 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3735 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3736 sc->sc_rxcfg |= RXCFG_ATX; 3737 else 3738 sc->sc_rxcfg &= ~RXCFG_ATX; 3739 3740 /* 3741 * XXX 802.3x flow control. 3742 */ 3743 3744 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3745 sc->sc_txcfg); 3746 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3747 sc->sc_rxcfg); 3748 3749 /* 3750 * Some DP83815s experience problems when used with short 3751 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3752 * sequence adjusts the DSP's signal attenuation to fix the 3753 * problem. 3754 */ 3755 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3756 uint32_t reg; 3757 3758 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3759 3760 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3761 reg &= 0x0fff; 3762 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3763 delay(100); 3764 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3765 reg &= 0x00ff; 3766 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3767 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3768 0x00e8); 3769 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3770 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3771 reg | 0x20); 3772 } 3773 3774 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3775 } 3776 } 3777 3778 static void 3779 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3780 const struct pci_attach_args *pa, uint8_t *enaddr) 3781 { 3782 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3783 uint8_t cksum, *e, match; 3784 int i; 3785 3786 /* 3787 * EEPROM data format for the DP83820 can be found in 3788 * the DP83820 manual, section 4.2.4. 3789 */ 3790 3791 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3792 3793 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3794 match = ~(match - 1); 3795 3796 cksum = 0x55; 3797 e = (uint8_t *)eeprom_data; 3798 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3799 cksum += *e++; 3800 3801 if (cksum != match) 3802 printf("%s: Checksum (%x) mismatch (%x)", 3803 device_xname(sc->sc_dev), cksum, match); 3804 3805 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3806 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3807 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3808 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3809 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3810 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3811 } 3812 3813 static void 3814 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3815 { 3816 int i; 3817 3818 /* 3819 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3820 * a reason, but I don't know it. 3821 */ 3822 for (i = 0; i < 10; i++) 3823 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3824 } 3825 3826 static void 3827 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3828 const struct pci_attach_args *pa, uint8_t *enaddr) 3829 { 3830 uint16_t myea[ETHER_ADDR_LEN / 2]; 3831 3832 switch (sc->sc_rev) { 3833 case SIS_REV_630S: 3834 case SIS_REV_630E: 3835 case SIS_REV_630EA1: 3836 case SIS_REV_630ET: 3837 case SIS_REV_635: 3838 /* 3839 * The MAC address for the on-board Ethernet of 3840 * the SiS 630 chipset is in the NVRAM. Kick 3841 * the chip into re-loading it from NVRAM, and 3842 * read the MAC address out of the filter registers. 3843 */ 3844 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3845 3846 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3847 RFCR_RFADDR_NODE0); 3848 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3849 0xffff; 3850 3851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3852 RFCR_RFADDR_NODE2); 3853 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3854 0xffff; 3855 3856 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3857 RFCR_RFADDR_NODE4); 3858 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3859 0xffff; 3860 break; 3861 3862 case SIS_REV_960: 3863 { 3864 #define SIS_SET_EROMAR(x, y) \ 3865 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3866 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3867 3868 #define SIS_CLR_EROMAR(x, y) \ 3869 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3870 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3871 3872 int waittime, i; 3873 3874 /* Allow to read EEPROM from LAN. It is shared 3875 * between a 1394 controller and the NIC and each 3876 * time we access it, we need to set SIS_EECMD_REQ. 3877 */ 3878 SIS_SET_EROMAR(sc, EROMAR_REQ); 3879 3880 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3881 /* Force EEPROM to idle state. */ 3882 3883 /* 3884 * XXX-cube This is ugly. 3885 * I'll look for docs about it. 3886 */ 3887 SIS_SET_EROMAR(sc, EROMAR_EECS); 3888 sipcom_sis900_eeprom_delay(sc); 3889 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3890 SIS_SET_EROMAR(sc, EROMAR_EESK); 3891 sipcom_sis900_eeprom_delay(sc); 3892 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3893 sipcom_sis900_eeprom_delay(sc); 3894 } 3895 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3896 sipcom_sis900_eeprom_delay(sc); 3897 bus_space_write_4(sc->sc_st, sc->sc_sh, 3898 SIP_EROMAR, 0); 3899 3900 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3901 SIP_EROMAR) & EROMAR_GNT) { 3902 sipcom_read_eeprom(sc, 3903 SIP_EEPROM_ETHERNET_ID0 >> 1, 3904 sizeof(myea) / sizeof(myea[0]), 3905 myea); 3906 break; 3907 } 3908 DELAY(1); 3909 } 3910 3911 /* 3912 * Set SIS_EECTL_CLK to high, so a other master 3913 * can operate on the i2c bus. 3914 */ 3915 SIS_SET_EROMAR(sc, EROMAR_EESK); 3916 3917 /* Refuse EEPROM access by LAN */ 3918 SIS_SET_EROMAR(sc, EROMAR_DONE); 3919 } break; 3920 3921 default: 3922 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3923 sizeof(myea) / sizeof(myea[0]), myea); 3924 } 3925 3926 enaddr[0] = myea[0] & 0xff; 3927 enaddr[1] = myea[0] >> 8; 3928 enaddr[2] = myea[1] & 0xff; 3929 enaddr[3] = myea[1] >> 8; 3930 enaddr[4] = myea[2] & 0xff; 3931 enaddr[5] = myea[2] >> 8; 3932 } 3933 3934 /* Table and macro to bit-reverse an octet. */ 3935 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3936 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3937 3938 static void 3939 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3940 const struct pci_attach_args *pa, uint8_t *enaddr) 3941 { 3942 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3943 uint8_t cksum, *e, match; 3944 int i; 3945 3946 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3947 sizeof(eeprom_data[0]), eeprom_data); 3948 3949 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3950 match = ~(match - 1); 3951 3952 cksum = 0x55; 3953 e = (uint8_t *)eeprom_data; 3954 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3955 cksum += *e++; 3956 3957 if (cksum != match) 3958 printf("%s: Checksum (%x) mismatch (%x)", 3959 device_xname(sc->sc_dev), cksum, match); 3960 3961 /* 3962 * Unrolled because it makes slightly more sense this way. 3963 * The DP83815 stores the MAC address in bit 0 of word 6 3964 * through bit 15 of word 8. 3965 */ 3966 ea = &eeprom_data[6]; 3967 enaddr[0] = ((*ea & 0x1) << 7); 3968 ea++; 3969 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3970 enaddr[1] = ((*ea & 0x1FE) >> 1); 3971 enaddr[2] = ((*ea & 0x1) << 7); 3972 ea++; 3973 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3974 enaddr[3] = ((*ea & 0x1FE) >> 1); 3975 enaddr[4] = ((*ea & 0x1) << 7); 3976 ea++; 3977 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3978 enaddr[5] = ((*ea & 0x1FE) >> 1); 3979 3980 /* 3981 * In case that's not weird enough, we also need to reverse 3982 * the bits in each byte. This all actually makes more sense 3983 * if you think about the EEPROM storage as an array of bits 3984 * being shifted into bytes, but that's not how we're looking 3985 * at it here... 3986 */ 3987 for (i = 0; i < 6 ;i++) 3988 enaddr[i] = bbr(enaddr[i]); 3989 } 3990 3991 /* 3992 * sip_mediastatus: [ifmedia interface function] 3993 * 3994 * Get the current interface media status. 3995 */ 3996 static void 3997 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3998 { 3999 struct sip_softc *sc = ifp->if_softc; 4000 4001 if (!device_is_active(sc->sc_dev)) { 4002 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 4003 ifmr->ifm_status = 0; 4004 return; 4005 } 4006 ether_mediastatus(ifp, ifmr); 4007 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 4008 sc->sc_flowflags; 4009 } 4010