1 /* $NetBSD: if_sip.c,v 1.149 2010/11/13 13:52:06 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.149 2010/11/13 13:52:06 uebayasi Exp $"); 77 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #if NRND > 0 93 #include <sys/rnd.h> 94 #endif 95 96 #include <net/if.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_ether.h> 100 101 #include <net/bpf.h> 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/endian.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <dev/mii/mii_bitbang.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_sipreg.h> 116 117 /* 118 * Transmit descriptor list size. This is arbitrary, but allocate 119 * enough descriptors for 128 pending transmissions, and 8 segments 120 * per packet (64 for DP83820 for jumbo frames). 121 * 122 * This MUST work out to a power of 2. 123 */ 124 #define GSIP_NTXSEGS_ALLOC 16 125 #define SIP_NTXSEGS_ALLOC 8 126 127 #define SIP_TXQUEUELEN 256 128 #define MAX_SIP_NTXDESC \ 129 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 * 135 * Actually, on the DP83820, we allow the packet to consume more than 136 * one buffer, in order to support jumbo Ethernet frames. In that 137 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 138 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 139 * so we'd better be quick about handling receive interrupts. 140 */ 141 #define GSIP_NRXDESC 256 142 #define SIP_NRXDESC 128 143 144 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 145 146 /* 147 * Control structures are DMA'd to the SiS900 chip. We allocate them in 148 * a single clump that maps to a single DMA segment to make several things 149 * easier. 150 */ 151 struct sip_control_data { 152 /* 153 * The transmit descriptors. 154 */ 155 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 156 157 /* 158 * The receive descriptors. 159 */ 160 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 161 }; 162 163 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 164 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 165 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 166 167 /* 168 * Software state for transmit jobs. 169 */ 170 struct sip_txsoft { 171 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 172 bus_dmamap_t txs_dmamap; /* our DMA map */ 173 int txs_firstdesc; /* first descriptor in packet */ 174 int txs_lastdesc; /* last descriptor in packet */ 175 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 176 }; 177 178 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct sip_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 enum sip_attach_stage { 189 SIP_ATTACH_FIN = 0 190 , SIP_ATTACH_CREATE_RXMAP 191 , SIP_ATTACH_CREATE_TXMAP 192 , SIP_ATTACH_LOAD_MAP 193 , SIP_ATTACH_CREATE_MAP 194 , SIP_ATTACH_MAP_MEM 195 , SIP_ATTACH_ALLOC_MEM 196 , SIP_ATTACH_INTR 197 , SIP_ATTACH_MAP 198 }; 199 200 /* 201 * Software state per device. 202 */ 203 struct sip_softc { 204 device_t sc_dev; /* generic device information */ 205 device_suspensor_t sc_suspensor; 206 pmf_qual_t sc_qual; 207 208 bus_space_tag_t sc_st; /* bus space tag */ 209 bus_space_handle_t sc_sh; /* bus space handle */ 210 bus_size_t sc_sz; /* bus space size */ 211 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 212 pci_chipset_tag_t sc_pc; 213 bus_dma_segment_t sc_seg; 214 struct ethercom sc_ethercom; /* ethernet common data */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 int sc_gigabit; /* 1: 83820, 0: other */ 218 int sc_rev; /* chip revision */ 219 220 void *sc_ih; /* interrupt cookie */ 221 222 struct mii_data sc_mii; /* MII/media information */ 223 224 callout_t sc_tick_ch; /* tick callout */ 225 226 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 227 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 228 229 /* 230 * Software state for transmit and receive descriptors. 231 */ 232 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 233 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 234 235 /* 236 * Control data structures. 237 */ 238 struct sip_control_data *sc_control_data; 239 #define sc_txdescs sc_control_data->scd_txdescs 240 #define sc_rxdescs sc_control_data->scd_rxdescs 241 242 #ifdef SIP_EVENT_COUNTERS 243 /* 244 * Event counters. 245 */ 246 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 247 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 248 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 249 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 250 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 251 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 252 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 253 struct evcnt sc_ev_rxpause; /* PAUSE received */ 254 /* DP83820 only */ 255 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 256 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 257 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 258 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 259 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 260 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 261 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 262 #endif /* SIP_EVENT_COUNTERS */ 263 264 u_int32_t sc_txcfg; /* prototype TXCFG register */ 265 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 266 u_int32_t sc_imr; /* prototype IMR register */ 267 u_int32_t sc_rfcr; /* prototype RFCR register */ 268 269 u_int32_t sc_cfg; /* prototype CFG register */ 270 271 u_int32_t sc_gpior; /* prototype GPIOR register */ 272 273 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 274 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 275 276 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 277 278 int sc_flowflags; /* 802.3x flow control flags */ 279 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 280 int sc_paused; /* paused indication */ 281 282 int sc_txfree; /* number of free Tx descriptors */ 283 int sc_txnext; /* next ready Tx descriptor */ 284 int sc_txwin; /* Tx descriptors since last intr */ 285 286 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 287 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 288 289 /* values of interface state at last init */ 290 struct { 291 /* if_capenable */ 292 uint64_t if_capenable; 293 /* ec_capenable */ 294 int ec_capenable; 295 /* VLAN_ATTACHED */ 296 int is_vlan; 297 } sc_prev; 298 299 short sc_if_flags; 300 301 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 308 int sc_ntxdesc; 309 int sc_ntxdesc_mask; 310 311 int sc_nrxdesc_mask; 312 313 const struct sip_parm { 314 const struct sip_regs { 315 int r_rxcfg; 316 int r_txcfg; 317 } p_regs; 318 319 const struct sip_bits { 320 uint32_t b_txcfg_mxdma_8; 321 uint32_t b_txcfg_mxdma_16; 322 uint32_t b_txcfg_mxdma_32; 323 uint32_t b_txcfg_mxdma_64; 324 uint32_t b_txcfg_mxdma_128; 325 uint32_t b_txcfg_mxdma_256; 326 uint32_t b_txcfg_mxdma_512; 327 uint32_t b_txcfg_flth_mask; 328 uint32_t b_txcfg_drth_mask; 329 330 uint32_t b_rxcfg_mxdma_8; 331 uint32_t b_rxcfg_mxdma_16; 332 uint32_t b_rxcfg_mxdma_32; 333 uint32_t b_rxcfg_mxdma_64; 334 uint32_t b_rxcfg_mxdma_128; 335 uint32_t b_rxcfg_mxdma_256; 336 uint32_t b_rxcfg_mxdma_512; 337 338 uint32_t b_isr_txrcmp; 339 uint32_t b_isr_rxrcmp; 340 uint32_t b_isr_dperr; 341 uint32_t b_isr_sserr; 342 uint32_t b_isr_rmabt; 343 uint32_t b_isr_rtabt; 344 345 uint32_t b_cmdsts_size_mask; 346 } p_bits; 347 int p_filtmem; 348 int p_rxbuf_len; 349 bus_size_t p_tx_dmamap_size; 350 int p_ntxsegs; 351 int p_ntxsegs_alloc; 352 int p_nrxdesc; 353 } *sc_parm; 354 355 void (*sc_rxintr)(struct sip_softc *); 356 357 #if NRND > 0 358 rndsource_element_t rnd_source; /* random source */ 359 #endif 360 }; 361 362 #define sc_bits sc_parm->p_bits 363 #define sc_regs sc_parm->p_regs 364 365 static const struct sip_parm sip_parm = { 366 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 367 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 368 , .p_tx_dmamap_size = MCLBYTES 369 , .p_ntxsegs = 16 370 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 371 , .p_nrxdesc = SIP_NRXDESC 372 , .p_bits = { 373 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 374 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 375 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 376 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 377 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 378 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 379 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 380 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 381 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 382 383 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 384 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 385 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 386 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 387 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 388 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 389 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 390 391 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 392 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 393 , .b_isr_dperr = 0x00800000 /* detected parity error */ 394 , .b_isr_sserr = 0x00400000 /* signalled system error */ 395 , .b_isr_rmabt = 0x00200000 /* received master abort */ 396 , .b_isr_rtabt = 0x00100000 /* received target abort */ 397 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 398 } 399 , .p_regs = { 400 .r_rxcfg = OTHER_SIP_RXCFG, 401 .r_txcfg = OTHER_SIP_TXCFG 402 } 403 }, gsip_parm = { 404 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 405 , .p_rxbuf_len = MCLBYTES - 8 406 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 407 , .p_ntxsegs = 64 408 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 409 , .p_nrxdesc = GSIP_NRXDESC 410 , .p_bits = { 411 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 412 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 413 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 414 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 415 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 416 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 417 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 418 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 419 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 420 421 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 422 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 423 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 424 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 425 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 426 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 427 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 428 429 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 430 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 431 , .b_isr_dperr = 0x00100000 /* detected parity error */ 432 , .b_isr_sserr = 0x00080000 /* signalled system error */ 433 , .b_isr_rmabt = 0x00040000 /* received master abort */ 434 , .b_isr_rtabt = 0x00020000 /* received target abort */ 435 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 436 } 437 , .p_regs = { 438 .r_rxcfg = DP83820_SIP_RXCFG, 439 .r_txcfg = DP83820_SIP_TXCFG 440 } 441 }; 442 443 static inline int 444 sip_nexttx(const struct sip_softc *sc, int x) 445 { 446 return (x + 1) & sc->sc_ntxdesc_mask; 447 } 448 449 static inline int 450 sip_nextrx(const struct sip_softc *sc, int x) 451 { 452 return (x + 1) & sc->sc_nrxdesc_mask; 453 } 454 455 /* 83820 only */ 456 static inline void 457 sip_rxchain_reset(struct sip_softc *sc) 458 { 459 sc->sc_rxtailp = &sc->sc_rxhead; 460 *sc->sc_rxtailp = NULL; 461 sc->sc_rxlen = 0; 462 } 463 464 /* 83820 only */ 465 static inline void 466 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 467 { 468 *sc->sc_rxtailp = sc->sc_rxtail = m; 469 sc->sc_rxtailp = &m->m_next; 470 } 471 472 #ifdef SIP_EVENT_COUNTERS 473 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 474 #else 475 #define SIP_EVCNT_INCR(ev) /* nothing */ 476 #endif 477 478 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 479 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 480 481 static inline void 482 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 483 { 484 int x, n; 485 486 x = x0; 487 n = n0; 488 489 /* If it will wrap around, sync to the end of the ring. */ 490 if (x + n > sc->sc_ntxdesc) { 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 493 (sc->sc_ntxdesc - x), ops); 494 n -= (sc->sc_ntxdesc - x); 495 x = 0; 496 } 497 498 /* Now sync whatever is left. */ 499 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 500 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 501 } 502 503 static inline void 504 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 505 { 506 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 507 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 508 } 509 510 #if 0 511 #ifdef DP83820 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 u_int32_t sipd_cmdsts; /* command/status word */ 514 #else 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 517 #endif /* DP83820 */ 518 #endif /* 0 */ 519 520 static inline volatile uint32_t * 521 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 522 { 523 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 524 } 525 526 static inline volatile uint32_t * 527 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 528 { 529 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 530 } 531 532 static inline void 533 sip_init_rxdesc(struct sip_softc *sc, int x) 534 { 535 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 536 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 537 538 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 539 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 540 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 541 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 542 sipd->sipd_extsts = 0; 543 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 544 } 545 546 #define SIP_CHIP_VERS(sc, v, p, r) \ 547 ((sc)->sc_model->sip_vendor == (v) && \ 548 (sc)->sc_model->sip_product == (p) && \ 549 (sc)->sc_rev == (r)) 550 551 #define SIP_CHIP_MODEL(sc, v, p) \ 552 ((sc)->sc_model->sip_vendor == (v) && \ 553 (sc)->sc_model->sip_product == (p)) 554 555 #define SIP_SIS900_REV(sc, rev) \ 556 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 557 558 #define SIP_TIMEOUT 1000 559 560 static int sip_ifflags_cb(struct ethercom *); 561 static void sipcom_start(struct ifnet *); 562 static void sipcom_watchdog(struct ifnet *); 563 static int sipcom_ioctl(struct ifnet *, u_long, void *); 564 static int sipcom_init(struct ifnet *); 565 static void sipcom_stop(struct ifnet *, int); 566 567 static bool sipcom_reset(struct sip_softc *); 568 static void sipcom_rxdrain(struct sip_softc *); 569 static int sipcom_add_rxbuf(struct sip_softc *, int); 570 static void sipcom_read_eeprom(struct sip_softc *, int, int, 571 u_int16_t *); 572 static void sipcom_tick(void *); 573 574 static void sipcom_sis900_set_filter(struct sip_softc *); 575 static void sipcom_dp83815_set_filter(struct sip_softc *); 576 577 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 578 const struct pci_attach_args *, u_int8_t *); 579 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 580 static void sipcom_sis900_read_macaddr(struct sip_softc *, 581 const struct pci_attach_args *, u_int8_t *); 582 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 585 static int sipcom_intr(void *); 586 static void sipcom_txintr(struct sip_softc *); 587 static void sip_rxintr(struct sip_softc *); 588 static void gsip_rxintr(struct sip_softc *); 589 590 static int sipcom_dp83820_mii_readreg(device_t, int, int); 591 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 592 static void sipcom_dp83820_mii_statchg(device_t); 593 594 static int sipcom_sis900_mii_readreg(device_t, int, int); 595 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 596 static void sipcom_sis900_mii_statchg(device_t); 597 598 static int sipcom_dp83815_mii_readreg(device_t, int, int); 599 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 600 static void sipcom_dp83815_mii_statchg(device_t); 601 602 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 603 604 static int sipcom_match(device_t, cfdata_t, void *); 605 static void sipcom_attach(device_t, device_t, void *); 606 static void sipcom_do_detach(device_t, enum sip_attach_stage); 607 static int sipcom_detach(device_t, int); 608 static bool sipcom_resume(device_t, const pmf_qual_t *); 609 static bool sipcom_suspend(device_t, const pmf_qual_t *); 610 611 int gsip_copy_small = 0; 612 int sip_copy_small = 0; 613 614 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 615 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 616 DVF_DETACH_SHUTDOWN); 617 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 618 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 619 DVF_DETACH_SHUTDOWN); 620 621 /* 622 * Descriptions of the variants of the SiS900. 623 */ 624 struct sip_variant { 625 int (*sipv_mii_readreg)(device_t, int, int); 626 void (*sipv_mii_writereg)(device_t, int, int, int); 627 void (*sipv_mii_statchg)(device_t); 628 void (*sipv_set_filter)(struct sip_softc *); 629 void (*sipv_read_macaddr)(struct sip_softc *, 630 const struct pci_attach_args *, u_int8_t *); 631 }; 632 633 static u_int32_t sipcom_mii_bitbang_read(device_t); 634 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 635 636 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 637 sipcom_mii_bitbang_read, 638 sipcom_mii_bitbang_write, 639 { 640 EROMAR_MDIO, /* MII_BIT_MDO */ 641 EROMAR_MDIO, /* MII_BIT_MDI */ 642 EROMAR_MDC, /* MII_BIT_MDC */ 643 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 644 0, /* MII_BIT_DIR_PHY_HOST */ 645 } 646 }; 647 648 static const struct sip_variant sipcom_variant_dp83820 = { 649 sipcom_dp83820_mii_readreg, 650 sipcom_dp83820_mii_writereg, 651 sipcom_dp83820_mii_statchg, 652 sipcom_dp83815_set_filter, 653 sipcom_dp83820_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_sis900 = { 657 sipcom_sis900_mii_readreg, 658 sipcom_sis900_mii_writereg, 659 sipcom_sis900_mii_statchg, 660 sipcom_sis900_set_filter, 661 sipcom_sis900_read_macaddr, 662 }; 663 664 static const struct sip_variant sipcom_variant_dp83815 = { 665 sipcom_dp83815_mii_readreg, 666 sipcom_dp83815_mii_writereg, 667 sipcom_dp83815_mii_statchg, 668 sipcom_dp83815_set_filter, 669 sipcom_dp83815_read_macaddr, 670 }; 671 672 673 /* 674 * Devices supported by this driver. 675 */ 676 static const struct sip_product { 677 pci_vendor_id_t sip_vendor; 678 pci_product_id_t sip_product; 679 const char *sip_name; 680 const struct sip_variant *sip_variant; 681 int sip_gigabit; 682 } sipcom_products[] = { 683 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 684 "NatSemi DP83820 Gigabit Ethernet", 685 &sipcom_variant_dp83820, 1 }, 686 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 687 "SiS 900 10/100 Ethernet", 688 &sipcom_variant_sis900, 0 }, 689 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 690 "SiS 7016 10/100 Ethernet", 691 &sipcom_variant_sis900, 0 }, 692 693 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 694 "NatSemi DP83815 10/100 Ethernet", 695 &sipcom_variant_dp83815, 0 }, 696 697 { 0, 0, 698 NULL, 699 NULL, 0 }, 700 }; 701 702 static const struct sip_product * 703 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 704 { 705 const struct sip_product *sip; 706 707 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 708 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 709 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 710 sip->sip_gigabit == gigabit) 711 return sip; 712 } 713 return NULL; 714 } 715 716 /* 717 * I really hate stupid hardware vendors. There's a bit in the EEPROM 718 * which indicates if the card can do 64-bit data transfers. Unfortunately, 719 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 720 * which means we try to use 64-bit data transfers on those cards if we 721 * happen to be plugged into a 32-bit slot. 722 * 723 * What we do is use this table of cards known to be 64-bit cards. If 724 * you have a 64-bit card who's subsystem ID is not listed in this table, 725 * send the output of "pcictl dump ..." of the device to me so that your 726 * card will use the 64-bit data path when plugged into a 64-bit slot. 727 * 728 * -- Jason R. Thorpe <thorpej@NetBSD.org> 729 * June 30, 2002 730 */ 731 static int 732 sipcom_check_64bit(const struct pci_attach_args *pa) 733 { 734 static const struct { 735 pci_vendor_id_t c64_vendor; 736 pci_product_id_t c64_product; 737 } card64[] = { 738 /* Asante GigaNIX */ 739 { 0x128a, 0x0002 }, 740 741 /* Accton EN1407-T, Planex GN-1000TE */ 742 { 0x1113, 0x1407 }, 743 744 /* Netgear GA-621 */ 745 { 0x1385, 0x621a }, 746 747 /* SMC EZ Card */ 748 { 0x10b8, 0x9462 }, 749 750 { 0, 0} 751 }; 752 pcireg_t subsys; 753 int i; 754 755 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 756 757 for (i = 0; card64[i].c64_vendor != 0; i++) { 758 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 759 PCI_PRODUCT(subsys) == card64[i].c64_product) 760 return (1); 761 } 762 763 return (0); 764 } 765 766 static int 767 sipcom_match(device_t parent, cfdata_t cf, void *aux) 768 { 769 struct pci_attach_args *pa = aux; 770 771 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 772 return 1; 773 774 return 0; 775 } 776 777 static void 778 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 779 { 780 u_int32_t reg; 781 int i; 782 783 /* 784 * Cause the chip to load configuration data from the EEPROM. 785 */ 786 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 787 for (i = 0; i < 10000; i++) { 788 delay(10); 789 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 790 PTSCR_EELOAD_EN) == 0) 791 break; 792 } 793 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 794 PTSCR_EELOAD_EN) { 795 printf("%s: timeout loading configuration from EEPROM\n", 796 device_xname(sc->sc_dev)); 797 return; 798 } 799 800 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 801 802 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 803 if (reg & CFG_PCI64_DET) { 804 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 805 /* 806 * Check to see if this card is 64-bit. If so, enable 64-bit 807 * data transfers. 808 * 809 * We can't use the DATA64_EN bit in the EEPROM, because 810 * vendors of 32-bit cards fail to clear that bit in many 811 * cases (yet the card still detects that it's in a 64-bit 812 * slot; go figure). 813 */ 814 if (sipcom_check_64bit(pa)) { 815 sc->sc_cfg |= CFG_DATA64_EN; 816 printf(", using 64-bit data transfers"); 817 } 818 printf("\n"); 819 } 820 821 /* 822 * XXX Need some PCI flags indicating support for 823 * XXX 64-bit addressing. 824 */ 825 #if 0 826 if (reg & CFG_M64ADDR) 827 sc->sc_cfg |= CFG_M64ADDR; 828 if (reg & CFG_T64ADDR) 829 sc->sc_cfg |= CFG_T64ADDR; 830 #endif 831 832 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 833 const char *sep = ""; 834 printf("%s: using ", device_xname(sc->sc_dev)); 835 if (reg & CFG_EXT_125) { 836 sc->sc_cfg |= CFG_EXT_125; 837 printf("%s125MHz clock", sep); 838 sep = ", "; 839 } 840 if (reg & CFG_TBI_EN) { 841 sc->sc_cfg |= CFG_TBI_EN; 842 printf("%sten-bit interface", sep); 843 sep = ", "; 844 } 845 printf("\n"); 846 } 847 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 848 (reg & CFG_MRM_DIS) != 0) 849 sc->sc_cfg |= CFG_MRM_DIS; 850 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 851 (reg & CFG_MWI_DIS) != 0) 852 sc->sc_cfg |= CFG_MWI_DIS; 853 854 /* 855 * Use the extended descriptor format on the DP83820. This 856 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 857 * checksumming. 858 */ 859 sc->sc_cfg |= CFG_EXTSTS_EN; 860 } 861 862 static int 863 sipcom_detach(device_t self, int flags) 864 { 865 int s; 866 867 s = splnet(); 868 sipcom_do_detach(self, SIP_ATTACH_FIN); 869 splx(s); 870 871 return 0; 872 } 873 874 static void 875 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 876 { 877 int i; 878 struct sip_softc *sc = device_private(self); 879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 880 881 /* 882 * Free any resources we've allocated during attach. 883 * Do this in reverse order and fall through. 884 */ 885 switch (stage) { 886 case SIP_ATTACH_FIN: 887 sipcom_stop(ifp, 1); 888 pmf_device_deregister(self); 889 #ifdef SIP_EVENT_COUNTERS 890 /* 891 * Attach event counters. 892 */ 893 evcnt_detach(&sc->sc_ev_txforceintr); 894 evcnt_detach(&sc->sc_ev_txdstall); 895 evcnt_detach(&sc->sc_ev_txsstall); 896 evcnt_detach(&sc->sc_ev_hiberr); 897 evcnt_detach(&sc->sc_ev_rxintr); 898 evcnt_detach(&sc->sc_ev_txiintr); 899 evcnt_detach(&sc->sc_ev_txdintr); 900 if (!sc->sc_gigabit) { 901 evcnt_detach(&sc->sc_ev_rxpause); 902 } else { 903 evcnt_detach(&sc->sc_ev_txudpsum); 904 evcnt_detach(&sc->sc_ev_txtcpsum); 905 evcnt_detach(&sc->sc_ev_txipsum); 906 evcnt_detach(&sc->sc_ev_rxudpsum); 907 evcnt_detach(&sc->sc_ev_rxtcpsum); 908 evcnt_detach(&sc->sc_ev_rxipsum); 909 evcnt_detach(&sc->sc_ev_txpause); 910 evcnt_detach(&sc->sc_ev_rxpause); 911 } 912 #endif /* SIP_EVENT_COUNTERS */ 913 914 #if NRND > 0 915 rnd_detach_source(&sc->rnd_source); 916 #endif 917 918 ether_ifdetach(ifp); 919 if_detach(ifp); 920 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 921 922 /*FALLTHROUGH*/ 923 case SIP_ATTACH_CREATE_RXMAP: 924 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 925 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 926 bus_dmamap_destroy(sc->sc_dmat, 927 sc->sc_rxsoft[i].rxs_dmamap); 928 } 929 /*FALLTHROUGH*/ 930 case SIP_ATTACH_CREATE_TXMAP: 931 for (i = 0; i < SIP_TXQUEUELEN; i++) { 932 if (sc->sc_txsoft[i].txs_dmamap != NULL) 933 bus_dmamap_destroy(sc->sc_dmat, 934 sc->sc_txsoft[i].txs_dmamap); 935 } 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_LOAD_MAP: 938 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_CREATE_MAP: 941 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 942 /*FALLTHROUGH*/ 943 case SIP_ATTACH_MAP_MEM: 944 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 945 sizeof(struct sip_control_data)); 946 /*FALLTHROUGH*/ 947 case SIP_ATTACH_ALLOC_MEM: 948 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_INTR: 951 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 952 /* FALLTHROUGH*/ 953 case SIP_ATTACH_MAP: 954 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 955 break; 956 default: 957 break; 958 } 959 return; 960 } 961 962 static bool 963 sipcom_resume(device_t self, const pmf_qual_t *qual) 964 { 965 struct sip_softc *sc = device_private(self); 966 967 return sipcom_reset(sc); 968 } 969 970 static bool 971 sipcom_suspend(device_t self, const pmf_qual_t *qual) 972 { 973 struct sip_softc *sc = device_private(self); 974 975 sipcom_rxdrain(sc); 976 return true; 977 } 978 979 static void 980 sipcom_attach(device_t parent, device_t self, void *aux) 981 { 982 struct sip_softc *sc = device_private(self); 983 struct pci_attach_args *pa = aux; 984 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 985 pci_chipset_tag_t pc = pa->pa_pc; 986 pci_intr_handle_t ih; 987 const char *intrstr = NULL; 988 bus_space_tag_t iot, memt; 989 bus_space_handle_t ioh, memh; 990 bus_size_t iosz, memsz; 991 int ioh_valid, memh_valid; 992 int i, rseg, error; 993 const struct sip_product *sip; 994 u_int8_t enaddr[ETHER_ADDR_LEN]; 995 pcireg_t csr; 996 pcireg_t memtype; 997 bus_size_t tx_dmamap_size; 998 int ntxsegs_alloc; 999 cfdata_t cf = device_cfdata(self); 1000 1001 callout_init(&sc->sc_tick_ch, 0); 1002 1003 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1004 if (sip == NULL) { 1005 printf("\n"); 1006 panic("%s: impossible", __func__); 1007 } 1008 sc->sc_dev = self; 1009 sc->sc_gigabit = sip->sip_gigabit; 1010 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1011 sc->sc_pc = pc; 1012 1013 if (sc->sc_gigabit) { 1014 sc->sc_rxintr = gsip_rxintr; 1015 sc->sc_parm = &gsip_parm; 1016 } else { 1017 sc->sc_rxintr = sip_rxintr; 1018 sc->sc_parm = &sip_parm; 1019 } 1020 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1021 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1022 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1023 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1024 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1025 1026 sc->sc_rev = PCI_REVISION(pa->pa_class); 1027 1028 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1029 1030 sc->sc_model = sip; 1031 1032 /* 1033 * XXX Work-around broken PXE firmware on some boards. 1034 * 1035 * The DP83815 shares an address decoder with the MEM BAR 1036 * and the ROM BAR. Make sure the ROM BAR is disabled, 1037 * so that memory mapped access works. 1038 */ 1039 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1040 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1041 ~PCI_MAPREG_ROM_ENABLE); 1042 1043 /* 1044 * Map the device. 1045 */ 1046 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1047 PCI_MAPREG_TYPE_IO, 0, 1048 &iot, &ioh, NULL, &iosz) == 0); 1049 if (sc->sc_gigabit) { 1050 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1051 switch (memtype) { 1052 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1053 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1054 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1055 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1056 break; 1057 default: 1058 memh_valid = 0; 1059 } 1060 } else { 1061 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1062 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1063 &memt, &memh, NULL, &memsz) == 0); 1064 } 1065 1066 if (memh_valid) { 1067 sc->sc_st = memt; 1068 sc->sc_sh = memh; 1069 sc->sc_sz = memsz; 1070 } else if (ioh_valid) { 1071 sc->sc_st = iot; 1072 sc->sc_sh = ioh; 1073 sc->sc_sz = iosz; 1074 } else { 1075 printf("%s: unable to map device registers\n", 1076 device_xname(sc->sc_dev)); 1077 return; 1078 } 1079 1080 sc->sc_dmat = pa->pa_dmat; 1081 1082 /* 1083 * Make sure bus mastering is enabled. Also make sure 1084 * Write/Invalidate is enabled if we're allowed to use it. 1085 */ 1086 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1087 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1088 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1089 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1090 csr | PCI_COMMAND_MASTER_ENABLE); 1091 1092 /* power up chip */ 1093 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1094 if (error != 0 && error != EOPNOTSUPP) { 1095 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1096 return; 1097 } 1098 1099 /* 1100 * Map and establish our interrupt. 1101 */ 1102 if (pci_intr_map(pa, &ih)) { 1103 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1104 return; 1105 } 1106 intrstr = pci_intr_string(pc, ih); 1107 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1108 if (sc->sc_ih == NULL) { 1109 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1110 if (intrstr != NULL) 1111 aprint_error(" at %s", intrstr); 1112 aprint_error("\n"); 1113 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1114 } 1115 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1116 1117 SIMPLEQ_INIT(&sc->sc_txfreeq); 1118 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1119 1120 /* 1121 * Allocate the control data structures, and create and load the 1122 * DMA map for it. 1123 */ 1124 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1125 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1126 &rseg, 0)) != 0) { 1127 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1128 error); 1129 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1133 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1134 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1135 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1136 error); 1137 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1138 } 1139 1140 if ((error = bus_dmamap_create(sc->sc_dmat, 1141 sizeof(struct sip_control_data), 1, 1142 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1143 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1144 "error = %d\n", error); 1145 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1146 } 1147 1148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1149 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1150 0)) != 0) { 1151 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1152 error); 1153 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1154 } 1155 1156 /* 1157 * Create the transmit buffer DMA maps. 1158 */ 1159 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1160 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1161 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1162 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1163 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1164 "error = %d\n", i, error); 1165 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1166 } 1167 } 1168 1169 /* 1170 * Create the receive buffer DMA maps. 1171 */ 1172 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1173 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1174 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1175 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1176 "error = %d\n", i, error); 1177 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1178 } 1179 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1180 } 1181 1182 /* 1183 * Reset the chip to a known state. 1184 */ 1185 sipcom_reset(sc); 1186 1187 /* 1188 * Read the Ethernet address from the EEPROM. This might 1189 * also fetch other stuff from the EEPROM and stash it 1190 * in the softc. 1191 */ 1192 sc->sc_cfg = 0; 1193 if (!sc->sc_gigabit) { 1194 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1195 SIP_SIS900_REV(sc,SIS_REV_900B)) 1196 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1197 1198 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1199 SIP_SIS900_REV(sc,SIS_REV_960) || 1200 SIP_SIS900_REV(sc,SIS_REV_900B)) 1201 sc->sc_cfg |= 1202 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1203 CFG_EDBMASTEN); 1204 } 1205 1206 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1207 1208 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1209 ether_sprintf(enaddr)); 1210 1211 /* 1212 * Initialize the configuration register: aggressive PCI 1213 * bus request algorithm, default backoff, default OW timer, 1214 * default parity error detection. 1215 * 1216 * NOTE: "Big endian mode" is useless on the SiS900 and 1217 * friends -- it affects packet data, not descriptors. 1218 */ 1219 if (sc->sc_gigabit) 1220 sipcom_dp83820_attach(sc, pa); 1221 1222 /* 1223 * Initialize our media structures and probe the MII. 1224 */ 1225 sc->sc_mii.mii_ifp = ifp; 1226 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1227 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1228 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1229 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1230 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1231 sipcom_mediastatus); 1232 1233 /* 1234 * XXX We cannot handle flow control on the DP83815. 1235 */ 1236 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1237 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, 0); 1239 else 1240 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1241 MII_OFFSET_ANY, MIIF_DOPAUSE); 1242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1245 } else 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1247 1248 ifp = &sc->sc_ethercom.ec_if; 1249 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1250 ifp->if_softc = sc; 1251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1252 sc->sc_if_flags = ifp->if_flags; 1253 ifp->if_ioctl = sipcom_ioctl; 1254 ifp->if_start = sipcom_start; 1255 ifp->if_watchdog = sipcom_watchdog; 1256 ifp->if_init = sipcom_init; 1257 ifp->if_stop = sipcom_stop; 1258 IFQ_SET_READY(&ifp->if_snd); 1259 1260 /* 1261 * We can support 802.1Q VLAN-sized frames. 1262 */ 1263 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1264 1265 if (sc->sc_gigabit) { 1266 /* 1267 * And the DP83820 can do VLAN tagging in hardware, and 1268 * support the jumbo Ethernet MTU. 1269 */ 1270 sc->sc_ethercom.ec_capabilities |= 1271 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1272 1273 /* 1274 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1275 * in hardware. 1276 */ 1277 ifp->if_capabilities |= 1278 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1279 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1280 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1281 } 1282 1283 /* 1284 * Attach the interface. 1285 */ 1286 if_attach(ifp); 1287 ether_ifattach(ifp, enaddr); 1288 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1289 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1290 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1291 sc->sc_prev.if_capenable = ifp->if_capenable; 1292 #if NRND > 0 1293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1294 RND_TYPE_NET, 0); 1295 #endif 1296 1297 /* 1298 * The number of bytes that must be available in 1299 * the Tx FIFO before the bus master can DMA more 1300 * data into the FIFO. 1301 */ 1302 sc->sc_tx_fill_thresh = 64 / 32; 1303 1304 /* 1305 * Start at a drain threshold of 512 bytes. We will 1306 * increase it if a DMA underrun occurs. 1307 * 1308 * XXX The minimum value of this variable should be 1309 * tuned. We may be able to improve performance 1310 * by starting with a lower value. That, however, 1311 * may trash the first few outgoing packets if the 1312 * PCI bus is saturated. 1313 */ 1314 if (sc->sc_gigabit) 1315 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1316 else 1317 sc->sc_tx_drain_thresh = 1504 / 32; 1318 1319 /* 1320 * Initialize the Rx FIFO drain threshold. 1321 * 1322 * This is in units of 8 bytes. 1323 * 1324 * We should never set this value lower than 2; 14 bytes are 1325 * required to filter the packet. 1326 */ 1327 sc->sc_rx_drain_thresh = 128 / 8; 1328 1329 #ifdef SIP_EVENT_COUNTERS 1330 /* 1331 * Attach event counters. 1332 */ 1333 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1334 NULL, device_xname(sc->sc_dev), "txsstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1336 NULL, device_xname(sc->sc_dev), "txdstall"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "txforceintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txdintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "txiintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "rxintr"); 1345 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1346 NULL, device_xname(sc->sc_dev), "hiberr"); 1347 if (!sc->sc_gigabit) { 1348 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1349 NULL, device_xname(sc->sc_dev), "rxpause"); 1350 } else { 1351 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "rxpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "txpause"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "rxipsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "txipsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1365 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1366 NULL, device_xname(sc->sc_dev), "txudpsum"); 1367 } 1368 #endif /* SIP_EVENT_COUNTERS */ 1369 1370 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1371 pmf_class_network_register(self, ifp); 1372 else 1373 aprint_error_dev(self, "couldn't establish power handler\n"); 1374 } 1375 1376 static inline void 1377 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1378 uint64_t capenable) 1379 { 1380 struct m_tag *mtag; 1381 u_int32_t extsts; 1382 #ifdef DEBUG 1383 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1384 #endif 1385 /* 1386 * If VLANs are enabled and the packet has a VLAN tag, set 1387 * up the descriptor to encapsulate the packet for us. 1388 * 1389 * This apparently has to be on the last descriptor of 1390 * the packet. 1391 */ 1392 1393 /* 1394 * Byte swapping is tricky. We need to provide the tag 1395 * in a network byte order. On a big-endian machine, 1396 * the byteorder is correct, but we need to swap it 1397 * anyway, because this will be undone by the outside 1398 * htole32(). That's why there must be an 1399 * unconditional swap instead of htons() inside. 1400 */ 1401 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1402 sc->sc_txdescs[lasttx].sipd_extsts |= 1403 htole32(EXTSTS_VPKT | 1404 (bswap16(VLAN_TAG_VALUE(mtag)) & 1405 EXTSTS_VTCI)); 1406 } 1407 1408 /* 1409 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1410 * checksumming, set up the descriptor to do this work 1411 * for us. 1412 * 1413 * This apparently has to be on the first descriptor of 1414 * the packet. 1415 * 1416 * Byte-swap constants so the compiler can optimize. 1417 */ 1418 extsts = 0; 1419 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1420 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1421 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1422 extsts |= htole32(EXTSTS_IPPKT); 1423 } 1424 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1425 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1426 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1427 extsts |= htole32(EXTSTS_TCPPKT); 1428 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1429 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1430 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1431 extsts |= htole32(EXTSTS_UDPPKT); 1432 } 1433 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1434 } 1435 1436 /* 1437 * sip_start: [ifnet interface function] 1438 * 1439 * Start packet transmission on the interface. 1440 */ 1441 static void 1442 sipcom_start(struct ifnet *ifp) 1443 { 1444 struct sip_softc *sc = ifp->if_softc; 1445 struct mbuf *m0; 1446 struct mbuf *m; 1447 struct sip_txsoft *txs; 1448 bus_dmamap_t dmamap; 1449 int error, nexttx, lasttx, seg; 1450 int ofree = sc->sc_txfree; 1451 #if 0 1452 int firsttx = sc->sc_txnext; 1453 #endif 1454 1455 /* 1456 * If we've been told to pause, don't transmit any more packets. 1457 */ 1458 if (!sc->sc_gigabit && sc->sc_paused) 1459 ifp->if_flags |= IFF_OACTIVE; 1460 1461 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1462 return; 1463 1464 /* 1465 * Loop through the send queue, setting up transmit descriptors 1466 * until we drain the queue, or use up all available transmit 1467 * descriptors. 1468 */ 1469 for (;;) { 1470 /* Get a work queue entry. */ 1471 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1472 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1473 break; 1474 } 1475 1476 /* 1477 * Grab a packet off the queue. 1478 */ 1479 IFQ_POLL(&ifp->if_snd, m0); 1480 if (m0 == NULL) 1481 break; 1482 m = NULL; 1483 1484 dmamap = txs->txs_dmamap; 1485 1486 /* 1487 * Load the DMA map. If this fails, the packet either 1488 * didn't fit in the alloted number of segments, or we 1489 * were short on resources. 1490 */ 1491 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1492 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1493 /* In the non-gigabit case, we'll copy and try again. */ 1494 if (error != 0 && !sc->sc_gigabit) { 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m == NULL) { 1497 printf("%s: unable to allocate Tx mbuf\n", 1498 device_xname(sc->sc_dev)); 1499 break; 1500 } 1501 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1502 if (m0->m_pkthdr.len > MHLEN) { 1503 MCLGET(m, M_DONTWAIT); 1504 if ((m->m_flags & M_EXT) == 0) { 1505 printf("%s: unable to allocate Tx " 1506 "cluster\n", device_xname(sc->sc_dev)); 1507 m_freem(m); 1508 break; 1509 } 1510 } 1511 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1512 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1513 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1514 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1515 if (error) { 1516 printf("%s: unable to load Tx buffer, " 1517 "error = %d\n", device_xname(sc->sc_dev), error); 1518 break; 1519 } 1520 } else if (error == EFBIG) { 1521 /* 1522 * For the too-many-segments case, we simply 1523 * report an error and drop the packet, 1524 * since we can't sanely copy a jumbo packet 1525 * to a single buffer. 1526 */ 1527 printf("%s: Tx packet consumes too many " 1528 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1529 IFQ_DEQUEUE(&ifp->if_snd, m0); 1530 m_freem(m0); 1531 continue; 1532 } else if (error != 0) { 1533 /* 1534 * Short on resources, just stop for now. 1535 */ 1536 break; 1537 } 1538 1539 /* 1540 * Ensure we have enough descriptors free to describe 1541 * the packet. Note, we always reserve one descriptor 1542 * at the end of the ring as a termination point, to 1543 * prevent wrap-around. 1544 */ 1545 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1546 /* 1547 * Not enough free descriptors to transmit this 1548 * packet. We haven't committed anything yet, 1549 * so just unload the DMA map, put the packet 1550 * back on the queue, and punt. Notify the upper 1551 * layer that there are not more slots left. 1552 * 1553 * XXX We could allocate an mbuf and copy, but 1554 * XXX is it worth it? 1555 */ 1556 ifp->if_flags |= IFF_OACTIVE; 1557 bus_dmamap_unload(sc->sc_dmat, dmamap); 1558 if (m != NULL) 1559 m_freem(m); 1560 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1561 break; 1562 } 1563 1564 IFQ_DEQUEUE(&ifp->if_snd, m0); 1565 if (m != NULL) { 1566 m_freem(m0); 1567 m0 = m; 1568 } 1569 1570 /* 1571 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1572 */ 1573 1574 /* Sync the DMA map. */ 1575 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1576 BUS_DMASYNC_PREWRITE); 1577 1578 /* 1579 * Initialize the transmit descriptors. 1580 */ 1581 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1582 seg < dmamap->dm_nsegs; 1583 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1584 /* 1585 * If this is the first descriptor we're 1586 * enqueueing, don't set the OWN bit just 1587 * yet. That could cause a race condition. 1588 * We'll do it below. 1589 */ 1590 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1591 htole32(dmamap->dm_segs[seg].ds_addr); 1592 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1593 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1594 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1595 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1596 lasttx = nexttx; 1597 } 1598 1599 /* Clear the MORE bit on the last segment. */ 1600 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1601 htole32(~CMDSTS_MORE); 1602 1603 /* 1604 * If we're in the interrupt delay window, delay the 1605 * interrupt. 1606 */ 1607 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1608 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1609 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1610 htole32(CMDSTS_INTR); 1611 sc->sc_txwin = 0; 1612 } 1613 1614 if (sc->sc_gigabit) 1615 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1616 1617 /* Sync the descriptors we're using. */ 1618 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1619 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1620 1621 /* 1622 * The entire packet is set up. Give the first descrptor 1623 * to the chip now. 1624 */ 1625 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1626 htole32(CMDSTS_OWN); 1627 sip_cdtxsync(sc, sc->sc_txnext, 1, 1628 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1629 1630 /* 1631 * Store a pointer to the packet so we can free it later, 1632 * and remember what txdirty will be once the packet is 1633 * done. 1634 */ 1635 txs->txs_mbuf = m0; 1636 txs->txs_firstdesc = sc->sc_txnext; 1637 txs->txs_lastdesc = lasttx; 1638 1639 /* Advance the tx pointer. */ 1640 sc->sc_txfree -= dmamap->dm_nsegs; 1641 sc->sc_txnext = nexttx; 1642 1643 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1644 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1645 1646 /* 1647 * Pass the packet to any BPF listeners. 1648 */ 1649 bpf_mtap(ifp, m0); 1650 } 1651 1652 if (txs == NULL || sc->sc_txfree == 0) { 1653 /* No more slots left; notify upper layer. */ 1654 ifp->if_flags |= IFF_OACTIVE; 1655 } 1656 1657 if (sc->sc_txfree != ofree) { 1658 /* 1659 * Start the transmit process. Note, the manual says 1660 * that if there are no pending transmissions in the 1661 * chip's internal queue (indicated by TXE being clear), 1662 * then the driver software must set the TXDP to the 1663 * first descriptor to be transmitted. However, if we 1664 * do this, it causes serious performance degredation on 1665 * the DP83820 under load, not setting TXDP doesn't seem 1666 * to adversely affect the SiS 900 or DP83815. 1667 * 1668 * Well, I guess it wouldn't be the first time a manual 1669 * has lied -- and they could be speaking of the NULL- 1670 * terminated descriptor list case, rather than OWN- 1671 * terminated rings. 1672 */ 1673 #if 0 1674 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1675 CR_TXE) == 0) { 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1677 SIP_CDTXADDR(sc, firsttx)); 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1679 } 1680 #else 1681 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1682 #endif 1683 1684 /* Set a watchdog timer in case the chip flakes out. */ 1685 /* Gigabit autonegotiation takes 5 seconds. */ 1686 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1687 } 1688 } 1689 1690 /* 1691 * sip_watchdog: [ifnet interface function] 1692 * 1693 * Watchdog timer handler. 1694 */ 1695 static void 1696 sipcom_watchdog(struct ifnet *ifp) 1697 { 1698 struct sip_softc *sc = ifp->if_softc; 1699 1700 /* 1701 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1702 * If we get a timeout, try and sweep up transmit descriptors. 1703 * If we manage to sweep them all up, ignore the lack of 1704 * interrupt. 1705 */ 1706 sipcom_txintr(sc); 1707 1708 if (sc->sc_txfree != sc->sc_ntxdesc) { 1709 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1710 ifp->if_oerrors++; 1711 1712 /* Reset the interface. */ 1713 (void) sipcom_init(ifp); 1714 } else if (ifp->if_flags & IFF_DEBUG) 1715 printf("%s: recovered from device timeout\n", 1716 device_xname(sc->sc_dev)); 1717 1718 /* Try to get more packets going. */ 1719 sipcom_start(ifp); 1720 } 1721 1722 /* If the interface is up and running, only modify the receive 1723 * filter when setting promiscuous or debug mode. Otherwise fall 1724 * through to ether_ioctl, which will reset the chip. 1725 */ 1726 static int 1727 sip_ifflags_cb(struct ethercom *ec) 1728 { 1729 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1730 == (sc)->sc_ethercom.ec_capenable) \ 1731 && ((sc)->sc_prev.is_vlan == \ 1732 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1733 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1734 struct ifnet *ifp = &ec->ec_if; 1735 struct sip_softc *sc = ifp->if_softc; 1736 int change = ifp->if_flags ^ sc->sc_if_flags; 1737 1738 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1739 !COMPARE_IC(sc, ifp)) 1740 return ENETRESET; 1741 /* Set up the receive filter. */ 1742 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1743 return 0; 1744 } 1745 1746 /* 1747 * sip_ioctl: [ifnet interface function] 1748 * 1749 * Handle control requests from the operator. 1750 */ 1751 static int 1752 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1753 { 1754 struct sip_softc *sc = ifp->if_softc; 1755 struct ifreq *ifr = (struct ifreq *)data; 1756 int s, error; 1757 1758 s = splnet(); 1759 1760 switch (cmd) { 1761 case SIOCSIFMEDIA: 1762 /* Flow control requires full-duplex mode. */ 1763 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1764 (ifr->ifr_media & IFM_FDX) == 0) 1765 ifr->ifr_media &= ~IFM_ETH_FMASK; 1766 1767 /* XXX */ 1768 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1769 ifr->ifr_media &= ~IFM_ETH_FMASK; 1770 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1771 if (sc->sc_gigabit && 1772 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1773 /* We can do both TXPAUSE and RXPAUSE. */ 1774 ifr->ifr_media |= 1775 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1776 } else if (ifr->ifr_media & IFM_FLOW) { 1777 /* 1778 * Both TXPAUSE and RXPAUSE must be set. 1779 * (SiS900 and DP83815 don't have PAUSE_ASYM 1780 * feature.) 1781 * 1782 * XXX Can SiS900 and DP83815 send PAUSE? 1783 */ 1784 ifr->ifr_media |= 1785 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1786 } 1787 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1788 } 1789 /*FALLTHROUGH*/ 1790 default: 1791 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1792 break; 1793 1794 error = 0; 1795 1796 if (cmd == SIOCSIFCAP) 1797 error = (*ifp->if_init)(ifp); 1798 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1799 ; 1800 else if (ifp->if_flags & IFF_RUNNING) { 1801 /* 1802 * Multicast list has changed; set the hardware filter 1803 * accordingly. 1804 */ 1805 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1806 } 1807 break; 1808 } 1809 1810 /* Try to get more packets going. */ 1811 sipcom_start(ifp); 1812 1813 sc->sc_if_flags = ifp->if_flags; 1814 splx(s); 1815 return (error); 1816 } 1817 1818 /* 1819 * sip_intr: 1820 * 1821 * Interrupt service routine. 1822 */ 1823 static int 1824 sipcom_intr(void *arg) 1825 { 1826 struct sip_softc *sc = arg; 1827 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1828 u_int32_t isr; 1829 int handled = 0; 1830 1831 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1832 return 0; 1833 1834 /* Disable interrupts. */ 1835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1836 1837 for (;;) { 1838 /* Reading clears interrupt. */ 1839 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1840 if ((isr & sc->sc_imr) == 0) 1841 break; 1842 1843 #if NRND > 0 1844 if (RND_ENABLED(&sc->rnd_source)) 1845 rnd_add_uint32(&sc->rnd_source, isr); 1846 #endif 1847 1848 handled = 1; 1849 1850 if ((ifp->if_flags & IFF_RUNNING) == 0) 1851 break; 1852 1853 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1854 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1855 1856 /* Grab any new packets. */ 1857 (*sc->sc_rxintr)(sc); 1858 1859 if (isr & ISR_RXORN) { 1860 printf("%s: receive FIFO overrun\n", 1861 device_xname(sc->sc_dev)); 1862 1863 /* XXX adjust rx_drain_thresh? */ 1864 } 1865 1866 if (isr & ISR_RXIDLE) { 1867 printf("%s: receive ring overrun\n", 1868 device_xname(sc->sc_dev)); 1869 1870 /* Get the receive process going again. */ 1871 bus_space_write_4(sc->sc_st, sc->sc_sh, 1872 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1873 bus_space_write_4(sc->sc_st, sc->sc_sh, 1874 SIP_CR, CR_RXE); 1875 } 1876 } 1877 1878 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1879 #ifdef SIP_EVENT_COUNTERS 1880 if (isr & ISR_TXDESC) 1881 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1882 else if (isr & ISR_TXIDLE) 1883 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1884 #endif 1885 1886 /* Sweep up transmit descriptors. */ 1887 sipcom_txintr(sc); 1888 1889 if (isr & ISR_TXURN) { 1890 u_int32_t thresh; 1891 int txfifo_size = (sc->sc_gigabit) 1892 ? DP83820_SIP_TXFIFO_SIZE 1893 : OTHER_SIP_TXFIFO_SIZE; 1894 1895 printf("%s: transmit FIFO underrun", 1896 device_xname(sc->sc_dev)); 1897 thresh = sc->sc_tx_drain_thresh + 1; 1898 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1899 && (thresh * 32) <= (txfifo_size - 1900 (sc->sc_tx_fill_thresh * 32))) { 1901 printf("; increasing Tx drain " 1902 "threshold to %u bytes\n", 1903 thresh * 32); 1904 sc->sc_tx_drain_thresh = thresh; 1905 (void) sipcom_init(ifp); 1906 } else { 1907 (void) sipcom_init(ifp); 1908 printf("\n"); 1909 } 1910 } 1911 } 1912 1913 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1914 if (isr & ISR_PAUSE_ST) { 1915 sc->sc_paused = 1; 1916 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1917 ifp->if_flags |= IFF_OACTIVE; 1918 } 1919 if (isr & ISR_PAUSE_END) { 1920 sc->sc_paused = 0; 1921 ifp->if_flags &= ~IFF_OACTIVE; 1922 } 1923 } 1924 1925 if (isr & ISR_HIBERR) { 1926 int want_init = 0; 1927 1928 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1929 1930 #define PRINTERR(bit, str) \ 1931 do { \ 1932 if ((isr & (bit)) != 0) { \ 1933 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1934 printf("%s: %s\n", \ 1935 device_xname(sc->sc_dev), str); \ 1936 want_init = 1; \ 1937 } \ 1938 } while (/*CONSTCOND*/0) 1939 1940 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1941 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1942 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1943 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1944 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1945 /* 1946 * Ignore: 1947 * Tx reset complete 1948 * Rx reset complete 1949 */ 1950 if (want_init) 1951 (void) sipcom_init(ifp); 1952 #undef PRINTERR 1953 } 1954 } 1955 1956 /* Re-enable interrupts. */ 1957 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1958 1959 /* Try to get more packets going. */ 1960 sipcom_start(ifp); 1961 1962 return (handled); 1963 } 1964 1965 /* 1966 * sip_txintr: 1967 * 1968 * Helper; handle transmit interrupts. 1969 */ 1970 static void 1971 sipcom_txintr(struct sip_softc *sc) 1972 { 1973 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1974 struct sip_txsoft *txs; 1975 u_int32_t cmdsts; 1976 1977 if (sc->sc_paused == 0) 1978 ifp->if_flags &= ~IFF_OACTIVE; 1979 1980 /* 1981 * Go through our Tx list and free mbufs for those 1982 * frames which have been transmitted. 1983 */ 1984 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1985 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1986 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1987 1988 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1989 if (cmdsts & CMDSTS_OWN) 1990 break; 1991 1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1993 1994 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1995 1996 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1997 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1998 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1999 m_freem(txs->txs_mbuf); 2000 txs->txs_mbuf = NULL; 2001 2002 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2003 2004 /* 2005 * Check for errors and collisions. 2006 */ 2007 if (cmdsts & 2008 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2009 ifp->if_oerrors++; 2010 if (cmdsts & CMDSTS_Tx_EC) 2011 ifp->if_collisions += 16; 2012 if (ifp->if_flags & IFF_DEBUG) { 2013 if (cmdsts & CMDSTS_Tx_ED) 2014 printf("%s: excessive deferral\n", 2015 device_xname(sc->sc_dev)); 2016 if (cmdsts & CMDSTS_Tx_EC) 2017 printf("%s: excessive collisions\n", 2018 device_xname(sc->sc_dev)); 2019 } 2020 } else { 2021 /* Packet was transmitted successfully. */ 2022 ifp->if_opackets++; 2023 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2024 } 2025 } 2026 2027 /* 2028 * If there are no more pending transmissions, cancel the watchdog 2029 * timer. 2030 */ 2031 if (txs == NULL) { 2032 ifp->if_timer = 0; 2033 sc->sc_txwin = 0; 2034 } 2035 } 2036 2037 /* 2038 * gsip_rxintr: 2039 * 2040 * Helper; handle receive interrupts on gigabit parts. 2041 */ 2042 static void 2043 gsip_rxintr(struct sip_softc *sc) 2044 { 2045 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2046 struct sip_rxsoft *rxs; 2047 struct mbuf *m; 2048 u_int32_t cmdsts, extsts; 2049 int i, len; 2050 2051 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2052 rxs = &sc->sc_rxsoft[i]; 2053 2054 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2055 2056 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2057 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2058 len = CMDSTS_SIZE(sc, cmdsts); 2059 2060 /* 2061 * NOTE: OWN is set if owned by _consumer_. We're the 2062 * consumer of the receive ring, so if the bit is clear, 2063 * we have processed all of the packets. 2064 */ 2065 if ((cmdsts & CMDSTS_OWN) == 0) { 2066 /* 2067 * We have processed all of the receive buffers. 2068 */ 2069 break; 2070 } 2071 2072 if (__predict_false(sc->sc_rxdiscard)) { 2073 sip_init_rxdesc(sc, i); 2074 if ((cmdsts & CMDSTS_MORE) == 0) { 2075 /* Reset our state. */ 2076 sc->sc_rxdiscard = 0; 2077 } 2078 continue; 2079 } 2080 2081 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2082 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2083 2084 m = rxs->rxs_mbuf; 2085 2086 /* 2087 * Add a new receive buffer to the ring. 2088 */ 2089 if (sipcom_add_rxbuf(sc, i) != 0) { 2090 /* 2091 * Failed, throw away what we've done so 2092 * far, and discard the rest of the packet. 2093 */ 2094 ifp->if_ierrors++; 2095 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2096 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2097 sip_init_rxdesc(sc, i); 2098 if (cmdsts & CMDSTS_MORE) 2099 sc->sc_rxdiscard = 1; 2100 if (sc->sc_rxhead != NULL) 2101 m_freem(sc->sc_rxhead); 2102 sip_rxchain_reset(sc); 2103 continue; 2104 } 2105 2106 sip_rxchain_link(sc, m); 2107 2108 m->m_len = len; 2109 2110 /* 2111 * If this is not the end of the packet, keep 2112 * looking. 2113 */ 2114 if (cmdsts & CMDSTS_MORE) { 2115 sc->sc_rxlen += len; 2116 continue; 2117 } 2118 2119 /* 2120 * Okay, we have the entire packet now. The chip includes 2121 * the FCS, so we need to trim it. 2122 */ 2123 m->m_len -= ETHER_CRC_LEN; 2124 2125 *sc->sc_rxtailp = NULL; 2126 len = m->m_len + sc->sc_rxlen; 2127 m = sc->sc_rxhead; 2128 2129 sip_rxchain_reset(sc); 2130 2131 /* 2132 * If an error occurred, update stats and drop the packet. 2133 */ 2134 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2135 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2136 ifp->if_ierrors++; 2137 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2138 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2139 /* Receive overrun handled elsewhere. */ 2140 printf("%s: receive descriptor error\n", 2141 device_xname(sc->sc_dev)); 2142 } 2143 #define PRINTERR(bit, str) \ 2144 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2145 (cmdsts & (bit)) != 0) \ 2146 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2147 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2148 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2149 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2150 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2151 #undef PRINTERR 2152 m_freem(m); 2153 continue; 2154 } 2155 2156 /* 2157 * If the packet is small enough to fit in a 2158 * single header mbuf, allocate one and copy 2159 * the data into it. This greatly reduces 2160 * memory consumption when we receive lots 2161 * of small packets. 2162 */ 2163 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2164 struct mbuf *nm; 2165 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2166 if (nm == NULL) { 2167 ifp->if_ierrors++; 2168 m_freem(m); 2169 continue; 2170 } 2171 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2172 nm->m_data += 2; 2173 nm->m_pkthdr.len = nm->m_len = len; 2174 m_copydata(m, 0, len, mtod(nm, void *)); 2175 m_freem(m); 2176 m = nm; 2177 } 2178 #ifndef __NO_STRICT_ALIGNMENT 2179 else { 2180 /* 2181 * The DP83820's receive buffers must be 4-byte 2182 * aligned. But this means that the data after 2183 * the Ethernet header is misaligned. To compensate, 2184 * we have artificially shortened the buffer size 2185 * in the descriptor, and we do an overlapping copy 2186 * of the data two bytes further in (in the first 2187 * buffer of the chain only). 2188 */ 2189 memmove(mtod(m, char *) + 2, mtod(m, void *), 2190 m->m_len); 2191 m->m_data += 2; 2192 } 2193 #endif /* ! __NO_STRICT_ALIGNMENT */ 2194 2195 /* 2196 * If VLANs are enabled, VLAN packets have been unwrapped 2197 * for us. Associate the tag with the packet. 2198 */ 2199 2200 /* 2201 * Again, byte swapping is tricky. Hardware provided 2202 * the tag in the network byte order, but extsts was 2203 * passed through le32toh() in the meantime. On a 2204 * big-endian machine, we need to swap it again. On a 2205 * little-endian machine, we need to convert from the 2206 * network to host byte order. This means that we must 2207 * swap it in any case, so unconditional swap instead 2208 * of htons() is used. 2209 */ 2210 if ((extsts & EXTSTS_VPKT) != 0) { 2211 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2212 continue); 2213 } 2214 2215 /* 2216 * Set the incoming checksum information for the 2217 * packet. 2218 */ 2219 if ((extsts & EXTSTS_IPPKT) != 0) { 2220 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2221 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2222 if (extsts & EXTSTS_Rx_IPERR) 2223 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2224 if (extsts & EXTSTS_TCPPKT) { 2225 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2226 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2227 if (extsts & EXTSTS_Rx_TCPERR) 2228 m->m_pkthdr.csum_flags |= 2229 M_CSUM_TCP_UDP_BAD; 2230 } else if (extsts & EXTSTS_UDPPKT) { 2231 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2232 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2233 if (extsts & EXTSTS_Rx_UDPERR) 2234 m->m_pkthdr.csum_flags |= 2235 M_CSUM_TCP_UDP_BAD; 2236 } 2237 } 2238 2239 ifp->if_ipackets++; 2240 m->m_pkthdr.rcvif = ifp; 2241 m->m_pkthdr.len = len; 2242 2243 /* 2244 * Pass this up to any BPF listeners, but only 2245 * pass if up the stack if it's for us. 2246 */ 2247 bpf_mtap(ifp, m); 2248 2249 /* Pass it on. */ 2250 (*ifp->if_input)(ifp, m); 2251 } 2252 2253 /* Update the receive pointer. */ 2254 sc->sc_rxptr = i; 2255 } 2256 2257 /* 2258 * sip_rxintr: 2259 * 2260 * Helper; handle receive interrupts on 10/100 parts. 2261 */ 2262 static void 2263 sip_rxintr(struct sip_softc *sc) 2264 { 2265 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2266 struct sip_rxsoft *rxs; 2267 struct mbuf *m; 2268 u_int32_t cmdsts; 2269 int i, len; 2270 2271 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2272 rxs = &sc->sc_rxsoft[i]; 2273 2274 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2275 2276 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2277 2278 /* 2279 * NOTE: OWN is set if owned by _consumer_. We're the 2280 * consumer of the receive ring, so if the bit is clear, 2281 * we have processed all of the packets. 2282 */ 2283 if ((cmdsts & CMDSTS_OWN) == 0) { 2284 /* 2285 * We have processed all of the receive buffers. 2286 */ 2287 break; 2288 } 2289 2290 /* 2291 * If any collisions were seen on the wire, count one. 2292 */ 2293 if (cmdsts & CMDSTS_Rx_COL) 2294 ifp->if_collisions++; 2295 2296 /* 2297 * If an error occurred, update stats, clear the status 2298 * word, and leave the packet buffer in place. It will 2299 * simply be reused the next time the ring comes around. 2300 */ 2301 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2302 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2303 ifp->if_ierrors++; 2304 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2305 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2306 /* Receive overrun handled elsewhere. */ 2307 printf("%s: receive descriptor error\n", 2308 device_xname(sc->sc_dev)); 2309 } 2310 #define PRINTERR(bit, str) \ 2311 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2312 (cmdsts & (bit)) != 0) \ 2313 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2314 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2315 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2316 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2317 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2318 #undef PRINTERR 2319 sip_init_rxdesc(sc, i); 2320 continue; 2321 } 2322 2323 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2324 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2325 2326 /* 2327 * No errors; receive the packet. Note, the SiS 900 2328 * includes the CRC with every packet. 2329 */ 2330 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2331 2332 #ifdef __NO_STRICT_ALIGNMENT 2333 /* 2334 * If the packet is small enough to fit in a 2335 * single header mbuf, allocate one and copy 2336 * the data into it. This greatly reduces 2337 * memory consumption when we receive lots 2338 * of small packets. 2339 * 2340 * Otherwise, we add a new buffer to the receive 2341 * chain. If this fails, we drop the packet and 2342 * recycle the old buffer. 2343 */ 2344 if (sip_copy_small != 0 && len <= MHLEN) { 2345 MGETHDR(m, M_DONTWAIT, MT_DATA); 2346 if (m == NULL) 2347 goto dropit; 2348 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2349 memcpy(mtod(m, void *), 2350 mtod(rxs->rxs_mbuf, void *), len); 2351 sip_init_rxdesc(sc, i); 2352 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2353 rxs->rxs_dmamap->dm_mapsize, 2354 BUS_DMASYNC_PREREAD); 2355 } else { 2356 m = rxs->rxs_mbuf; 2357 if (sipcom_add_rxbuf(sc, i) != 0) { 2358 dropit: 2359 ifp->if_ierrors++; 2360 sip_init_rxdesc(sc, i); 2361 bus_dmamap_sync(sc->sc_dmat, 2362 rxs->rxs_dmamap, 0, 2363 rxs->rxs_dmamap->dm_mapsize, 2364 BUS_DMASYNC_PREREAD); 2365 continue; 2366 } 2367 } 2368 #else 2369 /* 2370 * The SiS 900's receive buffers must be 4-byte aligned. 2371 * But this means that the data after the Ethernet header 2372 * is misaligned. We must allocate a new buffer and 2373 * copy the data, shifted forward 2 bytes. 2374 */ 2375 MGETHDR(m, M_DONTWAIT, MT_DATA); 2376 if (m == NULL) { 2377 dropit: 2378 ifp->if_ierrors++; 2379 sip_init_rxdesc(sc, i); 2380 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2381 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2382 continue; 2383 } 2384 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2385 if (len > (MHLEN - 2)) { 2386 MCLGET(m, M_DONTWAIT); 2387 if ((m->m_flags & M_EXT) == 0) { 2388 m_freem(m); 2389 goto dropit; 2390 } 2391 } 2392 m->m_data += 2; 2393 2394 /* 2395 * Note that we use clusters for incoming frames, so the 2396 * buffer is virtually contiguous. 2397 */ 2398 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2399 2400 /* Allow the receive descriptor to continue using its mbuf. */ 2401 sip_init_rxdesc(sc, i); 2402 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2403 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2404 #endif /* __NO_STRICT_ALIGNMENT */ 2405 2406 ifp->if_ipackets++; 2407 m->m_pkthdr.rcvif = ifp; 2408 m->m_pkthdr.len = m->m_len = len; 2409 2410 /* 2411 * Pass this up to any BPF listeners, but only 2412 * pass if up the stack if it's for us. 2413 */ 2414 bpf_mtap(ifp, m); 2415 2416 /* Pass it on. */ 2417 (*ifp->if_input)(ifp, m); 2418 } 2419 2420 /* Update the receive pointer. */ 2421 sc->sc_rxptr = i; 2422 } 2423 2424 /* 2425 * sip_tick: 2426 * 2427 * One second timer, used to tick the MII. 2428 */ 2429 static void 2430 sipcom_tick(void *arg) 2431 { 2432 struct sip_softc *sc = arg; 2433 int s; 2434 2435 s = splnet(); 2436 #ifdef SIP_EVENT_COUNTERS 2437 if (sc->sc_gigabit) { 2438 /* Read PAUSE related counts from MIB registers. */ 2439 sc->sc_ev_rxpause.ev_count += 2440 bus_space_read_4(sc->sc_st, sc->sc_sh, 2441 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2442 sc->sc_ev_txpause.ev_count += 2443 bus_space_read_4(sc->sc_st, sc->sc_sh, 2444 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2445 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2446 } 2447 #endif /* SIP_EVENT_COUNTERS */ 2448 mii_tick(&sc->sc_mii); 2449 splx(s); 2450 2451 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2452 } 2453 2454 /* 2455 * sip_reset: 2456 * 2457 * Perform a soft reset on the SiS 900. 2458 */ 2459 static bool 2460 sipcom_reset(struct sip_softc *sc) 2461 { 2462 bus_space_tag_t st = sc->sc_st; 2463 bus_space_handle_t sh = sc->sc_sh; 2464 int i; 2465 2466 bus_space_write_4(st, sh, SIP_IER, 0); 2467 bus_space_write_4(st, sh, SIP_IMR, 0); 2468 bus_space_write_4(st, sh, SIP_RFCR, 0); 2469 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2470 2471 for (i = 0; i < SIP_TIMEOUT; i++) { 2472 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2473 break; 2474 delay(2); 2475 } 2476 2477 if (i == SIP_TIMEOUT) { 2478 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2479 return false; 2480 } 2481 2482 delay(1000); 2483 2484 if (sc->sc_gigabit) { 2485 /* 2486 * Set the general purpose I/O bits. Do it here in case we 2487 * need to have GPIO set up to talk to the media interface. 2488 */ 2489 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2490 delay(1000); 2491 } 2492 return true; 2493 } 2494 2495 static void 2496 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2497 { 2498 u_int32_t reg; 2499 bus_space_tag_t st = sc->sc_st; 2500 bus_space_handle_t sh = sc->sc_sh; 2501 /* 2502 * Initialize the VLAN/IP receive control register. 2503 * We enable checksum computation on all incoming 2504 * packets, and do not reject packets w/ bad checksums. 2505 */ 2506 reg = 0; 2507 if (capenable & 2508 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2509 reg |= VRCR_IPEN; 2510 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2511 reg |= VRCR_VTDEN|VRCR_VTREN; 2512 bus_space_write_4(st, sh, SIP_VRCR, reg); 2513 2514 /* 2515 * Initialize the VLAN/IP transmit control register. 2516 * We enable outgoing checksum computation on a 2517 * per-packet basis. 2518 */ 2519 reg = 0; 2520 if (capenable & 2521 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2522 reg |= VTCR_PPCHK; 2523 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2524 reg |= VTCR_VPPTI; 2525 bus_space_write_4(st, sh, SIP_VTCR, reg); 2526 2527 /* 2528 * If we're using VLANs, initialize the VLAN data register. 2529 * To understand why we bswap the VLAN Ethertype, see section 2530 * 4.2.36 of the DP83820 manual. 2531 */ 2532 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2533 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2534 } 2535 2536 /* 2537 * sip_init: [ ifnet interface function ] 2538 * 2539 * Initialize the interface. Must be called at splnet(). 2540 */ 2541 static int 2542 sipcom_init(struct ifnet *ifp) 2543 { 2544 struct sip_softc *sc = ifp->if_softc; 2545 bus_space_tag_t st = sc->sc_st; 2546 bus_space_handle_t sh = sc->sc_sh; 2547 struct sip_txsoft *txs; 2548 struct sip_rxsoft *rxs; 2549 struct sip_desc *sipd; 2550 int i, error = 0; 2551 2552 if (device_is_active(sc->sc_dev)) { 2553 /* 2554 * Cancel any pending I/O. 2555 */ 2556 sipcom_stop(ifp, 0); 2557 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2558 !device_is_active(sc->sc_dev)) 2559 return 0; 2560 2561 /* 2562 * Reset the chip to a known state. 2563 */ 2564 if (!sipcom_reset(sc)) 2565 return EBUSY; 2566 2567 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2568 /* 2569 * DP83815 manual, page 78: 2570 * 4.4 Recommended Registers Configuration 2571 * For optimum performance of the DP83815, version noted 2572 * as DP83815CVNG (SRR = 203h), the listed register 2573 * modifications must be followed in sequence... 2574 * 2575 * It's not clear if this should be 302h or 203h because that 2576 * chip name is listed as SRR 302h in the description of the 2577 * SRR register. However, my revision 302h DP83815 on the 2578 * Netgear FA311 purchased in 02/2001 needs these settings 2579 * to avoid tons of errors in AcceptPerfectMatch (non- 2580 * IFF_PROMISC) mode. I do not know if other revisions need 2581 * this set or not. [briggs -- 09 March 2001] 2582 * 2583 * Note that only the low-order 12 bits of 0xe4 are documented 2584 * and that this sets reserved bits in that register. 2585 */ 2586 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2587 2588 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2589 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2590 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2591 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2592 2593 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2594 } 2595 2596 /* 2597 * Initialize the transmit descriptor ring. 2598 */ 2599 for (i = 0; i < sc->sc_ntxdesc; i++) { 2600 sipd = &sc->sc_txdescs[i]; 2601 memset(sipd, 0, sizeof(struct sip_desc)); 2602 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2603 } 2604 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2605 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2606 sc->sc_txfree = sc->sc_ntxdesc; 2607 sc->sc_txnext = 0; 2608 sc->sc_txwin = 0; 2609 2610 /* 2611 * Initialize the transmit job descriptors. 2612 */ 2613 SIMPLEQ_INIT(&sc->sc_txfreeq); 2614 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2615 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2616 txs = &sc->sc_txsoft[i]; 2617 txs->txs_mbuf = NULL; 2618 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2619 } 2620 2621 /* 2622 * Initialize the receive descriptor and receive job 2623 * descriptor rings. 2624 */ 2625 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2626 rxs = &sc->sc_rxsoft[i]; 2627 if (rxs->rxs_mbuf == NULL) { 2628 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2629 printf("%s: unable to allocate or map rx " 2630 "buffer %d, error = %d\n", 2631 device_xname(sc->sc_dev), i, error); 2632 /* 2633 * XXX Should attempt to run with fewer receive 2634 * XXX buffers instead of just failing. 2635 */ 2636 sipcom_rxdrain(sc); 2637 goto out; 2638 } 2639 } else 2640 sip_init_rxdesc(sc, i); 2641 } 2642 sc->sc_rxptr = 0; 2643 sc->sc_rxdiscard = 0; 2644 sip_rxchain_reset(sc); 2645 2646 /* 2647 * Set the configuration register; it's already initialized 2648 * in sip_attach(). 2649 */ 2650 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2651 2652 /* 2653 * Initialize the prototype TXCFG register. 2654 */ 2655 if (sc->sc_gigabit) { 2656 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2657 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2658 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2659 SIP_SIS900_REV(sc, SIS_REV_960) || 2660 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2661 (sc->sc_cfg & CFG_EDBMASTEN)) { 2662 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2663 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2664 } else { 2665 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2666 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2667 } 2668 2669 sc->sc_txcfg |= TXCFG_ATP | 2670 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2671 sc->sc_tx_drain_thresh; 2672 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2673 2674 /* 2675 * Initialize the receive drain threshold if we have never 2676 * done so. 2677 */ 2678 if (sc->sc_rx_drain_thresh == 0) { 2679 /* 2680 * XXX This value should be tuned. This is set to the 2681 * maximum of 248 bytes, and we may be able to improve 2682 * performance by decreasing it (although we should never 2683 * set this value lower than 2; 14 bytes are required to 2684 * filter the packet). 2685 */ 2686 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2687 } 2688 2689 /* 2690 * Initialize the prototype RXCFG register. 2691 */ 2692 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2693 /* 2694 * Accept long packets (including FCS) so we can handle 2695 * 802.1q-tagged frames and jumbo frames properly. 2696 */ 2697 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2698 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2699 sc->sc_rxcfg |= RXCFG_ALP; 2700 2701 /* 2702 * Checksum offloading is disabled if the user selects an MTU 2703 * larger than 8109. (FreeBSD says 8152, but there is emperical 2704 * evidence that >8109 does not work on some boards, such as the 2705 * Planex GN-1000TE). 2706 */ 2707 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2708 (ifp->if_capenable & 2709 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2710 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2711 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2712 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2713 "disabled.\n", device_xname(sc->sc_dev)); 2714 ifp->if_capenable &= 2715 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2716 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2717 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2718 ifp->if_csum_flags_tx = 0; 2719 ifp->if_csum_flags_rx = 0; 2720 } 2721 2722 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2723 2724 if (sc->sc_gigabit) 2725 sipcom_dp83820_init(sc, ifp->if_capenable); 2726 2727 /* 2728 * Give the transmit and receive rings to the chip. 2729 */ 2730 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2731 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2732 2733 /* 2734 * Initialize the interrupt mask. 2735 */ 2736 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2737 sc->sc_bits.b_isr_sserr | 2738 sc->sc_bits.b_isr_rmabt | 2739 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2740 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2741 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2742 2743 /* Set up the receive filter. */ 2744 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2745 2746 /* 2747 * Tune sc_rx_flow_thresh. 2748 * XXX "More than 8KB" is too short for jumbo frames. 2749 * XXX TODO: Threshold value should be user-settable. 2750 */ 2751 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2752 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2753 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2754 2755 /* 2756 * Set the current media. Do this after initializing the prototype 2757 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2758 * control. 2759 */ 2760 if ((error = ether_mediachange(ifp)) != 0) 2761 goto out; 2762 2763 /* 2764 * Set the interrupt hold-off timer to 100us. 2765 */ 2766 if (sc->sc_gigabit) 2767 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2768 2769 /* 2770 * Enable interrupts. 2771 */ 2772 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2773 2774 /* 2775 * Start the transmit and receive processes. 2776 */ 2777 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2778 2779 /* 2780 * Start the one second MII clock. 2781 */ 2782 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2783 2784 /* 2785 * ...all done! 2786 */ 2787 ifp->if_flags |= IFF_RUNNING; 2788 ifp->if_flags &= ~IFF_OACTIVE; 2789 sc->sc_if_flags = ifp->if_flags; 2790 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2791 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2792 sc->sc_prev.if_capenable = ifp->if_capenable; 2793 2794 out: 2795 if (error) 2796 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2797 return (error); 2798 } 2799 2800 /* 2801 * sip_drain: 2802 * 2803 * Drain the receive queue. 2804 */ 2805 static void 2806 sipcom_rxdrain(struct sip_softc *sc) 2807 { 2808 struct sip_rxsoft *rxs; 2809 int i; 2810 2811 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2812 rxs = &sc->sc_rxsoft[i]; 2813 if (rxs->rxs_mbuf != NULL) { 2814 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2815 m_freem(rxs->rxs_mbuf); 2816 rxs->rxs_mbuf = NULL; 2817 } 2818 } 2819 } 2820 2821 /* 2822 * sip_stop: [ ifnet interface function ] 2823 * 2824 * Stop transmission on the interface. 2825 */ 2826 static void 2827 sipcom_stop(struct ifnet *ifp, int disable) 2828 { 2829 struct sip_softc *sc = ifp->if_softc; 2830 bus_space_tag_t st = sc->sc_st; 2831 bus_space_handle_t sh = sc->sc_sh; 2832 struct sip_txsoft *txs; 2833 u_int32_t cmdsts = 0; /* DEBUG */ 2834 2835 /* 2836 * Stop the one second clock. 2837 */ 2838 callout_stop(&sc->sc_tick_ch); 2839 2840 /* Down the MII. */ 2841 mii_down(&sc->sc_mii); 2842 2843 if (device_is_active(sc->sc_dev)) { 2844 /* 2845 * Disable interrupts. 2846 */ 2847 bus_space_write_4(st, sh, SIP_IER, 0); 2848 2849 /* 2850 * Stop receiver and transmitter. 2851 */ 2852 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2853 } 2854 2855 /* 2856 * Release any queued transmit buffers. 2857 */ 2858 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2859 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2860 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2861 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2862 CMDSTS_INTR) == 0) 2863 printf("%s: sip_stop: last descriptor does not " 2864 "have INTR bit set\n", device_xname(sc->sc_dev)); 2865 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2866 #ifdef DIAGNOSTIC 2867 if (txs->txs_mbuf == NULL) { 2868 printf("%s: dirty txsoft with no mbuf chain\n", 2869 device_xname(sc->sc_dev)); 2870 panic("sip_stop"); 2871 } 2872 #endif 2873 cmdsts |= /* DEBUG */ 2874 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2875 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2876 m_freem(txs->txs_mbuf); 2877 txs->txs_mbuf = NULL; 2878 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2879 } 2880 2881 /* 2882 * Mark the interface down and cancel the watchdog timer. 2883 */ 2884 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2885 ifp->if_timer = 0; 2886 2887 if (disable) 2888 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2889 2890 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2891 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2892 printf("%s: sip_stop: no INTR bits set in dirty tx " 2893 "descriptors\n", device_xname(sc->sc_dev)); 2894 } 2895 2896 /* 2897 * sip_read_eeprom: 2898 * 2899 * Read data from the serial EEPROM. 2900 */ 2901 static void 2902 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2903 u_int16_t *data) 2904 { 2905 bus_space_tag_t st = sc->sc_st; 2906 bus_space_handle_t sh = sc->sc_sh; 2907 u_int16_t reg; 2908 int i, x; 2909 2910 for (i = 0; i < wordcnt; i++) { 2911 /* Send CHIP SELECT. */ 2912 reg = EROMAR_EECS; 2913 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2914 2915 /* Shift in the READ opcode. */ 2916 for (x = 3; x > 0; x--) { 2917 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2918 reg |= EROMAR_EEDI; 2919 else 2920 reg &= ~EROMAR_EEDI; 2921 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2922 bus_space_write_4(st, sh, SIP_EROMAR, 2923 reg | EROMAR_EESK); 2924 delay(4); 2925 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2926 delay(4); 2927 } 2928 2929 /* Shift in address. */ 2930 for (x = 6; x > 0; x--) { 2931 if ((word + i) & (1 << (x - 1))) 2932 reg |= EROMAR_EEDI; 2933 else 2934 reg &= ~EROMAR_EEDI; 2935 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2936 bus_space_write_4(st, sh, SIP_EROMAR, 2937 reg | EROMAR_EESK); 2938 delay(4); 2939 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2940 delay(4); 2941 } 2942 2943 /* Shift out data. */ 2944 reg = EROMAR_EECS; 2945 data[i] = 0; 2946 for (x = 16; x > 0; x--) { 2947 bus_space_write_4(st, sh, SIP_EROMAR, 2948 reg | EROMAR_EESK); 2949 delay(4); 2950 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2951 data[i] |= (1 << (x - 1)); 2952 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2953 delay(4); 2954 } 2955 2956 /* Clear CHIP SELECT. */ 2957 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2958 delay(4); 2959 } 2960 } 2961 2962 /* 2963 * sipcom_add_rxbuf: 2964 * 2965 * Add a receive buffer to the indicated descriptor. 2966 */ 2967 static int 2968 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2969 { 2970 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2971 struct mbuf *m; 2972 int error; 2973 2974 MGETHDR(m, M_DONTWAIT, MT_DATA); 2975 if (m == NULL) 2976 return (ENOBUFS); 2977 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2978 2979 MCLGET(m, M_DONTWAIT); 2980 if ((m->m_flags & M_EXT) == 0) { 2981 m_freem(m); 2982 return (ENOBUFS); 2983 } 2984 2985 /* XXX I don't believe this is necessary. --dyoung */ 2986 if (sc->sc_gigabit) 2987 m->m_len = sc->sc_parm->p_rxbuf_len; 2988 2989 if (rxs->rxs_mbuf != NULL) 2990 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2991 2992 rxs->rxs_mbuf = m; 2993 2994 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2995 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2996 BUS_DMA_READ|BUS_DMA_NOWAIT); 2997 if (error) { 2998 printf("%s: can't load rx DMA map %d, error = %d\n", 2999 device_xname(sc->sc_dev), idx, error); 3000 panic("%s", __func__); /* XXX */ 3001 } 3002 3003 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3004 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3005 3006 sip_init_rxdesc(sc, idx); 3007 3008 return (0); 3009 } 3010 3011 /* 3012 * sip_sis900_set_filter: 3013 * 3014 * Set up the receive filter. 3015 */ 3016 static void 3017 sipcom_sis900_set_filter(struct sip_softc *sc) 3018 { 3019 bus_space_tag_t st = sc->sc_st; 3020 bus_space_handle_t sh = sc->sc_sh; 3021 struct ethercom *ec = &sc->sc_ethercom; 3022 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3023 struct ether_multi *enm; 3024 const u_int8_t *cp; 3025 struct ether_multistep step; 3026 u_int32_t crc, mchash[16]; 3027 3028 /* 3029 * Initialize the prototype RFCR. 3030 */ 3031 sc->sc_rfcr = RFCR_RFEN; 3032 if (ifp->if_flags & IFF_BROADCAST) 3033 sc->sc_rfcr |= RFCR_AAB; 3034 if (ifp->if_flags & IFF_PROMISC) { 3035 sc->sc_rfcr |= RFCR_AAP; 3036 goto allmulti; 3037 } 3038 3039 /* 3040 * Set up the multicast address filter by passing all multicast 3041 * addresses through a CRC generator, and then using the high-order 3042 * 6 bits as an index into the 128 bit multicast hash table (only 3043 * the lower 16 bits of each 32 bit multicast hash register are 3044 * valid). The high order bits select the register, while the 3045 * rest of the bits select the bit within the register. 3046 */ 3047 3048 memset(mchash, 0, sizeof(mchash)); 3049 3050 /* 3051 * SiS900 (at least SiS963) requires us to register the address of 3052 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3053 */ 3054 crc = 0x0ed423f9; 3055 3056 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3057 SIP_SIS900_REV(sc, SIS_REV_960) || 3058 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3059 /* Just want the 8 most significant bits. */ 3060 crc >>= 24; 3061 } else { 3062 /* Just want the 7 most significant bits. */ 3063 crc >>= 25; 3064 } 3065 3066 /* Set the corresponding bit in the hash table. */ 3067 mchash[crc >> 4] |= 1 << (crc & 0xf); 3068 3069 ETHER_FIRST_MULTI(step, ec, enm); 3070 while (enm != NULL) { 3071 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3072 /* 3073 * We must listen to a range of multicast addresses. 3074 * For now, just accept all multicasts, rather than 3075 * trying to set only those filter bits needed to match 3076 * the range. (At this time, the only use of address 3077 * ranges is for IP multicast routing, for which the 3078 * range is big enough to require all bits set.) 3079 */ 3080 goto allmulti; 3081 } 3082 3083 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3084 3085 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3086 SIP_SIS900_REV(sc, SIS_REV_960) || 3087 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3088 /* Just want the 8 most significant bits. */ 3089 crc >>= 24; 3090 } else { 3091 /* Just want the 7 most significant bits. */ 3092 crc >>= 25; 3093 } 3094 3095 /* Set the corresponding bit in the hash table. */ 3096 mchash[crc >> 4] |= 1 << (crc & 0xf); 3097 3098 ETHER_NEXT_MULTI(step, enm); 3099 } 3100 3101 ifp->if_flags &= ~IFF_ALLMULTI; 3102 goto setit; 3103 3104 allmulti: 3105 ifp->if_flags |= IFF_ALLMULTI; 3106 sc->sc_rfcr |= RFCR_AAM; 3107 3108 setit: 3109 #define FILTER_EMIT(addr, data) \ 3110 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3111 delay(1); \ 3112 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3113 delay(1) 3114 3115 /* 3116 * Disable receive filter, and program the node address. 3117 */ 3118 cp = CLLADDR(ifp->if_sadl); 3119 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3120 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3121 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3122 3123 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3124 /* 3125 * Program the multicast hash table. 3126 */ 3127 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3128 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3129 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3130 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3131 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3132 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3133 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3134 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3135 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3136 SIP_SIS900_REV(sc, SIS_REV_960) || 3137 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3138 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3139 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3140 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3141 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3142 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3143 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3144 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3145 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3146 } 3147 } 3148 #undef FILTER_EMIT 3149 3150 /* 3151 * Re-enable the receiver filter. 3152 */ 3153 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3154 } 3155 3156 /* 3157 * sip_dp83815_set_filter: 3158 * 3159 * Set up the receive filter. 3160 */ 3161 static void 3162 sipcom_dp83815_set_filter(struct sip_softc *sc) 3163 { 3164 bus_space_tag_t st = sc->sc_st; 3165 bus_space_handle_t sh = sc->sc_sh; 3166 struct ethercom *ec = &sc->sc_ethercom; 3167 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3168 struct ether_multi *enm; 3169 const u_int8_t *cp; 3170 struct ether_multistep step; 3171 u_int32_t crc, hash, slot, bit; 3172 #define MCHASH_NWORDS_83820 128 3173 #define MCHASH_NWORDS_83815 32 3174 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3175 u_int16_t mchash[MCHASH_NWORDS]; 3176 int i; 3177 3178 /* 3179 * Initialize the prototype RFCR. 3180 * Enable the receive filter, and accept on 3181 * Perfect (destination address) Match 3182 * If IFF_BROADCAST, also accept all broadcast packets. 3183 * If IFF_PROMISC, accept all unicast packets (and later, set 3184 * IFF_ALLMULTI and accept all multicast, too). 3185 */ 3186 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3187 if (ifp->if_flags & IFF_BROADCAST) 3188 sc->sc_rfcr |= RFCR_AAB; 3189 if (ifp->if_flags & IFF_PROMISC) { 3190 sc->sc_rfcr |= RFCR_AAP; 3191 goto allmulti; 3192 } 3193 3194 /* 3195 * Set up the DP83820/DP83815 multicast address filter by 3196 * passing all multicast addresses through a CRC generator, 3197 * and then using the high-order 11/9 bits as an index into 3198 * the 2048/512 bit multicast hash table. The high-order 3199 * 7/5 bits select the slot, while the low-order 4 bits 3200 * select the bit within the slot. Note that only the low 3201 * 16-bits of each filter word are used, and there are 3202 * 128/32 filter words. 3203 */ 3204 3205 memset(mchash, 0, sizeof(mchash)); 3206 3207 ifp->if_flags &= ~IFF_ALLMULTI; 3208 ETHER_FIRST_MULTI(step, ec, enm); 3209 if (enm == NULL) 3210 goto setit; 3211 while (enm != NULL) { 3212 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3213 /* 3214 * We must listen to a range of multicast addresses. 3215 * For now, just accept all multicasts, rather than 3216 * trying to set only those filter bits needed to match 3217 * the range. (At this time, the only use of address 3218 * ranges is for IP multicast routing, for which the 3219 * range is big enough to require all bits set.) 3220 */ 3221 goto allmulti; 3222 } 3223 3224 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3225 3226 if (sc->sc_gigabit) { 3227 /* Just want the 11 most significant bits. */ 3228 hash = crc >> 21; 3229 } else { 3230 /* Just want the 9 most significant bits. */ 3231 hash = crc >> 23; 3232 } 3233 3234 slot = hash >> 4; 3235 bit = hash & 0xf; 3236 3237 /* Set the corresponding bit in the hash table. */ 3238 mchash[slot] |= 1 << bit; 3239 3240 ETHER_NEXT_MULTI(step, enm); 3241 } 3242 sc->sc_rfcr |= RFCR_MHEN; 3243 goto setit; 3244 3245 allmulti: 3246 ifp->if_flags |= IFF_ALLMULTI; 3247 sc->sc_rfcr |= RFCR_AAM; 3248 3249 setit: 3250 #define FILTER_EMIT(addr, data) \ 3251 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3252 delay(1); \ 3253 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3254 delay(1) 3255 3256 /* 3257 * Disable receive filter, and program the node address. 3258 */ 3259 cp = CLLADDR(ifp->if_sadl); 3260 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3261 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3262 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3263 3264 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3265 int nwords = 3266 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3267 /* 3268 * Program the multicast hash table. 3269 */ 3270 for (i = 0; i < nwords; i++) { 3271 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3272 } 3273 } 3274 #undef FILTER_EMIT 3275 #undef MCHASH_NWORDS 3276 #undef MCHASH_NWORDS_83815 3277 #undef MCHASH_NWORDS_83820 3278 3279 /* 3280 * Re-enable the receiver filter. 3281 */ 3282 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3283 } 3284 3285 /* 3286 * sip_dp83820_mii_readreg: [mii interface function] 3287 * 3288 * Read a PHY register on the MII of the DP83820. 3289 */ 3290 static int 3291 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3292 { 3293 struct sip_softc *sc = device_private(self); 3294 3295 if (sc->sc_cfg & CFG_TBI_EN) { 3296 bus_addr_t tbireg; 3297 int rv; 3298 3299 if (phy != 0) 3300 return (0); 3301 3302 switch (reg) { 3303 case MII_BMCR: tbireg = SIP_TBICR; break; 3304 case MII_BMSR: tbireg = SIP_TBISR; break; 3305 case MII_ANAR: tbireg = SIP_TANAR; break; 3306 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3307 case MII_ANER: tbireg = SIP_TANER; break; 3308 case MII_EXTSR: 3309 /* 3310 * Don't even bother reading the TESR register. 3311 * The manual documents that the device has 3312 * 1000baseX full/half capability, but the 3313 * register itself seems read back 0 on some 3314 * boards. Just hard-code the result. 3315 */ 3316 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3317 3318 default: 3319 return (0); 3320 } 3321 3322 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3323 if (tbireg == SIP_TBISR) { 3324 /* LINK and ACOMP are switched! */ 3325 int val = rv; 3326 3327 rv = 0; 3328 if (val & TBISR_MR_LINK_STATUS) 3329 rv |= BMSR_LINK; 3330 if (val & TBISR_MR_AN_COMPLETE) 3331 rv |= BMSR_ACOMP; 3332 3333 /* 3334 * The manual claims this register reads back 0 3335 * on hard and soft reset. But we want to let 3336 * the gentbi driver know that we support auto- 3337 * negotiation, so hard-code this bit in the 3338 * result. 3339 */ 3340 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3341 } 3342 3343 return (rv); 3344 } 3345 3346 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3347 } 3348 3349 /* 3350 * sip_dp83820_mii_writereg: [mii interface function] 3351 * 3352 * Write a PHY register on the MII of the DP83820. 3353 */ 3354 static void 3355 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3356 { 3357 struct sip_softc *sc = device_private(self); 3358 3359 if (sc->sc_cfg & CFG_TBI_EN) { 3360 bus_addr_t tbireg; 3361 3362 if (phy != 0) 3363 return; 3364 3365 switch (reg) { 3366 case MII_BMCR: tbireg = SIP_TBICR; break; 3367 case MII_ANAR: tbireg = SIP_TANAR; break; 3368 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3369 default: 3370 return; 3371 } 3372 3373 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3374 return; 3375 } 3376 3377 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3378 } 3379 3380 /* 3381 * sip_dp83820_mii_statchg: [mii interface function] 3382 * 3383 * Callback from MII layer when media changes. 3384 */ 3385 static void 3386 sipcom_dp83820_mii_statchg(device_t self) 3387 { 3388 struct sip_softc *sc = device_private(self); 3389 struct mii_data *mii = &sc->sc_mii; 3390 u_int32_t cfg, pcr; 3391 3392 /* 3393 * Get flow control negotiation result. 3394 */ 3395 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3396 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3397 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3398 mii->mii_media_active &= ~IFM_ETH_FMASK; 3399 } 3400 3401 /* 3402 * Update TXCFG for full-duplex operation. 3403 */ 3404 if ((mii->mii_media_active & IFM_FDX) != 0) 3405 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3406 else 3407 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3408 3409 /* 3410 * Update RXCFG for full-duplex or loopback. 3411 */ 3412 if ((mii->mii_media_active & IFM_FDX) != 0 || 3413 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3414 sc->sc_rxcfg |= RXCFG_ATX; 3415 else 3416 sc->sc_rxcfg &= ~RXCFG_ATX; 3417 3418 /* 3419 * Update CFG for MII/GMII. 3420 */ 3421 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3422 cfg = sc->sc_cfg | CFG_MODE_1000; 3423 else 3424 cfg = sc->sc_cfg; 3425 3426 /* 3427 * 802.3x flow control. 3428 */ 3429 pcr = 0; 3430 if (sc->sc_flowflags & IFM_FLOW) { 3431 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3432 pcr |= sc->sc_rx_flow_thresh; 3433 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3434 pcr |= PCR_PSEN | PCR_PS_MCAST; 3435 } 3436 3437 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3438 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3439 sc->sc_txcfg); 3440 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3441 sc->sc_rxcfg); 3442 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3443 } 3444 3445 /* 3446 * sip_mii_bitbang_read: [mii bit-bang interface function] 3447 * 3448 * Read the MII serial port for the MII bit-bang module. 3449 */ 3450 static u_int32_t 3451 sipcom_mii_bitbang_read(device_t self) 3452 { 3453 struct sip_softc *sc = device_private(self); 3454 3455 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3456 } 3457 3458 /* 3459 * sip_mii_bitbang_write: [mii big-bang interface function] 3460 * 3461 * Write the MII serial port for the MII bit-bang module. 3462 */ 3463 static void 3464 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3465 { 3466 struct sip_softc *sc = device_private(self); 3467 3468 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3469 } 3470 3471 /* 3472 * sip_sis900_mii_readreg: [mii interface function] 3473 * 3474 * Read a PHY register on the MII. 3475 */ 3476 static int 3477 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3478 { 3479 struct sip_softc *sc = device_private(self); 3480 u_int32_t enphy; 3481 3482 /* 3483 * The PHY of recent SiS chipsets is accessed through bitbang 3484 * operations. 3485 */ 3486 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3487 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3488 phy, reg); 3489 3490 #ifndef SIS900_MII_RESTRICT 3491 /* 3492 * The SiS 900 has only an internal PHY on the MII. Only allow 3493 * MII address 0. 3494 */ 3495 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3496 return (0); 3497 #endif 3498 3499 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3500 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3501 ENPHY_RWCMD | ENPHY_ACCESS); 3502 do { 3503 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3504 } while (enphy & ENPHY_ACCESS); 3505 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3506 } 3507 3508 /* 3509 * sip_sis900_mii_writereg: [mii interface function] 3510 * 3511 * Write a PHY register on the MII. 3512 */ 3513 static void 3514 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3515 { 3516 struct sip_softc *sc = device_private(self); 3517 u_int32_t enphy; 3518 3519 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3520 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3521 phy, reg, val); 3522 return; 3523 } 3524 3525 #ifndef SIS900_MII_RESTRICT 3526 /* 3527 * The SiS 900 has only an internal PHY on the MII. Only allow 3528 * MII address 0. 3529 */ 3530 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3531 return; 3532 #endif 3533 3534 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3535 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3536 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3537 do { 3538 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3539 } while (enphy & ENPHY_ACCESS); 3540 } 3541 3542 /* 3543 * sip_sis900_mii_statchg: [mii interface function] 3544 * 3545 * Callback from MII layer when media changes. 3546 */ 3547 static void 3548 sipcom_sis900_mii_statchg(device_t self) 3549 { 3550 struct sip_softc *sc = device_private(self); 3551 struct mii_data *mii = &sc->sc_mii; 3552 u_int32_t flowctl; 3553 3554 /* 3555 * Get flow control negotiation result. 3556 */ 3557 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3558 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3559 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3560 mii->mii_media_active &= ~IFM_ETH_FMASK; 3561 } 3562 3563 /* 3564 * Update TXCFG for full-duplex operation. 3565 */ 3566 if ((mii->mii_media_active & IFM_FDX) != 0) 3567 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3568 else 3569 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3570 3571 /* 3572 * Update RXCFG for full-duplex or loopback. 3573 */ 3574 if ((mii->mii_media_active & IFM_FDX) != 0 || 3575 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3576 sc->sc_rxcfg |= RXCFG_ATX; 3577 else 3578 sc->sc_rxcfg &= ~RXCFG_ATX; 3579 3580 /* 3581 * Update IMR for use of 802.3x flow control. 3582 */ 3583 if (sc->sc_flowflags & IFM_FLOW) { 3584 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3585 flowctl = FLOWCTL_FLOWEN; 3586 } else { 3587 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3588 flowctl = 0; 3589 } 3590 3591 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3592 sc->sc_txcfg); 3593 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3594 sc->sc_rxcfg); 3595 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3596 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3597 } 3598 3599 /* 3600 * sip_dp83815_mii_readreg: [mii interface function] 3601 * 3602 * Read a PHY register on the MII. 3603 */ 3604 static int 3605 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3606 { 3607 struct sip_softc *sc = device_private(self); 3608 u_int32_t val; 3609 3610 /* 3611 * The DP83815 only has an internal PHY. Only allow 3612 * MII address 0. 3613 */ 3614 if (phy != 0) 3615 return (0); 3616 3617 /* 3618 * Apparently, after a reset, the DP83815 can take a while 3619 * to respond. During this recovery period, the BMSR returns 3620 * a value of 0. Catch this -- it's not supposed to happen 3621 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3622 * PHY to come back to life. 3623 * 3624 * This works out because the BMSR is the first register 3625 * read during the PHY probe process. 3626 */ 3627 do { 3628 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3629 } while (reg == MII_BMSR && val == 0); 3630 3631 return (val & 0xffff); 3632 } 3633 3634 /* 3635 * sip_dp83815_mii_writereg: [mii interface function] 3636 * 3637 * Write a PHY register to the MII. 3638 */ 3639 static void 3640 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3641 { 3642 struct sip_softc *sc = device_private(self); 3643 3644 /* 3645 * The DP83815 only has an internal PHY. Only allow 3646 * MII address 0. 3647 */ 3648 if (phy != 0) 3649 return; 3650 3651 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3652 } 3653 3654 /* 3655 * sip_dp83815_mii_statchg: [mii interface function] 3656 * 3657 * Callback from MII layer when media changes. 3658 */ 3659 static void 3660 sipcom_dp83815_mii_statchg(device_t self) 3661 { 3662 struct sip_softc *sc = device_private(self); 3663 3664 /* 3665 * Update TXCFG for full-duplex operation. 3666 */ 3667 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3668 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3669 else 3670 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3671 3672 /* 3673 * Update RXCFG for full-duplex or loopback. 3674 */ 3675 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3676 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3677 sc->sc_rxcfg |= RXCFG_ATX; 3678 else 3679 sc->sc_rxcfg &= ~RXCFG_ATX; 3680 3681 /* 3682 * XXX 802.3x flow control. 3683 */ 3684 3685 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3686 sc->sc_txcfg); 3687 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3688 sc->sc_rxcfg); 3689 3690 /* 3691 * Some DP83815s experience problems when used with short 3692 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3693 * sequence adjusts the DSP's signal attenuation to fix the 3694 * problem. 3695 */ 3696 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3697 uint32_t reg; 3698 3699 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3700 3701 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3702 reg &= 0x0fff; 3703 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3704 delay(100); 3705 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3706 reg &= 0x00ff; 3707 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3708 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3709 0x00e8); 3710 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3711 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3712 reg | 0x20); 3713 } 3714 3715 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3716 } 3717 } 3718 3719 static void 3720 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3721 const struct pci_attach_args *pa, u_int8_t *enaddr) 3722 { 3723 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3724 u_int8_t cksum, *e, match; 3725 int i; 3726 3727 /* 3728 * EEPROM data format for the DP83820 can be found in 3729 * the DP83820 manual, section 4.2.4. 3730 */ 3731 3732 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3733 3734 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3735 match = ~(match - 1); 3736 3737 cksum = 0x55; 3738 e = (u_int8_t *) eeprom_data; 3739 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3740 cksum += *e++; 3741 3742 if (cksum != match) 3743 printf("%s: Checksum (%x) mismatch (%x)", 3744 device_xname(sc->sc_dev), cksum, match); 3745 3746 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3747 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3748 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3749 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3750 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3751 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3752 } 3753 3754 static void 3755 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3756 { 3757 int i; 3758 3759 /* 3760 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3761 * a reason, but I don't know it. 3762 */ 3763 for (i = 0; i < 10; i++) 3764 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3765 } 3766 3767 static void 3768 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3769 const struct pci_attach_args *pa, u_int8_t *enaddr) 3770 { 3771 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3772 3773 switch (sc->sc_rev) { 3774 case SIS_REV_630S: 3775 case SIS_REV_630E: 3776 case SIS_REV_630EA1: 3777 case SIS_REV_630ET: 3778 case SIS_REV_635: 3779 /* 3780 * The MAC address for the on-board Ethernet of 3781 * the SiS 630 chipset is in the NVRAM. Kick 3782 * the chip into re-loading it from NVRAM, and 3783 * read the MAC address out of the filter registers. 3784 */ 3785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3786 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3788 RFCR_RFADDR_NODE0); 3789 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3790 0xffff; 3791 3792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3793 RFCR_RFADDR_NODE2); 3794 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3795 0xffff; 3796 3797 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3798 RFCR_RFADDR_NODE4); 3799 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3800 0xffff; 3801 break; 3802 3803 case SIS_REV_960: 3804 { 3805 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3806 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3807 3808 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3809 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3810 3811 int waittime, i; 3812 3813 /* Allow to read EEPROM from LAN. It is shared 3814 * between a 1394 controller and the NIC and each 3815 * time we access it, we need to set SIS_EECMD_REQ. 3816 */ 3817 SIS_SET_EROMAR(sc, EROMAR_REQ); 3818 3819 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3820 /* Force EEPROM to idle state. */ 3821 3822 /* 3823 * XXX-cube This is ugly. I'll look for docs about it. 3824 */ 3825 SIS_SET_EROMAR(sc, EROMAR_EECS); 3826 sipcom_sis900_eeprom_delay(sc); 3827 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3828 SIS_SET_EROMAR(sc, EROMAR_EESK); 3829 sipcom_sis900_eeprom_delay(sc); 3830 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3831 sipcom_sis900_eeprom_delay(sc); 3832 } 3833 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3834 sipcom_sis900_eeprom_delay(sc); 3835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3836 3837 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3838 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3839 sizeof(myea) / sizeof(myea[0]), myea); 3840 break; 3841 } 3842 DELAY(1); 3843 } 3844 3845 /* 3846 * Set SIS_EECTL_CLK to high, so a other master 3847 * can operate on the i2c bus. 3848 */ 3849 SIS_SET_EROMAR(sc, EROMAR_EESK); 3850 3851 /* Refuse EEPROM access by LAN */ 3852 SIS_SET_EROMAR(sc, EROMAR_DONE); 3853 } break; 3854 3855 default: 3856 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3857 sizeof(myea) / sizeof(myea[0]), myea); 3858 } 3859 3860 enaddr[0] = myea[0] & 0xff; 3861 enaddr[1] = myea[0] >> 8; 3862 enaddr[2] = myea[1] & 0xff; 3863 enaddr[3] = myea[1] >> 8; 3864 enaddr[4] = myea[2] & 0xff; 3865 enaddr[5] = myea[2] >> 8; 3866 } 3867 3868 /* Table and macro to bit-reverse an octet. */ 3869 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3870 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3871 3872 static void 3873 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3874 const struct pci_attach_args *pa, u_int8_t *enaddr) 3875 { 3876 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3877 u_int8_t cksum, *e, match; 3878 int i; 3879 3880 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3881 sizeof(eeprom_data[0]), eeprom_data); 3882 3883 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3884 match = ~(match - 1); 3885 3886 cksum = 0x55; 3887 e = (u_int8_t *) eeprom_data; 3888 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3889 cksum += *e++; 3890 } 3891 if (cksum != match) { 3892 printf("%s: Checksum (%x) mismatch (%x)", 3893 device_xname(sc->sc_dev), cksum, match); 3894 } 3895 3896 /* 3897 * Unrolled because it makes slightly more sense this way. 3898 * The DP83815 stores the MAC address in bit 0 of word 6 3899 * through bit 15 of word 8. 3900 */ 3901 ea = &eeprom_data[6]; 3902 enaddr[0] = ((*ea & 0x1) << 7); 3903 ea++; 3904 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3905 enaddr[1] = ((*ea & 0x1FE) >> 1); 3906 enaddr[2] = ((*ea & 0x1) << 7); 3907 ea++; 3908 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3909 enaddr[3] = ((*ea & 0x1FE) >> 1); 3910 enaddr[4] = ((*ea & 0x1) << 7); 3911 ea++; 3912 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3913 enaddr[5] = ((*ea & 0x1FE) >> 1); 3914 3915 /* 3916 * In case that's not weird enough, we also need to reverse 3917 * the bits in each byte. This all actually makes more sense 3918 * if you think about the EEPROM storage as an array of bits 3919 * being shifted into bytes, but that's not how we're looking 3920 * at it here... 3921 */ 3922 for (i = 0; i < 6 ;i++) 3923 enaddr[i] = bbr(enaddr[i]); 3924 } 3925 3926 /* 3927 * sip_mediastatus: [ifmedia interface function] 3928 * 3929 * Get the current interface media status. 3930 */ 3931 static void 3932 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3933 { 3934 struct sip_softc *sc = ifp->if_softc; 3935 3936 if (!device_is_active(sc->sc_dev)) { 3937 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3938 ifmr->ifm_status = 0; 3939 return; 3940 } 3941 ether_mediastatus(ifp, ifmr); 3942 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3943 sc->sc_flowflags; 3944 } 3945