xref: /netbsd-src/sys/dev/pci/if_sip.c (revision aa73cae19608873cc4d1f712c4a0f8f8435f1ffa)
1 /*	$NetBSD: if_sip.c,v 1.101 2005/02/27 00:27:33 perry Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by the NetBSD
21  *	Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*-
40  * Copyright (c) 1999 Network Computer, Inc.
41  * All rights reserved.
42  *
43  * Redistribution and use in source and binary forms, with or without
44  * modification, are permitted provided that the following conditions
45  * are met:
46  * 1. Redistributions of source code must retain the above copyright
47  *    notice, this list of conditions and the following disclaimer.
48  * 2. Redistributions in binary form must reproduce the above copyright
49  *    notice, this list of conditions and the following disclaimer in the
50  *    documentation and/or other materials provided with the distribution.
51  * 3. Neither the name of Network Computer, Inc. nor the names of its
52  *    contributors may be used to endorse or promote products derived
53  *    from this software without specific prior written permission.
54  *
55  * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
56  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
59  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65  * POSSIBILITY OF SUCH DAMAGE.
66  */
67 
68 /*
69  * Device driver for the Silicon Integrated Systems SiS 900,
70  * SiS 7016 10/100, National Semiconductor DP83815 10/100, and
71  * National Semiconductor DP83820 10/100/1000 PCI Ethernet
72  * controllers.
73  *
74  * Originally written to support the SiS 900 by Jason R. Thorpe for
75  * Network Computer, Inc.
76  *
77  * TODO:
78  *
79  *	- Reduce the Rx interrupt load.
80  */
81 
82 #include <sys/cdefs.h>
83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.101 2005/02/27 00:27:33 perry Exp $");
84 
85 #include "bpfilter.h"
86 #include "rnd.h"
87 
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/callout.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/socket.h>
95 #include <sys/ioctl.h>
96 #include <sys/errno.h>
97 #include <sys/device.h>
98 #include <sys/queue.h>
99 
100 #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
101 
102 #if NRND > 0
103 #include <sys/rnd.h>
104 #endif
105 
106 #include <net/if.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_ether.h>
110 
111 #if NBPFILTER > 0
112 #include <net/bpf.h>
113 #endif
114 
115 #include <machine/bus.h>
116 #include <machine/intr.h>
117 #include <machine/endian.h>
118 
119 #include <dev/mii/mii.h>
120 #include <dev/mii/miivar.h>
121 #include <dev/mii/mii_bitbang.h>
122 
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
125 #include <dev/pci/pcidevs.h>
126 
127 #include <dev/pci/if_sipreg.h>
128 
129 #ifdef DP83820		/* DP83820 Gigabit Ethernet */
130 #define	SIP_DECL(x)	__CONCAT(gsip_,x)
131 #else			/* SiS900 and DP83815 */
132 #define	SIP_DECL(x)	__CONCAT(sip_,x)
133 #endif
134 
135 #define	SIP_STR(x)	__STRING(SIP_DECL(x))
136 
137 /*
138  * Transmit descriptor list size.  This is arbitrary, but allocate
139  * enough descriptors for 128 pending transmissions, and 8 segments
140  * per packet (64 for DP83820 for jumbo frames).
141  *
142  * This MUST work out to a power of 2.
143  */
144 #ifdef DP83820
145 #define	SIP_NTXSEGS		64
146 #define	SIP_NTXSEGS_ALLOC	16
147 #else
148 #define	SIP_NTXSEGS		16
149 #define	SIP_NTXSEGS_ALLOC	8
150 #endif
151 
152 #define	SIP_TXQUEUELEN		256
153 #define	SIP_NTXDESC		(SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC)
154 #define	SIP_NTXDESC_MASK	(SIP_NTXDESC - 1)
155 #define	SIP_NEXTTX(x)		(((x) + 1) & SIP_NTXDESC_MASK)
156 
157 #if defined(DP83820)
158 #define	TX_DMAMAP_SIZE		ETHER_MAX_LEN_JUMBO
159 #else
160 #define	TX_DMAMAP_SIZE		MCLBYTES
161 #endif
162 
163 /*
164  * Receive descriptor list size.  We have one Rx buffer per incoming
165  * packet, so this logic is a little simpler.
166  *
167  * Actually, on the DP83820, we allow the packet to consume more than
168  * one buffer, in order to support jumbo Ethernet frames.  In that
169  * case, a packet may consume up to 5 buffers (assuming a 2048 byte
170  * mbuf cluster).  256 receive buffers is only 51 maximum size packets,
171  * so we'd better be quick about handling receive interrupts.
172  */
173 #if defined(DP83820)
174 #define	SIP_NRXDESC		256
175 #else
176 #define	SIP_NRXDESC		128
177 #endif /* DP83820 */
178 #define	SIP_NRXDESC_MASK	(SIP_NRXDESC - 1)
179 #define	SIP_NEXTRX(x)		(((x) + 1) & SIP_NRXDESC_MASK)
180 
181 /*
182  * Control structures are DMA'd to the SiS900 chip.  We allocate them in
183  * a single clump that maps to a single DMA segment to make several things
184  * easier.
185  */
186 struct sip_control_data {
187 	/*
188 	 * The transmit descriptors.
189 	 */
190 	struct sip_desc scd_txdescs[SIP_NTXDESC];
191 
192 	/*
193 	 * The receive descriptors.
194 	 */
195 	struct sip_desc scd_rxdescs[SIP_NRXDESC];
196 };
197 
198 #define	SIP_CDOFF(x)	offsetof(struct sip_control_data, x)
199 #define	SIP_CDTXOFF(x)	SIP_CDOFF(scd_txdescs[(x)])
200 #define	SIP_CDRXOFF(x)	SIP_CDOFF(scd_rxdescs[(x)])
201 
202 /*
203  * Software state for transmit jobs.
204  */
205 struct sip_txsoft {
206 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
207 	bus_dmamap_t txs_dmamap;	/* our DMA map */
208 	int txs_firstdesc;		/* first descriptor in packet */
209 	int txs_lastdesc;		/* last descriptor in packet */
210 	SIMPLEQ_ENTRY(sip_txsoft) txs_q;
211 };
212 
213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft);
214 
215 /*
216  * Software state for receive jobs.
217  */
218 struct sip_rxsoft {
219 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
220 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
221 };
222 
223 /*
224  * Software state per device.
225  */
226 struct sip_softc {
227 	struct device sc_dev;		/* generic device information */
228 	bus_space_tag_t sc_st;		/* bus space tag */
229 	bus_space_handle_t sc_sh;	/* bus space handle */
230 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
231 	struct ethercom sc_ethercom;	/* ethernet common data */
232 	void *sc_sdhook;		/* shutdown hook */
233 
234 	const struct sip_product *sc_model; /* which model are we? */
235 	int sc_rev;			/* chip revision */
236 
237 	void *sc_ih;			/* interrupt cookie */
238 
239 	struct mii_data sc_mii;		/* MII/media information */
240 
241 	struct callout sc_tick_ch;	/* tick callout */
242 
243 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
244 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
245 
246 	/*
247 	 * Software state for transmit and receive descriptors.
248 	 */
249 	struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN];
250 	struct sip_rxsoft sc_rxsoft[SIP_NRXDESC];
251 
252 	/*
253 	 * Control data structures.
254 	 */
255 	struct sip_control_data *sc_control_data;
256 #define	sc_txdescs	sc_control_data->scd_txdescs
257 #define	sc_rxdescs	sc_control_data->scd_rxdescs
258 
259 #ifdef SIP_EVENT_COUNTERS
260 	/*
261 	 * Event counters.
262 	 */
263 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
264 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
265 	struct evcnt sc_ev_txforceintr;	/* Tx interrupts forced */
266 	struct evcnt sc_ev_txdintr;	/* Tx descriptor interrupts */
267 	struct evcnt sc_ev_txiintr;	/* Tx idle interrupts */
268 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
269 	struct evcnt sc_ev_hiberr;	/* HIBERR interrupts */
270 	struct evcnt sc_ev_rxpause;	/* PAUSE received */
271 #ifdef DP83820
272 	struct evcnt sc_ev_txpause;	/* PAUSE transmitted */
273 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
274 	struct evcnt sc_ev_rxtcpsum;	/* TCP checksums checked in-bound */
275 	struct evcnt sc_ev_rxudpsum;	/* UDP checksums checked in-boudn */
276 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
277 	struct evcnt sc_ev_txtcpsum;	/* TCP checksums comp. out-bound */
278 	struct evcnt sc_ev_txudpsum;	/* UDP checksums comp. out-bound */
279 #endif /* DP83820 */
280 #endif /* SIP_EVENT_COUNTERS */
281 
282 	u_int32_t sc_txcfg;		/* prototype TXCFG register */
283 	u_int32_t sc_rxcfg;		/* prototype RXCFG register */
284 	u_int32_t sc_imr;		/* prototype IMR register */
285 	u_int32_t sc_rfcr;		/* prototype RFCR register */
286 
287 	u_int32_t sc_cfg;		/* prototype CFG register */
288 
289 #ifdef DP83820
290 	u_int32_t sc_gpior;		/* prototype GPIOR register */
291 #endif /* DP83820 */
292 
293 	u_int32_t sc_tx_fill_thresh;	/* transmit fill threshold */
294 	u_int32_t sc_tx_drain_thresh;	/* transmit drain threshold */
295 
296 	u_int32_t sc_rx_drain_thresh;	/* receive drain threshold */
297 
298 	int	sc_flowflags;		/* 802.3x flow control flags */
299 #ifdef DP83820
300 	int	sc_rx_flow_thresh;	/* Rx FIFO threshold for flow control */
301 #else
302 	int	sc_paused;		/* paused indication */
303 #endif
304 
305 	int	sc_txfree;		/* number of free Tx descriptors */
306 	int	sc_txnext;		/* next ready Tx descriptor */
307 	int	sc_txwin;		/* Tx descriptors since last intr */
308 
309 	struct sip_txsq sc_txfreeq;	/* free Tx descsofts */
310 	struct sip_txsq sc_txdirtyq;	/* dirty Tx descsofts */
311 
312 	short	sc_if_flags;
313 
314 	int	sc_rxptr;		/* next ready Rx descriptor/descsoft */
315 #if defined(DP83820)
316 	int	sc_rxdiscard;
317 	int	sc_rxlen;
318 	struct mbuf *sc_rxhead;
319 	struct mbuf *sc_rxtail;
320 	struct mbuf **sc_rxtailp;
321 #endif /* DP83820 */
322 
323 #if NRND > 0
324 	rndsource_element_t rnd_source;	/* random source */
325 #endif
326 };
327 
328 #ifdef DP83820
329 #define	SIP_RXCHAIN_RESET(sc)						\
330 do {									\
331 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
332 	*(sc)->sc_rxtailp = NULL;					\
333 	(sc)->sc_rxlen = 0;						\
334 } while (/*CONSTCOND*/0)
335 
336 #define	SIP_RXCHAIN_LINK(sc, m)						\
337 do {									\
338 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
339 	(sc)->sc_rxtailp = &(m)->m_next;				\
340 } while (/*CONSTCOND*/0)
341 #endif /* DP83820 */
342 
343 #ifdef SIP_EVENT_COUNTERS
344 #define	SIP_EVCNT_INCR(ev)	(ev)->ev_count++
345 #else
346 #define	SIP_EVCNT_INCR(ev)	/* nothing */
347 #endif
348 
349 #define	SIP_CDTXADDR(sc, x)	((sc)->sc_cddma + SIP_CDTXOFF((x)))
350 #define	SIP_CDRXADDR(sc, x)	((sc)->sc_cddma + SIP_CDRXOFF((x)))
351 
352 #define	SIP_CDTXSYNC(sc, x, n, ops)					\
353 do {									\
354 	int __x, __n;							\
355 									\
356 	__x = (x);							\
357 	__n = (n);							\
358 									\
359 	/* If it will wrap around, sync to the end of the ring. */	\
360 	if ((__x + __n) > SIP_NTXDESC) {				\
361 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
362 		    SIP_CDTXOFF(__x), sizeof(struct sip_desc) *		\
363 		    (SIP_NTXDESC - __x), (ops));			\
364 		__n -= (SIP_NTXDESC - __x);				\
365 		__x = 0;						\
366 	}								\
367 									\
368 	/* Now sync whatever is left. */				\
369 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
370 	    SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops));	\
371 } while (0)
372 
373 #define	SIP_CDRXSYNC(sc, x, ops)					\
374 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
375 	    SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops))
376 
377 #ifdef DP83820
378 #define	SIP_INIT_RXDESC_EXTSTS	__sipd->sipd_extsts = 0;
379 #define	SIP_RXBUF_LEN		(MCLBYTES - 8)
380 #else
381 #define	SIP_INIT_RXDESC_EXTSTS	/* nothing */
382 #define	SIP_RXBUF_LEN		(MCLBYTES - 1)	/* field width */
383 #endif
384 #define	SIP_INIT_RXDESC(sc, x)						\
385 do {									\
386 	struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
387 	struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)];		\
388 									\
389 	__sipd->sipd_link =						\
390 	    htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x))));		\
391 	__sipd->sipd_bufptr =						\
392 	    htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr);		\
393 	__sipd->sipd_cmdsts = htole32(CMDSTS_INTR |			\
394 	    (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK));			\
395 	SIP_INIT_RXDESC_EXTSTS						\
396 	SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
397 } while (0)
398 
399 #define	SIP_CHIP_VERS(sc, v, p, r)					\
400 	((sc)->sc_model->sip_vendor == (v) &&				\
401 	 (sc)->sc_model->sip_product == (p) &&				\
402 	 (sc)->sc_rev == (r))
403 
404 #define	SIP_CHIP_MODEL(sc, v, p)					\
405 	((sc)->sc_model->sip_vendor == (v) &&				\
406 	 (sc)->sc_model->sip_product == (p))
407 
408 #if !defined(DP83820)
409 #define	SIP_SIS900_REV(sc, rev)						\
410 	SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev))
411 #endif
412 
413 #define SIP_TIMEOUT 1000
414 
415 static void	SIP_DECL(start)(struct ifnet *);
416 static void	SIP_DECL(watchdog)(struct ifnet *);
417 static int	SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t);
418 static int	SIP_DECL(init)(struct ifnet *);
419 static void	SIP_DECL(stop)(struct ifnet *, int);
420 
421 static void	SIP_DECL(shutdown)(void *);
422 
423 static void	SIP_DECL(reset)(struct sip_softc *);
424 static void	SIP_DECL(rxdrain)(struct sip_softc *);
425 static int	SIP_DECL(add_rxbuf)(struct sip_softc *, int);
426 static void	SIP_DECL(read_eeprom)(struct sip_softc *, int, int,
427 				      u_int16_t *);
428 static void	SIP_DECL(tick)(void *);
429 
430 #if !defined(DP83820)
431 static void	SIP_DECL(sis900_set_filter)(struct sip_softc *);
432 #endif /* ! DP83820 */
433 static void	SIP_DECL(dp83815_set_filter)(struct sip_softc *);
434 
435 #if defined(DP83820)
436 static void	SIP_DECL(dp83820_read_macaddr)(struct sip_softc *,
437 		    const struct pci_attach_args *, u_int8_t *);
438 #else
439 static void	SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc);
440 static void	SIP_DECL(sis900_read_macaddr)(struct sip_softc *,
441 		    const struct pci_attach_args *, u_int8_t *);
442 static void	SIP_DECL(dp83815_read_macaddr)(struct sip_softc *,
443 		    const struct pci_attach_args *, u_int8_t *);
444 #endif /* DP83820 */
445 
446 static int	SIP_DECL(intr)(void *);
447 static void	SIP_DECL(txintr)(struct sip_softc *);
448 static void	SIP_DECL(rxintr)(struct sip_softc *);
449 
450 #if defined(DP83820)
451 static int	SIP_DECL(dp83820_mii_readreg)(struct device *, int, int);
452 static void	SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int);
453 static void	SIP_DECL(dp83820_mii_statchg)(struct device *);
454 #else
455 static int	SIP_DECL(sis900_mii_readreg)(struct device *, int, int);
456 static void	SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int);
457 static void	SIP_DECL(sis900_mii_statchg)(struct device *);
458 
459 static int	SIP_DECL(dp83815_mii_readreg)(struct device *, int, int);
460 static void	SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int);
461 static void	SIP_DECL(dp83815_mii_statchg)(struct device *);
462 #endif /* DP83820 */
463 
464 static int	SIP_DECL(mediachange)(struct ifnet *);
465 static void	SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *);
466 
467 static int	SIP_DECL(match)(struct device *, struct cfdata *, void *);
468 static void	SIP_DECL(attach)(struct device *, struct device *, void *);
469 
470 int	SIP_DECL(copy_small) = 0;
471 
472 #ifdef DP83820
473 CFATTACH_DECL(gsip, sizeof(struct sip_softc),
474     gsip_match, gsip_attach, NULL, NULL);
475 #else
476 CFATTACH_DECL(sip, sizeof(struct sip_softc),
477     sip_match, sip_attach, NULL, NULL);
478 #endif
479 
480 /*
481  * Descriptions of the variants of the SiS900.
482  */
483 struct sip_variant {
484 	int	(*sipv_mii_readreg)(struct device *, int, int);
485 	void	(*sipv_mii_writereg)(struct device *, int, int, int);
486 	void	(*sipv_mii_statchg)(struct device *);
487 	void	(*sipv_set_filter)(struct sip_softc *);
488 	void	(*sipv_read_macaddr)(struct sip_softc *,
489 		    const struct pci_attach_args *, u_int8_t *);
490 };
491 
492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *);
493 static void	SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t);
494 
495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = {
496 	SIP_DECL(mii_bitbang_read),
497 	SIP_DECL(mii_bitbang_write),
498 	{
499 		EROMAR_MDIO,		/* MII_BIT_MDO */
500 		EROMAR_MDIO,		/* MII_BIT_MDI */
501 		EROMAR_MDC,		/* MII_BIT_MDC */
502 		EROMAR_MDDIR,		/* MII_BIT_DIR_HOST_PHY */
503 		0,			/* MII_BIT_DIR_PHY_HOST */
504 	}
505 };
506 
507 #if defined(DP83820)
508 static const struct sip_variant SIP_DECL(variant_dp83820) = {
509 	SIP_DECL(dp83820_mii_readreg),
510 	SIP_DECL(dp83820_mii_writereg),
511 	SIP_DECL(dp83820_mii_statchg),
512 	SIP_DECL(dp83815_set_filter),
513 	SIP_DECL(dp83820_read_macaddr),
514 };
515 #else
516 static const struct sip_variant SIP_DECL(variant_sis900) = {
517 	SIP_DECL(sis900_mii_readreg),
518 	SIP_DECL(sis900_mii_writereg),
519 	SIP_DECL(sis900_mii_statchg),
520 	SIP_DECL(sis900_set_filter),
521 	SIP_DECL(sis900_read_macaddr),
522 };
523 
524 static const struct sip_variant SIP_DECL(variant_dp83815) = {
525 	SIP_DECL(dp83815_mii_readreg),
526 	SIP_DECL(dp83815_mii_writereg),
527 	SIP_DECL(dp83815_mii_statchg),
528 	SIP_DECL(dp83815_set_filter),
529 	SIP_DECL(dp83815_read_macaddr),
530 };
531 #endif /* DP83820 */
532 
533 /*
534  * Devices supported by this driver.
535  */
536 static const struct sip_product {
537 	pci_vendor_id_t		sip_vendor;
538 	pci_product_id_t	sip_product;
539 	const char		*sip_name;
540 	const struct sip_variant *sip_variant;
541 } SIP_DECL(products)[] = {
542 #if defined(DP83820)
543 	{ PCI_VENDOR_NS,	PCI_PRODUCT_NS_DP83820,
544 	  "NatSemi DP83820 Gigabit Ethernet",
545 	  &SIP_DECL(variant_dp83820) },
546 #else
547 	{ PCI_VENDOR_SIS,	PCI_PRODUCT_SIS_900,
548 	  "SiS 900 10/100 Ethernet",
549 	  &SIP_DECL(variant_sis900) },
550 	{ PCI_VENDOR_SIS,	PCI_PRODUCT_SIS_7016,
551 	  "SiS 7016 10/100 Ethernet",
552 	  &SIP_DECL(variant_sis900) },
553 
554 	{ PCI_VENDOR_NS,	PCI_PRODUCT_NS_DP83815,
555 	  "NatSemi DP83815 10/100 Ethernet",
556 	  &SIP_DECL(variant_dp83815) },
557 #endif /* DP83820 */
558 
559 	{ 0,			0,
560 	  NULL,
561 	  NULL },
562 };
563 
564 static const struct sip_product *
565 SIP_DECL(lookup)(const struct pci_attach_args *pa)
566 {
567 	const struct sip_product *sip;
568 
569 	for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) {
570 		if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor &&
571 		    PCI_PRODUCT(pa->pa_id) == sip->sip_product)
572 			return (sip);
573 	}
574 	return (NULL);
575 }
576 
577 #ifdef DP83820
578 /*
579  * I really hate stupid hardware vendors.  There's a bit in the EEPROM
580  * which indicates if the card can do 64-bit data transfers.  Unfortunately,
581  * several vendors of 32-bit cards fail to clear this bit in the EEPROM,
582  * which means we try to use 64-bit data transfers on those cards if we
583  * happen to be plugged into a 32-bit slot.
584  *
585  * What we do is use this table of cards known to be 64-bit cards.  If
586  * you have a 64-bit card who's subsystem ID is not listed in this table,
587  * send the output of "pcictl dump ..." of the device to me so that your
588  * card will use the 64-bit data path when plugged into a 64-bit slot.
589  *
590  *	-- Jason R. Thorpe <thorpej@NetBSD.org>
591  *	   June 30, 2002
592  */
593 static int
594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa)
595 {
596 	static const struct {
597 		pci_vendor_id_t c64_vendor;
598 		pci_product_id_t c64_product;
599 	} card64[] = {
600 		/* Asante GigaNIX */
601 		{ 0x128a,	0x0002 },
602 
603 		/* Accton EN1407-T, Planex GN-1000TE */
604 		{ 0x1113,	0x1407 },
605 
606 		/* Netgear GA-621 */
607 		{ 0x1385,	0x621a },
608 
609 		/* SMC EZ Card */
610 		{ 0x10b8,	0x9462 },
611 
612 		{ 0, 0}
613 	};
614 	pcireg_t subsys;
615 	int i;
616 
617 	subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
618 
619 	for (i = 0; card64[i].c64_vendor != 0; i++) {
620 		if (PCI_VENDOR(subsys) == card64[i].c64_vendor &&
621 		    PCI_PRODUCT(subsys) == card64[i].c64_product)
622 			return (1);
623 	}
624 
625 	return (0);
626 }
627 #endif /* DP83820 */
628 
629 static int
630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux)
631 {
632 	struct pci_attach_args *pa = aux;
633 
634 	if (SIP_DECL(lookup)(pa) != NULL)
635 		return (1);
636 
637 	return (0);
638 }
639 
640 static void
641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux)
642 {
643 	struct sip_softc *sc = (struct sip_softc *) self;
644 	struct pci_attach_args *pa = aux;
645 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
646 	pci_chipset_tag_t pc = pa->pa_pc;
647 	pci_intr_handle_t ih;
648 	const char *intrstr = NULL;
649 	bus_space_tag_t iot, memt;
650 	bus_space_handle_t ioh, memh;
651 	bus_dma_segment_t seg;
652 	int ioh_valid, memh_valid;
653 	int i, rseg, error;
654 	const struct sip_product *sip;
655 	pcireg_t pmode;
656 	u_int8_t enaddr[ETHER_ADDR_LEN];
657 	int pmreg;
658 #ifdef DP83820
659 	pcireg_t memtype;
660 	u_int32_t reg;
661 #endif /* DP83820 */
662 
663 	callout_init(&sc->sc_tick_ch);
664 
665 	sip = SIP_DECL(lookup)(pa);
666 	if (sip == NULL) {
667 		printf("\n");
668 		panic(SIP_STR(attach) ": impossible");
669 	}
670 	sc->sc_rev = PCI_REVISION(pa->pa_class);
671 
672 	printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev);
673 
674 	sc->sc_model = sip;
675 
676 	/*
677 	 * XXX Work-around broken PXE firmware on some boards.
678 	 *
679 	 * The DP83815 shares an address decoder with the MEM BAR
680 	 * and the ROM BAR.  Make sure the ROM BAR is disabled,
681 	 * so that memory mapped access works.
682 	 */
683 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
684 	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
685 	    ~PCI_MAPREG_ROM_ENABLE);
686 
687 	/*
688 	 * Map the device.
689 	 */
690 	ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA,
691 	    PCI_MAPREG_TYPE_IO, 0,
692 	    &iot, &ioh, NULL, NULL) == 0);
693 #ifdef DP83820
694 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA);
695 	switch (memtype) {
696 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
697 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
698 		memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
699 		    memtype, 0, &memt, &memh, NULL, NULL) == 0);
700 		break;
701 	default:
702 		memh_valid = 0;
703 	}
704 #else
705 	memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
706 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
707 	    &memt, &memh, NULL, NULL) == 0);
708 #endif /* DP83820 */
709 
710 	if (memh_valid) {
711 		sc->sc_st = memt;
712 		sc->sc_sh = memh;
713 	} else if (ioh_valid) {
714 		sc->sc_st = iot;
715 		sc->sc_sh = ioh;
716 	} else {
717 		printf("%s: unable to map device registers\n",
718 		    sc->sc_dev.dv_xname);
719 		return;
720 	}
721 
722 	sc->sc_dmat = pa->pa_dmat;
723 
724 	/*
725 	 * Make sure bus mastering is enabled.  Also make sure
726 	 * Write/Invalidate is enabled if we're allowed to use it.
727 	 */
728 	pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
729 	if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
730 		pmreg |= PCI_COMMAND_INVALIDATE_ENABLE;
731 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
732 	    pmreg | PCI_COMMAND_MASTER_ENABLE);
733 
734 	/* Get it out of power save mode if needed. */
735 	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
736 		pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) &
737 		    PCI_PMCSR_STATE_MASK;
738 		if (pmode == PCI_PMCSR_STATE_D3) {
739 			/*
740 			 * The card has lost all configuration data in
741 			 * this state, so punt.
742 			 */
743 			printf("%s: unable to wake up from power state D3\n",
744 			    sc->sc_dev.dv_xname);
745 			return;
746 		}
747 		if (pmode != PCI_PMCSR_STATE_D0) {
748 			printf("%s: waking up from power state D%d\n",
749 			    sc->sc_dev.dv_xname, pmode);
750 			pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
751 			    PCI_PMCSR_STATE_D0);
752 		}
753 	}
754 
755 	/*
756 	 * Map and establish our interrupt.
757 	 */
758 	if (pci_intr_map(pa, &ih)) {
759 		printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
760 		return;
761 	}
762 	intrstr = pci_intr_string(pc, ih);
763 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc);
764 	if (sc->sc_ih == NULL) {
765 		printf("%s: unable to establish interrupt",
766 		    sc->sc_dev.dv_xname);
767 		if (intrstr != NULL)
768 			printf(" at %s", intrstr);
769 		printf("\n");
770 		return;
771 	}
772 	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
773 
774 	SIMPLEQ_INIT(&sc->sc_txfreeq);
775 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
776 
777 	/*
778 	 * Allocate the control data structures, and create and load the
779 	 * DMA map for it.
780 	 */
781 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
782 	    sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
783 	    0)) != 0) {
784 		printf("%s: unable to allocate control data, error = %d\n",
785 		    sc->sc_dev.dv_xname, error);
786 		goto fail_0;
787 	}
788 
789 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
790 	    sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data,
791 	    BUS_DMA_COHERENT)) != 0) {
792 		printf("%s: unable to map control data, error = %d\n",
793 		    sc->sc_dev.dv_xname, error);
794 		goto fail_1;
795 	}
796 
797 	if ((error = bus_dmamap_create(sc->sc_dmat,
798 	    sizeof(struct sip_control_data), 1,
799 	    sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
800 		printf("%s: unable to create control data DMA map, "
801 		    "error = %d\n", sc->sc_dev.dv_xname, error);
802 		goto fail_2;
803 	}
804 
805 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
806 	    sc->sc_control_data, sizeof(struct sip_control_data), NULL,
807 	    0)) != 0) {
808 		printf("%s: unable to load control data DMA map, error = %d\n",
809 		    sc->sc_dev.dv_xname, error);
810 		goto fail_3;
811 	}
812 
813 	/*
814 	 * Create the transmit buffer DMA maps.
815 	 */
816 	for (i = 0; i < SIP_TXQUEUELEN; i++) {
817 		if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE,
818 		    SIP_NTXSEGS, MCLBYTES, 0, 0,
819 		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
820 			printf("%s: unable to create tx DMA map %d, "
821 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
822 			goto fail_4;
823 		}
824 	}
825 
826 	/*
827 	 * Create the receive buffer DMA maps.
828 	 */
829 	for (i = 0; i < SIP_NRXDESC; i++) {
830 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
831 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
832 			printf("%s: unable to create rx DMA map %d, "
833 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
834 			goto fail_5;
835 		}
836 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
837 	}
838 
839 	/*
840 	 * Reset the chip to a known state.
841 	 */
842 	SIP_DECL(reset)(sc);
843 
844 	/*
845 	 * Read the Ethernet address from the EEPROM.  This might
846 	 * also fetch other stuff from the EEPROM and stash it
847 	 * in the softc.
848 	 */
849 	sc->sc_cfg = 0;
850 #if !defined(DP83820)
851 	if (SIP_SIS900_REV(sc,SIS_REV_635) ||
852 	    SIP_SIS900_REV(sc,SIS_REV_900B))
853 		sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT);
854 
855 	if (SIP_SIS900_REV(sc,SIS_REV_635) ||
856 	    SIP_SIS900_REV(sc,SIS_REV_960) ||
857 	    SIP_SIS900_REV(sc,SIS_REV_900B))
858 		sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh,
859 						SIP_CFG) & CFG_EDBMASTEN);
860 #endif
861 
862 	(*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr);
863 
864 	printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
865 	    ether_sprintf(enaddr));
866 
867 	/*
868 	 * Initialize the configuration register: aggressive PCI
869 	 * bus request algorithm, default backoff, default OW timer,
870 	 * default parity error detection.
871 	 *
872 	 * NOTE: "Big endian mode" is useless on the SiS900 and
873 	 * friends -- it affects packet data, not descriptors.
874 	 */
875 #ifdef DP83820
876 	/*
877 	 * Cause the chip to load configuration data from the EEPROM.
878 	 */
879 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN);
880 	for (i = 0; i < 10000; i++) {
881 		delay(10);
882 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
883 		    PTSCR_EELOAD_EN) == 0)
884 			break;
885 	}
886 	if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
887 	    PTSCR_EELOAD_EN) {
888 		printf("%s: timeout loading configuration from EEPROM\n",
889 		    sc->sc_dev.dv_xname);
890 		return;
891 	}
892 
893 	sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR);
894 
895 	reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG);
896 	if (reg & CFG_PCI64_DET) {
897 		printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname);
898 		/*
899 		 * Check to see if this card is 64-bit.  If so, enable 64-bit
900 		 * data transfers.
901 		 *
902 		 * We can't use the DATA64_EN bit in the EEPROM, because
903 		 * vendors of 32-bit cards fail to clear that bit in many
904 		 * cases (yet the card still detects that it's in a 64-bit
905 		 * slot; go figure).
906 		 */
907 		if (SIP_DECL(check_64bit)(pa)) {
908 			sc->sc_cfg |= CFG_DATA64_EN;
909 			printf(", using 64-bit data transfers");
910 		}
911 		printf("\n");
912 	}
913 
914 	/*
915 	 * XXX Need some PCI flags indicating support for
916 	 * XXX 64-bit addressing.
917 	 */
918 #if 0
919 	if (reg & CFG_M64ADDR)
920 		sc->sc_cfg |= CFG_M64ADDR;
921 	if (reg & CFG_T64ADDR)
922 		sc->sc_cfg |= CFG_T64ADDR;
923 #endif
924 
925 	if (reg & (CFG_TBI_EN|CFG_EXT_125)) {
926 		const char *sep = "";
927 		printf("%s: using ", sc->sc_dev.dv_xname);
928 		if (reg & CFG_EXT_125) {
929 			sc->sc_cfg |= CFG_EXT_125;
930 			printf("%s125MHz clock", sep);
931 			sep = ", ";
932 		}
933 		if (reg & CFG_TBI_EN) {
934 			sc->sc_cfg |= CFG_TBI_EN;
935 			printf("%sten-bit interface", sep);
936 			sep = ", ";
937 		}
938 		printf("\n");
939 	}
940 	if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 ||
941 	    (reg & CFG_MRM_DIS) != 0)
942 		sc->sc_cfg |= CFG_MRM_DIS;
943 	if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 ||
944 	    (reg & CFG_MWI_DIS) != 0)
945 		sc->sc_cfg |= CFG_MWI_DIS;
946 
947 	/*
948 	 * Use the extended descriptor format on the DP83820.  This
949 	 * gives us an interface to VLAN tagging and IPv4/TCP/UDP
950 	 * checksumming.
951 	 */
952 	sc->sc_cfg |= CFG_EXTSTS_EN;
953 #endif /* DP83820 */
954 
955 	/*
956 	 * Initialize our media structures and probe the MII.
957 	 */
958 	sc->sc_mii.mii_ifp = ifp;
959 	sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg;
960 	sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg;
961 	sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg;
962 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange),
963 	    SIP_DECL(mediastatus));
964 
965 	/*
966 	 * XXX We cannot handle flow control on the DP83815.
967 	 */
968 	if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815))
969 		mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
970 			   MII_OFFSET_ANY, 0);
971 	else
972 		mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
973 			   MII_OFFSET_ANY, MIIF_DOPAUSE);
974 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
975 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
976 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
977 	} else
978 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
979 
980 	ifp = &sc->sc_ethercom.ec_if;
981 	strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
982 	ifp->if_softc = sc;
983 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
984 	sc->sc_if_flags = ifp->if_flags;
985 	ifp->if_ioctl = SIP_DECL(ioctl);
986 	ifp->if_start = SIP_DECL(start);
987 	ifp->if_watchdog = SIP_DECL(watchdog);
988 	ifp->if_init = SIP_DECL(init);
989 	ifp->if_stop = SIP_DECL(stop);
990 	IFQ_SET_READY(&ifp->if_snd);
991 
992 	/*
993 	 * We can support 802.1Q VLAN-sized frames.
994 	 */
995 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
996 
997 #ifdef DP83820
998 	/*
999 	 * And the DP83820 can do VLAN tagging in hardware, and
1000 	 * support the jumbo Ethernet MTU.
1001 	 */
1002 	sc->sc_ethercom.ec_capabilities |=
1003 	    ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU;
1004 
1005 	/*
1006 	 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums
1007 	 * in hardware.
1008 	 */
1009 	ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 |
1010 	    IFCAP_CSUM_UDPv4;
1011 #endif /* DP83820 */
1012 
1013 	/*
1014 	 * Attach the interface.
1015 	 */
1016 	if_attach(ifp);
1017 	ether_ifattach(ifp, enaddr);
1018 #if NRND > 0
1019 	rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
1020 	    RND_TYPE_NET, 0);
1021 #endif
1022 
1023 	/*
1024 	 * The number of bytes that must be available in
1025 	 * the Tx FIFO before the bus master can DMA more
1026 	 * data into the FIFO.
1027 	 */
1028 	sc->sc_tx_fill_thresh = 64 / 32;
1029 
1030 	/*
1031 	 * Start at a drain threshold of 512 bytes.  We will
1032 	 * increase it if a DMA underrun occurs.
1033 	 *
1034 	 * XXX The minimum value of this variable should be
1035 	 * tuned.  We may be able to improve performance
1036 	 * by starting with a lower value.  That, however,
1037 	 * may trash the first few outgoing packets if the
1038 	 * PCI bus is saturated.
1039 	 */
1040 #ifdef DP83820
1041 	sc->sc_tx_drain_thresh = 6400 / 32;	/* from FreeBSD nge(4) */
1042 #else
1043 	sc->sc_tx_drain_thresh = 1504 / 32;
1044 #endif
1045 
1046 	/*
1047 	 * Initialize the Rx FIFO drain threshold.
1048 	 *
1049 	 * This is in units of 8 bytes.
1050 	 *
1051 	 * We should never set this value lower than 2; 14 bytes are
1052 	 * required to filter the packet.
1053 	 */
1054 	sc->sc_rx_drain_thresh = 128 / 8;
1055 
1056 #ifdef SIP_EVENT_COUNTERS
1057 	/*
1058 	 * Attach event counters.
1059 	 */
1060 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
1061 	    NULL, sc->sc_dev.dv_xname, "txsstall");
1062 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
1063 	    NULL, sc->sc_dev.dv_xname, "txdstall");
1064 	evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR,
1065 	    NULL, sc->sc_dev.dv_xname, "txforceintr");
1066 	evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR,
1067 	    NULL, sc->sc_dev.dv_xname, "txdintr");
1068 	evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR,
1069 	    NULL, sc->sc_dev.dv_xname, "txiintr");
1070 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
1071 	    NULL, sc->sc_dev.dv_xname, "rxintr");
1072 	evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR,
1073 	    NULL, sc->sc_dev.dv_xname, "hiberr");
1074 #ifndef DP83820
1075 	evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR,
1076 	    NULL, sc->sc_dev.dv_xname, "rxpause");
1077 #endif /* !DP83820 */
1078 #ifdef DP83820
1079 	evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC,
1080 	    NULL, sc->sc_dev.dv_xname, "rxpause");
1081 	evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC,
1082 	    NULL, sc->sc_dev.dv_xname, "txpause");
1083 	evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
1084 	    NULL, sc->sc_dev.dv_xname, "rxipsum");
1085 	evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,
1086 	    NULL, sc->sc_dev.dv_xname, "rxtcpsum");
1087 	evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,
1088 	    NULL, sc->sc_dev.dv_xname, "rxudpsum");
1089 	evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
1090 	    NULL, sc->sc_dev.dv_xname, "txipsum");
1091 	evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
1092 	    NULL, sc->sc_dev.dv_xname, "txtcpsum");
1093 	evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
1094 	    NULL, sc->sc_dev.dv_xname, "txudpsum");
1095 #endif /* DP83820 */
1096 #endif /* SIP_EVENT_COUNTERS */
1097 
1098 	/*
1099 	 * Make sure the interface is shutdown during reboot.
1100 	 */
1101 	sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc);
1102 	if (sc->sc_sdhook == NULL)
1103 		printf("%s: WARNING: unable to establish shutdown hook\n",
1104 		    sc->sc_dev.dv_xname);
1105 	return;
1106 
1107 	/*
1108 	 * Free any resources we've allocated during the failed attach
1109 	 * attempt.  Do this in reverse order and fall through.
1110 	 */
1111  fail_5:
1112 	for (i = 0; i < SIP_NRXDESC; i++) {
1113 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
1114 			bus_dmamap_destroy(sc->sc_dmat,
1115 			    sc->sc_rxsoft[i].rxs_dmamap);
1116 	}
1117  fail_4:
1118 	for (i = 0; i < SIP_TXQUEUELEN; i++) {
1119 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
1120 			bus_dmamap_destroy(sc->sc_dmat,
1121 			    sc->sc_txsoft[i].txs_dmamap);
1122 	}
1123 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
1124  fail_3:
1125 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
1126  fail_2:
1127 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
1128 	    sizeof(struct sip_control_data));
1129  fail_1:
1130 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
1131  fail_0:
1132 	return;
1133 }
1134 
1135 /*
1136  * sip_shutdown:
1137  *
1138  *	Make sure the interface is stopped at reboot time.
1139  */
1140 static void
1141 SIP_DECL(shutdown)(void *arg)
1142 {
1143 	struct sip_softc *sc = arg;
1144 
1145 	SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1);
1146 }
1147 
1148 /*
1149  * sip_start:		[ifnet interface function]
1150  *
1151  *	Start packet transmission on the interface.
1152  */
1153 static void
1154 SIP_DECL(start)(struct ifnet *ifp)
1155 {
1156 	struct sip_softc *sc = ifp->if_softc;
1157 	struct mbuf *m0;
1158 #ifndef DP83820
1159 	struct mbuf *m;
1160 #endif
1161 	struct sip_txsoft *txs;
1162 	bus_dmamap_t dmamap;
1163 	int error, nexttx, lasttx, seg;
1164 	int ofree = sc->sc_txfree;
1165 #if 0
1166 	int firsttx = sc->sc_txnext;
1167 #endif
1168 #ifdef DP83820
1169 	struct m_tag *mtag;
1170 	u_int32_t extsts;
1171 #endif
1172 
1173 #ifndef DP83820
1174 	/*
1175 	 * If we've been told to pause, don't transmit any more packets.
1176 	 */
1177 	if (sc->sc_paused)
1178 		ifp->if_flags |= IFF_OACTIVE;
1179 #endif
1180 
1181 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1182 		return;
1183 
1184 	/*
1185 	 * Loop through the send queue, setting up transmit descriptors
1186 	 * until we drain the queue, or use up all available transmit
1187 	 * descriptors.
1188 	 */
1189 	for (;;) {
1190 		/* Get a work queue entry. */
1191 		if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1192 			SIP_EVCNT_INCR(&sc->sc_ev_txsstall);
1193 			break;
1194 		}
1195 
1196 		/*
1197 		 * Grab a packet off the queue.
1198 		 */
1199 		IFQ_POLL(&ifp->if_snd, m0);
1200 		if (m0 == NULL)
1201 			break;
1202 #ifndef DP83820
1203 		m = NULL;
1204 #endif
1205 
1206 		dmamap = txs->txs_dmamap;
1207 
1208 #ifdef DP83820
1209 		/*
1210 		 * Load the DMA map.  If this fails, the packet either
1211 		 * didn't fit in the allotted number of segments, or we
1212 		 * were short on resources.  For the too-many-segments
1213 		 * case, we simply report an error and drop the packet,
1214 		 * since we can't sanely copy a jumbo packet to a single
1215 		 * buffer.
1216 		 */
1217 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1218 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1219 		if (error) {
1220 			if (error == EFBIG) {
1221 				printf("%s: Tx packet consumes too many "
1222 				    "DMA segments, dropping...\n",
1223 				    sc->sc_dev.dv_xname);
1224 				IFQ_DEQUEUE(&ifp->if_snd, m0);
1225 				m_freem(m0);
1226 				continue;
1227 			}
1228 			/*
1229 			 * Short on resources, just stop for now.
1230 			 */
1231 			break;
1232 		}
1233 #else /* DP83820 */
1234 		/*
1235 		 * Load the DMA map.  If this fails, the packet either
1236 		 * didn't fit in the alloted number of segments, or we
1237 		 * were short on resources.  In this case, we'll copy
1238 		 * and try again.
1239 		 */
1240 		if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1241 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
1242 			MGETHDR(m, M_DONTWAIT, MT_DATA);
1243 			if (m == NULL) {
1244 				printf("%s: unable to allocate Tx mbuf\n",
1245 				    sc->sc_dev.dv_xname);
1246 				break;
1247 			}
1248 			if (m0->m_pkthdr.len > MHLEN) {
1249 				MCLGET(m, M_DONTWAIT);
1250 				if ((m->m_flags & M_EXT) == 0) {
1251 					printf("%s: unable to allocate Tx "
1252 					    "cluster\n", sc->sc_dev.dv_xname);
1253 					m_freem(m);
1254 					break;
1255 				}
1256 			}
1257 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
1258 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
1259 			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
1260 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1261 			if (error) {
1262 				printf("%s: unable to load Tx buffer, "
1263 				    "error = %d\n", sc->sc_dev.dv_xname, error);
1264 				break;
1265 			}
1266 		}
1267 #endif /* DP83820 */
1268 
1269 		/*
1270 		 * Ensure we have enough descriptors free to describe
1271 		 * the packet.  Note, we always reserve one descriptor
1272 		 * at the end of the ring as a termination point, to
1273 		 * prevent wrap-around.
1274 		 */
1275 		if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) {
1276 			/*
1277 			 * Not enough free descriptors to transmit this
1278 			 * packet.  We haven't committed anything yet,
1279 			 * so just unload the DMA map, put the packet
1280 			 * back on the queue, and punt.  Notify the upper
1281 			 * layer that there are not more slots left.
1282 			 *
1283 			 * XXX We could allocate an mbuf and copy, but
1284 			 * XXX is it worth it?
1285 			 */
1286 			ifp->if_flags |= IFF_OACTIVE;
1287 			bus_dmamap_unload(sc->sc_dmat, dmamap);
1288 #ifndef DP83820
1289 			if (m != NULL)
1290 				m_freem(m);
1291 #endif
1292 			SIP_EVCNT_INCR(&sc->sc_ev_txdstall);
1293 			break;
1294 		}
1295 
1296 		IFQ_DEQUEUE(&ifp->if_snd, m0);
1297 #ifndef DP83820
1298 		if (m != NULL) {
1299 			m_freem(m0);
1300 			m0 = m;
1301 		}
1302 #endif
1303 
1304 		/*
1305 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1306 		 */
1307 
1308 		/* Sync the DMA map. */
1309 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1310 		    BUS_DMASYNC_PREWRITE);
1311 
1312 		/*
1313 		 * Initialize the transmit descriptors.
1314 		 */
1315 		for (nexttx = lasttx = sc->sc_txnext, seg = 0;
1316 		     seg < dmamap->dm_nsegs;
1317 		     seg++, nexttx = SIP_NEXTTX(nexttx)) {
1318 			/*
1319 			 * If this is the first descriptor we're
1320 			 * enqueueing, don't set the OWN bit just
1321 			 * yet.  That could cause a race condition.
1322 			 * We'll do it below.
1323 			 */
1324 			sc->sc_txdescs[nexttx].sipd_bufptr =
1325 			    htole32(dmamap->dm_segs[seg].ds_addr);
1326 			sc->sc_txdescs[nexttx].sipd_cmdsts =
1327 			    htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) |
1328 			    CMDSTS_MORE | dmamap->dm_segs[seg].ds_len);
1329 #ifdef DP83820
1330 			sc->sc_txdescs[nexttx].sipd_extsts = 0;
1331 #endif /* DP83820 */
1332 			lasttx = nexttx;
1333 		}
1334 
1335 		/* Clear the MORE bit on the last segment. */
1336 		sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE);
1337 
1338 		/*
1339 		 * If we're in the interrupt delay window, delay the
1340 		 * interrupt.
1341 		 */
1342 		if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) {
1343 			SIP_EVCNT_INCR(&sc->sc_ev_txforceintr);
1344 			sc->sc_txdescs[lasttx].sipd_cmdsts |=
1345 			    htole32(CMDSTS_INTR);
1346 			sc->sc_txwin = 0;
1347 		}
1348 
1349 #ifdef DP83820
1350 		/*
1351 		 * If VLANs are enabled and the packet has a VLAN tag, set
1352 		 * up the descriptor to encapsulate the packet for us.
1353 		 *
1354 		 * This apparently has to be on the last descriptor of
1355 		 * the packet.
1356 		 */
1357 		if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
1358 			sc->sc_txdescs[lasttx].sipd_extsts |=
1359 			    htole32(EXTSTS_VPKT |
1360 				    (VLAN_TAG_VALUE(mtag) & EXTSTS_VTCI));
1361 		}
1362 
1363 		/*
1364 		 * If the upper-layer has requested IPv4/TCPv4/UDPv4
1365 		 * checksumming, set up the descriptor to do this work
1366 		 * for us.
1367 		 *
1368 		 * This apparently has to be on the first descriptor of
1369 		 * the packet.
1370 		 *
1371 		 * Byte-swap constants so the compiler can optimize.
1372 		 */
1373 		extsts = 0;
1374 		if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
1375 			KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4);
1376 			SIP_EVCNT_INCR(&sc->sc_ev_txipsum);
1377 			extsts |= htole32(EXTSTS_IPPKT);
1378 		}
1379 		if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
1380 			KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4);
1381 			SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum);
1382 			extsts |= htole32(EXTSTS_TCPPKT);
1383 		} else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
1384 			KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4);
1385 			SIP_EVCNT_INCR(&sc->sc_ev_txudpsum);
1386 			extsts |= htole32(EXTSTS_UDPPKT);
1387 		}
1388 		sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts;
1389 #endif /* DP83820 */
1390 
1391 		/* Sync the descriptors we're using. */
1392 		SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
1393 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1394 
1395 		/*
1396 		 * The entire packet is set up.  Give the first descrptor
1397 		 * to the chip now.
1398 		 */
1399 		sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |=
1400 		    htole32(CMDSTS_OWN);
1401 		SIP_CDTXSYNC(sc, sc->sc_txnext, 1,
1402 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1403 
1404 		/*
1405 		 * Store a pointer to the packet so we can free it later,
1406 		 * and remember what txdirty will be once the packet is
1407 		 * done.
1408 		 */
1409 		txs->txs_mbuf = m0;
1410 		txs->txs_firstdesc = sc->sc_txnext;
1411 		txs->txs_lastdesc = lasttx;
1412 
1413 		/* Advance the tx pointer. */
1414 		sc->sc_txfree -= dmamap->dm_nsegs;
1415 		sc->sc_txnext = nexttx;
1416 
1417 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1418 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1419 
1420 #if NBPFILTER > 0
1421 		/*
1422 		 * Pass the packet to any BPF listeners.
1423 		 */
1424 		if (ifp->if_bpf)
1425 			bpf_mtap(ifp->if_bpf, m0);
1426 #endif /* NBPFILTER > 0 */
1427 	}
1428 
1429 	if (txs == NULL || sc->sc_txfree == 0) {
1430 		/* No more slots left; notify upper layer. */
1431 		ifp->if_flags |= IFF_OACTIVE;
1432 	}
1433 
1434 	if (sc->sc_txfree != ofree) {
1435 		/*
1436 		 * Start the transmit process.  Note, the manual says
1437 		 * that if there are no pending transmissions in the
1438 		 * chip's internal queue (indicated by TXE being clear),
1439 		 * then the driver software must set the TXDP to the
1440 		 * first descriptor to be transmitted.  However, if we
1441 		 * do this, it causes serious performance degredation on
1442 		 * the DP83820 under load, not setting TXDP doesn't seem
1443 		 * to adversely affect the SiS 900 or DP83815.
1444 		 *
1445 		 * Well, I guess it wouldn't be the first time a manual
1446 		 * has lied -- and they could be speaking of the NULL-
1447 		 * terminated descriptor list case, rather than OWN-
1448 		 * terminated rings.
1449 		 */
1450 #if 0
1451 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) &
1452 		     CR_TXE) == 0) {
1453 			bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP,
1454 			    SIP_CDTXADDR(sc, firsttx));
1455 			bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
1456 		}
1457 #else
1458 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
1459 #endif
1460 
1461 		/* Set a watchdog timer in case the chip flakes out. */
1462 #ifdef DP83820
1463 		/* Gigabit autonegotiation takes 5 seconds. */
1464 		ifp->if_timer = 10;
1465 #else
1466 		ifp->if_timer = 5;
1467 #endif
1468 	}
1469 }
1470 
1471 /*
1472  * sip_watchdog:	[ifnet interface function]
1473  *
1474  *	Watchdog timer handler.
1475  */
1476 static void
1477 SIP_DECL(watchdog)(struct ifnet *ifp)
1478 {
1479 	struct sip_softc *sc = ifp->if_softc;
1480 
1481 	/*
1482 	 * The chip seems to ignore the CMDSTS_INTR bit sometimes!
1483 	 * If we get a timeout, try and sweep up transmit descriptors.
1484 	 * If we manage to sweep them all up, ignore the lack of
1485 	 * interrupt.
1486 	 */
1487 	SIP_DECL(txintr)(sc);
1488 
1489 	if (sc->sc_txfree != SIP_NTXDESC) {
1490 		printf("%s: device timeout\n", sc->sc_dev.dv_xname);
1491 		ifp->if_oerrors++;
1492 
1493 		/* Reset the interface. */
1494 		(void) SIP_DECL(init)(ifp);
1495 	} else if (ifp->if_flags & IFF_DEBUG)
1496 		printf("%s: recovered from device timeout\n",
1497 		    sc->sc_dev.dv_xname);
1498 
1499 	/* Try to get more packets going. */
1500 	SIP_DECL(start)(ifp);
1501 }
1502 
1503 /*
1504  * sip_ioctl:		[ifnet interface function]
1505  *
1506  *	Handle control requests from the operator.
1507  */
1508 static int
1509 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data)
1510 {
1511 	struct sip_softc *sc = ifp->if_softc;
1512 	struct ifreq *ifr = (struct ifreq *)data;
1513 	int s, error;
1514 
1515 	s = splnet();
1516 
1517 	switch (cmd) {
1518 	case SIOCSIFMEDIA:
1519 		/* Flow control requires full-duplex mode. */
1520 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1521 		    (ifr->ifr_media & IFM_FDX) == 0)
1522 		    	ifr->ifr_media &= ~IFM_ETH_FMASK;
1523 #ifdef DP83820
1524 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1525 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1526 				/* We can do both TXPAUSE and RXPAUSE. */
1527 				ifr->ifr_media |=
1528 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1529 			}
1530 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1531 		}
1532 #else
1533 		/* XXX */
1534 		if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815))
1535 			ifr->ifr_media &= ~IFM_ETH_FMASK;
1536 
1537 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1538 			if (ifr->ifr_media & IFM_FLOW) {
1539 				/*
1540 				 * Both TXPAUSE and RXPAUSE must be set.
1541 				 * (SiS900 and DP83815 don't have PAUSE_ASYM
1542 				 * feature.)
1543 				 *
1544 				 * XXX Can SiS900 and DP83815 send PAUSE?
1545 				 */
1546 				ifr->ifr_media |=
1547 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1548 			}
1549 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1550 		}
1551 #endif
1552 		/* FALLTHROUGH */
1553 	case SIOCGIFMEDIA:
1554 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1555 		break;
1556 	case SIOCSIFFLAGS:
1557 		/* If the interface is up and running, only modify the receive
1558 		 * filter when setting promiscuous or debug mode.  Otherwise
1559 		 * fall through to ether_ioctl, which will reset the chip.
1560 		 */
1561 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG)
1562 		if (((ifp->if_flags & (IFF_UP|IFF_RUNNING))
1563 		    == (IFF_UP|IFF_RUNNING))
1564 		    && ((ifp->if_flags & (~RESETIGN))
1565 		    == (sc->sc_if_flags & (~RESETIGN)))) {
1566 			/* Set up the receive filter. */
1567 			(*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1568 			error = 0;
1569 			break;
1570 #undef RESETIGN
1571 		}
1572 		/* FALLTHROUGH */
1573 	default:
1574 		error = ether_ioctl(ifp, cmd, data);
1575 		if (error == ENETRESET) {
1576 			/*
1577 			 * Multicast list has changed; set the hardware filter
1578 			 * accordingly.
1579 			 */
1580 			if (ifp->if_flags & IFF_RUNNING)
1581 			    (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1582 			error = 0;
1583 		}
1584 		break;
1585 	}
1586 
1587 	/* Try to get more packets going. */
1588 	SIP_DECL(start)(ifp);
1589 
1590 	sc->sc_if_flags = ifp->if_flags;
1591 	splx(s);
1592 	return (error);
1593 }
1594 
1595 /*
1596  * sip_intr:
1597  *
1598  *	Interrupt service routine.
1599  */
1600 static int
1601 SIP_DECL(intr)(void *arg)
1602 {
1603 	struct sip_softc *sc = arg;
1604 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1605 	u_int32_t isr;
1606 	int handled = 0;
1607 
1608 	/* Disable interrupts. */
1609 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0);
1610 
1611 	for (;;) {
1612 		/* Reading clears interrupt. */
1613 		isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR);
1614 		if ((isr & sc->sc_imr) == 0)
1615 			break;
1616 
1617 #if NRND > 0
1618 		if (RND_ENABLED(&sc->rnd_source))
1619 			rnd_add_uint32(&sc->rnd_source, isr);
1620 #endif
1621 
1622 		handled = 1;
1623 
1624 		if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) {
1625 			SIP_EVCNT_INCR(&sc->sc_ev_rxintr);
1626 
1627 			/* Grab any new packets. */
1628 			SIP_DECL(rxintr)(sc);
1629 
1630 			if (isr & ISR_RXORN) {
1631 				printf("%s: receive FIFO overrun\n",
1632 				    sc->sc_dev.dv_xname);
1633 
1634 				/* XXX adjust rx_drain_thresh? */
1635 			}
1636 
1637 			if (isr & ISR_RXIDLE) {
1638 				printf("%s: receive ring overrun\n",
1639 				    sc->sc_dev.dv_xname);
1640 
1641 				/* Get the receive process going again. */
1642 				bus_space_write_4(sc->sc_st, sc->sc_sh,
1643 				    SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
1644 				bus_space_write_4(sc->sc_st, sc->sc_sh,
1645 				    SIP_CR, CR_RXE);
1646 			}
1647 		}
1648 
1649 		if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) {
1650 #ifdef SIP_EVENT_COUNTERS
1651 			if (isr & ISR_TXDESC)
1652 				SIP_EVCNT_INCR(&sc->sc_ev_txdintr);
1653 			else if (isr & ISR_TXIDLE)
1654 				SIP_EVCNT_INCR(&sc->sc_ev_txiintr);
1655 #endif
1656 
1657 			/* Sweep up transmit descriptors. */
1658 			SIP_DECL(txintr)(sc);
1659 
1660 			if (isr & ISR_TXURN) {
1661 				u_int32_t thresh;
1662 
1663 				printf("%s: transmit FIFO underrun",
1664 				    sc->sc_dev.dv_xname);
1665 
1666 				thresh = sc->sc_tx_drain_thresh + 1;
1667 				if (thresh <= TXCFG_DRTH &&
1668 				    (thresh * 32) <= (SIP_TXFIFO_SIZE -
1669 				     (sc->sc_tx_fill_thresh * 32))) {
1670 					printf("; increasing Tx drain "
1671 					    "threshold to %u bytes\n",
1672 					    thresh * 32);
1673 					sc->sc_tx_drain_thresh = thresh;
1674 					(void) SIP_DECL(init)(ifp);
1675 				} else {
1676 					(void) SIP_DECL(init)(ifp);
1677 					printf("\n");
1678 				}
1679 			}
1680 		}
1681 
1682 #if !defined(DP83820)
1683 		if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) {
1684 			if (isr & ISR_PAUSE_ST) {
1685 				sc->sc_paused = 1;
1686 				SIP_EVCNT_INCR(&sc->sc_ev_rxpause);
1687 				ifp->if_flags |= IFF_OACTIVE;
1688 			}
1689 			if (isr & ISR_PAUSE_END) {
1690 				sc->sc_paused = 0;
1691 				ifp->if_flags &= ~IFF_OACTIVE;
1692 			}
1693 		}
1694 #endif /* ! DP83820 */
1695 
1696 		if (isr & ISR_HIBERR) {
1697 			int want_init = 0;
1698 
1699 			SIP_EVCNT_INCR(&sc->sc_ev_hiberr);
1700 
1701 #define	PRINTERR(bit, str)						\
1702 			do {						\
1703 				if ((isr & (bit)) != 0) {		\
1704 					if ((ifp->if_flags & IFF_DEBUG) != 0) \
1705 						printf("%s: %s\n",	\
1706 						    sc->sc_dev.dv_xname, str); \
1707 					want_init = 1;			\
1708 				}					\
1709 			} while (/*CONSTCOND*/0)
1710 
1711 			PRINTERR(ISR_DPERR, "parity error");
1712 			PRINTERR(ISR_SSERR, "system error");
1713 			PRINTERR(ISR_RMABT, "master abort");
1714 			PRINTERR(ISR_RTABT, "target abort");
1715 			PRINTERR(ISR_RXSOVR, "receive status FIFO overrun");
1716 			/*
1717 			 * Ignore:
1718 			 *	Tx reset complete
1719 			 *	Rx reset complete
1720 			 */
1721 			if (want_init)
1722 				(void) SIP_DECL(init)(ifp);
1723 #undef PRINTERR
1724 		}
1725 	}
1726 
1727 	/* Re-enable interrupts. */
1728 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE);
1729 
1730 	/* Try to get more packets going. */
1731 	SIP_DECL(start)(ifp);
1732 
1733 	return (handled);
1734 }
1735 
1736 /*
1737  * sip_txintr:
1738  *
1739  *	Helper; handle transmit interrupts.
1740  */
1741 static void
1742 SIP_DECL(txintr)(struct sip_softc *sc)
1743 {
1744 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1745 	struct sip_txsoft *txs;
1746 	u_int32_t cmdsts;
1747 
1748 #ifndef DP83820
1749 	if (sc->sc_paused == 0)
1750 #endif
1751 		ifp->if_flags &= ~IFF_OACTIVE;
1752 
1753 	/*
1754 	 * Go through our Tx list and free mbufs for those
1755 	 * frames which have been transmitted.
1756 	 */
1757 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1758 		SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs,
1759 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1760 
1761 		cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts);
1762 		if (cmdsts & CMDSTS_OWN)
1763 			break;
1764 
1765 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1766 
1767 		sc->sc_txfree += txs->txs_dmamap->dm_nsegs;
1768 
1769 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
1770 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1771 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1772 		m_freem(txs->txs_mbuf);
1773 		txs->txs_mbuf = NULL;
1774 
1775 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1776 
1777 		/*
1778 		 * Check for errors and collisions.
1779 		 */
1780 		if (cmdsts &
1781 		    (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) {
1782 			ifp->if_oerrors++;
1783 			if (cmdsts & CMDSTS_Tx_EC)
1784 				ifp->if_collisions += 16;
1785 			if (ifp->if_flags & IFF_DEBUG) {
1786 				if (cmdsts & CMDSTS_Tx_ED)
1787 					printf("%s: excessive deferral\n",
1788 					    sc->sc_dev.dv_xname);
1789 				if (cmdsts & CMDSTS_Tx_EC)
1790 					printf("%s: excessive collisions\n",
1791 					    sc->sc_dev.dv_xname);
1792 			}
1793 		} else {
1794 			/* Packet was transmitted successfully. */
1795 			ifp->if_opackets++;
1796 			ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts);
1797 		}
1798 	}
1799 
1800 	/*
1801 	 * If there are no more pending transmissions, cancel the watchdog
1802 	 * timer.
1803 	 */
1804 	if (txs == NULL) {
1805 		ifp->if_timer = 0;
1806 		sc->sc_txwin = 0;
1807 	}
1808 }
1809 
1810 #if defined(DP83820)
1811 /*
1812  * sip_rxintr:
1813  *
1814  *	Helper; handle receive interrupts.
1815  */
1816 static void
1817 SIP_DECL(rxintr)(struct sip_softc *sc)
1818 {
1819 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1820 	struct sip_rxsoft *rxs;
1821 	struct mbuf *m;
1822 	u_int32_t cmdsts, extsts;
1823 	int i, len;
1824 
1825 	for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) {
1826 		rxs = &sc->sc_rxsoft[i];
1827 
1828 		SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1829 
1830 		cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts);
1831 		extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts);
1832 		len = CMDSTS_SIZE(cmdsts);
1833 
1834 		/*
1835 		 * NOTE: OWN is set if owned by _consumer_.  We're the
1836 		 * consumer of the receive ring, so if the bit is clear,
1837 		 * we have processed all of the packets.
1838 		 */
1839 		if ((cmdsts & CMDSTS_OWN) == 0) {
1840 			/*
1841 			 * We have processed all of the receive buffers.
1842 			 */
1843 			break;
1844 		}
1845 
1846 		if (__predict_false(sc->sc_rxdiscard)) {
1847 			SIP_INIT_RXDESC(sc, i);
1848 			if ((cmdsts & CMDSTS_MORE) == 0) {
1849 				/* Reset our state. */
1850 				sc->sc_rxdiscard = 0;
1851 			}
1852 			continue;
1853 		}
1854 
1855 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1856 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1857 
1858 		m = rxs->rxs_mbuf;
1859 
1860 		/*
1861 		 * Add a new receive buffer to the ring.
1862 		 */
1863 		if (SIP_DECL(add_rxbuf)(sc, i) != 0) {
1864 			/*
1865 			 * Failed, throw away what we've done so
1866 			 * far, and discard the rest of the packet.
1867 			 */
1868 			ifp->if_ierrors++;
1869 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1870 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1871 			SIP_INIT_RXDESC(sc, i);
1872 			if (cmdsts & CMDSTS_MORE)
1873 				sc->sc_rxdiscard = 1;
1874 			if (sc->sc_rxhead != NULL)
1875 				m_freem(sc->sc_rxhead);
1876 			SIP_RXCHAIN_RESET(sc);
1877 			continue;
1878 		}
1879 
1880 		SIP_RXCHAIN_LINK(sc, m);
1881 
1882 		m->m_len = len;
1883 
1884 		/*
1885 		 * If this is not the end of the packet, keep
1886 		 * looking.
1887 		 */
1888 		if (cmdsts & CMDSTS_MORE) {
1889 			sc->sc_rxlen += len;
1890 			continue;
1891 		}
1892 
1893 		/*
1894 		 * Okay, we have the entire packet now.  The chip includes
1895 		 * the FCS, so we need to trim it.
1896 		 */
1897 		m->m_len -= ETHER_CRC_LEN;
1898 
1899 		*sc->sc_rxtailp = NULL;
1900 		m = sc->sc_rxhead;
1901 		len = m->m_len + sc->sc_rxlen;
1902 
1903 		SIP_RXCHAIN_RESET(sc);
1904 
1905 		/*
1906 		 * If an error occurred, update stats and drop the packet.
1907 		 */
1908 		if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT|
1909 		    CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) {
1910 			ifp->if_ierrors++;
1911 			if ((cmdsts & CMDSTS_Rx_RXA) != 0 &&
1912 			    (cmdsts & CMDSTS_Rx_RXO) == 0) {
1913 				/* Receive overrun handled elsewhere. */
1914 				printf("%s: receive descriptor error\n",
1915 				    sc->sc_dev.dv_xname);
1916 			}
1917 #define	PRINTERR(bit, str)						\
1918 			if ((ifp->if_flags & IFF_DEBUG) != 0 &&		\
1919 			    (cmdsts & (bit)) != 0)			\
1920 				printf("%s: %s\n", sc->sc_dev.dv_xname, str)
1921 			PRINTERR(CMDSTS_Rx_RUNT, "runt packet");
1922 			PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error");
1923 			PRINTERR(CMDSTS_Rx_CRCE, "CRC error");
1924 			PRINTERR(CMDSTS_Rx_FAE, "frame alignment error");
1925 #undef PRINTERR
1926 			m_freem(m);
1927 			continue;
1928 		}
1929 
1930 		/*
1931 		 * If the packet is small enough to fit in a
1932 		 * single header mbuf, allocate one and copy
1933 		 * the data into it.  This greatly reduces
1934 		 * memory consumption when we receive lots
1935 		 * of small packets.
1936 		 */
1937 		if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) {
1938 			struct mbuf *nm;
1939 			MGETHDR(nm, M_DONTWAIT, MT_DATA);
1940 			if (nm == NULL) {
1941 				ifp->if_ierrors++;
1942 				m_freem(m);
1943 				continue;
1944 			}
1945 			nm->m_data += 2;
1946 			nm->m_pkthdr.len = nm->m_len = len;
1947 			m_copydata(m, 0, len, mtod(nm, caddr_t));
1948 			m_freem(m);
1949 			m = nm;
1950 		}
1951 #ifndef __NO_STRICT_ALIGNMENT
1952 		else {
1953 			/*
1954 			 * The DP83820's receive buffers must be 4-byte
1955 			 * aligned.  But this means that the data after
1956 			 * the Ethernet header is misaligned.  To compensate,
1957 			 * we have artificially shortened the buffer size
1958 			 * in the descriptor, and we do an overlapping copy
1959 			 * of the data two bytes further in (in the first
1960 			 * buffer of the chain only).
1961 			 */
1962 			memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t),
1963 			    m->m_len);
1964 			m->m_data += 2;
1965 		}
1966 #endif /* ! __NO_STRICT_ALIGNMENT */
1967 
1968 		/*
1969 		 * If VLANs are enabled, VLAN packets have been unwrapped
1970 		 * for us.  Associate the tag with the packet.
1971 		 */
1972 		if ((extsts & EXTSTS_VPKT) != 0) {
1973 			VLAN_INPUT_TAG(ifp, m, ntohs(extsts & EXTSTS_VTCI),
1974 			    continue);
1975 		}
1976 
1977 		/*
1978 		 * Set the incoming checksum information for the
1979 		 * packet.
1980 		 */
1981 		if ((extsts & EXTSTS_IPPKT) != 0) {
1982 			SIP_EVCNT_INCR(&sc->sc_ev_rxipsum);
1983 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1984 			if (extsts & EXTSTS_Rx_IPERR)
1985 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1986 			if (extsts & EXTSTS_TCPPKT) {
1987 				SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum);
1988 				m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1989 				if (extsts & EXTSTS_Rx_TCPERR)
1990 					m->m_pkthdr.csum_flags |=
1991 					    M_CSUM_TCP_UDP_BAD;
1992 			} else if (extsts & EXTSTS_UDPPKT) {
1993 				SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum);
1994 				m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1995 				if (extsts & EXTSTS_Rx_UDPERR)
1996 					m->m_pkthdr.csum_flags |=
1997 					    M_CSUM_TCP_UDP_BAD;
1998 			}
1999 		}
2000 
2001 		ifp->if_ipackets++;
2002 		m->m_pkthdr.rcvif = ifp;
2003 		m->m_pkthdr.len = len;
2004 
2005 #if NBPFILTER > 0
2006 		/*
2007 		 * Pass this up to any BPF listeners, but only
2008 		 * pass if up the stack if it's for us.
2009 		 */
2010 		if (ifp->if_bpf)
2011 			bpf_mtap(ifp->if_bpf, m);
2012 #endif /* NBPFILTER > 0 */
2013 
2014 		/* Pass it on. */
2015 		(*ifp->if_input)(ifp, m);
2016 	}
2017 
2018 	/* Update the receive pointer. */
2019 	sc->sc_rxptr = i;
2020 }
2021 #else /* ! DP83820 */
2022 /*
2023  * sip_rxintr:
2024  *
2025  *	Helper; handle receive interrupts.
2026  */
2027 static void
2028 SIP_DECL(rxintr)(struct sip_softc *sc)
2029 {
2030 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2031 	struct sip_rxsoft *rxs;
2032 	struct mbuf *m;
2033 	u_int32_t cmdsts;
2034 	int i, len;
2035 
2036 	for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) {
2037 		rxs = &sc->sc_rxsoft[i];
2038 
2039 		SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2040 
2041 		cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts);
2042 
2043 		/*
2044 		 * NOTE: OWN is set if owned by _consumer_.  We're the
2045 		 * consumer of the receive ring, so if the bit is clear,
2046 		 * we have processed all of the packets.
2047 		 */
2048 		if ((cmdsts & CMDSTS_OWN) == 0) {
2049 			/*
2050 			 * We have processed all of the receive buffers.
2051 			 */
2052 			break;
2053 		}
2054 
2055 		/*
2056 		 * If any collisions were seen on the wire, count one.
2057 		 */
2058 		if (cmdsts & CMDSTS_Rx_COL)
2059 			ifp->if_collisions++;
2060 
2061 		/*
2062 		 * If an error occurred, update stats, clear the status
2063 		 * word, and leave the packet buffer in place.  It will
2064 		 * simply be reused the next time the ring comes around.
2065 		 */
2066 		if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT|
2067 		    CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) {
2068 			ifp->if_ierrors++;
2069 			if ((cmdsts & CMDSTS_Rx_RXA) != 0 &&
2070 			    (cmdsts & CMDSTS_Rx_RXO) == 0) {
2071 				/* Receive overrun handled elsewhere. */
2072 				printf("%s: receive descriptor error\n",
2073 				    sc->sc_dev.dv_xname);
2074 			}
2075 #define	PRINTERR(bit, str)						\
2076 			if ((ifp->if_flags & IFF_DEBUG) != 0 &&		\
2077 			    (cmdsts & (bit)) != 0)			\
2078 				printf("%s: %s\n", sc->sc_dev.dv_xname, str)
2079 			PRINTERR(CMDSTS_Rx_RUNT, "runt packet");
2080 			PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error");
2081 			PRINTERR(CMDSTS_Rx_CRCE, "CRC error");
2082 			PRINTERR(CMDSTS_Rx_FAE, "frame alignment error");
2083 #undef PRINTERR
2084 			SIP_INIT_RXDESC(sc, i);
2085 			continue;
2086 		}
2087 
2088 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2089 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2090 
2091 		/*
2092 		 * No errors; receive the packet.  Note, the SiS 900
2093 		 * includes the CRC with every packet.
2094 		 */
2095 		len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN;
2096 
2097 #ifdef __NO_STRICT_ALIGNMENT
2098 		/*
2099 		 * If the packet is small enough to fit in a
2100 		 * single header mbuf, allocate one and copy
2101 		 * the data into it.  This greatly reduces
2102 		 * memory consumption when we receive lots
2103 		 * of small packets.
2104 		 *
2105 		 * Otherwise, we add a new buffer to the receive
2106 		 * chain.  If this fails, we drop the packet and
2107 		 * recycle the old buffer.
2108 		 */
2109 		if (SIP_DECL(copy_small) != 0 && len <= MHLEN) {
2110 			MGETHDR(m, M_DONTWAIT, MT_DATA);
2111 			if (m == NULL)
2112 				goto dropit;
2113 			memcpy(mtod(m, caddr_t),
2114 			    mtod(rxs->rxs_mbuf, caddr_t), len);
2115 			SIP_INIT_RXDESC(sc, i);
2116 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2117 			    rxs->rxs_dmamap->dm_mapsize,
2118 			    BUS_DMASYNC_PREREAD);
2119 		} else {
2120 			m = rxs->rxs_mbuf;
2121 			if (SIP_DECL(add_rxbuf)(sc, i) != 0) {
2122  dropit:
2123 				ifp->if_ierrors++;
2124 				SIP_INIT_RXDESC(sc, i);
2125 				bus_dmamap_sync(sc->sc_dmat,
2126 				    rxs->rxs_dmamap, 0,
2127 				    rxs->rxs_dmamap->dm_mapsize,
2128 				    BUS_DMASYNC_PREREAD);
2129 				continue;
2130 			}
2131 		}
2132 #else
2133 		/*
2134 		 * The SiS 900's receive buffers must be 4-byte aligned.
2135 		 * But this means that the data after the Ethernet header
2136 		 * is misaligned.  We must allocate a new buffer and
2137 		 * copy the data, shifted forward 2 bytes.
2138 		 */
2139 		MGETHDR(m, M_DONTWAIT, MT_DATA);
2140 		if (m == NULL) {
2141  dropit:
2142 			ifp->if_ierrors++;
2143 			SIP_INIT_RXDESC(sc, i);
2144 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2145 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2146 			continue;
2147 		}
2148 		if (len > (MHLEN - 2)) {
2149 			MCLGET(m, M_DONTWAIT);
2150 			if ((m->m_flags & M_EXT) == 0) {
2151 				m_freem(m);
2152 				goto dropit;
2153 			}
2154 		}
2155 		m->m_data += 2;
2156 
2157 		/*
2158 		 * Note that we use clusters for incoming frames, so the
2159 		 * buffer is virtually contiguous.
2160 		 */
2161 		memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len);
2162 
2163 		/* Allow the receive descriptor to continue using its mbuf. */
2164 		SIP_INIT_RXDESC(sc, i);
2165 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2166 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2167 #endif /* __NO_STRICT_ALIGNMENT */
2168 
2169 		ifp->if_ipackets++;
2170 		m->m_pkthdr.rcvif = ifp;
2171 		m->m_pkthdr.len = m->m_len = len;
2172 
2173 #if NBPFILTER > 0
2174 		/*
2175 		 * Pass this up to any BPF listeners, but only
2176 		 * pass if up the stack if it's for us.
2177 		 */
2178 		if (ifp->if_bpf)
2179 			bpf_mtap(ifp->if_bpf, m);
2180 #endif /* NBPFILTER > 0 */
2181 
2182 		/* Pass it on. */
2183 		(*ifp->if_input)(ifp, m);
2184 	}
2185 
2186 	/* Update the receive pointer. */
2187 	sc->sc_rxptr = i;
2188 }
2189 #endif /* DP83820 */
2190 
2191 /*
2192  * sip_tick:
2193  *
2194  *	One second timer, used to tick the MII.
2195  */
2196 static void
2197 SIP_DECL(tick)(void *arg)
2198 {
2199 	struct sip_softc *sc = arg;
2200 	int s;
2201 
2202 	s = splnet();
2203 #ifdef DP83820
2204 #ifdef SIP_EVENT_COUNTERS
2205 	/* Read PAUSE related counts from MIB registers. */
2206 	sc->sc_ev_rxpause.ev_count +=
2207 	    bus_space_read_4(sc->sc_st, sc->sc_sh,
2208 			     SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff;
2209 	sc->sc_ev_txpause.ev_count +=
2210 	    bus_space_read_4(sc->sc_st, sc->sc_sh,
2211 			     SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff;
2212 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR);
2213 #endif /* SIP_EVENT_COUNTERS */
2214 #endif /* DP83820 */
2215 	mii_tick(&sc->sc_mii);
2216 	splx(s);
2217 
2218 	callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc);
2219 }
2220 
2221 /*
2222  * sip_reset:
2223  *
2224  *	Perform a soft reset on the SiS 900.
2225  */
2226 static void
2227 SIP_DECL(reset)(struct sip_softc *sc)
2228 {
2229 	bus_space_tag_t st = sc->sc_st;
2230 	bus_space_handle_t sh = sc->sc_sh;
2231 	int i;
2232 
2233 	bus_space_write_4(st, sh, SIP_IER, 0);
2234 	bus_space_write_4(st, sh, SIP_IMR, 0);
2235 	bus_space_write_4(st, sh, SIP_RFCR, 0);
2236 	bus_space_write_4(st, sh, SIP_CR, CR_RST);
2237 
2238 	for (i = 0; i < SIP_TIMEOUT; i++) {
2239 		if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0)
2240 			break;
2241 		delay(2);
2242 	}
2243 
2244 	if (i == SIP_TIMEOUT)
2245 		printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
2246 
2247 	delay(1000);
2248 
2249 #ifdef DP83820
2250 	/*
2251 	 * Set the general purpose I/O bits.  Do it here in case we
2252 	 * need to have GPIO set up to talk to the media interface.
2253 	 */
2254 	bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior);
2255 	delay(1000);
2256 #endif /* DP83820 */
2257 }
2258 
2259 /*
2260  * sip_init:		[ ifnet interface function ]
2261  *
2262  *	Initialize the interface.  Must be called at splnet().
2263  */
2264 static int
2265 SIP_DECL(init)(struct ifnet *ifp)
2266 {
2267 	struct sip_softc *sc = ifp->if_softc;
2268 	bus_space_tag_t st = sc->sc_st;
2269 	bus_space_handle_t sh = sc->sc_sh;
2270 	struct sip_txsoft *txs;
2271 	struct sip_rxsoft *rxs;
2272 	struct sip_desc *sipd;
2273 #if defined(DP83820)
2274 	u_int32_t reg;
2275 #endif
2276 	int i, error = 0;
2277 
2278 	/*
2279 	 * Cancel any pending I/O.
2280 	 */
2281 	SIP_DECL(stop)(ifp, 0);
2282 
2283 	/*
2284 	 * Reset the chip to a known state.
2285 	 */
2286 	SIP_DECL(reset)(sc);
2287 
2288 #if !defined(DP83820)
2289 	if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) {
2290 		/*
2291 		 * DP83815 manual, page 78:
2292 		 *    4.4 Recommended Registers Configuration
2293 		 *    For optimum performance of the DP83815, version noted
2294 		 *    as DP83815CVNG (SRR = 203h), the listed register
2295 		 *    modifications must be followed in sequence...
2296 		 *
2297 		 * It's not clear if this should be 302h or 203h because that
2298 		 * chip name is listed as SRR 302h in the description of the
2299 		 * SRR register.  However, my revision 302h DP83815 on the
2300 		 * Netgear FA311 purchased in 02/2001 needs these settings
2301 		 * to avoid tons of errors in AcceptPerfectMatch (non-
2302 		 * IFF_PROMISC) mode.  I do not know if other revisions need
2303 		 * this set or not.  [briggs -- 09 March 2001]
2304 		 *
2305 		 * Note that only the low-order 12 bits of 0xe4 are documented
2306 		 * and that this sets reserved bits in that register.
2307 		 */
2308 		bus_space_write_4(st, sh, 0x00cc, 0x0001);
2309 
2310 		bus_space_write_4(st, sh, 0x00e4, 0x189C);
2311 		bus_space_write_4(st, sh, 0x00fc, 0x0000);
2312 		bus_space_write_4(st, sh, 0x00f4, 0x5040);
2313 		bus_space_write_4(st, sh, 0x00f8, 0x008c);
2314 
2315 		bus_space_write_4(st, sh, 0x00cc, 0x0000);
2316 	}
2317 #endif /* ! DP83820 */
2318 
2319 	/*
2320 	 * Initialize the transmit descriptor ring.
2321 	 */
2322 	for (i = 0; i < SIP_NTXDESC; i++) {
2323 		sipd = &sc->sc_txdescs[i];
2324 		memset(sipd, 0, sizeof(struct sip_desc));
2325 		sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i)));
2326 	}
2327 	SIP_CDTXSYNC(sc, 0, SIP_NTXDESC,
2328 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2329 	sc->sc_txfree = SIP_NTXDESC;
2330 	sc->sc_txnext = 0;
2331 	sc->sc_txwin = 0;
2332 
2333 	/*
2334 	 * Initialize the transmit job descriptors.
2335 	 */
2336 	SIMPLEQ_INIT(&sc->sc_txfreeq);
2337 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
2338 	for (i = 0; i < SIP_TXQUEUELEN; i++) {
2339 		txs = &sc->sc_txsoft[i];
2340 		txs->txs_mbuf = NULL;
2341 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2342 	}
2343 
2344 	/*
2345 	 * Initialize the receive descriptor and receive job
2346 	 * descriptor rings.
2347 	 */
2348 	for (i = 0; i < SIP_NRXDESC; i++) {
2349 		rxs = &sc->sc_rxsoft[i];
2350 		if (rxs->rxs_mbuf == NULL) {
2351 			if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) {
2352 				printf("%s: unable to allocate or map rx "
2353 				    "buffer %d, error = %d\n",
2354 				    sc->sc_dev.dv_xname, i, error);
2355 				/*
2356 				 * XXX Should attempt to run with fewer receive
2357 				 * XXX buffers instead of just failing.
2358 				 */
2359 				SIP_DECL(rxdrain)(sc);
2360 				goto out;
2361 			}
2362 		} else
2363 			SIP_INIT_RXDESC(sc, i);
2364 	}
2365 	sc->sc_rxptr = 0;
2366 #ifdef DP83820
2367 	sc->sc_rxdiscard = 0;
2368 	SIP_RXCHAIN_RESET(sc);
2369 #endif /* DP83820 */
2370 
2371 	/*
2372 	 * Set the configuration register; it's already initialized
2373 	 * in sip_attach().
2374 	 */
2375 	bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg);
2376 
2377 	/*
2378 	 * Initialize the prototype TXCFG register.
2379 	 */
2380 #if defined(DP83820)
2381 	sc->sc_txcfg = TXCFG_MXDMA_512;
2382 	sc->sc_rxcfg = RXCFG_MXDMA_512;
2383 #else
2384 	if ((SIP_SIS900_REV(sc, SIS_REV_635) ||
2385 	     SIP_SIS900_REV(sc, SIS_REV_960) ||
2386 	     SIP_SIS900_REV(sc, SIS_REV_900B)) &&
2387 	    (sc->sc_cfg & CFG_EDBMASTEN)) {
2388 		sc->sc_txcfg = TXCFG_MXDMA_64;
2389 		sc->sc_rxcfg = RXCFG_MXDMA_64;
2390 	} else {
2391 		sc->sc_txcfg = TXCFG_MXDMA_512;
2392 		sc->sc_rxcfg = RXCFG_MXDMA_512;
2393 	}
2394 #endif /* DP83820 */
2395 
2396 	sc->sc_txcfg |= TXCFG_ATP |
2397 	    (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) |
2398 	    sc->sc_tx_drain_thresh;
2399 	bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg);
2400 
2401 	/*
2402 	 * Initialize the receive drain threshold if we have never
2403 	 * done so.
2404 	 */
2405 	if (sc->sc_rx_drain_thresh == 0) {
2406 		/*
2407 		 * XXX This value should be tuned.  This is set to the
2408 		 * maximum of 248 bytes, and we may be able to improve
2409 		 * performance by decreasing it (although we should never
2410 		 * set this value lower than 2; 14 bytes are required to
2411 		 * filter the packet).
2412 		 */
2413 		sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT;
2414 	}
2415 
2416 	/*
2417 	 * Initialize the prototype RXCFG register.
2418 	 */
2419 	sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT);
2420 #ifdef DP83820
2421 	/*
2422 	 * Accept long packets (including FCS) so we can handle
2423 	 * 802.1q-tagged frames and jumbo frames properly.
2424 	 */
2425 	if (ifp->if_mtu > ETHERMTU ||
2426 	    (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU))
2427 		sc->sc_rxcfg |= RXCFG_ALP;
2428 
2429 	/*
2430 	 * Checksum offloading is disabled if the user selects an MTU
2431 	 * larger than 8109.  (FreeBSD says 8152, but there is emperical
2432 	 * evidence that >8109 does not work on some boards, such as the
2433 	 * Planex GN-1000TE).
2434 	 */
2435 	if (ifp->if_mtu > 8109 &&
2436 	    (ifp->if_capenable &
2437 	     (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) {
2438 		printf("%s: Checksum offloading does not work if MTU > 8109 - "
2439 		       "disabled.\n", sc->sc_dev.dv_xname);
2440 		ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|
2441 				       IFCAP_CSUM_UDPv4);
2442 		ifp->if_csum_flags_tx = 0;
2443 		ifp->if_csum_flags_rx = 0;
2444 	}
2445 #else
2446 	/*
2447 	 * Accept packets >1518 bytes (including FCS) so we can handle
2448 	 * 802.1q-tagged frames properly.
2449 	 */
2450 	if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
2451 		sc->sc_rxcfg |= RXCFG_ALP;
2452 #endif
2453 	bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg);
2454 
2455 #ifdef DP83820
2456 	/*
2457 	 * Initialize the VLAN/IP receive control register.
2458 	 * We enable checksum computation on all incoming
2459 	 * packets, and do not reject packets w/ bad checksums.
2460 	 */
2461 	reg = 0;
2462 	if (ifp->if_capenable &
2463 	    (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))
2464 		reg |= VRCR_IPEN;
2465 	if (VLAN_ATTACHED(&sc->sc_ethercom))
2466 		reg |= VRCR_VTDEN|VRCR_VTREN;
2467 	bus_space_write_4(st, sh, SIP_VRCR, reg);
2468 
2469 	/*
2470 	 * Initialize the VLAN/IP transmit control register.
2471 	 * We enable outgoing checksum computation on a
2472 	 * per-packet basis.
2473 	 */
2474 	reg = 0;
2475 	if (ifp->if_capenable &
2476 	    (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))
2477 		reg |= VTCR_PPCHK;
2478 	if (VLAN_ATTACHED(&sc->sc_ethercom))
2479 		reg |= VTCR_VPPTI;
2480 	bus_space_write_4(st, sh, SIP_VTCR, reg);
2481 
2482 	/*
2483 	 * If we're using VLANs, initialize the VLAN data register.
2484 	 * To understand why we bswap the VLAN Ethertype, see section
2485 	 * 4.2.36 of the DP83820 manual.
2486 	 */
2487 	if (VLAN_ATTACHED(&sc->sc_ethercom))
2488 		bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN));
2489 #endif /* DP83820 */
2490 
2491 	/*
2492 	 * Give the transmit and receive rings to the chip.
2493 	 */
2494 	bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext));
2495 	bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
2496 
2497 	/*
2498 	 * Initialize the interrupt mask.
2499 	 */
2500 	sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR|
2501 	    ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC;
2502 	bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr);
2503 
2504 	/* Set up the receive filter. */
2505 	(*sc->sc_model->sip_variant->sipv_set_filter)(sc);
2506 
2507 #ifdef DP83820
2508 	/*
2509 	 * Tune sc_rx_flow_thresh.
2510 	 * XXX "More than 8KB" is too short for jumbo frames.
2511 	 * XXX TODO: Threshold value should be user-settable.
2512 	 */
2513 	sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 |
2514 				 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 |
2515 				 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK));
2516 #endif
2517 
2518 	/*
2519 	 * Set the current media.  Do this after initializing the prototype
2520 	 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow
2521 	 * control.
2522 	 */
2523 	mii_mediachg(&sc->sc_mii);
2524 
2525 #ifdef DP83820
2526 	/*
2527 	 * Set the interrupt hold-off timer to 100us.
2528 	 */
2529 	bus_space_write_4(st, sh, SIP_IHR, 0x01);
2530 #endif
2531 
2532 	/*
2533 	 * Enable interrupts.
2534 	 */
2535 	bus_space_write_4(st, sh, SIP_IER, IER_IE);
2536 
2537 	/*
2538 	 * Start the transmit and receive processes.
2539 	 */
2540 	bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE);
2541 
2542 	/*
2543 	 * Start the one second MII clock.
2544 	 */
2545 	callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc);
2546 
2547 	/*
2548 	 * ...all done!
2549 	 */
2550 	ifp->if_flags |= IFF_RUNNING;
2551 	ifp->if_flags &= ~IFF_OACTIVE;
2552 	sc->sc_if_flags = ifp->if_flags;
2553 
2554  out:
2555 	if (error)
2556 		printf("%s: interface not running\n", sc->sc_dev.dv_xname);
2557 	return (error);
2558 }
2559 
2560 /*
2561  * sip_drain:
2562  *
2563  *	Drain the receive queue.
2564  */
2565 static void
2566 SIP_DECL(rxdrain)(struct sip_softc *sc)
2567 {
2568 	struct sip_rxsoft *rxs;
2569 	int i;
2570 
2571 	for (i = 0; i < SIP_NRXDESC; i++) {
2572 		rxs = &sc->sc_rxsoft[i];
2573 		if (rxs->rxs_mbuf != NULL) {
2574 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2575 			m_freem(rxs->rxs_mbuf);
2576 			rxs->rxs_mbuf = NULL;
2577 		}
2578 	}
2579 }
2580 
2581 /*
2582  * sip_stop:		[ ifnet interface function ]
2583  *
2584  *	Stop transmission on the interface.
2585  */
2586 static void
2587 SIP_DECL(stop)(struct ifnet *ifp, int disable)
2588 {
2589 	struct sip_softc *sc = ifp->if_softc;
2590 	bus_space_tag_t st = sc->sc_st;
2591 	bus_space_handle_t sh = sc->sc_sh;
2592 	struct sip_txsoft *txs;
2593 	u_int32_t cmdsts = 0;		/* DEBUG */
2594 
2595 	/*
2596 	 * Stop the one second clock.
2597 	 */
2598 	callout_stop(&sc->sc_tick_ch);
2599 
2600 	/* Down the MII. */
2601 	mii_down(&sc->sc_mii);
2602 
2603 	/*
2604 	 * Disable interrupts.
2605 	 */
2606 	bus_space_write_4(st, sh, SIP_IER, 0);
2607 
2608 	/*
2609 	 * Stop receiver and transmitter.
2610 	 */
2611 	bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD);
2612 
2613 	/*
2614 	 * Release any queued transmit buffers.
2615 	 */
2616 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
2617 		if ((ifp->if_flags & IFF_DEBUG) != 0 &&
2618 		    SIMPLEQ_NEXT(txs, txs_q) == NULL &&
2619 		    (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) &
2620 		     CMDSTS_INTR) == 0)
2621 			printf("%s: sip_stop: last descriptor does not "
2622 			    "have INTR bit set\n", sc->sc_dev.dv_xname);
2623 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
2624 #ifdef DIAGNOSTIC
2625 		if (txs->txs_mbuf == NULL) {
2626 			printf("%s: dirty txsoft with no mbuf chain\n",
2627 			    sc->sc_dev.dv_xname);
2628 			panic("sip_stop");
2629 		}
2630 #endif
2631 		cmdsts |=		/* DEBUG */
2632 		    le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts);
2633 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2634 		m_freem(txs->txs_mbuf);
2635 		txs->txs_mbuf = NULL;
2636 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2637 	}
2638 
2639 	if (disable)
2640 		SIP_DECL(rxdrain)(sc);
2641 
2642 	/*
2643 	 * Mark the interface down and cancel the watchdog timer.
2644 	 */
2645 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2646 	ifp->if_timer = 0;
2647 
2648 	if ((ifp->if_flags & IFF_DEBUG) != 0 &&
2649 	    (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC)
2650 		printf("%s: sip_stop: no INTR bits set in dirty tx "
2651 		    "descriptors\n", sc->sc_dev.dv_xname);
2652 }
2653 
2654 /*
2655  * sip_read_eeprom:
2656  *
2657  *	Read data from the serial EEPROM.
2658  */
2659 static void
2660 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt,
2661     u_int16_t *data)
2662 {
2663 	bus_space_tag_t st = sc->sc_st;
2664 	bus_space_handle_t sh = sc->sc_sh;
2665 	u_int16_t reg;
2666 	int i, x;
2667 
2668 	for (i = 0; i < wordcnt; i++) {
2669 		/* Send CHIP SELECT. */
2670 		reg = EROMAR_EECS;
2671 		bus_space_write_4(st, sh, SIP_EROMAR, reg);
2672 
2673 		/* Shift in the READ opcode. */
2674 		for (x = 3; x > 0; x--) {
2675 			if (SIP_EEPROM_OPC_READ & (1 << (x - 1)))
2676 				reg |= EROMAR_EEDI;
2677 			else
2678 				reg &= ~EROMAR_EEDI;
2679 			bus_space_write_4(st, sh, SIP_EROMAR, reg);
2680 			bus_space_write_4(st, sh, SIP_EROMAR,
2681 			    reg | EROMAR_EESK);
2682 			delay(4);
2683 			bus_space_write_4(st, sh, SIP_EROMAR, reg);
2684 			delay(4);
2685 		}
2686 
2687 		/* Shift in address. */
2688 		for (x = 6; x > 0; x--) {
2689 			if ((word + i) & (1 << (x - 1)))
2690 				reg |= EROMAR_EEDI;
2691 			else
2692 				reg &= ~EROMAR_EEDI;
2693 			bus_space_write_4(st, sh, SIP_EROMAR, reg);
2694 			bus_space_write_4(st, sh, SIP_EROMAR,
2695 			    reg | EROMAR_EESK);
2696 			delay(4);
2697 			bus_space_write_4(st, sh, SIP_EROMAR, reg);
2698 			delay(4);
2699 		}
2700 
2701 		/* Shift out data. */
2702 		reg = EROMAR_EECS;
2703 		data[i] = 0;
2704 		for (x = 16; x > 0; x--) {
2705 			bus_space_write_4(st, sh, SIP_EROMAR,
2706 			    reg | EROMAR_EESK);
2707 			delay(4);
2708 			if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO)
2709 				data[i] |= (1 << (x - 1));
2710 			bus_space_write_4(st, sh, SIP_EROMAR, reg);
2711 			delay(4);
2712 		}
2713 
2714 		/* Clear CHIP SELECT. */
2715 		bus_space_write_4(st, sh, SIP_EROMAR, 0);
2716 		delay(4);
2717 	}
2718 }
2719 
2720 /*
2721  * sip_add_rxbuf:
2722  *
2723  *	Add a receive buffer to the indicated descriptor.
2724  */
2725 static int
2726 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx)
2727 {
2728 	struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx];
2729 	struct mbuf *m;
2730 	int error;
2731 
2732 	MGETHDR(m, M_DONTWAIT, MT_DATA);
2733 	if (m == NULL)
2734 		return (ENOBUFS);
2735 
2736 	MCLGET(m, M_DONTWAIT);
2737 	if ((m->m_flags & M_EXT) == 0) {
2738 		m_freem(m);
2739 		return (ENOBUFS);
2740 	}
2741 
2742 #if defined(DP83820)
2743 	m->m_len = SIP_RXBUF_LEN;
2744 #endif /* DP83820 */
2745 
2746 	if (rxs->rxs_mbuf != NULL)
2747 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2748 
2749 	rxs->rxs_mbuf = m;
2750 
2751 	error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
2752 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
2753 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
2754 	if (error) {
2755 		printf("%s: can't load rx DMA map %d, error = %d\n",
2756 		    sc->sc_dev.dv_xname, idx, error);
2757 		panic("sip_add_rxbuf");		/* XXX */
2758 	}
2759 
2760 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2761 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2762 
2763 	SIP_INIT_RXDESC(sc, idx);
2764 
2765 	return (0);
2766 }
2767 
2768 #if !defined(DP83820)
2769 /*
2770  * sip_sis900_set_filter:
2771  *
2772  *	Set up the receive filter.
2773  */
2774 static void
2775 SIP_DECL(sis900_set_filter)(struct sip_softc *sc)
2776 {
2777 	bus_space_tag_t st = sc->sc_st;
2778 	bus_space_handle_t sh = sc->sc_sh;
2779 	struct ethercom *ec = &sc->sc_ethercom;
2780 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2781 	struct ether_multi *enm;
2782 	u_int8_t *cp;
2783 	struct ether_multistep step;
2784 	u_int32_t crc, mchash[16];
2785 
2786 	/*
2787 	 * Initialize the prototype RFCR.
2788 	 */
2789 	sc->sc_rfcr = RFCR_RFEN;
2790 	if (ifp->if_flags & IFF_BROADCAST)
2791 		sc->sc_rfcr |= RFCR_AAB;
2792 	if (ifp->if_flags & IFF_PROMISC) {
2793 		sc->sc_rfcr |= RFCR_AAP;
2794 		goto allmulti;
2795 	}
2796 
2797 	/*
2798 	 * Set up the multicast address filter by passing all multicast
2799 	 * addresses through a CRC generator, and then using the high-order
2800 	 * 6 bits as an index into the 128 bit multicast hash table (only
2801 	 * the lower 16 bits of each 32 bit multicast hash register are
2802 	 * valid).  The high order bits select the register, while the
2803 	 * rest of the bits select the bit within the register.
2804 	 */
2805 
2806 	memset(mchash, 0, sizeof(mchash));
2807 
2808 	/*
2809 	 * SiS900 (at least SiS963) requires us to register the address of
2810 	 * the PAUSE packet (01:80:c2:00:00:01) into the address filter.
2811 	 */
2812 	crc = 0x0ed423f9;
2813 
2814 	if (SIP_SIS900_REV(sc, SIS_REV_635) ||
2815 	    SIP_SIS900_REV(sc, SIS_REV_960) ||
2816 	    SIP_SIS900_REV(sc, SIS_REV_900B)) {
2817 		/* Just want the 8 most significant bits. */
2818 		crc >>= 24;
2819 	} else {
2820 		/* Just want the 7 most significant bits. */
2821 		crc >>= 25;
2822 	}
2823 
2824 	/* Set the corresponding bit in the hash table. */
2825 	mchash[crc >> 4] |= 1 << (crc & 0xf);
2826 
2827 	ETHER_FIRST_MULTI(step, ec, enm);
2828 	while (enm != NULL) {
2829 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2830 			/*
2831 			 * We must listen to a range of multicast addresses.
2832 			 * For now, just accept all multicasts, rather than
2833 			 * trying to set only those filter bits needed to match
2834 			 * the range.  (At this time, the only use of address
2835 			 * ranges is for IP multicast routing, for which the
2836 			 * range is big enough to require all bits set.)
2837 			 */
2838 			goto allmulti;
2839 		}
2840 
2841 		crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
2842 
2843 		if (SIP_SIS900_REV(sc, SIS_REV_635) ||
2844 		    SIP_SIS900_REV(sc, SIS_REV_960) ||
2845 		    SIP_SIS900_REV(sc, SIS_REV_900B)) {
2846 			/* Just want the 8 most significant bits. */
2847 			crc >>= 24;
2848 		} else {
2849 			/* Just want the 7 most significant bits. */
2850 			crc >>= 25;
2851 		}
2852 
2853 		/* Set the corresponding bit in the hash table. */
2854 		mchash[crc >> 4] |= 1 << (crc & 0xf);
2855 
2856 		ETHER_NEXT_MULTI(step, enm);
2857 	}
2858 
2859 	ifp->if_flags &= ~IFF_ALLMULTI;
2860 	goto setit;
2861 
2862  allmulti:
2863 	ifp->if_flags |= IFF_ALLMULTI;
2864 	sc->sc_rfcr |= RFCR_AAM;
2865 
2866  setit:
2867 #define	FILTER_EMIT(addr, data)						\
2868 	bus_space_write_4(st, sh, SIP_RFCR, (addr));			\
2869 	delay(1);							\
2870 	bus_space_write_4(st, sh, SIP_RFDR, (data));			\
2871 	delay(1)
2872 
2873 	/*
2874 	 * Disable receive filter, and program the node address.
2875 	 */
2876 	cp = LLADDR(ifp->if_sadl);
2877 	FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]);
2878 	FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]);
2879 	FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]);
2880 
2881 	if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2882 		/*
2883 		 * Program the multicast hash table.
2884 		 */
2885 		FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]);
2886 		FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]);
2887 		FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]);
2888 		FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]);
2889 		FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]);
2890 		FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]);
2891 		FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]);
2892 		FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]);
2893 		if (SIP_SIS900_REV(sc, SIS_REV_635) ||
2894 		    SIP_SIS900_REV(sc, SIS_REV_960) ||
2895 		    SIP_SIS900_REV(sc, SIS_REV_900B)) {
2896 			FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]);
2897 			FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]);
2898 			FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]);
2899 			FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]);
2900 			FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]);
2901 			FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]);
2902 			FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]);
2903 			FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]);
2904 		}
2905 	}
2906 #undef FILTER_EMIT
2907 
2908 	/*
2909 	 * Re-enable the receiver filter.
2910 	 */
2911 	bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
2912 }
2913 #endif /* ! DP83820 */
2914 
2915 /*
2916  * sip_dp83815_set_filter:
2917  *
2918  *	Set up the receive filter.
2919  */
2920 static void
2921 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc)
2922 {
2923 	bus_space_tag_t st = sc->sc_st;
2924 	bus_space_handle_t sh = sc->sc_sh;
2925 	struct ethercom *ec = &sc->sc_ethercom;
2926 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2927 	struct ether_multi *enm;
2928 	u_int8_t *cp;
2929 	struct ether_multistep step;
2930 	u_int32_t crc, hash, slot, bit;
2931 #ifdef DP83820
2932 #define	MCHASH_NWORDS	128
2933 #else
2934 #define	MCHASH_NWORDS	32
2935 #endif /* DP83820 */
2936 	u_int16_t mchash[MCHASH_NWORDS];
2937 	int i;
2938 
2939 	/*
2940 	 * Initialize the prototype RFCR.
2941 	 * Enable the receive filter, and accept on
2942 	 *    Perfect (destination address) Match
2943 	 * If IFF_BROADCAST, also accept all broadcast packets.
2944 	 * If IFF_PROMISC, accept all unicast packets (and later, set
2945 	 *    IFF_ALLMULTI and accept all multicast, too).
2946 	 */
2947 	sc->sc_rfcr = RFCR_RFEN | RFCR_APM;
2948 	if (ifp->if_flags & IFF_BROADCAST)
2949 		sc->sc_rfcr |= RFCR_AAB;
2950 	if (ifp->if_flags & IFF_PROMISC) {
2951 		sc->sc_rfcr |= RFCR_AAP;
2952 		goto allmulti;
2953 	}
2954 
2955 #ifdef DP83820
2956 	/*
2957 	 * Set up the DP83820 multicast address filter by passing all multicast
2958 	 * addresses through a CRC generator, and then using the high-order
2959 	 * 11 bits as an index into the 2048 bit multicast hash table.  The
2960 	 * high-order 7 bits select the slot, while the low-order 4 bits
2961 	 * select the bit within the slot.  Note that only the low 16-bits
2962 	 * of each filter word are used, and there are 128 filter words.
2963 	 */
2964 #else
2965 	/*
2966 	 * Set up the DP83815 multicast address filter by passing all multicast
2967 	 * addresses through a CRC generator, and then using the high-order
2968 	 * 9 bits as an index into the 512 bit multicast hash table.  The
2969 	 * high-order 5 bits select the slot, while the low-order 4 bits
2970 	 * select the bit within the slot.  Note that only the low 16-bits
2971 	 * of each filter word are used, and there are 32 filter words.
2972 	 */
2973 #endif /* DP83820 */
2974 
2975 	memset(mchash, 0, sizeof(mchash));
2976 
2977 	ifp->if_flags &= ~IFF_ALLMULTI;
2978 	ETHER_FIRST_MULTI(step, ec, enm);
2979 	if (enm == NULL)
2980 		goto setit;
2981 	while (enm != NULL) {
2982 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2983 			/*
2984 			 * We must listen to a range of multicast addresses.
2985 			 * For now, just accept all multicasts, rather than
2986 			 * trying to set only those filter bits needed to match
2987 			 * the range.  (At this time, the only use of address
2988 			 * ranges is for IP multicast routing, for which the
2989 			 * range is big enough to require all bits set.)
2990 			 */
2991 			goto allmulti;
2992 		}
2993 
2994 		crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
2995 
2996 #ifdef DP83820
2997 		/* Just want the 11 most significant bits. */
2998 		hash = crc >> 21;
2999 #else
3000 		/* Just want the 9 most significant bits. */
3001 		hash = crc >> 23;
3002 #endif /* DP83820 */
3003 
3004 		slot = hash >> 4;
3005 		bit = hash & 0xf;
3006 
3007 		/* Set the corresponding bit in the hash table. */
3008 		mchash[slot] |= 1 << bit;
3009 
3010 		ETHER_NEXT_MULTI(step, enm);
3011 	}
3012 	sc->sc_rfcr |= RFCR_MHEN;
3013 	goto setit;
3014 
3015  allmulti:
3016 	ifp->if_flags |= IFF_ALLMULTI;
3017 	sc->sc_rfcr |= RFCR_AAM;
3018 
3019  setit:
3020 #define	FILTER_EMIT(addr, data)						\
3021 	bus_space_write_4(st, sh, SIP_RFCR, (addr));			\
3022 	delay(1);							\
3023 	bus_space_write_4(st, sh, SIP_RFDR, (data));			\
3024 	delay(1)
3025 
3026 	/*
3027 	 * Disable receive filter, and program the node address.
3028 	 */
3029 	cp = LLADDR(ifp->if_sadl);
3030 	FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]);
3031 	FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]);
3032 	FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]);
3033 
3034 	if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3035 		/*
3036 		 * Program the multicast hash table.
3037 		 */
3038 		for (i = 0; i < MCHASH_NWORDS; i++) {
3039 			FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2),
3040 			    mchash[i]);
3041 		}
3042 	}
3043 #undef FILTER_EMIT
3044 #undef MCHASH_NWORDS
3045 
3046 	/*
3047 	 * Re-enable the receiver filter.
3048 	 */
3049 	bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
3050 }
3051 
3052 #if defined(DP83820)
3053 /*
3054  * sip_dp83820_mii_readreg:	[mii interface function]
3055  *
3056  *	Read a PHY register on the MII of the DP83820.
3057  */
3058 static int
3059 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg)
3060 {
3061 	struct sip_softc *sc = (void *) self;
3062 
3063 	if (sc->sc_cfg & CFG_TBI_EN) {
3064 		bus_addr_t tbireg;
3065 		int rv;
3066 
3067 		if (phy != 0)
3068 			return (0);
3069 
3070 		switch (reg) {
3071 		case MII_BMCR:		tbireg = SIP_TBICR; break;
3072 		case MII_BMSR:		tbireg = SIP_TBISR; break;
3073 		case MII_ANAR:		tbireg = SIP_TANAR; break;
3074 		case MII_ANLPAR:	tbireg = SIP_TANLPAR; break;
3075 		case MII_ANER:		tbireg = SIP_TANER; break;
3076 		case MII_EXTSR:
3077 			/*
3078 			 * Don't even bother reading the TESR register.
3079 			 * The manual documents that the device has
3080 			 * 1000baseX full/half capability, but the
3081 			 * register itself seems read back 0 on some
3082 			 * boards.  Just hard-code the result.
3083 			 */
3084 			return (EXTSR_1000XFDX|EXTSR_1000XHDX);
3085 
3086 		default:
3087 			return (0);
3088 		}
3089 
3090 		rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff;
3091 		if (tbireg == SIP_TBISR) {
3092 			/* LINK and ACOMP are switched! */
3093 			int val = rv;
3094 
3095 			rv = 0;
3096 			if (val & TBISR_MR_LINK_STATUS)
3097 				rv |= BMSR_LINK;
3098 			if (val & TBISR_MR_AN_COMPLETE)
3099 				rv |= BMSR_ACOMP;
3100 
3101 			/*
3102 			 * The manual claims this register reads back 0
3103 			 * on hard and soft reset.  But we want to let
3104 			 * the gentbi driver know that we support auto-
3105 			 * negotiation, so hard-code this bit in the
3106 			 * result.
3107 			 */
3108 			rv |= BMSR_ANEG | BMSR_EXTSTAT;
3109 		}
3110 
3111 		return (rv);
3112 	}
3113 
3114 	return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops),
3115 	    phy, reg));
3116 }
3117 
3118 /*
3119  * sip_dp83820_mii_writereg:	[mii interface function]
3120  *
3121  *	Write a PHY register on the MII of the DP83820.
3122  */
3123 static void
3124 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val)
3125 {
3126 	struct sip_softc *sc = (void *) self;
3127 
3128 	if (sc->sc_cfg & CFG_TBI_EN) {
3129 		bus_addr_t tbireg;
3130 
3131 		if (phy != 0)
3132 			return;
3133 
3134 		switch (reg) {
3135 		case MII_BMCR:		tbireg = SIP_TBICR; break;
3136 		case MII_ANAR:		tbireg = SIP_TANAR; break;
3137 		case MII_ANLPAR:	tbireg = SIP_TANLPAR; break;
3138 		default:
3139 			return;
3140 		}
3141 
3142 		bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val);
3143 		return;
3144 	}
3145 
3146 	mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops),
3147 	    phy, reg, val);
3148 }
3149 
3150 /*
3151  * sip_dp83820_mii_statchg:	[mii interface function]
3152  *
3153  *	Callback from MII layer when media changes.
3154  */
3155 static void
3156 SIP_DECL(dp83820_mii_statchg)(struct device *self)
3157 {
3158 	struct sip_softc *sc = (struct sip_softc *) self;
3159 	struct mii_data *mii = &sc->sc_mii;
3160 	u_int32_t cfg, pcr;
3161 
3162 	/*
3163 	 * Get flow control negotiation result.
3164 	 */
3165 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
3166 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
3167 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
3168 		mii->mii_media_active &= ~IFM_ETH_FMASK;
3169 	}
3170 
3171 	/*
3172 	 * Update TXCFG for full-duplex operation.
3173 	 */
3174 	if ((mii->mii_media_active & IFM_FDX) != 0)
3175 		sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3176 	else
3177 		sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3178 
3179 	/*
3180 	 * Update RXCFG for full-duplex or loopback.
3181 	 */
3182 	if ((mii->mii_media_active & IFM_FDX) != 0 ||
3183 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP)
3184 		sc->sc_rxcfg |= RXCFG_ATX;
3185 	else
3186 		sc->sc_rxcfg &= ~RXCFG_ATX;
3187 
3188 	/*
3189 	 * Update CFG for MII/GMII.
3190 	 */
3191 	if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
3192 		cfg = sc->sc_cfg | CFG_MODE_1000;
3193 	else
3194 		cfg = sc->sc_cfg;
3195 
3196 	/*
3197 	 * 802.3x flow control.
3198 	 */
3199 	pcr = 0;
3200 	if (sc->sc_flowflags & IFM_FLOW) {
3201 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE)
3202 			pcr |= sc->sc_rx_flow_thresh;
3203 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
3204 			pcr |= PCR_PSEN | PCR_PS_MCAST;
3205 	}
3206 
3207 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg);
3208 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg);
3209 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg);
3210 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr);
3211 }
3212 #endif /* ! DP83820 */
3213 
3214 /*
3215  * sip_mii_bitbang_read: [mii bit-bang interface function]
3216  *
3217  *	Read the MII serial port for the MII bit-bang module.
3218  */
3219 static u_int32_t
3220 SIP_DECL(mii_bitbang_read)(struct device *self)
3221 {
3222 	struct sip_softc *sc = (void *) self;
3223 
3224 	return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR));
3225 }
3226 
3227 /*
3228  * sip_mii_bitbang_write: [mii big-bang interface function]
3229  *
3230  *	Write the MII serial port for the MII bit-bang module.
3231  */
3232 static void
3233 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val)
3234 {
3235 	struct sip_softc *sc = (void *) self;
3236 
3237 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val);
3238 }
3239 
3240 #ifndef DP83820
3241 /*
3242  * sip_sis900_mii_readreg:	[mii interface function]
3243  *
3244  *	Read a PHY register on the MII.
3245  */
3246 static int
3247 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg)
3248 {
3249 	struct sip_softc *sc = (struct sip_softc *) self;
3250 	u_int32_t enphy;
3251 
3252 	/*
3253 	 * The PHY of recent SiS chipsets is accessed through bitbang
3254 	 * operations.
3255 	 */
3256 	if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900)
3257 		return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops),
3258 		    phy, reg));
3259 
3260 #ifndef SIS900_MII_RESTRICT
3261 	/*
3262 	 * The SiS 900 has only an internal PHY on the MII.  Only allow
3263 	 * MII address 0.
3264 	 */
3265 	if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
3266 		return (0);
3267 #endif
3268 
3269 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
3270 	    (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) |
3271 	    ENPHY_RWCMD | ENPHY_ACCESS);
3272 	do {
3273 		enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
3274 	} while (enphy & ENPHY_ACCESS);
3275 	return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT);
3276 }
3277 
3278 /*
3279  * sip_sis900_mii_writereg:	[mii interface function]
3280  *
3281  *	Write a PHY register on the MII.
3282  */
3283 static void
3284 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val)
3285 {
3286 	struct sip_softc *sc = (struct sip_softc *) self;
3287 	u_int32_t enphy;
3288 
3289 	if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) {
3290 		mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops),
3291 		    phy, reg, val);
3292 		return;
3293 	}
3294 
3295 #ifndef SIS900_MII_RESTRICT
3296 	/*
3297 	 * The SiS 900 has only an internal PHY on the MII.  Only allow
3298 	 * MII address 0.
3299 	 */
3300 	if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
3301 		return;
3302 #endif
3303 
3304 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
3305 	    (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) |
3306 	    (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS);
3307 	do {
3308 		enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
3309 	} while (enphy & ENPHY_ACCESS);
3310 }
3311 
3312 /*
3313  * sip_sis900_mii_statchg:	[mii interface function]
3314  *
3315  *	Callback from MII layer when media changes.
3316  */
3317 static void
3318 SIP_DECL(sis900_mii_statchg)(struct device *self)
3319 {
3320 	struct sip_softc *sc = (struct sip_softc *) self;
3321 	struct mii_data *mii = &sc->sc_mii;
3322 	u_int32_t flowctl;
3323 
3324 	/*
3325 	 * Get flow control negotiation result.
3326 	 */
3327 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
3328 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
3329 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
3330 		mii->mii_media_active &= ~IFM_ETH_FMASK;
3331 	}
3332 
3333 	/*
3334 	 * Update TXCFG for full-duplex operation.
3335 	 */
3336 	if ((mii->mii_media_active & IFM_FDX) != 0)
3337 		sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3338 	else
3339 		sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3340 
3341 	/*
3342 	 * Update RXCFG for full-duplex or loopback.
3343 	 */
3344 	if ((mii->mii_media_active & IFM_FDX) != 0 ||
3345 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP)
3346 		sc->sc_rxcfg |= RXCFG_ATX;
3347 	else
3348 		sc->sc_rxcfg &= ~RXCFG_ATX;
3349 
3350 	/*
3351 	 * Update IMR for use of 802.3x flow control.
3352 	 */
3353 	if (sc->sc_flowflags & IFM_FLOW) {
3354 		sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST);
3355 		flowctl = FLOWCTL_FLOWEN;
3356 	} else {
3357 		sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST);
3358 		flowctl = 0;
3359 	}
3360 
3361 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg);
3362 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg);
3363 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr);
3364 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl);
3365 }
3366 
3367 /*
3368  * sip_dp83815_mii_readreg:	[mii interface function]
3369  *
3370  *	Read a PHY register on the MII.
3371  */
3372 static int
3373 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg)
3374 {
3375 	struct sip_softc *sc = (struct sip_softc *) self;
3376 	u_int32_t val;
3377 
3378 	/*
3379 	 * The DP83815 only has an internal PHY.  Only allow
3380 	 * MII address 0.
3381 	 */
3382 	if (phy != 0)
3383 		return (0);
3384 
3385 	/*
3386 	 * Apparently, after a reset, the DP83815 can take a while
3387 	 * to respond.  During this recovery period, the BMSR returns
3388 	 * a value of 0.  Catch this -- it's not supposed to happen
3389 	 * (the BMSR has some hardcoded-to-1 bits), and wait for the
3390 	 * PHY to come back to life.
3391 	 *
3392 	 * This works out because the BMSR is the first register
3393 	 * read during the PHY probe process.
3394 	 */
3395 	do {
3396 		val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg));
3397 	} while (reg == MII_BMSR && val == 0);
3398 
3399 	return (val & 0xffff);
3400 }
3401 
3402 /*
3403  * sip_dp83815_mii_writereg:	[mii interface function]
3404  *
3405  *	Write a PHY register to the MII.
3406  */
3407 static void
3408 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val)
3409 {
3410 	struct sip_softc *sc = (struct sip_softc *) self;
3411 
3412 	/*
3413 	 * The DP83815 only has an internal PHY.  Only allow
3414 	 * MII address 0.
3415 	 */
3416 	if (phy != 0)
3417 		return;
3418 
3419 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val);
3420 }
3421 
3422 /*
3423  * sip_dp83815_mii_statchg:	[mii interface function]
3424  *
3425  *	Callback from MII layer when media changes.
3426  */
3427 static void
3428 SIP_DECL(dp83815_mii_statchg)(struct device *self)
3429 {
3430 	struct sip_softc *sc = (struct sip_softc *) self;
3431 
3432 	/*
3433 	 * Update TXCFG for full-duplex operation.
3434 	 */
3435 	if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
3436 		sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3437 	else
3438 		sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3439 
3440 	/*
3441 	 * Update RXCFG for full-duplex or loopback.
3442 	 */
3443 	if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 ||
3444 	    IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP)
3445 		sc->sc_rxcfg |= RXCFG_ATX;
3446 	else
3447 		sc->sc_rxcfg &= ~RXCFG_ATX;
3448 
3449 	/*
3450 	 * XXX 802.3x flow control.
3451 	 */
3452 
3453 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg);
3454 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg);
3455 
3456 	/*
3457 	 * Some DP83815s experience problems when used with short
3458 	 * (< 30m/100ft) Ethernet cables in 100BaseTX mode.  This
3459 	 * sequence adjusts the DSP's signal attenuation to fix the
3460 	 * problem.
3461 	 */
3462 	if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) {
3463 		uint32_t reg;
3464 
3465 		bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001);
3466 
3467 		reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);
3468 		reg &= 0x0fff;
3469 		bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000);
3470 		delay(100);
3471 		reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc);
3472 		reg &= 0x00ff;
3473 		if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) {
3474 			bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc,
3475 			    0x00e8);
3476 			reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);
3477 			bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4,
3478 			    reg | 0x20);
3479 		}
3480 
3481 		bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0);
3482 	}
3483 }
3484 #endif /* DP83820 */
3485 
3486 #if defined(DP83820)
3487 static void
3488 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc,
3489     const struct pci_attach_args *pa, u_int8_t *enaddr)
3490 {
3491 	u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2];
3492 	u_int8_t cksum, *e, match;
3493 	int i;
3494 
3495 	/*
3496 	 * EEPROM data format for the DP83820 can be found in
3497 	 * the DP83820 manual, section 4.2.4.
3498 	 */
3499 
3500 	SIP_DECL(read_eeprom)(sc, 0,
3501 	    sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data);
3502 
3503 	match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8;
3504 	match = ~(match - 1);
3505 
3506 	cksum = 0x55;
3507 	e = (u_int8_t *) eeprom_data;
3508 	for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++)
3509 		cksum += *e++;
3510 
3511 	if (cksum != match)
3512 		printf("%s: Checksum (%x) mismatch (%x)",
3513 		    sc->sc_dev.dv_xname, cksum, match);
3514 
3515 	enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff;
3516 	enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8;
3517 	enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff;
3518 	enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8;
3519 	enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff;
3520 	enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8;
3521 }
3522 #else /* ! DP83820 */
3523 static void
3524 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc)
3525 {
3526 	int i;
3527 
3528 	/*
3529 	 * FreeBSD goes from (300/33)+1 [10] to 0.  There must be
3530 	 * a reason, but I don't know it.
3531 	 */
3532 	for (i = 0; i < 10; i++)
3533 		bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR);
3534 }
3535 
3536 static void
3537 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc,
3538     const struct pci_attach_args *pa, u_int8_t *enaddr)
3539 {
3540 	u_int16_t myea[ETHER_ADDR_LEN / 2];
3541 
3542 	switch (sc->sc_rev) {
3543 	case SIS_REV_630S:
3544 	case SIS_REV_630E:
3545 	case SIS_REV_630EA1:
3546 	case SIS_REV_630ET:
3547 	case SIS_REV_635:
3548 		/*
3549 		 * The MAC address for the on-board Ethernet of
3550 		 * the SiS 630 chipset is in the NVRAM.  Kick
3551 		 * the chip into re-loading it from NVRAM, and
3552 		 * read the MAC address out of the filter registers.
3553 		 */
3554 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD);
3555 
3556 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3557 		    RFCR_RFADDR_NODE0);
3558 		myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3559 		    0xffff;
3560 
3561 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3562 		    RFCR_RFADDR_NODE2);
3563 		myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3564 		    0xffff;
3565 
3566 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3567 		    RFCR_RFADDR_NODE4);
3568 		myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3569 		    0xffff;
3570 		break;
3571 
3572 	case SIS_REV_960:
3573 		{
3574 #define	SIS_SET_EROMAR(x,y)	bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR,	\
3575 				    bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y))
3576 
3577 #define	SIS_CLR_EROMAR(x,y)	bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR,	\
3578 				    bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y))
3579 
3580 			int waittime, i;
3581 
3582 			/* Allow to read EEPROM from LAN. It is shared
3583 			 * between a 1394 controller and the NIC and each
3584 			 * time we access it, we need to set SIS_EECMD_REQ.
3585 			 */
3586 			SIS_SET_EROMAR(sc, EROMAR_REQ);
3587 
3588 			for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */
3589 				/* Force EEPROM to idle state. */
3590 
3591 				/*
3592 				 * XXX-cube This is ugly.  I'll look for docs about it.
3593 				 */
3594 				SIS_SET_EROMAR(sc, EROMAR_EECS);
3595 				SIP_DECL(sis900_eeprom_delay)(sc);
3596 				for (i = 0; i <= 25; i++) { /* Yes, 26 times. */
3597 					SIS_SET_EROMAR(sc, EROMAR_EESK);
3598 					SIP_DECL(sis900_eeprom_delay)(sc);
3599 					SIS_CLR_EROMAR(sc, EROMAR_EESK);
3600 					SIP_DECL(sis900_eeprom_delay)(sc);
3601 				}
3602 				SIS_CLR_EROMAR(sc, EROMAR_EECS);
3603 				SIP_DECL(sis900_eeprom_delay)(sc);
3604 				bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0);
3605 
3606 				if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) {
3607 					SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1,
3608 					    sizeof(myea) / sizeof(myea[0]), myea);
3609 					break;
3610 				}
3611 				DELAY(1);
3612 			}
3613 
3614 			/*
3615 			 * Set SIS_EECTL_CLK to high, so a other master
3616 			 * can operate on the i2c bus.
3617 			 */
3618 			SIS_SET_EROMAR(sc, EROMAR_EESK);
3619 
3620 			/* Refuse EEPROM access by LAN */
3621 			SIS_SET_EROMAR(sc, EROMAR_DONE);
3622 		} break;
3623 
3624 	default:
3625 		SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1,
3626 		    sizeof(myea) / sizeof(myea[0]), myea);
3627 	}
3628 
3629 	enaddr[0] = myea[0] & 0xff;
3630 	enaddr[1] = myea[0] >> 8;
3631 	enaddr[2] = myea[1] & 0xff;
3632 	enaddr[3] = myea[1] >> 8;
3633 	enaddr[4] = myea[2] & 0xff;
3634 	enaddr[5] = myea[2] >> 8;
3635 }
3636 
3637 /* Table and macro to bit-reverse an octet. */
3638 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15};
3639 #define bbr(v)	((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf])
3640 
3641 static void
3642 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc,
3643     const struct pci_attach_args *pa, u_int8_t *enaddr)
3644 {
3645 	u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea;
3646 	u_int8_t cksum, *e, match;
3647 	int i;
3648 
3649 	SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) /
3650 	    sizeof(eeprom_data[0]), eeprom_data);
3651 
3652 	match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8;
3653 	match = ~(match - 1);
3654 
3655 	cksum = 0x55;
3656 	e = (u_int8_t *) eeprom_data;
3657 	for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) {
3658 		cksum += *e++;
3659 	}
3660 	if (cksum != match) {
3661 		printf("%s: Checksum (%x) mismatch (%x)",
3662 		    sc->sc_dev.dv_xname, cksum, match);
3663 	}
3664 
3665 	/*
3666 	 * Unrolled because it makes slightly more sense this way.
3667 	 * The DP83815 stores the MAC address in bit 0 of word 6
3668 	 * through bit 15 of word 8.
3669 	 */
3670 	ea = &eeprom_data[6];
3671 	enaddr[0] = ((*ea & 0x1) << 7);
3672 	ea++;
3673 	enaddr[0] |= ((*ea & 0xFE00) >> 9);
3674 	enaddr[1] = ((*ea & 0x1FE) >> 1);
3675 	enaddr[2] = ((*ea & 0x1) << 7);
3676 	ea++;
3677 	enaddr[2] |= ((*ea & 0xFE00) >> 9);
3678 	enaddr[3] = ((*ea & 0x1FE) >> 1);
3679 	enaddr[4] = ((*ea & 0x1) << 7);
3680 	ea++;
3681 	enaddr[4] |= ((*ea & 0xFE00) >> 9);
3682 	enaddr[5] = ((*ea & 0x1FE) >> 1);
3683 
3684 	/*
3685 	 * In case that's not weird enough, we also need to reverse
3686 	 * the bits in each byte.  This all actually makes more sense
3687 	 * if you think about the EEPROM storage as an array of bits
3688 	 * being shifted into bytes, but that's not how we're looking
3689 	 * at it here...
3690 	 */
3691 	for (i = 0; i < 6 ;i++)
3692 		enaddr[i] = bbr(enaddr[i]);
3693 }
3694 #endif /* DP83820 */
3695 
3696 /*
3697  * sip_mediastatus:	[ifmedia interface function]
3698  *
3699  *	Get the current interface media status.
3700  */
3701 static void
3702 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr)
3703 {
3704 	struct sip_softc *sc = ifp->if_softc;
3705 
3706 	mii_pollstat(&sc->sc_mii);
3707 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
3708 	ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) |
3709 			   sc->sc_flowflags;
3710 }
3711 
3712 /*
3713  * sip_mediachange:	[ifmedia interface function]
3714  *
3715  *	Set hardware to newly-selected media.
3716  */
3717 static int
3718 SIP_DECL(mediachange)(struct ifnet *ifp)
3719 {
3720 	struct sip_softc *sc = ifp->if_softc;
3721 
3722 	if (ifp->if_flags & IFF_UP)
3723 		mii_mediachg(&sc->sc_mii);
3724 	return (0);
3725 }
3726