1 /* $NetBSD: if_sip.c,v 1.4 1999/11/12 18:14:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Silicon Integrated Systems SiS900 10/100 PCI 34 * Ethernet controller. 35 * 36 * Written by Jason R. Thorpe for Network Computer, Inc. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <vm/vm.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #endif 69 70 #ifdef NS 71 #include <netns/ns.h> 72 #include <netns/ns_if.h> 73 #endif 74 75 #include <machine/bus.h> 76 #include <machine/intr.h> 77 78 #include <dev/mii/miivar.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_sipreg.h> 85 86 /* 87 * Devices supported by this driver. 88 */ 89 const struct sip_product { 90 pci_vendor_id_t sip_vendor; 91 pci_product_id_t sip_product; 92 const char *sip_name; 93 } sip_products[] = { 94 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 95 "SiS 900 10/100 Ethernet" }, 96 97 { 0, 0, 98 NULL }, 99 }; 100 101 /* 102 * Transmit descriptor list size. This is arbitrary, but allocate 103 * enough descriptors for 64 pending transmissions, and 16 segments 104 * per packet. This MUST work out to a power of 2. 105 */ 106 #define SIP_NTXSEGS 16 107 108 #define SIP_TXQUEUELEN 64 109 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 110 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 111 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 112 113 /* 114 * Receive descriptor list size. We have one Rx buffer per incoming 115 * packet, so this logic is a little simpler. 116 */ 117 #define SIP_NRXDESC 64 118 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 119 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 120 121 /* 122 * Control structures are DMA'd to the SiS900 chip. We allocate them in 123 * a single clump that maps to a single DMA segment to make several things 124 * easier. 125 */ 126 struct sip_control_data { 127 /* 128 * The transmit descriptors. 129 */ 130 struct sip_desc scd_txdescs[SIP_NTXDESC]; 131 132 /* 133 * The receive descriptors. 134 */ 135 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 136 }; 137 138 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 139 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 140 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 141 142 /* 143 * Software state for transmit jobs. 144 */ 145 struct sip_txsoft { 146 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 147 bus_dmamap_t txs_dmamap; /* our DMA map */ 148 int txs_firstdesc; /* first descriptor in packet */ 149 int txs_lastdesc; /* last descriptor in packet */ 150 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 151 }; 152 153 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 154 155 /* 156 * Software state for receive jobs. 157 */ 158 struct sip_rxsoft { 159 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 160 bus_dmamap_t rxs_dmamap; /* our DMA map */ 161 }; 162 163 /* 164 * Software state per device. 165 */ 166 struct sip_softc { 167 struct device sc_dev; /* generic device information */ 168 bus_space_tag_t sc_st; /* bus space tag */ 169 bus_space_handle_t sc_sh; /* bus space handle */ 170 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 171 struct ethercom sc_ethercom; /* ethernet common data */ 172 void *sc_sdhook; /* shutdown hook */ 173 174 void *sc_ih; /* interrupt cookie */ 175 176 struct mii_data sc_mii; /* MII/media information */ 177 178 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 179 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 180 181 /* 182 * Software state for transmit and receive descriptors. 183 */ 184 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 185 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 186 187 /* 188 * Control data structures. 189 */ 190 struct sip_control_data *sc_control_data; 191 #define sc_txdescs sc_control_data->scd_txdescs 192 #define sc_rxdescs sc_control_data->scd_rxdescs 193 194 u_int32_t sc_txcfg; /* prototype TXCFG register */ 195 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 196 u_int32_t sc_imr; /* prototype IMR register */ 197 u_int32_t sc_rfcr; /* prototype RFCR register */ 198 199 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 200 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 201 202 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 203 204 int sc_flags; /* misc. flags; see below */ 205 206 int sc_txfree; /* number of free Tx descriptors */ 207 int sc_txnext; /* next ready Tx descriptor */ 208 209 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 210 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 211 212 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 213 }; 214 215 /* sc_flags */ 216 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 217 218 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 219 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 220 221 #define SIP_CDTXSYNC(sc, x, n, ops) \ 222 do { \ 223 int __x, __n; \ 224 \ 225 __x = (x); \ 226 __n = (n); \ 227 \ 228 /* If it will wrap around, sync to the end of the ring. */ \ 229 if ((__x + __n) > SIP_NTXDESC) { \ 230 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 231 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 232 (SIP_NTXDESC - __x), (ops)); \ 233 __n -= (SIP_NTXDESC - __x); \ 234 __x = 0; \ 235 } \ 236 \ 237 /* Now sync whatever is left. */ \ 238 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 239 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 240 } while (0) 241 242 #define SIP_CDRXSYNC(sc, x, ops) \ 243 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 244 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 245 246 /* 247 * Note we rely on MCLBYTES being a power of two below. 248 */ 249 #define SIP_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 252 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 253 \ 254 __sipd->sipd_link = SIP_CDRXADDR((sc), SIP_NEXTRX((x))); \ 255 __sipd->sipd_bufptr = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 256 __sipd->sipd_cmdsts = CMDSTS_INTR | \ 257 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK); \ 258 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 259 } while (0) 260 261 void sip_start __P((struct ifnet *)); 262 void sip_watchdog __P((struct ifnet *)); 263 int sip_ioctl __P((struct ifnet *, u_long, caddr_t)); 264 265 void sip_shutdown __P((void *)); 266 267 void sip_reset __P((struct sip_softc *)); 268 int sip_init __P((struct sip_softc *)); 269 void sip_stop __P((struct sip_softc *, int)); 270 void sip_rxdrain __P((struct sip_softc *)); 271 int sip_add_rxbuf __P((struct sip_softc *, int)); 272 void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *)); 273 void sip_set_filter __P((struct sip_softc *)); 274 void sip_tick __P((void *)); 275 276 int sip_intr __P((void *)); 277 void sip_txintr __P((struct sip_softc *)); 278 void sip_rxintr __P((struct sip_softc *)); 279 280 int sip_mii_readreg __P((struct device *, int, int)); 281 void sip_mii_writereg __P((struct device *, int, int, int)); 282 void sip_mii_statchg __P((struct device *)); 283 284 int sip_mediachange __P((struct ifnet *)); 285 void sip_mediastatus __P((struct ifnet *, struct ifmediareq *)); 286 287 int sip_match __P((struct device *, struct cfdata *, void *)); 288 void sip_attach __P((struct device *, struct device *, void *)); 289 290 int sip_copy_small = 0; 291 292 struct cfattach sip_ca = { 293 sizeof(struct sip_softc), sip_match, sip_attach, 294 }; 295 296 const struct sip_product *sip_lookup __P((const struct pci_attach_args *)); 297 298 const struct sip_product * 299 sip_lookup(pa) 300 const struct pci_attach_args *pa; 301 { 302 const struct sip_product *sip; 303 304 for (sip = sip_products; sip->sip_name != NULL; sip++) { 305 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 306 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 307 return (sip); 308 } 309 return (NULL); 310 } 311 312 int 313 sip_match(parent, cf, aux) 314 struct device *parent; 315 struct cfdata *cf; 316 void *aux; 317 { 318 struct pci_attach_args *pa = aux; 319 320 if (sip_lookup(pa) != NULL) 321 return (1); 322 323 return (0); 324 } 325 326 void 327 sip_attach(parent, self, aux) 328 struct device *parent, *self; 329 void *aux; 330 { 331 struct sip_softc *sc = (struct sip_softc *) self; 332 struct pci_attach_args *pa = aux; 333 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 334 pci_chipset_tag_t pc = pa->pa_pc; 335 pci_intr_handle_t ih; 336 const char *intrstr = NULL; 337 bus_space_tag_t iot, memt; 338 bus_space_handle_t ioh, memh; 339 bus_dma_segment_t seg; 340 int ioh_valid, memh_valid; 341 int i, rseg, error; 342 const struct sip_product *sip; 343 pcireg_t pmode; 344 u_int16_t enaddr[ETHER_ADDR_LEN / 2]; 345 346 sip = sip_lookup(pa); 347 if (sip == NULL) { 348 printf("\n"); 349 panic("sip_attach: impossible"); 350 } 351 352 printf(": %s\n", sip->sip_name); 353 354 /* 355 * Map the device. 356 */ 357 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 358 PCI_MAPREG_TYPE_IO, 0, 359 &iot, &ioh, NULL, NULL) == 0); 360 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 361 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 362 &memt, &memh, NULL, NULL) == 0); 363 364 if (memh_valid) { 365 sc->sc_st = memt; 366 sc->sc_sh = memh; 367 } else if (ioh_valid) { 368 sc->sc_st = iot; 369 sc->sc_sh = ioh; 370 } else { 371 printf("%s: unable to map device registers\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } 375 376 sc->sc_dmat = pa->pa_dmat; 377 378 /* Enable bus mastering. */ 379 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 380 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 381 PCI_COMMAND_MASTER_ENABLE); 382 383 /* Get it out of power save mode if needed. */ 384 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 0, 0)) { 385 pmode = pci_conf_read(pc, pa->pa_tag, SIP_PCI_CFGPMCSR) & 0x3; 386 if (pmode == 3) { 387 /* 388 * The card has lost all configuration data in 389 * this state, so punt. 390 */ 391 printf("%s: unable to wake up from power state D3\n", 392 sc->sc_dev.dv_xname); 393 return; 394 } 395 if (pmode != 0) { 396 printf("%s: waking up from power state D%d\n", 397 sc->sc_dev.dv_xname, pmode); 398 pci_conf_write(pc, pa->pa_tag, SIP_PCI_CFGPMCSR, 0); 399 } 400 } 401 402 /* 403 * Map and establish our interrupt. 404 */ 405 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 406 pa->pa_intrline, &ih)) { 407 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 408 return; 409 } 410 intrstr = pci_intr_string(pc, ih); 411 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 412 if (sc->sc_ih == NULL) { 413 printf("%s: unable to establish interrupt", 414 sc->sc_dev.dv_xname); 415 if (intrstr != NULL) 416 printf(" at %s", intrstr); 417 printf("\n"); 418 return; 419 } 420 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 421 422 SIMPLEQ_INIT(&sc->sc_txfreeq); 423 SIMPLEQ_INIT(&sc->sc_txdirtyq); 424 425 /* 426 * Allocate the control data structures, and create and load the 427 * DMA map for it. 428 */ 429 if ((error = bus_dmamem_alloc(sc->sc_dmat, 430 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 431 0)) != 0) { 432 printf("%s: unable to allocate control data, error = %d\n", 433 sc->sc_dev.dv_xname, error); 434 goto fail_0; 435 } 436 437 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 438 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 439 BUS_DMA_COHERENT)) != 0) { 440 printf("%s: unable to map control data, error = %d\n", 441 sc->sc_dev.dv_xname, error); 442 goto fail_1; 443 } 444 445 if ((error = bus_dmamap_create(sc->sc_dmat, 446 sizeof(struct sip_control_data), 1, 447 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 448 printf("%s: unable to create control data DMA map, " 449 "error = %d\n", sc->sc_dev.dv_xname, error); 450 goto fail_2; 451 } 452 453 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 454 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 455 0)) != 0) { 456 printf("%s: unable to load control data DMA map, error = %d\n", 457 sc->sc_dev.dv_xname, error); 458 goto fail_3; 459 } 460 461 /* 462 * Create the transmit buffer DMA maps. 463 */ 464 for (i = 0; i < SIP_TXQUEUELEN; i++) { 465 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 466 SIP_NTXSEGS, MCLBYTES, 0, 0, 467 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 468 printf("%s: unable to create tx DMA map %d, " 469 "error = %d\n", sc->sc_dev.dv_xname, i, error); 470 goto fail_4; 471 } 472 } 473 474 /* 475 * Create the receive buffer DMA maps. 476 */ 477 for (i = 0; i < SIP_NRXDESC; i++) { 478 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 479 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 480 printf("%s: unable to create rx DMA map %d, " 481 "error = %d\n", sc->sc_dev.dv_xname, i, error); 482 goto fail_5; 483 } 484 sc->sc_rxsoft[i].rxs_mbuf = NULL; 485 } 486 487 /* 488 * Reset the chip to a known state. 489 */ 490 sip_reset(sc); 491 492 /* 493 * Read the Ethernet address from the EEPROM. 494 */ 495 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 496 sizeof(enaddr) / sizeof(enaddr[0]), enaddr); 497 498 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 499 ether_sprintf((u_int8_t *)enaddr)); 500 501 /* 502 * Initialize our media structures and probe the MII. 503 */ 504 sc->sc_mii.mii_ifp = ifp; 505 sc->sc_mii.mii_readreg = sip_mii_readreg; 506 sc->sc_mii.mii_writereg = sip_mii_writereg; 507 sc->sc_mii.mii_statchg = sip_mii_statchg; 508 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 509 sip_mediastatus); 510 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 511 MII_OFFSET_ANY); 512 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 515 } else 516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 517 518 ifp = &sc->sc_ethercom.ec_if; 519 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 520 ifp->if_softc = sc; 521 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 522 ifp->if_ioctl = sip_ioctl; 523 ifp->if_start = sip_start; 524 ifp->if_watchdog = sip_watchdog; 525 526 /* 527 * Attach the interface. 528 */ 529 if_attach(ifp); 530 ether_ifattach(ifp, (u_int8_t *)enaddr); 531 #if NBPFILTER > 0 532 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 533 sizeof(struct ether_header)); 534 #endif 535 536 /* 537 * Make sure the interface is shutdown during reboot. 538 */ 539 sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc); 540 if (sc->sc_sdhook == NULL) 541 printf("%s: WARNING: unable to establish shutdown hook\n", 542 sc->sc_dev.dv_xname); 543 return; 544 545 /* 546 * Free any resources we've allocated during the failed attach 547 * attempt. Do this in reverse order and fall through. 548 */ 549 fail_5: 550 for (i = 0; i < SIP_NRXDESC; i++) { 551 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 552 bus_dmamap_destroy(sc->sc_dmat, 553 sc->sc_rxsoft[i].rxs_dmamap); 554 } 555 fail_4: 556 for (i = 0; i < SIP_TXQUEUELEN; i++) { 557 if (sc->sc_txsoft[i].txs_dmamap != NULL) 558 bus_dmamap_destroy(sc->sc_dmat, 559 sc->sc_txsoft[i].txs_dmamap); 560 } 561 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 562 fail_3: 563 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 564 fail_2: 565 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 566 sizeof(struct sip_control_data)); 567 fail_1: 568 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 569 fail_0: 570 return; 571 } 572 573 /* 574 * sip_shutdown: 575 * 576 * Make sure the interface is stopped at reboot time. 577 */ 578 void 579 sip_shutdown(arg) 580 void *arg; 581 { 582 struct sip_softc *sc = arg; 583 584 sip_stop(sc, 1); 585 } 586 587 /* 588 * sip_start: [ifnet interface function] 589 * 590 * Start packet transmission on the interface. 591 */ 592 void 593 sip_start(ifp) 594 struct ifnet *ifp; 595 { 596 struct sip_softc *sc = ifp->if_softc; 597 struct mbuf *m0, *m; 598 struct sip_txsoft *txs; 599 bus_dmamap_t dmamap; 600 int error, firsttx, nexttx, lasttx, ofree, seg; 601 602 /* 603 * If we've been told to pause, don't transmit any more packets. 604 */ 605 if (sc->sc_flags & SIPF_PAUSED) 606 ifp->if_flags |= IFF_OACTIVE; 607 608 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 609 return; 610 611 /* 612 * Remember the previous number of free descriptors and 613 * the first descriptor we'll use. 614 */ 615 ofree = sc->sc_txfree; 616 firsttx = sc->sc_txnext; 617 618 /* 619 * Loop through the send queue, setting up transmit descriptors 620 * until we drain the queue, or use up all available transmit 621 * descriptors. 622 */ 623 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 624 sc->sc_txfree != 0) { 625 /* 626 * Grab a packet off the queue. 627 */ 628 IF_DEQUEUE(&ifp->if_snd, m0); 629 if (m0 == NULL) 630 break; 631 632 dmamap = txs->txs_dmamap; 633 634 /* 635 * Load the DMA map. If this fails, the packet either 636 * didn't fit in the alloted number of segments, or we 637 * were short on resources. In this case, we'll copy 638 * and try again. 639 */ 640 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 641 BUS_DMA_NOWAIT) != 0) { 642 MGETHDR(m, M_DONTWAIT, MT_DATA); 643 if (m == NULL) { 644 printf("%s: unable to allocate Tx mbuf\n", 645 sc->sc_dev.dv_xname); 646 IF_PREPEND(&ifp->if_snd, m0); 647 break; 648 } 649 if (m0->m_pkthdr.len > MHLEN) { 650 MCLGET(m, M_DONTWAIT); 651 if ((m->m_flags & M_EXT) == 0) { 652 printf("%s: unable to allocate Tx " 653 "cluster\n", sc->sc_dev.dv_xname); 654 m_freem(m); 655 IF_PREPEND(&ifp->if_snd, m0); 656 break; 657 } 658 } 659 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 660 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 661 m_freem(m0); 662 m0 = m; 663 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 664 m0, BUS_DMA_NOWAIT); 665 if (error) { 666 printf("%s: unable to load Tx buffer, " 667 "error = %d\n", sc->sc_dev.dv_xname, error); 668 IF_PREPEND(&ifp->if_snd, m0); 669 break; 670 } 671 } 672 673 /* 674 * Ensure we have enough descriptors free to describe 675 * the packet. 676 */ 677 if (dmamap->dm_nsegs > sc->sc_txfree) { 678 /* 679 * Not enough free descriptors to transmit this 680 * packet. We haven't committed anything yet, 681 * so just unload the DMA map, put the packet 682 * back on the queue, and punt. Notify the upper 683 * layer that there are not more slots left. 684 * 685 * XXX We could allocate an mbuf and copy, but 686 * XXX is it worth it? 687 */ 688 ifp->if_flags |= IFF_OACTIVE; 689 bus_dmamap_unload(sc->sc_dmat, dmamap); 690 IF_PREPEND(&ifp->if_snd, m0); 691 break; 692 } 693 694 /* 695 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 696 */ 697 698 /* Sync the DMA map. */ 699 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 700 BUS_DMASYNC_PREWRITE); 701 702 /* 703 * Initialize the transmit descriptors. 704 */ 705 for (nexttx = sc->sc_txnext, seg = 0; 706 seg < dmamap->dm_nsegs; 707 seg++, nexttx = SIP_NEXTTX(nexttx)) { 708 /* 709 * If this is the first descriptor we're 710 * enqueueing, don't set the OWN bit just 711 * yet. That could cause a race condition. 712 * We'll do it below. 713 */ 714 sc->sc_txdescs[nexttx].sipd_bufptr = 715 dmamap->dm_segs[seg].ds_addr; 716 sc->sc_txdescs[nexttx].sipd_cmdsts = 717 (nexttx == firsttx ? 0 : CMDSTS_OWN) | 718 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len; 719 lasttx = nexttx; 720 } 721 722 /* Clear the MORE bit on the last segment. */ 723 sc->sc_txdescs[lasttx].sipd_cmdsts &= ~CMDSTS_MORE; 724 725 /* Sync the descriptors we're using. */ 726 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 727 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 728 729 /* 730 * Store a pointer to the packet so we can free it later, 731 * and remember what txdirty will be once the packet is 732 * done. 733 */ 734 txs->txs_mbuf = m0; 735 txs->txs_firstdesc = sc->sc_txnext; 736 txs->txs_lastdesc = lasttx; 737 738 /* Advance the tx pointer. */ 739 sc->sc_txfree -= dmamap->dm_nsegs; 740 sc->sc_txnext = nexttx; 741 742 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 743 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 744 745 #if NBPFILTER > 0 746 /* 747 * Pass the packet to any BPF listeners. 748 */ 749 if (ifp->if_bpf) 750 bpf_mtap(ifp->if_bpf, m0); 751 #endif /* NBPFILTER > 0 */ 752 } 753 754 if (txs == NULL || sc->sc_txfree == 0) { 755 /* No more slots left; notify upper layer. */ 756 ifp->if_flags |= IFF_OACTIVE; 757 } 758 759 if (sc->sc_txfree != ofree) { 760 /* 761 * Cause a descriptor interrupt to happen on the 762 * last packet we enqueued. 763 */ 764 sc->sc_txdescs[lasttx].sipd_cmdsts |= CMDSTS_INTR; 765 SIP_CDTXSYNC(sc, lasttx, 1, 766 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 767 768 /* 769 * The entire packet chain is set up. Give the 770 * first descrptor to the chip now. 771 */ 772 sc->sc_txdescs[firsttx].sipd_cmdsts |= CMDSTS_OWN; 773 SIP_CDTXSYNC(sc, firsttx, 1, 774 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 775 776 /* Start the transmit process. */ 777 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 778 CR_TXE) == 0) { 779 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 780 SIP_CDTXADDR(sc, firsttx)); 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 782 } 783 784 /* Set a watchdog timer in case the chip flakes out. */ 785 ifp->if_timer = 5; 786 } 787 } 788 789 /* 790 * sip_watchdog: [ifnet interface function] 791 * 792 * Watchdog timer handler. 793 */ 794 void 795 sip_watchdog(ifp) 796 struct ifnet *ifp; 797 { 798 struct sip_softc *sc = ifp->if_softc; 799 800 /* 801 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 802 * If we get a timeout, try and sweep up transmit descriptors. 803 * If we manage to sweep them all up, ignore the lack of 804 * interrupt. 805 */ 806 sip_txintr(sc); 807 808 if (sc->sc_txfree != SIP_NTXDESC) { 809 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 810 ifp->if_oerrors++; 811 812 /* Reset the interface. */ 813 (void) sip_init(sc); 814 } else if (ifp->if_flags & IFF_DEBUG) 815 printf("%s: recovered from device timeout\n", 816 sc->sc_dev.dv_xname); 817 818 /* Try to get more packets going. */ 819 sip_start(ifp); 820 } 821 822 /* 823 * sip_ioctl: [ifnet interface function] 824 * 825 * Handle control requests from the operator. 826 */ 827 int 828 sip_ioctl(ifp, cmd, data) 829 struct ifnet *ifp; 830 u_long cmd; 831 caddr_t data; 832 { 833 struct sip_softc *sc = ifp->if_softc; 834 struct ifreq *ifr = (struct ifreq *)data; 835 struct ifaddr *ifa = (struct ifaddr *)data; 836 int s, error = 0; 837 838 s = splnet(); 839 840 switch (cmd) { 841 case SIOCSIFADDR: 842 ifp->if_flags |= IFF_UP; 843 844 switch (ifa->ifa_addr->sa_family) { 845 #ifdef INET 846 case AF_INET: 847 if ((error = sip_init(sc)) != 0) 848 break; 849 arp_ifinit(ifp, ifa); 850 break; 851 #endif /* INET */ 852 #ifdef NS 853 case AF_NS: 854 { 855 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 856 857 if (ns_nullhost(*ina)) 858 ina->x_host = *(union ns_host *) 859 LLADDR(ifp->if_sadl); 860 else 861 memcpy(LLADDR(ifp->if_sadl), 862 ina->x_host.c_host, ifp->if_addrlen); 863 error = sip_init(sc); 864 break; 865 } 866 #endif /* NS */ 867 default: 868 error = sip_init(sc); 869 break; 870 } 871 break; 872 873 case SIOCSIFMTU: 874 if (ifr->ifr_mtu > ETHERMTU) 875 error = EINVAL; 876 else 877 ifp->if_mtu = ifr->ifr_mtu; 878 break; 879 880 case SIOCSIFFLAGS: 881 if ((ifp->if_flags & IFF_UP) == 0 && 882 (ifp->if_flags & IFF_RUNNING) != 0) { 883 /* 884 * If interface is marked down and it is running, then 885 * stop it. 886 */ 887 sip_stop(sc, 1); 888 } else if ((ifp->if_flags & IFF_UP) != 0 && 889 (ifp->if_flags & IFF_RUNNING) == 0) { 890 /* 891 * If interfase it marked up and it is stopped, then 892 * start it. 893 */ 894 error = sip_init(sc); 895 } else if ((ifp->if_flags & IFF_UP) != 0) { 896 /* 897 * Reset the interface to pick up changes in any other 898 * flags that affect the hardware state. 899 */ 900 error = sip_init(sc); 901 } 902 break; 903 904 case SIOCADDMULTI: 905 case SIOCDELMULTI: 906 error = (cmd == SIOCADDMULTI) ? 907 ether_addmulti(ifr, &sc->sc_ethercom) : 908 ether_delmulti(ifr, &sc->sc_ethercom); 909 910 if (error == ENETRESET) { 911 /* 912 * Multicast list has changed; set the hardware filter 913 * accordingly. 914 */ 915 sip_set_filter(sc); 916 error = 0; 917 } 918 break; 919 920 case SIOCSIFMEDIA: 921 case SIOCGIFMEDIA: 922 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 923 break; 924 925 default: 926 error = EINVAL; 927 break; 928 } 929 930 /* Try to get more packets going. */ 931 sip_start(ifp); 932 933 splx(s); 934 return (error); 935 } 936 937 /* 938 * sip_intr: 939 * 940 * Interrupt service routine. 941 */ 942 int 943 sip_intr(arg) 944 void *arg; 945 { 946 struct sip_softc *sc = arg; 947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 948 u_int32_t isr; 949 int handled = 0; 950 951 for (;;) { 952 /* Reading clears interrupt. */ 953 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 954 if ((isr & sc->sc_imr) == 0) 955 break; 956 957 handled = 1; 958 959 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 960 /* Grab any new packets. */ 961 sip_rxintr(sc); 962 963 if (isr & ISR_RXORN) { 964 printf("%s: receive FIFO overrun\n", 965 sc->sc_dev.dv_xname); 966 967 /* XXX adjust rx_drain_thresh? */ 968 } 969 970 if (isr & ISR_RXIDLE) { 971 printf("%s: receive ring overrun\n", 972 sc->sc_dev.dv_xname); 973 974 /* Get the receive process going again. */ 975 bus_space_write_4(sc->sc_st, sc->sc_sh, 976 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 977 bus_space_write_4(sc->sc_st, sc->sc_sh, 978 SIP_CR, CR_RXE); 979 } 980 } 981 982 if (isr & (ISR_TXURN|ISR_TXDESC)) { 983 /* Sweep up transmit descriptors. */ 984 sip_txintr(sc); 985 986 if (isr & ISR_TXURN) { 987 u_int32_t thresh; 988 989 printf("%s: transmit FIFO underrun", 990 sc->sc_dev.dv_xname); 991 992 thresh = sc->sc_tx_drain_thresh + 1; 993 if (thresh <= TXCFG_DRTH && 994 (thresh * 32) <= (SIP_TXFIFO_SIZE - 995 (sc->sc_tx_fill_thresh * 32))) { 996 printf("; increasing Tx drain " 997 "threshold to %u bytes\n", 998 thresh * 32); 999 sc->sc_tx_drain_thresh = thresh; 1000 (void) sip_init(sc); 1001 } else { 1002 (void) sip_init(sc); 1003 printf("\n"); 1004 } 1005 } 1006 } 1007 1008 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1009 if (isr & ISR_PAUSE_ST) { 1010 sc->sc_flags |= SIPF_PAUSED; 1011 ifp->if_flags |= IFF_OACTIVE; 1012 } 1013 if (isr & ISR_PAUSE_END) { 1014 sc->sc_flags &= ~SIPF_PAUSED; 1015 ifp->if_flags &= ~IFF_OACTIVE; 1016 } 1017 } 1018 1019 if (isr & ISR_HIBERR) { 1020 #define PRINTERR(bit, str) \ 1021 if (isr & (bit)) \ 1022 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1023 PRINTERR(ISR_DPERR, "parity error"); 1024 PRINTERR(ISR_SSERR, "system error"); 1025 PRINTERR(ISR_RMABT, "master abort"); 1026 PRINTERR(ISR_RTABT, "target abort"); 1027 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1028 (void) sip_init(sc); 1029 #undef PRINTERR 1030 } 1031 } 1032 1033 /* Try to get more packets going. */ 1034 sip_start(ifp); 1035 1036 return (handled); 1037 } 1038 1039 /* 1040 * sip_txintr: 1041 * 1042 * Helper; handle transmit interrupts. 1043 */ 1044 void 1045 sip_txintr(sc) 1046 struct sip_softc *sc; 1047 { 1048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1049 struct sip_txsoft *txs; 1050 u_int32_t cmdsts; 1051 1052 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1053 ifp->if_flags &= ~IFF_OACTIVE; 1054 1055 /* 1056 * Go through our Tx list and free mbufs for those 1057 * frames which have been transmitted. 1058 */ 1059 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1060 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1061 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1062 1063 cmdsts = sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1064 if (cmdsts & CMDSTS_OWN) 1065 break; 1066 1067 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1068 1069 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1070 1071 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1072 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1073 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1074 m_freem(txs->txs_mbuf); 1075 txs->txs_mbuf = NULL; 1076 1077 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1078 1079 /* 1080 * Check for errors and collisions. 1081 */ 1082 if (cmdsts & 1083 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1084 if (ifp->if_flags & IFF_DEBUG) { 1085 if (CMDSTS_Tx_ED) 1086 printf("%s: excessive deferral\n", 1087 sc->sc_dev.dv_xname); 1088 if (CMDSTS_Tx_EC) { 1089 printf("%s: excessive collisions\n", 1090 sc->sc_dev.dv_xname); 1091 ifp->if_collisions += 16; 1092 } 1093 } 1094 } else { 1095 /* Packet was transmitted successfully. */ 1096 ifp->if_opackets++; 1097 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1098 } 1099 } 1100 1101 /* 1102 * If there are no more pending transmissions, cancel the watchdog 1103 * timer. 1104 */ 1105 if (txs == NULL) 1106 ifp->if_timer = 0; 1107 } 1108 1109 /* 1110 * sip_rxintr: 1111 * 1112 * Helper; handle receive interrupts. 1113 */ 1114 void 1115 sip_rxintr(sc) 1116 struct sip_softc *sc; 1117 { 1118 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1119 struct ether_header *eh; 1120 struct sip_rxsoft *rxs; 1121 struct mbuf *m; 1122 u_int32_t cmdsts; 1123 int i, len; 1124 1125 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1126 rxs = &sc->sc_rxsoft[i]; 1127 1128 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1129 1130 cmdsts = sc->sc_rxdescs[i].sipd_cmdsts; 1131 1132 /* 1133 * NOTE: OWN is set if owned by _consumer_. We're the 1134 * consumer of the receive ring, so if the bit is clear, 1135 * we have processed all of the packets. 1136 */ 1137 if ((cmdsts & CMDSTS_OWN) == 0) { 1138 /* 1139 * We have processed all of the receive buffers. 1140 */ 1141 break; 1142 } 1143 1144 /* 1145 * If any collisions were seen on the wire, count one. 1146 */ 1147 if (cmdsts & CMDSTS_Rx_COL) 1148 ifp->if_collisions++; 1149 1150 /* 1151 * If an error occurred, update stats, clear the status 1152 * word, and leave the packet buffer in place. It will 1153 * simply be reused the next time the ring comes around. 1154 */ 1155 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1156 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1157 ifp->if_ierrors++; 1158 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1159 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1160 /* Receive overrun handled elsewhere. */ 1161 printf("%s: receive descriptor error\n", 1162 sc->sc_dev.dv_xname); 1163 } 1164 #define PRINTERR(bit, str) \ 1165 if (cmdsts & (bit)) \ 1166 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1167 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1168 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1169 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1170 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1171 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1172 #undef PRINTERR 1173 SIP_INIT_RXDESC(sc, i); 1174 continue; 1175 } 1176 1177 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1178 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1179 1180 /* 1181 * No errors; receive the packet. Note, the SiS 900 1182 * includes the CRC with every packet; trim it. 1183 */ 1184 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 1185 1186 #ifdef __NO_STRICT_ALIGNMENT 1187 /* 1188 * If the packet is small enough to fit in a 1189 * single header mbuf, allocate one and copy 1190 * the data into it. This greatly reduces 1191 * memory consumption when we receive lots 1192 * of small packets. 1193 * 1194 * Otherwise, we add a new buffer to the receive 1195 * chain. If this fails, we drop the packet and 1196 * recycle the old buffer. 1197 */ 1198 if (sip_copy_small != 0 && len <= MHLEN) { 1199 MGETHDR(m, M_DONTWAIT, MT_DATA); 1200 if (m == NULL) 1201 goto dropit; 1202 memcpy(mtod(m, caddr_t), 1203 mtod(rxs->rxs_mbuf, caddr_t), len); 1204 SIP_INIT_RXDESC(sc, i); 1205 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1206 rxs->rxs_dmamap->dm_mapsize, 1207 BUS_DMASYNC_PREREAD); 1208 } else { 1209 m = rxs->rxs_mbuf; 1210 if (sip_add_rxbuf(sc, i) != 0) { 1211 dropit: 1212 ifp->if_ierrors++; 1213 SIP_INIT_RXDESC(sc, i); 1214 bus_dmamap_sync(sc->sc_dmat, 1215 rxs->rxs_dmamap, 0, 1216 rxs->rxs_dmamap->dm_mapsize, 1217 BUS_DMASYNC_PREREAD); 1218 continue; 1219 } 1220 } 1221 #else 1222 /* 1223 * The SiS 900's receive buffers must be 4-byte aligned. 1224 * But this means that the data after the Ethernet header 1225 * is misaligned. We must allocate a new buffer and 1226 * copy the data, shifted forward 2 bytes. 1227 */ 1228 MGETHDR(m, M_DONTWAIT, MT_DATA); 1229 if (m == NULL) { 1230 dropit: 1231 ifp->if_ierrors++; 1232 SIP_INIT_RXDESC(sc, i); 1233 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1234 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1235 continue; 1236 } 1237 if (len > (MHLEN - 2)) { 1238 MCLGET(m, M_DONTWAIT); 1239 if ((m->m_flags & M_EXT) == 0) { 1240 m_freem(m); 1241 goto dropit; 1242 } 1243 } 1244 m->m_data += 2; 1245 1246 /* 1247 * Note that we use clusters for incoming frames, so the 1248 * buffer is virtually contiguous. 1249 */ 1250 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1251 1252 /* Allow the receive descriptor to continue using its mbuf. */ 1253 SIP_INIT_RXDESC(sc, i); 1254 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1255 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1256 #endif /* __NO_STRICT_ALIGNMENT */ 1257 1258 ifp->if_ipackets++; 1259 eh = mtod(m, struct ether_header *); 1260 m->m_pkthdr.rcvif = ifp; 1261 m->m_pkthdr.len = m->m_len = len; 1262 1263 #if NBPFILTER > 0 1264 /* 1265 * Pass this up to any BPF listeners, but only 1266 * pass if up the stack if it's for us. 1267 */ 1268 if (ifp->if_bpf) { 1269 bpf_mtap(ifp->if_bpf, m); 1270 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1271 (cmdsts & CMDSTS_Rx_DEST) == CMDSTS_Rx_DEST_REJ) { 1272 m_freem(m); 1273 continue; 1274 } 1275 } 1276 #endif /* NBPFILTER > 0 */ 1277 1278 /* Pass it on. */ 1279 (*ifp->if_input)(ifp, m); 1280 } 1281 1282 /* Update the receive pointer. */ 1283 sc->sc_rxptr = i; 1284 } 1285 1286 /* 1287 * sip_tick: 1288 * 1289 * One second timer, used to tick the MII. 1290 */ 1291 void 1292 sip_tick(arg) 1293 void *arg; 1294 { 1295 struct sip_softc *sc = arg; 1296 int s; 1297 1298 s = splnet(); 1299 mii_tick(&sc->sc_mii); 1300 splx(s); 1301 1302 timeout(sip_tick, sc, hz); 1303 } 1304 1305 /* 1306 * sip_reset: 1307 * 1308 * Perform a soft reset on the SiS 900. 1309 */ 1310 void 1311 sip_reset(sc) 1312 struct sip_softc *sc; 1313 { 1314 bus_space_tag_t st = sc->sc_st; 1315 bus_space_handle_t sh = sc->sc_sh; 1316 int i; 1317 1318 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1319 1320 for (i = 0; i < 1000; i++) { 1321 if ((bus_space_read_4(st, sh, SIP_ISR) & 1322 (ISR_TXRCMP|ISR_RXRCMP)) == (ISR_TXRCMP|ISR_RXRCMP)) 1323 return; 1324 delay(2); 1325 } 1326 1327 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1328 } 1329 1330 /* 1331 * sip_init: 1332 * 1333 * Initialize the interface. Must be called at splnet(). 1334 */ 1335 int 1336 sip_init(sc) 1337 struct sip_softc *sc; 1338 { 1339 bus_space_tag_t st = sc->sc_st; 1340 bus_space_handle_t sh = sc->sc_sh; 1341 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1342 struct sip_txsoft *txs; 1343 struct sip_rxsoft *rxs; 1344 struct sip_desc *sipd; 1345 u_int32_t cfg; 1346 int i, error = 0; 1347 1348 /* 1349 * Cancel any pending I/O. 1350 */ 1351 sip_stop(sc, 0); 1352 1353 /* 1354 * Reset the chip to a known state. 1355 */ 1356 sip_reset(sc); 1357 1358 /* 1359 * Initialize the transmit descriptor ring. 1360 */ 1361 for (i = 0; i < SIP_NTXDESC; i++) { 1362 sipd = &sc->sc_txdescs[i]; 1363 memset(sipd, 0, sizeof(struct sip_desc)); 1364 sipd->sipd_link = SIP_CDTXADDR(sc, SIP_NEXTTX(i)); 1365 } 1366 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1367 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1368 sc->sc_txfree = SIP_NTXDESC; 1369 sc->sc_txnext = 0; 1370 1371 /* 1372 * Initialize the transmit job descriptors. 1373 */ 1374 SIMPLEQ_INIT(&sc->sc_txfreeq); 1375 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1376 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1377 txs = &sc->sc_txsoft[i]; 1378 txs->txs_mbuf = NULL; 1379 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1380 } 1381 1382 /* 1383 * Initialize the receive descriptor and receive job 1384 * descriptor rings. 1385 */ 1386 for (i = 0; i < SIP_NRXDESC; i++) { 1387 rxs = &sc->sc_rxsoft[i]; 1388 if (rxs->rxs_mbuf == NULL) { 1389 if ((error = sip_add_rxbuf(sc, i)) != 0) { 1390 printf("%s: unable to allocate or map rx " 1391 "buffer %d, error = %d\n", 1392 sc->sc_dev.dv_xname, i, error); 1393 /* 1394 * XXX Should attempt to run with fewer receive 1395 * XXX buffers instead of just failing. 1396 */ 1397 sip_rxdrain(sc); 1398 goto out; 1399 } 1400 } 1401 } 1402 sc->sc_rxptr = 0; 1403 1404 /* 1405 * Initialize the configuration register: aggressive PCI 1406 * bus request algorithm, default backoff, default OW timer, 1407 * default parity error detection. 1408 */ 1409 cfg = 0; 1410 #if BYTE_ORDER == BIG_ENDIAN 1411 /* 1412 * ...descriptors in big-endian mode. 1413 */ 1414 cfg |= CFG_BEM; 1415 #endif 1416 bus_space_write_4(st, sh, SIP_CFG, cfg); 1417 1418 /* 1419 * Initialize the transmit fill and drain thresholds if 1420 * we have never done so. 1421 */ 1422 if (sc->sc_tx_fill_thresh == 0) { 1423 /* 1424 * XXX This value should be tuned. This is the 1425 * minimum (32 bytes), and we may be able to 1426 * improve performance by increasing it. 1427 */ 1428 sc->sc_tx_fill_thresh = 1; 1429 } 1430 if (sc->sc_tx_drain_thresh == 0) { 1431 /* 1432 * Start at a drain threshold of 128 bytes. We will 1433 * increase it if a DMA underrun occurs. 1434 * 1435 * XXX The minimum value of this variable should be 1436 * tuned. We may be able to improve performance 1437 * by starting with a lower value. That, however, 1438 * may trash the first few outgoing packets if the 1439 * PCI bus is saturated. 1440 */ 1441 sc->sc_tx_drain_thresh = 4; 1442 } 1443 1444 /* 1445 * Initialize the prototype TXCFG register. 1446 */ 1447 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1448 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1449 sc->sc_tx_drain_thresh; 1450 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1451 1452 /* 1453 * Initialize the receive drain threshold if we have never 1454 * done so. 1455 */ 1456 if (sc->sc_rx_drain_thresh == 0) { 1457 /* 1458 * XXX This value should be tuned. This is set to the 1459 * maximum of 248 bytes, and we may be able to improve 1460 * performance by decreasing it (although we should never 1461 * set this value lower than 2; 14 bytes are required to 1462 * filter the packet). 1463 */ 1464 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1465 } 1466 1467 /* 1468 * Initialize the prototype RXCFG register. 1469 */ 1470 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1471 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1472 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1473 1474 /* Set up the receive filter. */ 1475 sip_set_filter(sc); 1476 1477 /* 1478 * Give the transmit and receive rings to the chip. 1479 */ 1480 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1481 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1482 1483 /* 1484 * Initialize the interrupt mask. 1485 */ 1486 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1487 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1488 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1489 1490 /* 1491 * Set the current media. Do this after initializing the prototype 1492 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1493 * control. 1494 */ 1495 mii_mediachg(&sc->sc_mii); 1496 1497 /* 1498 * Enable interrupts. 1499 */ 1500 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1501 1502 /* 1503 * Start the transmit and receive processes. 1504 */ 1505 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1506 1507 /* 1508 * Start the one second MII clock. 1509 */ 1510 timeout(sip_tick, sc, hz); 1511 1512 /* 1513 * ...all done! 1514 */ 1515 ifp->if_flags |= IFF_RUNNING; 1516 ifp->if_flags &= ~IFF_OACTIVE; 1517 1518 out: 1519 if (error) 1520 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1521 return (error); 1522 } 1523 1524 /* 1525 * sip_drain: 1526 * 1527 * Drain the receive queue. 1528 */ 1529 void 1530 sip_rxdrain(sc) 1531 struct sip_softc *sc; 1532 { 1533 struct sip_rxsoft *rxs; 1534 int i; 1535 1536 for (i = 0; i < SIP_NRXDESC; i++) { 1537 rxs = &sc->sc_rxsoft[i]; 1538 if (rxs->rxs_mbuf != NULL) { 1539 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1540 m_freem(rxs->rxs_mbuf); 1541 rxs->rxs_mbuf = NULL; 1542 } 1543 } 1544 } 1545 1546 /* 1547 * sip_stop: 1548 * 1549 * Stop transmission on the interface. 1550 */ 1551 void 1552 sip_stop(sc, drain) 1553 struct sip_softc *sc; 1554 { 1555 bus_space_tag_t st = sc->sc_st; 1556 bus_space_handle_t sh = sc->sc_sh; 1557 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1558 struct sip_txsoft *txs; 1559 u_int32_t cmdsts = 0; /* DEBUG */ 1560 1561 /* 1562 * Stop the one second clock. 1563 */ 1564 untimeout(sip_tick, sc); 1565 1566 /* Down the MII. */ 1567 mii_down(&sc->sc_mii); 1568 1569 /* 1570 * Disable interrupts. 1571 */ 1572 bus_space_write_4(st, sh, SIP_IER, 0); 1573 1574 /* 1575 * Stop receiver and transmitter. 1576 */ 1577 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1578 1579 /* 1580 * Release any queued transmit buffers. 1581 */ 1582 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1583 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1584 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1585 (sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts & 1586 CMDSTS_INTR) == 0) 1587 printf("%s: sip_stop: last descriptor does not " 1588 "have INTR bit set\n", sc->sc_dev.dv_xname); 1589 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1590 #ifdef DIAGNOSTIC 1591 if (txs->txs_mbuf == NULL) { 1592 printf("%s: dirty txsoft with no mbuf chain\n", 1593 sc->sc_dev.dv_xname); 1594 panic("sip_stop"); 1595 } 1596 #endif 1597 cmdsts |= /* DEBUG */ 1598 sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1599 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1600 m_freem(txs->txs_mbuf); 1601 txs->txs_mbuf = NULL; 1602 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1603 } 1604 1605 if (drain) { 1606 /* 1607 * Release the receive buffers. 1608 */ 1609 sip_rxdrain(sc); 1610 } 1611 1612 /* 1613 * Mark the interface down and cancel the watchdog timer. 1614 */ 1615 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1616 ifp->if_timer = 0; 1617 1618 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1619 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1620 printf("%s: sip_stop: no INTR bits set in dirty tx " 1621 "descriptors\n", sc->sc_dev.dv_xname); 1622 } 1623 1624 /* 1625 * sip_read_eeprom: 1626 * 1627 * Read data from the serial EEPROM. 1628 */ 1629 void 1630 sip_read_eeprom(sc, word, wordcnt, data) 1631 struct sip_softc *sc; 1632 int word, wordcnt; 1633 u_int16_t *data; 1634 { 1635 bus_space_tag_t st = sc->sc_st; 1636 bus_space_handle_t sh = sc->sc_sh; 1637 u_int16_t reg; 1638 int i, x; 1639 1640 for (i = 0; i < wordcnt; i++) { 1641 /* Send CHIP SELECT. */ 1642 reg = EROMAR_EECS; 1643 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1644 1645 /* Shift in the READ opcode. */ 1646 for (x = 3; x > 0; x--) { 1647 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1648 reg |= EROMAR_EEDI; 1649 else 1650 reg &= ~EROMAR_EEDI; 1651 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1652 bus_space_write_4(st, sh, SIP_EROMAR, 1653 reg | EROMAR_EESK); 1654 delay(4); 1655 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1656 delay(4); 1657 } 1658 1659 /* Shift in address. */ 1660 for (x = 6; x > 0; x--) { 1661 if ((word + i) & (1 << (x - 1))) 1662 reg |= EROMAR_EEDI; 1663 else 1664 reg &= ~EROMAR_EEDI; 1665 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1666 bus_space_write_4(st, sh, SIP_EROMAR, 1667 reg | EROMAR_EESK); 1668 delay(4); 1669 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1670 delay(4); 1671 } 1672 1673 /* Shift out data. */ 1674 reg = EROMAR_EECS; 1675 data[i] = 0; 1676 for (x = 16; x > 0; x--) { 1677 bus_space_write_4(st, sh, SIP_EROMAR, 1678 reg | EROMAR_EESK); 1679 delay(4); 1680 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1681 data[i] |= (1 << (x - 1)); 1682 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1683 } 1684 1685 /* Clear CHIP SELECT. */ 1686 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1687 delay(4); 1688 } 1689 } 1690 1691 /* 1692 * sip_add_rxbuf: 1693 * 1694 * Add a receive buffer to the indicated descriptor. 1695 */ 1696 int 1697 sip_add_rxbuf(sc, idx) 1698 struct sip_softc *sc; 1699 int idx; 1700 { 1701 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1702 struct mbuf *m; 1703 int error; 1704 1705 MGETHDR(m, M_DONTWAIT, MT_DATA); 1706 if (m == NULL) 1707 return (ENOBUFS); 1708 1709 MCLGET(m, M_DONTWAIT); 1710 if ((m->m_flags & M_EXT) == 0) { 1711 m_freem(m); 1712 return (ENOBUFS); 1713 } 1714 1715 if (rxs->rxs_mbuf != NULL) 1716 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1717 1718 rxs->rxs_mbuf = m; 1719 1720 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1721 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1722 if (error) { 1723 printf("%s: can't load rx DMA map %d, error = %d\n", 1724 sc->sc_dev.dv_xname, idx, error); 1725 panic("sip_add_rxbuf"); /* XXX */ 1726 } 1727 1728 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1729 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1730 1731 SIP_INIT_RXDESC(sc, idx); 1732 1733 return (0); 1734 } 1735 1736 /* 1737 * sip_set_filter: 1738 * 1739 * Set up the receive filter. 1740 */ 1741 void 1742 sip_set_filter(sc) 1743 struct sip_softc *sc; 1744 { 1745 bus_space_tag_t st = sc->sc_st; 1746 bus_space_handle_t sh = sc->sc_sh; 1747 struct ethercom *ec = &sc->sc_ethercom; 1748 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1749 struct ether_multi *enm; 1750 struct ether_multistep step; 1751 u_int8_t *cp; 1752 u_int32_t crc, mchash[8]; 1753 int len; 1754 static const u_int32_t crctab[] = { 1755 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1756 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1757 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1758 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1759 }; 1760 1761 /* 1762 * Initialize the prototype RFCR. 1763 */ 1764 sc->sc_rfcr = RFCR_RFEN; 1765 if (ifp->if_flags & IFF_BROADCAST) 1766 sc->sc_rfcr |= RFCR_AAB; 1767 if (ifp->if_flags & IFF_PROMISC) { 1768 sc->sc_rfcr |= RFCR_AAP; 1769 goto allmulti; 1770 } 1771 1772 /* 1773 * Set up the multicast address filter by passing all multicast 1774 * addresses through a CRC generator, and then using the high-order 1775 * 6 bits as an index into the 128 bit multicast hash table (only 1776 * the lower 16 bits of each 32 bit multicast hash register are 1777 * valid). The high order bits select the register, while the 1778 * rest of the bits select the bit within the register. 1779 */ 1780 1781 memset(mchash, 0, sizeof(mchash)); 1782 1783 ETHER_FIRST_MULTI(step, ec, enm); 1784 while (enm != NULL) { 1785 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1786 /* 1787 * We must listen to a range of multicast addresses. 1788 * For now, just accept all multicasts, rather than 1789 * trying to set only those filter bits needed to match 1790 * the range. (At this time, the only use of address 1791 * ranges is for IP multicast routing, for which the 1792 * range is big enough to require all bits set.) 1793 */ 1794 goto allmulti; 1795 } 1796 1797 cp = enm->enm_addrlo; 1798 crc = 0xffffffff; 1799 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1800 crc ^= *cp++; 1801 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1802 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1803 } 1804 /* Just want the 7 most significant bits. */ 1805 crc >>= 25; 1806 1807 /* Set the corresponding bit in the hash table. */ 1808 mchash[crc >> 4] |= 1 << (crc & 0xf); 1809 1810 ETHER_NEXT_MULTI(step, enm); 1811 } 1812 1813 ifp->if_flags &= ~IFF_ALLMULTI; 1814 goto setit; 1815 1816 allmulti: 1817 ifp->if_flags |= IFF_ALLMULTI; 1818 sc->sc_rfcr |= RFCR_AAM; 1819 1820 setit: 1821 #define FILTER_EMIT(addr, data) \ 1822 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1823 bus_space_write_4(st, sh, SIP_RFDR, (data)) 1824 1825 /* 1826 * Disable receive filter, and program the node address. 1827 */ 1828 cp = LLADDR(ifp->if_sadl); 1829 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1830 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1831 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1832 1833 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1834 /* 1835 * Program the multicast hash table. 1836 */ 1837 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1838 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1839 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1840 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1841 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1842 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1843 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1844 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1845 } 1846 #undef FILTER_EMIT 1847 1848 /* 1849 * Re-enable the receiver filter. 1850 */ 1851 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1852 } 1853 1854 /* 1855 * sip_mii_readreg: [mii interface function] 1856 * 1857 * Read a PHY register on the MII. 1858 */ 1859 int 1860 sip_mii_readreg(self, phy, reg) 1861 struct device *self; 1862 int phy, reg; 1863 { 1864 struct sip_softc *sc = (struct sip_softc *) self; 1865 u_int32_t enphy; 1866 1867 /* 1868 * The SiS 900 has only an internal PHY on the MII. Only allow 1869 * MII address 0. 1870 */ 1871 if (phy != 0) 1872 return (0); 1873 1874 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1875 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_RWCMD | ENPHY_ACCESS); 1876 do { 1877 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1878 } while (enphy & ENPHY_ACCESS); 1879 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 1880 } 1881 1882 /* 1883 * sip_mii_writereg: [mii interface function] 1884 * 1885 * Write a PHY register on the MII. 1886 */ 1887 void 1888 sip_mii_writereg(self, phy, reg, val) 1889 struct device *self; 1890 int phy, reg, val; 1891 { 1892 struct sip_softc *sc = (struct sip_softc *) self; 1893 u_int32_t enphy; 1894 1895 /* 1896 * The SiS 900 has only an internal PHY on the MII. Only allow 1897 * MII address 0. 1898 */ 1899 if (phy != 0) 1900 return; 1901 1902 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1903 (val << ENPHY_DATA_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 1904 ENPHY_ACCESS); 1905 do { 1906 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1907 } while (enphy & ENPHY_ACCESS); 1908 } 1909 1910 /* 1911 * sip_mii_statchg: [mii interface function] 1912 * 1913 * Callback from MII layer when media changes. 1914 */ 1915 void 1916 sip_mii_statchg(self) 1917 struct device *self; 1918 { 1919 struct sip_softc *sc = (struct sip_softc *) self; 1920 u_int32_t flowctl; 1921 1922 /* 1923 * Update TXCFG for full-duplex operation. 1924 */ 1925 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1926 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 1927 else 1928 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 1929 1930 /* 1931 * Update RXCFG for full-duplex or loopback. 1932 */ 1933 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 1934 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 1935 sc->sc_rxcfg |= RXCFG_ATX; 1936 else 1937 sc->sc_rxcfg &= ~RXCFG_ATX; 1938 1939 /* 1940 * Update IMR for use of 802.3x flow control. 1941 */ 1942 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 1943 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 1944 flowctl = FLOWCTL_FLOWEN; 1945 } else { 1946 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 1947 flowctl = 0; 1948 } 1949 1950 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 1951 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 1952 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 1953 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 1954 1955 /* XXX Update ifp->if_baudrate */ 1956 } 1957 1958 /* 1959 * sip_mediastatus: [ifmedia interface function] 1960 * 1961 * Get the current interface media status. 1962 */ 1963 void 1964 sip_mediastatus(ifp, ifmr) 1965 struct ifnet *ifp; 1966 struct ifmediareq *ifmr; 1967 { 1968 struct sip_softc *sc = ifp->if_softc; 1969 1970 mii_pollstat(&sc->sc_mii); 1971 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1972 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1973 } 1974 1975 /* 1976 * sip_mediachange: [ifmedia interface function] 1977 * 1978 * Set hardware to newly-selected media. 1979 */ 1980 int 1981 sip_mediachange(ifp) 1982 struct ifnet *ifp; 1983 { 1984 struct sip_softc *sc = ifp->if_softc; 1985 1986 if (ifp->if_flags & IFF_UP) 1987 mii_mediachg(&sc->sc_mii); 1988 return (0); 1989 } 1990