1 /* $NetBSD: if_sip.c,v 1.21 2000/12/14 06:42:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Silicon Integrated Systems SiS 900 and 34 * SiS 7016 10/100 PCI Ethernet controllers. 35 * 36 * Written by Jason R. Thorpe for Network Computer, Inc. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <dev/pci/if_sipreg.h> 88 89 /* 90 * Transmit descriptor list size. This is arbitrary, but allocate 91 * enough descriptors for 64 pending transmissions, and 16 segments 92 * per packet. This MUST work out to a power of 2. 93 */ 94 #define SIP_NTXSEGS 16 95 96 #define SIP_TXQUEUELEN 64 97 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 98 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 99 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 100 101 /* 102 * Receive descriptor list size. We have one Rx buffer per incoming 103 * packet, so this logic is a little simpler. 104 */ 105 #define SIP_NRXDESC 64 106 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 107 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 108 109 /* 110 * Control structures are DMA'd to the SiS900 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct sip_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct sip_desc scd_txdescs[SIP_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 124 }; 125 126 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 127 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 128 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit jobs. 132 */ 133 struct sip_txsoft { 134 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t txs_dmamap; /* our DMA map */ 136 int txs_firstdesc; /* first descriptor in packet */ 137 int txs_lastdesc; /* last descriptor in packet */ 138 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 139 }; 140 141 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 142 143 /* 144 * Software state for receive jobs. 145 */ 146 struct sip_rxsoft { 147 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 148 bus_dmamap_t rxs_dmamap; /* our DMA map */ 149 }; 150 151 /* 152 * Software state per device. 153 */ 154 struct sip_softc { 155 struct device sc_dev; /* generic device information */ 156 bus_space_tag_t sc_st; /* bus space tag */ 157 bus_space_handle_t sc_sh; /* bus space handle */ 158 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 159 struct ethercom sc_ethercom; /* ethernet common data */ 160 void *sc_sdhook; /* shutdown hook */ 161 162 const struct sip_product *sc_model; /* which model are we? */ 163 164 void *sc_ih; /* interrupt cookie */ 165 166 struct mii_data sc_mii; /* MII/media information */ 167 168 struct callout sc_tick_ch; /* tick callout */ 169 170 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 171 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 172 173 /* 174 * Software state for transmit and receive descriptors. 175 */ 176 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 177 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 178 179 /* 180 * Control data structures. 181 */ 182 struct sip_control_data *sc_control_data; 183 #define sc_txdescs sc_control_data->scd_txdescs 184 #define sc_rxdescs sc_control_data->scd_rxdescs 185 186 u_int32_t sc_txcfg; /* prototype TXCFG register */ 187 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 188 u_int32_t sc_imr; /* prototype IMR register */ 189 u_int32_t sc_rfcr; /* prototype RFCR register */ 190 191 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 192 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 193 194 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 195 196 int sc_flags; /* misc. flags; see below */ 197 198 int sc_txfree; /* number of free Tx descriptors */ 199 int sc_txnext; /* next ready Tx descriptor */ 200 201 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 202 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 203 204 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 205 }; 206 207 /* sc_flags */ 208 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 209 210 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 211 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 212 213 #define SIP_CDTXSYNC(sc, x, n, ops) \ 214 do { \ 215 int __x, __n; \ 216 \ 217 __x = (x); \ 218 __n = (n); \ 219 \ 220 /* If it will wrap around, sync to the end of the ring. */ \ 221 if ((__x + __n) > SIP_NTXDESC) { \ 222 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 223 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 224 (SIP_NTXDESC - __x), (ops)); \ 225 __n -= (SIP_NTXDESC - __x); \ 226 __x = 0; \ 227 } \ 228 \ 229 /* Now sync whatever is left. */ \ 230 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 231 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 232 } while (0) 233 234 #define SIP_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 237 238 /* 239 * Note we rely on MCLBYTES being a power of two below. 240 */ 241 #define SIP_INIT_RXDESC(sc, x) \ 242 do { \ 243 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 244 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 245 \ 246 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 247 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 248 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 249 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 250 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 251 } while (0) 252 253 #define SIP_TIMEOUT 1000 254 255 void sip_start __P((struct ifnet *)); 256 void sip_watchdog __P((struct ifnet *)); 257 int sip_ioctl __P((struct ifnet *, u_long, caddr_t)); 258 int sip_init __P((struct ifnet *)); 259 void sip_stop __P((struct ifnet *, int)); 260 261 void sip_shutdown __P((void *)); 262 263 void sip_reset __P((struct sip_softc *)); 264 void sip_rxdrain __P((struct sip_softc *)); 265 int sip_add_rxbuf __P((struct sip_softc *, int)); 266 void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *)); 267 void sip_tick __P((void *)); 268 269 void sip_sis900_set_filter __P((struct sip_softc *)); 270 void sip_dp83815_set_filter __P((struct sip_softc *)); 271 272 int sip_intr __P((void *)); 273 void sip_txintr __P((struct sip_softc *)); 274 void sip_rxintr __P((struct sip_softc *)); 275 276 int sip_sis900_mii_readreg __P((struct device *, int, int)); 277 void sip_sis900_mii_writereg __P((struct device *, int, int, int)); 278 void sip_sis900_mii_statchg __P((struct device *)); 279 280 int sip_dp83815_mii_readreg __P((struct device *, int, int)); 281 void sip_dp83815_mii_writereg __P((struct device *, int, int, int)); 282 void sip_dp83815_mii_statchg __P((struct device *)); 283 284 int sip_mediachange __P((struct ifnet *)); 285 void sip_mediastatus __P((struct ifnet *, struct ifmediareq *)); 286 287 int sip_match __P((struct device *, struct cfdata *, void *)); 288 void sip_attach __P((struct device *, struct device *, void *)); 289 290 int sip_copy_small = 0; 291 292 struct cfattach sip_ca = { 293 sizeof(struct sip_softc), sip_match, sip_attach, 294 }; 295 296 /* 297 * Descriptions of the variants of the SiS900. 298 */ 299 struct sip_variant { 300 int (*sipv_mii_readreg) __P((struct device *, int, int)); 301 void (*sipv_mii_writereg) __P((struct device *, int, int, int)); 302 void (*sipv_mii_statchg) __P((struct device *)); 303 void (*sipv_set_filter) __P((struct sip_softc *)); 304 }; 305 306 const struct sip_variant sip_variant_sis900 = { 307 sip_sis900_mii_readreg, sip_sis900_mii_writereg, 308 sip_sis900_mii_statchg, sip_sis900_set_filter 309 }; 310 311 const struct sip_variant sip_variant_dp83815 = { 312 sip_dp83815_mii_readreg, sip_dp83815_mii_writereg, 313 sip_dp83815_mii_statchg, sip_dp83815_set_filter 314 }; 315 316 /* 317 * Devices supported by this driver. 318 */ 319 const struct sip_product { 320 pci_vendor_id_t sip_vendor; 321 pci_product_id_t sip_product; 322 const char *sip_name; 323 const struct sip_variant *sip_variant; 324 } sip_products[] = { 325 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 326 "SiS 900 10/100 Ethernet", 327 &sip_variant_sis900 }, 328 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 329 "SiS 7016 10/100 Ethernet", 330 &sip_variant_sis900 }, 331 332 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 333 "NatSemi DP83815 10/100 Ethernet", 334 &sip_variant_dp83815 }, 335 336 { 0, 0, 337 NULL, 338 NULL }, 339 }; 340 341 const struct sip_product *sip_lookup __P((const struct pci_attach_args *)); 342 343 const struct sip_product * 344 sip_lookup(pa) 345 const struct pci_attach_args *pa; 346 { 347 const struct sip_product *sip; 348 349 for (sip = sip_products; sip->sip_name != NULL; sip++) { 350 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 351 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 352 return (sip); 353 } 354 return (NULL); 355 } 356 357 int 358 sip_match(parent, cf, aux) 359 struct device *parent; 360 struct cfdata *cf; 361 void *aux; 362 { 363 struct pci_attach_args *pa = aux; 364 365 if (sip_lookup(pa) != NULL) 366 return (1); 367 368 return (0); 369 } 370 371 void 372 sip_attach(parent, self, aux) 373 struct device *parent, *self; 374 void *aux; 375 { 376 struct sip_softc *sc = (struct sip_softc *) self; 377 struct pci_attach_args *pa = aux; 378 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pci_intr_handle_t ih; 381 const char *intrstr = NULL; 382 bus_space_tag_t iot, memt; 383 bus_space_handle_t ioh, memh; 384 bus_dma_segment_t seg; 385 int ioh_valid, memh_valid; 386 int i, rseg, error; 387 const struct sip_product *sip; 388 pcireg_t pmode; 389 u_int16_t myea[ETHER_ADDR_LEN / 2]; 390 u_int8_t enaddr[ETHER_ADDR_LEN]; 391 int pmreg; 392 393 callout_init(&sc->sc_tick_ch); 394 395 sip = sip_lookup(pa); 396 if (sip == NULL) { 397 printf("\n"); 398 panic("sip_attach: impossible"); 399 } 400 401 printf(": %s\n", sip->sip_name); 402 403 sc->sc_model = sip; 404 405 /* 406 * Map the device. 407 */ 408 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 409 PCI_MAPREG_TYPE_IO, 0, 410 &iot, &ioh, NULL, NULL) == 0); 411 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 412 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 413 &memt, &memh, NULL, NULL) == 0); 414 415 if (memh_valid) { 416 sc->sc_st = memt; 417 sc->sc_sh = memh; 418 } else if (ioh_valid) { 419 sc->sc_st = iot; 420 sc->sc_sh = ioh; 421 } else { 422 printf("%s: unable to map device registers\n", 423 sc->sc_dev.dv_xname); 424 return; 425 } 426 427 sc->sc_dmat = pa->pa_dmat; 428 429 /* Enable bus mastering. */ 430 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 431 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 432 PCI_COMMAND_MASTER_ENABLE); 433 434 /* Get it out of power save mode if needed. */ 435 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 436 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 437 if (pmode == 3) { 438 /* 439 * The card has lost all configuration data in 440 * this state, so punt. 441 */ 442 printf("%s: unable to wake up from power state D3\n", 443 sc->sc_dev.dv_xname); 444 return; 445 } 446 if (pmode != 0) { 447 printf("%s: waking up from power state D%d\n", 448 sc->sc_dev.dv_xname, pmode); 449 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 450 } 451 } 452 453 /* 454 * Map and establish our interrupt. 455 */ 456 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 457 pa->pa_intrline, &ih)) { 458 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 459 return; 460 } 461 intrstr = pci_intr_string(pc, ih); 462 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 463 if (sc->sc_ih == NULL) { 464 printf("%s: unable to establish interrupt", 465 sc->sc_dev.dv_xname); 466 if (intrstr != NULL) 467 printf(" at %s", intrstr); 468 printf("\n"); 469 return; 470 } 471 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 472 473 SIMPLEQ_INIT(&sc->sc_txfreeq); 474 SIMPLEQ_INIT(&sc->sc_txdirtyq); 475 476 /* 477 * Allocate the control data structures, and create and load the 478 * DMA map for it. 479 */ 480 if ((error = bus_dmamem_alloc(sc->sc_dmat, 481 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 482 0)) != 0) { 483 printf("%s: unable to allocate control data, error = %d\n", 484 sc->sc_dev.dv_xname, error); 485 goto fail_0; 486 } 487 488 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 489 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 490 BUS_DMA_COHERENT)) != 0) { 491 printf("%s: unable to map control data, error = %d\n", 492 sc->sc_dev.dv_xname, error); 493 goto fail_1; 494 } 495 496 if ((error = bus_dmamap_create(sc->sc_dmat, 497 sizeof(struct sip_control_data), 1, 498 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 499 printf("%s: unable to create control data DMA map, " 500 "error = %d\n", sc->sc_dev.dv_xname, error); 501 goto fail_2; 502 } 503 504 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 505 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 506 0)) != 0) { 507 printf("%s: unable to load control data DMA map, error = %d\n", 508 sc->sc_dev.dv_xname, error); 509 goto fail_3; 510 } 511 512 /* 513 * Create the transmit buffer DMA maps. 514 */ 515 for (i = 0; i < SIP_TXQUEUELEN; i++) { 516 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 517 SIP_NTXSEGS, MCLBYTES, 0, 0, 518 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 519 printf("%s: unable to create tx DMA map %d, " 520 "error = %d\n", sc->sc_dev.dv_xname, i, error); 521 goto fail_4; 522 } 523 } 524 525 /* 526 * Create the receive buffer DMA maps. 527 */ 528 for (i = 0; i < SIP_NRXDESC; i++) { 529 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 530 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 531 printf("%s: unable to create rx DMA map %d, " 532 "error = %d\n", sc->sc_dev.dv_xname, i, error); 533 goto fail_5; 534 } 535 sc->sc_rxsoft[i].rxs_mbuf = NULL; 536 } 537 538 /* 539 * Reset the chip to a known state. 540 */ 541 sip_reset(sc); 542 543 /* 544 * Read the Ethernet address from the EEPROM. 545 */ 546 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 547 sizeof(myea) / sizeof(myea[0]), myea); 548 549 enaddr[0] = myea[0] & 0xff; 550 enaddr[1] = myea[0] >> 8; 551 enaddr[2] = myea[1] & 0xff; 552 enaddr[3] = myea[1] >> 8; 553 enaddr[4] = myea[2] & 0xff; 554 enaddr[5] = myea[2] >> 8; 555 556 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 557 ether_sprintf(enaddr)); 558 559 /* 560 * Initialize our media structures and probe the MII. 561 */ 562 sc->sc_mii.mii_ifp = ifp; 563 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 564 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 565 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 566 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 567 sip_mediastatus); 568 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 569 MII_OFFSET_ANY, 0); 570 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 571 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 572 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 573 } else 574 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 575 576 ifp = &sc->sc_ethercom.ec_if; 577 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 578 ifp->if_softc = sc; 579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 580 ifp->if_ioctl = sip_ioctl; 581 ifp->if_start = sip_start; 582 ifp->if_watchdog = sip_watchdog; 583 ifp->if_init = sip_init; 584 ifp->if_stop = sip_stop; 585 IFQ_SET_READY(&ifp->if_snd); 586 587 /* 588 * Attach the interface. 589 */ 590 if_attach(ifp); 591 ether_ifattach(ifp, enaddr); 592 593 /* 594 * Make sure the interface is shutdown during reboot. 595 */ 596 sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc); 597 if (sc->sc_sdhook == NULL) 598 printf("%s: WARNING: unable to establish shutdown hook\n", 599 sc->sc_dev.dv_xname); 600 return; 601 602 /* 603 * Free any resources we've allocated during the failed attach 604 * attempt. Do this in reverse order and fall through. 605 */ 606 fail_5: 607 for (i = 0; i < SIP_NRXDESC; i++) { 608 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 609 bus_dmamap_destroy(sc->sc_dmat, 610 sc->sc_rxsoft[i].rxs_dmamap); 611 } 612 fail_4: 613 for (i = 0; i < SIP_TXQUEUELEN; i++) { 614 if (sc->sc_txsoft[i].txs_dmamap != NULL) 615 bus_dmamap_destroy(sc->sc_dmat, 616 sc->sc_txsoft[i].txs_dmamap); 617 } 618 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 619 fail_3: 620 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 621 fail_2: 622 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 623 sizeof(struct sip_control_data)); 624 fail_1: 625 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 626 fail_0: 627 return; 628 } 629 630 /* 631 * sip_shutdown: 632 * 633 * Make sure the interface is stopped at reboot time. 634 */ 635 void 636 sip_shutdown(arg) 637 void *arg; 638 { 639 struct sip_softc *sc = arg; 640 641 sip_stop(&sc->sc_ethercom.ec_if, 1); 642 } 643 644 /* 645 * sip_start: [ifnet interface function] 646 * 647 * Start packet transmission on the interface. 648 */ 649 void 650 sip_start(ifp) 651 struct ifnet *ifp; 652 { 653 struct sip_softc *sc = ifp->if_softc; 654 struct mbuf *m0, *m; 655 struct sip_txsoft *txs; 656 bus_dmamap_t dmamap; 657 int error, firsttx, nexttx, lasttx, ofree, seg; 658 659 /* 660 * If we've been told to pause, don't transmit any more packets. 661 */ 662 if (sc->sc_flags & SIPF_PAUSED) 663 ifp->if_flags |= IFF_OACTIVE; 664 665 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 666 return; 667 668 /* 669 * Remember the previous number of free descriptors and 670 * the first descriptor we'll use. 671 */ 672 ofree = sc->sc_txfree; 673 firsttx = sc->sc_txnext; 674 675 /* 676 * Loop through the send queue, setting up transmit descriptors 677 * until we drain the queue, or use up all available transmit 678 * descriptors. 679 */ 680 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 681 sc->sc_txfree != 0) { 682 /* 683 * Grab a packet off the queue. 684 */ 685 IFQ_POLL(&ifp->if_snd, m0); 686 if (m0 == NULL) 687 break; 688 689 dmamap = txs->txs_dmamap; 690 691 /* 692 * Load the DMA map. If this fails, the packet either 693 * didn't fit in the alloted number of segments, or we 694 * were short on resources. In this case, we'll copy 695 * and try again. 696 */ 697 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 698 BUS_DMA_NOWAIT) != 0) { 699 MGETHDR(m, M_DONTWAIT, MT_DATA); 700 if (m == NULL) { 701 printf("%s: unable to allocate Tx mbuf\n", 702 sc->sc_dev.dv_xname); 703 break; 704 } 705 if (m0->m_pkthdr.len > MHLEN) { 706 MCLGET(m, M_DONTWAIT); 707 if ((m->m_flags & M_EXT) == 0) { 708 printf("%s: unable to allocate Tx " 709 "cluster\n", sc->sc_dev.dv_xname); 710 m_freem(m); 711 break; 712 } 713 } 714 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 715 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 716 m_freem(m0); 717 m0 = m; 718 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 719 m0, BUS_DMA_NOWAIT); 720 if (error) { 721 printf("%s: unable to load Tx buffer, " 722 "error = %d\n", sc->sc_dev.dv_xname, error); 723 break; 724 } 725 } 726 727 IFQ_DEQUEUE(&ifp->if_snd, m0); 728 729 /* 730 * Ensure we have enough descriptors free to describe 731 * the packet. 732 */ 733 if (dmamap->dm_nsegs > sc->sc_txfree) { 734 /* 735 * Not enough free descriptors to transmit this 736 * packet. We haven't committed anything yet, 737 * so just unload the DMA map, put the packet 738 * back on the queue, and punt. Notify the upper 739 * layer that there are not more slots left. 740 * 741 * XXX We could allocate an mbuf and copy, but 742 * XXX is it worth it? 743 */ 744 ifp->if_flags |= IFF_OACTIVE; 745 bus_dmamap_unload(sc->sc_dmat, dmamap); 746 IF_PREPEND(&ifp->if_snd, m0); 747 break; 748 } 749 750 /* 751 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 752 */ 753 754 /* Sync the DMA map. */ 755 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 756 BUS_DMASYNC_PREWRITE); 757 758 /* 759 * Initialize the transmit descriptors. 760 */ 761 for (nexttx = sc->sc_txnext, seg = 0; 762 seg < dmamap->dm_nsegs; 763 seg++, nexttx = SIP_NEXTTX(nexttx)) { 764 /* 765 * If this is the first descriptor we're 766 * enqueueing, don't set the OWN bit just 767 * yet. That could cause a race condition. 768 * We'll do it below. 769 */ 770 sc->sc_txdescs[nexttx].sipd_bufptr = 771 htole32(dmamap->dm_segs[seg].ds_addr); 772 sc->sc_txdescs[nexttx].sipd_cmdsts = 773 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 774 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 775 lasttx = nexttx; 776 } 777 778 /* Clear the MORE bit on the last segment. */ 779 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 780 781 /* Sync the descriptors we're using. */ 782 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 783 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 784 785 /* 786 * Store a pointer to the packet so we can free it later, 787 * and remember what txdirty will be once the packet is 788 * done. 789 */ 790 txs->txs_mbuf = m0; 791 txs->txs_firstdesc = sc->sc_txnext; 792 txs->txs_lastdesc = lasttx; 793 794 /* Advance the tx pointer. */ 795 sc->sc_txfree -= dmamap->dm_nsegs; 796 sc->sc_txnext = nexttx; 797 798 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 800 801 #if NBPFILTER > 0 802 /* 803 * Pass the packet to any BPF listeners. 804 */ 805 if (ifp->if_bpf) 806 bpf_mtap(ifp->if_bpf, m0); 807 #endif /* NBPFILTER > 0 */ 808 } 809 810 if (txs == NULL || sc->sc_txfree == 0) { 811 /* No more slots left; notify upper layer. */ 812 ifp->if_flags |= IFF_OACTIVE; 813 } 814 815 if (sc->sc_txfree != ofree) { 816 /* 817 * Cause a descriptor interrupt to happen on the 818 * last packet we enqueued. 819 */ 820 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 821 SIP_CDTXSYNC(sc, lasttx, 1, 822 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 823 824 /* 825 * The entire packet chain is set up. Give the 826 * first descrptor to the chip now. 827 */ 828 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 829 SIP_CDTXSYNC(sc, firsttx, 1, 830 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 831 832 /* Start the transmit process. */ 833 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 834 CR_TXE) == 0) { 835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 836 SIP_CDTXADDR(sc, firsttx)); 837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 838 } 839 840 /* Set a watchdog timer in case the chip flakes out. */ 841 ifp->if_timer = 5; 842 } 843 } 844 845 /* 846 * sip_watchdog: [ifnet interface function] 847 * 848 * Watchdog timer handler. 849 */ 850 void 851 sip_watchdog(ifp) 852 struct ifnet *ifp; 853 { 854 struct sip_softc *sc = ifp->if_softc; 855 856 /* 857 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 858 * If we get a timeout, try and sweep up transmit descriptors. 859 * If we manage to sweep them all up, ignore the lack of 860 * interrupt. 861 */ 862 sip_txintr(sc); 863 864 if (sc->sc_txfree != SIP_NTXDESC) { 865 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 866 ifp->if_oerrors++; 867 868 /* Reset the interface. */ 869 (void) sip_init(ifp); 870 } else if (ifp->if_flags & IFF_DEBUG) 871 printf("%s: recovered from device timeout\n", 872 sc->sc_dev.dv_xname); 873 874 /* Try to get more packets going. */ 875 sip_start(ifp); 876 } 877 878 /* 879 * sip_ioctl: [ifnet interface function] 880 * 881 * Handle control requests from the operator. 882 */ 883 int 884 sip_ioctl(ifp, cmd, data) 885 struct ifnet *ifp; 886 u_long cmd; 887 caddr_t data; 888 { 889 struct sip_softc *sc = ifp->if_softc; 890 struct ifreq *ifr = (struct ifreq *)data; 891 int s, error; 892 893 s = splnet(); 894 895 switch (cmd) { 896 case SIOCSIFMEDIA: 897 case SIOCGIFMEDIA: 898 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 899 break; 900 901 default: 902 error = ether_ioctl(ifp, cmd, data); 903 if (error == ENETRESET) { 904 /* 905 * Multicast list has changed; set the hardware filter 906 * accordingly. 907 */ 908 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 909 error = 0; 910 } 911 break; 912 } 913 914 /* Try to get more packets going. */ 915 sip_start(ifp); 916 917 splx(s); 918 return (error); 919 } 920 921 /* 922 * sip_intr: 923 * 924 * Interrupt service routine. 925 */ 926 int 927 sip_intr(arg) 928 void *arg; 929 { 930 struct sip_softc *sc = arg; 931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 932 u_int32_t isr; 933 int handled = 0; 934 935 for (;;) { 936 /* Reading clears interrupt. */ 937 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 938 if ((isr & sc->sc_imr) == 0) 939 break; 940 941 handled = 1; 942 943 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 944 /* Grab any new packets. */ 945 sip_rxintr(sc); 946 947 if (isr & ISR_RXORN) { 948 printf("%s: receive FIFO overrun\n", 949 sc->sc_dev.dv_xname); 950 951 /* XXX adjust rx_drain_thresh? */ 952 } 953 954 if (isr & ISR_RXIDLE) { 955 printf("%s: receive ring overrun\n", 956 sc->sc_dev.dv_xname); 957 958 /* Get the receive process going again. */ 959 bus_space_write_4(sc->sc_st, sc->sc_sh, 960 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 961 bus_space_write_4(sc->sc_st, sc->sc_sh, 962 SIP_CR, CR_RXE); 963 } 964 } 965 966 if (isr & (ISR_TXURN|ISR_TXDESC)) { 967 /* Sweep up transmit descriptors. */ 968 sip_txintr(sc); 969 970 if (isr & ISR_TXURN) { 971 u_int32_t thresh; 972 973 printf("%s: transmit FIFO underrun", 974 sc->sc_dev.dv_xname); 975 976 thresh = sc->sc_tx_drain_thresh + 1; 977 if (thresh <= TXCFG_DRTH && 978 (thresh * 32) <= (SIP_TXFIFO_SIZE - 979 (sc->sc_tx_fill_thresh * 32))) { 980 printf("; increasing Tx drain " 981 "threshold to %u bytes\n", 982 thresh * 32); 983 sc->sc_tx_drain_thresh = thresh; 984 (void) sip_init(ifp); 985 } else { 986 (void) sip_init(ifp); 987 printf("\n"); 988 } 989 } 990 } 991 992 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 993 if (isr & ISR_PAUSE_ST) { 994 sc->sc_flags |= SIPF_PAUSED; 995 ifp->if_flags |= IFF_OACTIVE; 996 } 997 if (isr & ISR_PAUSE_END) { 998 sc->sc_flags &= ~SIPF_PAUSED; 999 ifp->if_flags &= ~IFF_OACTIVE; 1000 } 1001 } 1002 1003 if (isr & ISR_HIBERR) { 1004 #define PRINTERR(bit, str) \ 1005 if (isr & (bit)) \ 1006 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1007 PRINTERR(ISR_DPERR, "parity error"); 1008 PRINTERR(ISR_SSERR, "system error"); 1009 PRINTERR(ISR_RMABT, "master abort"); 1010 PRINTERR(ISR_RTABT, "target abort"); 1011 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1012 (void) sip_init(ifp); 1013 #undef PRINTERR 1014 } 1015 } 1016 1017 /* Try to get more packets going. */ 1018 sip_start(ifp); 1019 1020 return (handled); 1021 } 1022 1023 /* 1024 * sip_txintr: 1025 * 1026 * Helper; handle transmit interrupts. 1027 */ 1028 void 1029 sip_txintr(sc) 1030 struct sip_softc *sc; 1031 { 1032 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1033 struct sip_txsoft *txs; 1034 u_int32_t cmdsts; 1035 1036 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 1039 /* 1040 * Go through our Tx list and free mbufs for those 1041 * frames which have been transmitted. 1042 */ 1043 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1044 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1046 1047 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1048 if (cmdsts & CMDSTS_OWN) 1049 break; 1050 1051 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1052 1053 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1054 1055 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1056 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1057 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1058 m_freem(txs->txs_mbuf); 1059 txs->txs_mbuf = NULL; 1060 1061 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1062 1063 /* 1064 * Check for errors and collisions. 1065 */ 1066 if (cmdsts & 1067 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1068 if (ifp->if_flags & IFF_DEBUG) { 1069 if (CMDSTS_Tx_ED) 1070 printf("%s: excessive deferral\n", 1071 sc->sc_dev.dv_xname); 1072 if (CMDSTS_Tx_EC) { 1073 printf("%s: excessive collisions\n", 1074 sc->sc_dev.dv_xname); 1075 ifp->if_collisions += 16; 1076 } 1077 } 1078 } else { 1079 /* Packet was transmitted successfully. */ 1080 ifp->if_opackets++; 1081 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1082 } 1083 } 1084 1085 /* 1086 * If there are no more pending transmissions, cancel the watchdog 1087 * timer. 1088 */ 1089 if (txs == NULL) 1090 ifp->if_timer = 0; 1091 } 1092 1093 /* 1094 * sip_rxintr: 1095 * 1096 * Helper; handle receive interrupts. 1097 */ 1098 void 1099 sip_rxintr(sc) 1100 struct sip_softc *sc; 1101 { 1102 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1103 struct sip_rxsoft *rxs; 1104 struct mbuf *m; 1105 u_int32_t cmdsts; 1106 int i, len; 1107 1108 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1109 rxs = &sc->sc_rxsoft[i]; 1110 1111 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1112 1113 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1114 1115 /* 1116 * NOTE: OWN is set if owned by _consumer_. We're the 1117 * consumer of the receive ring, so if the bit is clear, 1118 * we have processed all of the packets. 1119 */ 1120 if ((cmdsts & CMDSTS_OWN) == 0) { 1121 /* 1122 * We have processed all of the receive buffers. 1123 */ 1124 break; 1125 } 1126 1127 /* 1128 * If any collisions were seen on the wire, count one. 1129 */ 1130 if (cmdsts & CMDSTS_Rx_COL) 1131 ifp->if_collisions++; 1132 1133 /* 1134 * If an error occurred, update stats, clear the status 1135 * word, and leave the packet buffer in place. It will 1136 * simply be reused the next time the ring comes around. 1137 */ 1138 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1139 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1140 ifp->if_ierrors++; 1141 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1142 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1143 /* Receive overrun handled elsewhere. */ 1144 printf("%s: receive descriptor error\n", 1145 sc->sc_dev.dv_xname); 1146 } 1147 #define PRINTERR(bit, str) \ 1148 if (cmdsts & (bit)) \ 1149 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1150 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1151 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1152 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1153 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1154 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1155 #undef PRINTERR 1156 SIP_INIT_RXDESC(sc, i); 1157 continue; 1158 } 1159 1160 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1161 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1162 1163 /* 1164 * No errors; receive the packet. Note, the SiS 900 1165 * includes the CRC with every packet. 1166 */ 1167 len = CMDSTS_SIZE(cmdsts); 1168 1169 #ifdef __NO_STRICT_ALIGNMENT 1170 /* 1171 * If the packet is small enough to fit in a 1172 * single header mbuf, allocate one and copy 1173 * the data into it. This greatly reduces 1174 * memory consumption when we receive lots 1175 * of small packets. 1176 * 1177 * Otherwise, we add a new buffer to the receive 1178 * chain. If this fails, we drop the packet and 1179 * recycle the old buffer. 1180 */ 1181 if (sip_copy_small != 0 && len <= MHLEN) { 1182 MGETHDR(m, M_DONTWAIT, MT_DATA); 1183 if (m == NULL) 1184 goto dropit; 1185 memcpy(mtod(m, caddr_t), 1186 mtod(rxs->rxs_mbuf, caddr_t), len); 1187 SIP_INIT_RXDESC(sc, i); 1188 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1189 rxs->rxs_dmamap->dm_mapsize, 1190 BUS_DMASYNC_PREREAD); 1191 } else { 1192 m = rxs->rxs_mbuf; 1193 if (sip_add_rxbuf(sc, i) != 0) { 1194 dropit: 1195 ifp->if_ierrors++; 1196 SIP_INIT_RXDESC(sc, i); 1197 bus_dmamap_sync(sc->sc_dmat, 1198 rxs->rxs_dmamap, 0, 1199 rxs->rxs_dmamap->dm_mapsize, 1200 BUS_DMASYNC_PREREAD); 1201 continue; 1202 } 1203 } 1204 #else 1205 /* 1206 * The SiS 900's receive buffers must be 4-byte aligned. 1207 * But this means that the data after the Ethernet header 1208 * is misaligned. We must allocate a new buffer and 1209 * copy the data, shifted forward 2 bytes. 1210 */ 1211 MGETHDR(m, M_DONTWAIT, MT_DATA); 1212 if (m == NULL) { 1213 dropit: 1214 ifp->if_ierrors++; 1215 SIP_INIT_RXDESC(sc, i); 1216 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1217 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1218 continue; 1219 } 1220 if (len > (MHLEN - 2)) { 1221 MCLGET(m, M_DONTWAIT); 1222 if ((m->m_flags & M_EXT) == 0) { 1223 m_freem(m); 1224 goto dropit; 1225 } 1226 } 1227 m->m_data += 2; 1228 1229 /* 1230 * Note that we use clusters for incoming frames, so the 1231 * buffer is virtually contiguous. 1232 */ 1233 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1234 1235 /* Allow the receive descriptor to continue using its mbuf. */ 1236 SIP_INIT_RXDESC(sc, i); 1237 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1238 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1239 #endif /* __NO_STRICT_ALIGNMENT */ 1240 1241 ifp->if_ipackets++; 1242 m->m_flags |= M_HASFCS; 1243 m->m_pkthdr.rcvif = ifp; 1244 m->m_pkthdr.len = m->m_len = len; 1245 1246 #if NBPFILTER > 0 1247 /* 1248 * Pass this up to any BPF listeners, but only 1249 * pass if up the stack if it's for us. 1250 */ 1251 if (ifp->if_bpf) 1252 bpf_mtap(ifp->if_bpf, m); 1253 #endif /* NBPFILTER > 0 */ 1254 1255 /* Pass it on. */ 1256 (*ifp->if_input)(ifp, m); 1257 } 1258 1259 /* Update the receive pointer. */ 1260 sc->sc_rxptr = i; 1261 } 1262 1263 /* 1264 * sip_tick: 1265 * 1266 * One second timer, used to tick the MII. 1267 */ 1268 void 1269 sip_tick(arg) 1270 void *arg; 1271 { 1272 struct sip_softc *sc = arg; 1273 int s; 1274 1275 s = splnet(); 1276 mii_tick(&sc->sc_mii); 1277 splx(s); 1278 1279 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1280 } 1281 1282 /* 1283 * sip_reset: 1284 * 1285 * Perform a soft reset on the SiS 900. 1286 */ 1287 void 1288 sip_reset(sc) 1289 struct sip_softc *sc; 1290 { 1291 bus_space_tag_t st = sc->sc_st; 1292 bus_space_handle_t sh = sc->sc_sh; 1293 int i; 1294 1295 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1296 1297 for (i = 0; i < SIP_TIMEOUT; i++) { 1298 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1299 break; 1300 delay(2); 1301 } 1302 1303 if (i == SIP_TIMEOUT) 1304 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1305 1306 delay(1000); 1307 } 1308 1309 /* 1310 * sip_init: [ ifnet interface function ] 1311 * 1312 * Initialize the interface. Must be called at splnet(). 1313 */ 1314 int 1315 sip_init(ifp) 1316 struct ifnet *ifp; 1317 { 1318 struct sip_softc *sc = ifp->if_softc; 1319 bus_space_tag_t st = sc->sc_st; 1320 bus_space_handle_t sh = sc->sc_sh; 1321 struct sip_txsoft *txs; 1322 struct sip_rxsoft *rxs; 1323 struct sip_desc *sipd; 1324 u_int32_t cfg; 1325 int i, error = 0; 1326 1327 /* 1328 * Cancel any pending I/O. 1329 */ 1330 sip_stop(ifp, 0); 1331 1332 /* 1333 * Reset the chip to a known state. 1334 */ 1335 sip_reset(sc); 1336 1337 /* 1338 * Initialize the transmit descriptor ring. 1339 */ 1340 for (i = 0; i < SIP_NTXDESC; i++) { 1341 sipd = &sc->sc_txdescs[i]; 1342 memset(sipd, 0, sizeof(struct sip_desc)); 1343 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1344 } 1345 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1346 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1347 sc->sc_txfree = SIP_NTXDESC; 1348 sc->sc_txnext = 0; 1349 1350 /* 1351 * Initialize the transmit job descriptors. 1352 */ 1353 SIMPLEQ_INIT(&sc->sc_txfreeq); 1354 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1355 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1356 txs = &sc->sc_txsoft[i]; 1357 txs->txs_mbuf = NULL; 1358 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1359 } 1360 1361 /* 1362 * Initialize the receive descriptor and receive job 1363 * descriptor rings. 1364 */ 1365 for (i = 0; i < SIP_NRXDESC; i++) { 1366 rxs = &sc->sc_rxsoft[i]; 1367 if (rxs->rxs_mbuf == NULL) { 1368 if ((error = sip_add_rxbuf(sc, i)) != 0) { 1369 printf("%s: unable to allocate or map rx " 1370 "buffer %d, error = %d\n", 1371 sc->sc_dev.dv_xname, i, error); 1372 /* 1373 * XXX Should attempt to run with fewer receive 1374 * XXX buffers instead of just failing. 1375 */ 1376 sip_rxdrain(sc); 1377 goto out; 1378 } 1379 } 1380 } 1381 sc->sc_rxptr = 0; 1382 1383 /* 1384 * Initialize the configuration register: aggressive PCI 1385 * bus request algorithm, default backoff, default OW timer, 1386 * default parity error detection. 1387 */ 1388 cfg = 0; 1389 #if BYTE_ORDER == BIG_ENDIAN 1390 /* 1391 * ...descriptors in big-endian mode. 1392 */ 1393 #if 0 1394 /* "Big endian mode" does not work properly. */ 1395 cfg |= CFG_BEM; 1396 #endif 1397 #endif 1398 bus_space_write_4(st, sh, SIP_CFG, cfg); 1399 1400 /* 1401 * Initialize the transmit fill and drain thresholds if 1402 * we have never done so. 1403 */ 1404 if (sc->sc_tx_fill_thresh == 0) { 1405 /* 1406 * XXX This value should be tuned. This is the 1407 * minimum (32 bytes), and we may be able to 1408 * improve performance by increasing it. 1409 */ 1410 sc->sc_tx_fill_thresh = 1; 1411 } 1412 if (sc->sc_tx_drain_thresh == 0) { 1413 /* 1414 * Start at a drain threshold of 512 bytes. We will 1415 * increase it if a DMA underrun occurs. 1416 * 1417 * XXX The minimum value of this variable should be 1418 * tuned. We may be able to improve performance 1419 * by starting with a lower value. That, however, 1420 * may trash the first few outgoing packets if the 1421 * PCI bus is saturated. 1422 */ 1423 sc->sc_tx_drain_thresh = 512 / 32; 1424 } 1425 1426 /* 1427 * Initialize the prototype TXCFG register. 1428 */ 1429 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1430 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1431 sc->sc_tx_drain_thresh; 1432 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1433 1434 /* 1435 * Initialize the receive drain threshold if we have never 1436 * done so. 1437 */ 1438 if (sc->sc_rx_drain_thresh == 0) { 1439 /* 1440 * XXX This value should be tuned. This is set to the 1441 * maximum of 248 bytes, and we may be able to improve 1442 * performance by decreasing it (although we should never 1443 * set this value lower than 2; 14 bytes are required to 1444 * filter the packet). 1445 */ 1446 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1447 } 1448 1449 /* 1450 * Initialize the prototype RXCFG register. 1451 */ 1452 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1453 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1454 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1455 1456 /* Set up the receive filter. */ 1457 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1458 1459 /* 1460 * Give the transmit and receive rings to the chip. 1461 */ 1462 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1463 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1464 1465 /* 1466 * Initialize the interrupt mask. 1467 */ 1468 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1469 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1470 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1471 1472 /* 1473 * Set the current media. Do this after initializing the prototype 1474 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1475 * control. 1476 */ 1477 mii_mediachg(&sc->sc_mii); 1478 1479 /* 1480 * Enable interrupts. 1481 */ 1482 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1483 1484 /* 1485 * Start the transmit and receive processes. 1486 */ 1487 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1488 1489 /* 1490 * Start the one second MII clock. 1491 */ 1492 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1493 1494 /* 1495 * ...all done! 1496 */ 1497 ifp->if_flags |= IFF_RUNNING; 1498 ifp->if_flags &= ~IFF_OACTIVE; 1499 1500 out: 1501 if (error) 1502 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1503 return (error); 1504 } 1505 1506 /* 1507 * sip_drain: 1508 * 1509 * Drain the receive queue. 1510 */ 1511 void 1512 sip_rxdrain(sc) 1513 struct sip_softc *sc; 1514 { 1515 struct sip_rxsoft *rxs; 1516 int i; 1517 1518 for (i = 0; i < SIP_NRXDESC; i++) { 1519 rxs = &sc->sc_rxsoft[i]; 1520 if (rxs->rxs_mbuf != NULL) { 1521 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1522 m_freem(rxs->rxs_mbuf); 1523 rxs->rxs_mbuf = NULL; 1524 } 1525 } 1526 } 1527 1528 /* 1529 * sip_stop: [ ifnet interface function ] 1530 * 1531 * Stop transmission on the interface. 1532 */ 1533 void 1534 sip_stop(ifp, disable) 1535 struct ifnet *ifp; 1536 int disable; 1537 { 1538 struct sip_softc *sc = ifp->if_softc; 1539 bus_space_tag_t st = sc->sc_st; 1540 bus_space_handle_t sh = sc->sc_sh; 1541 struct sip_txsoft *txs; 1542 u_int32_t cmdsts = 0; /* DEBUG */ 1543 1544 /* 1545 * Stop the one second clock. 1546 */ 1547 callout_stop(&sc->sc_tick_ch); 1548 1549 /* Down the MII. */ 1550 mii_down(&sc->sc_mii); 1551 1552 /* 1553 * Disable interrupts. 1554 */ 1555 bus_space_write_4(st, sh, SIP_IER, 0); 1556 1557 /* 1558 * Stop receiver and transmitter. 1559 */ 1560 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1561 1562 /* 1563 * Release any queued transmit buffers. 1564 */ 1565 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1566 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1567 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1568 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 1569 CMDSTS_INTR) == 0) 1570 printf("%s: sip_stop: last descriptor does not " 1571 "have INTR bit set\n", sc->sc_dev.dv_xname); 1572 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1573 #ifdef DIAGNOSTIC 1574 if (txs->txs_mbuf == NULL) { 1575 printf("%s: dirty txsoft with no mbuf chain\n", 1576 sc->sc_dev.dv_xname); 1577 panic("sip_stop"); 1578 } 1579 #endif 1580 cmdsts |= /* DEBUG */ 1581 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1582 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1583 m_freem(txs->txs_mbuf); 1584 txs->txs_mbuf = NULL; 1585 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1586 } 1587 1588 if (disable) 1589 sip_rxdrain(sc); 1590 1591 /* 1592 * Mark the interface down and cancel the watchdog timer. 1593 */ 1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1595 ifp->if_timer = 0; 1596 1597 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1598 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1599 printf("%s: sip_stop: no INTR bits set in dirty tx " 1600 "descriptors\n", sc->sc_dev.dv_xname); 1601 } 1602 1603 /* 1604 * sip_read_eeprom: 1605 * 1606 * Read data from the serial EEPROM. 1607 */ 1608 void 1609 sip_read_eeprom(sc, word, wordcnt, data) 1610 struct sip_softc *sc; 1611 int word, wordcnt; 1612 u_int16_t *data; 1613 { 1614 bus_space_tag_t st = sc->sc_st; 1615 bus_space_handle_t sh = sc->sc_sh; 1616 u_int16_t reg; 1617 int i, x; 1618 1619 for (i = 0; i < wordcnt; i++) { 1620 /* Send CHIP SELECT. */ 1621 reg = EROMAR_EECS; 1622 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1623 1624 /* Shift in the READ opcode. */ 1625 for (x = 3; x > 0; x--) { 1626 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1627 reg |= EROMAR_EEDI; 1628 else 1629 reg &= ~EROMAR_EEDI; 1630 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1631 bus_space_write_4(st, sh, SIP_EROMAR, 1632 reg | EROMAR_EESK); 1633 delay(4); 1634 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1635 delay(4); 1636 } 1637 1638 /* Shift in address. */ 1639 for (x = 6; x > 0; x--) { 1640 if ((word + i) & (1 << (x - 1))) 1641 reg |= EROMAR_EEDI; 1642 else 1643 reg &= ~EROMAR_EEDI; 1644 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1645 bus_space_write_4(st, sh, SIP_EROMAR, 1646 reg | EROMAR_EESK); 1647 delay(4); 1648 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1649 delay(4); 1650 } 1651 1652 /* Shift out data. */ 1653 reg = EROMAR_EECS; 1654 data[i] = 0; 1655 for (x = 16; x > 0; x--) { 1656 bus_space_write_4(st, sh, SIP_EROMAR, 1657 reg | EROMAR_EESK); 1658 delay(4); 1659 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1660 data[i] |= (1 << (x - 1)); 1661 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1662 delay(4); 1663 } 1664 1665 /* Clear CHIP SELECT. */ 1666 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1667 delay(4); 1668 } 1669 } 1670 1671 /* 1672 * sip_add_rxbuf: 1673 * 1674 * Add a receive buffer to the indicated descriptor. 1675 */ 1676 int 1677 sip_add_rxbuf(sc, idx) 1678 struct sip_softc *sc; 1679 int idx; 1680 { 1681 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1682 struct mbuf *m; 1683 int error; 1684 1685 MGETHDR(m, M_DONTWAIT, MT_DATA); 1686 if (m == NULL) 1687 return (ENOBUFS); 1688 1689 MCLGET(m, M_DONTWAIT); 1690 if ((m->m_flags & M_EXT) == 0) { 1691 m_freem(m); 1692 return (ENOBUFS); 1693 } 1694 1695 if (rxs->rxs_mbuf != NULL) 1696 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1697 1698 rxs->rxs_mbuf = m; 1699 1700 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1701 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1702 if (error) { 1703 printf("%s: can't load rx DMA map %d, error = %d\n", 1704 sc->sc_dev.dv_xname, idx, error); 1705 panic("sip_add_rxbuf"); /* XXX */ 1706 } 1707 1708 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1709 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1710 1711 SIP_INIT_RXDESC(sc, idx); 1712 1713 return (0); 1714 } 1715 1716 /* 1717 * sip_sis900_set_filter: 1718 * 1719 * Set up the receive filter. 1720 */ 1721 void 1722 sip_sis900_set_filter(sc) 1723 struct sip_softc *sc; 1724 { 1725 bus_space_tag_t st = sc->sc_st; 1726 bus_space_handle_t sh = sc->sc_sh; 1727 struct ethercom *ec = &sc->sc_ethercom; 1728 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1729 struct ether_multi *enm; 1730 u_int8_t *cp; 1731 struct ether_multistep step; 1732 u_int32_t crc, mchash[8]; 1733 1734 /* 1735 * Initialize the prototype RFCR. 1736 */ 1737 sc->sc_rfcr = RFCR_RFEN; 1738 if (ifp->if_flags & IFF_BROADCAST) 1739 sc->sc_rfcr |= RFCR_AAB; 1740 if (ifp->if_flags & IFF_PROMISC) { 1741 sc->sc_rfcr |= RFCR_AAP; 1742 goto allmulti; 1743 } 1744 1745 /* 1746 * Set up the multicast address filter by passing all multicast 1747 * addresses through a CRC generator, and then using the high-order 1748 * 6 bits as an index into the 128 bit multicast hash table (only 1749 * the lower 16 bits of each 32 bit multicast hash register are 1750 * valid). The high order bits select the register, while the 1751 * rest of the bits select the bit within the register. 1752 */ 1753 1754 memset(mchash, 0, sizeof(mchash)); 1755 1756 ETHER_FIRST_MULTI(step, ec, enm); 1757 while (enm != NULL) { 1758 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1759 /* 1760 * We must listen to a range of multicast addresses. 1761 * For now, just accept all multicasts, rather than 1762 * trying to set only those filter bits needed to match 1763 * the range. (At this time, the only use of address 1764 * ranges is for IP multicast routing, for which the 1765 * range is big enough to require all bits set.) 1766 */ 1767 goto allmulti; 1768 } 1769 1770 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1771 1772 /* Just want the 7 most significant bits. */ 1773 crc >>= 25; 1774 1775 /* Set the corresponding bit in the hash table. */ 1776 mchash[crc >> 4] |= 1 << (crc & 0xf); 1777 1778 ETHER_NEXT_MULTI(step, enm); 1779 } 1780 1781 ifp->if_flags &= ~IFF_ALLMULTI; 1782 goto setit; 1783 1784 allmulti: 1785 ifp->if_flags |= IFF_ALLMULTI; 1786 sc->sc_rfcr |= RFCR_AAM; 1787 1788 setit: 1789 #define FILTER_EMIT(addr, data) \ 1790 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1791 delay(1); \ 1792 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1793 delay(1) 1794 1795 /* 1796 * Disable receive filter, and program the node address. 1797 */ 1798 cp = LLADDR(ifp->if_sadl); 1799 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1800 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1801 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1802 1803 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1804 /* 1805 * Program the multicast hash table. 1806 */ 1807 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1808 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1809 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1810 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1811 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1812 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1813 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1814 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1815 } 1816 #undef FILTER_EMIT 1817 1818 /* 1819 * Re-enable the receiver filter. 1820 */ 1821 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1822 } 1823 1824 /* 1825 * sip_dp83815_set_filter: 1826 * 1827 * Set up the receive filter. 1828 */ 1829 void 1830 sip_dp83815_set_filter(sc) 1831 struct sip_softc *sc; 1832 { 1833 bus_space_tag_t st = sc->sc_st; 1834 bus_space_handle_t sh = sc->sc_sh; 1835 struct ethercom *ec = &sc->sc_ethercom; 1836 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1837 struct ether_multi *enm; 1838 u_int8_t *cp; 1839 struct ether_multistep step; 1840 u_int32_t crc, mchash[16]; 1841 int i; 1842 1843 /* 1844 * Initialize the prototype RFCR. 1845 */ 1846 sc->sc_rfcr = RFCR_RFEN | RFCR_AARP | RFCR_APM; 1847 if (ifp->if_flags & IFF_BROADCAST) 1848 sc->sc_rfcr |= RFCR_AAB; 1849 if (ifp->if_flags & IFF_PROMISC) { 1850 sc->sc_rfcr |= RFCR_AAP; 1851 goto allmulti; 1852 } 1853 1854 /* 1855 * Set up the multicast address filter by passing all multicast 1856 * addresses through a CRC generator, and then using the high-order 1857 * 9 bits as an index into the 512 bit multicast hash table. The 1858 * high-order bits select the slot, while the rest of the bits 1859 * select the bit within the slot. Note that only the low 16-bits 1860 * of each filter word are used, and there are 64 filter words. 1861 */ 1862 1863 memset(mchash, 0, sizeof(mchash)); 1864 1865 ETHER_FIRST_MULTI(step, ec, enm); 1866 while (enm != NULL) { 1867 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1868 /* 1869 * We must listen to a range of multicast addresses. 1870 * For now, just accept all multicasts, rather than 1871 * trying to set only those filter bits needed to match 1872 * the range. (At this time, the only use of address 1873 * ranges is for IP multicast routing, for which the 1874 * range is big enough to require all bits set.) 1875 */ 1876 goto allmulti; 1877 } 1878 1879 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1880 1881 /* Just want the 9 most significant bits. */ 1882 crc >>= 23; 1883 1884 /* Set the corresponding bit in the hash table. */ 1885 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1886 1887 ETHER_NEXT_MULTI(step, enm); 1888 } 1889 1890 ifp->if_flags |= ~IFF_ALLMULTI; 1891 sc->sc_rfcr |= RFCR_MHEN; 1892 goto setit; 1893 1894 allmulti: 1895 ifp->if_flags |= IFF_ALLMULTI; 1896 sc->sc_rfcr |= RFCR_AAM; 1897 1898 setit: 1899 #define FILTER_EMIT(addr, data) \ 1900 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1901 delay(1); \ 1902 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1903 delay(1); 1904 1905 /* 1906 * Disable receive filter, and program the node address. 1907 */ 1908 cp = LLADDR(ifp->if_sadl); 1909 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[1] << 8) | cp[0]); 1910 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[3] << 8) | cp[2]); 1911 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[5] << 8) | cp[4]); 1912 1913 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1914 /* 1915 * Program the multicast hash table. 1916 */ 1917 for (i = 0; i < 16; i++) { 1918 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 1919 mchash[i] & 0xffff); 1920 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2) + 2, 1921 (mchash[i] >> 16) & 0xffff); 1922 } 1923 } 1924 #undef FILTER_EMIT 1925 1926 /* 1927 * Re-enable the receiver filter. 1928 */ 1929 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1930 } 1931 1932 /* 1933 * sip_sis900_mii_readreg: [mii interface function] 1934 * 1935 * Read a PHY register on the MII. 1936 */ 1937 int 1938 sip_sis900_mii_readreg(self, phy, reg) 1939 struct device *self; 1940 int phy, reg; 1941 { 1942 struct sip_softc *sc = (struct sip_softc *) self; 1943 u_int32_t enphy; 1944 1945 /* 1946 * The SiS 900 has only an internal PHY on the MII. Only allow 1947 * MII address 0. 1948 */ 1949 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 1950 return (0); 1951 1952 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1953 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 1954 ENPHY_RWCMD | ENPHY_ACCESS); 1955 do { 1956 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1957 } while (enphy & ENPHY_ACCESS); 1958 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 1959 } 1960 1961 /* 1962 * sip_sis900_mii_writereg: [mii interface function] 1963 * 1964 * Write a PHY register on the MII. 1965 */ 1966 void 1967 sip_sis900_mii_writereg(self, phy, reg, val) 1968 struct device *self; 1969 int phy, reg, val; 1970 { 1971 struct sip_softc *sc = (struct sip_softc *) self; 1972 u_int32_t enphy; 1973 1974 /* 1975 * The SiS 900 has only an internal PHY on the MII. Only allow 1976 * MII address 0. 1977 */ 1978 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 1979 return; 1980 1981 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1982 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 1983 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 1984 do { 1985 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1986 } while (enphy & ENPHY_ACCESS); 1987 } 1988 1989 /* 1990 * sip_sis900_mii_statchg: [mii interface function] 1991 * 1992 * Callback from MII layer when media changes. 1993 */ 1994 void 1995 sip_sis900_mii_statchg(self) 1996 struct device *self; 1997 { 1998 struct sip_softc *sc = (struct sip_softc *) self; 1999 u_int32_t flowctl; 2000 2001 /* 2002 * Update TXCFG for full-duplex operation. 2003 */ 2004 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2005 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2006 else 2007 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2008 2009 /* 2010 * Update RXCFG for full-duplex or loopback. 2011 */ 2012 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2013 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2014 sc->sc_rxcfg |= RXCFG_ATX; 2015 else 2016 sc->sc_rxcfg &= ~RXCFG_ATX; 2017 2018 /* 2019 * Update IMR for use of 802.3x flow control. 2020 */ 2021 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2022 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2023 flowctl = FLOWCTL_FLOWEN; 2024 } else { 2025 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2026 flowctl = 0; 2027 } 2028 2029 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2030 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2031 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2032 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2033 } 2034 2035 /* 2036 * sip_dp83815_mii_readreg: [mii interface function] 2037 * 2038 * Read a PHY register on the MII. 2039 */ 2040 int 2041 sip_dp83815_mii_readreg(self, phy, reg) 2042 struct device *self; 2043 int phy, reg; 2044 { 2045 struct sip_softc *sc = (struct sip_softc *) self; 2046 u_int32_t val; 2047 2048 /* 2049 * The DP83815 only has an internal PHY. Only allow 2050 * MII address 0. 2051 */ 2052 if (phy != 0) 2053 return (0); 2054 2055 /* 2056 * Apparently, after a reset, the DP83815 can take a while 2057 * to respond. During this recovery period, the BMSR returns 2058 * a value of 0. Catch this -- it's not supposed to happen 2059 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2060 * PHY to come back to life. 2061 * 2062 * This works out because the BMSR is the first register 2063 * read during the PHY probe process. 2064 */ 2065 do { 2066 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2067 } while (reg == MII_BMSR && val == 0); 2068 2069 return (val & 0xffff); 2070 } 2071 2072 /* 2073 * sip_dp83815_mii_writereg: [mii interface function] 2074 * 2075 * Write a PHY register to the MII. 2076 */ 2077 void 2078 sip_dp83815_mii_writereg(self, phy, reg, val) 2079 struct device *self; 2080 int phy, reg, val; 2081 { 2082 struct sip_softc *sc = (struct sip_softc *) self; 2083 2084 /* 2085 * The DP83815 only has an internal PHY. Only allow 2086 * MII address 0. 2087 */ 2088 if (phy != 0) 2089 return; 2090 2091 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2092 } 2093 2094 /* 2095 * sip_dp83815_mii_statchg: [mii interface function] 2096 * 2097 * Callback from MII layer when media changes. 2098 */ 2099 void 2100 sip_dp83815_mii_statchg(self) 2101 struct device *self; 2102 { 2103 struct sip_softc *sc = (struct sip_softc *) self; 2104 2105 /* 2106 * Update TXCFG for full-duplex operation. 2107 */ 2108 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2109 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2110 else 2111 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2112 2113 /* 2114 * Update RXCFG for full-duplex or loopback. 2115 */ 2116 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2117 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2118 sc->sc_rxcfg |= RXCFG_ATX; 2119 else 2120 sc->sc_rxcfg &= ~RXCFG_ATX; 2121 2122 /* 2123 * XXX 802.3x flow control. 2124 */ 2125 2126 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2127 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2128 } 2129 2130 /* 2131 * sip_mediastatus: [ifmedia interface function] 2132 * 2133 * Get the current interface media status. 2134 */ 2135 void 2136 sip_mediastatus(ifp, ifmr) 2137 struct ifnet *ifp; 2138 struct ifmediareq *ifmr; 2139 { 2140 struct sip_softc *sc = ifp->if_softc; 2141 2142 mii_pollstat(&sc->sc_mii); 2143 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2144 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2145 } 2146 2147 /* 2148 * sip_mediachange: [ifmedia interface function] 2149 * 2150 * Set hardware to newly-selected media. 2151 */ 2152 int 2153 sip_mediachange(ifp) 2154 struct ifnet *ifp; 2155 { 2156 struct sip_softc *sc = ifp->if_softc; 2157 2158 if (ifp->if_flags & IFF_UP) 2159 mii_mediachg(&sc->sc_mii); 2160 return (0); 2161 } 2162