1 /* $NetBSD: if_sip.c,v 1.12 2000/06/28 16:08:45 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Silicon Integrated Systems SiS 900 and 34 * SiS 7016 10/100 PCI Ethernet controllers. 35 * 36 * Written by Jason R. Thorpe for Network Computer, Inc. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcidevs.h> 84 85 #include <dev/pci/if_sipreg.h> 86 87 /* 88 * Devices supported by this driver. 89 */ 90 const struct sip_product { 91 pci_vendor_id_t sip_vendor; 92 pci_product_id_t sip_product; 93 const char *sip_name; 94 } sip_products[] = { 95 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 96 "SiS 900 10/100 Ethernet" }, 97 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 98 "SiS 7016 10/100 Ethernet" }, 99 100 { 0, 0, 101 NULL }, 102 }; 103 104 /* 105 * Transmit descriptor list size. This is arbitrary, but allocate 106 * enough descriptors for 64 pending transmissions, and 16 segments 107 * per packet. This MUST work out to a power of 2. 108 */ 109 #define SIP_NTXSEGS 16 110 111 #define SIP_TXQUEUELEN 64 112 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 113 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 114 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 115 116 /* 117 * Receive descriptor list size. We have one Rx buffer per incoming 118 * packet, so this logic is a little simpler. 119 */ 120 #define SIP_NRXDESC 64 121 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 122 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 123 124 /* 125 * Control structures are DMA'd to the SiS900 chip. We allocate them in 126 * a single clump that maps to a single DMA segment to make several things 127 * easier. 128 */ 129 struct sip_control_data { 130 /* 131 * The transmit descriptors. 132 */ 133 struct sip_desc scd_txdescs[SIP_NTXDESC]; 134 135 /* 136 * The receive descriptors. 137 */ 138 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 139 }; 140 141 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 142 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 143 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 144 145 /* 146 * Software state for transmit jobs. 147 */ 148 struct sip_txsoft { 149 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 150 bus_dmamap_t txs_dmamap; /* our DMA map */ 151 int txs_firstdesc; /* first descriptor in packet */ 152 int txs_lastdesc; /* last descriptor in packet */ 153 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 154 }; 155 156 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 157 158 /* 159 * Software state for receive jobs. 160 */ 161 struct sip_rxsoft { 162 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 163 bus_dmamap_t rxs_dmamap; /* our DMA map */ 164 }; 165 166 /* 167 * Software state per device. 168 */ 169 struct sip_softc { 170 struct device sc_dev; /* generic device information */ 171 bus_space_tag_t sc_st; /* bus space tag */ 172 bus_space_handle_t sc_sh; /* bus space handle */ 173 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 174 struct ethercom sc_ethercom; /* ethernet common data */ 175 void *sc_sdhook; /* shutdown hook */ 176 pci_product_id_t sc_model; /* which model are we? */ 177 178 void *sc_ih; /* interrupt cookie */ 179 180 struct mii_data sc_mii; /* MII/media information */ 181 182 struct callout sc_tick_ch; /* tick callout */ 183 184 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 185 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 186 187 /* 188 * Software state for transmit and receive descriptors. 189 */ 190 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 191 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 192 193 /* 194 * Control data structures. 195 */ 196 struct sip_control_data *sc_control_data; 197 #define sc_txdescs sc_control_data->scd_txdescs 198 #define sc_rxdescs sc_control_data->scd_rxdescs 199 200 u_int32_t sc_txcfg; /* prototype TXCFG register */ 201 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 202 u_int32_t sc_imr; /* prototype IMR register */ 203 u_int32_t sc_rfcr; /* prototype RFCR register */ 204 205 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 206 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 207 208 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 209 210 int sc_flags; /* misc. flags; see below */ 211 212 int sc_txfree; /* number of free Tx descriptors */ 213 int sc_txnext; /* next ready Tx descriptor */ 214 215 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 216 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 217 218 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 219 }; 220 221 /* sc_flags */ 222 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 223 224 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 225 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 226 227 #define SIP_CDTXSYNC(sc, x, n, ops) \ 228 do { \ 229 int __x, __n; \ 230 \ 231 __x = (x); \ 232 __n = (n); \ 233 \ 234 /* If it will wrap around, sync to the end of the ring. */ \ 235 if ((__x + __n) > SIP_NTXDESC) { \ 236 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 237 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 238 (SIP_NTXDESC - __x), (ops)); \ 239 __n -= (SIP_NTXDESC - __x); \ 240 __x = 0; \ 241 } \ 242 \ 243 /* Now sync whatever is left. */ \ 244 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 245 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 246 } while (0) 247 248 #define SIP_CDRXSYNC(sc, x, ops) \ 249 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 250 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 251 252 /* 253 * Note we rely on MCLBYTES being a power of two below. 254 */ 255 #define SIP_INIT_RXDESC(sc, x) \ 256 do { \ 257 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 258 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 259 \ 260 __sipd->sipd_link = SIP_CDRXADDR((sc), SIP_NEXTRX((x))); \ 261 __sipd->sipd_bufptr = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 262 __sipd->sipd_cmdsts = CMDSTS_INTR | \ 263 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK); \ 264 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 265 } while (0) 266 267 void sip_start __P((struct ifnet *)); 268 void sip_watchdog __P((struct ifnet *)); 269 int sip_ioctl __P((struct ifnet *, u_long, caddr_t)); 270 271 void sip_shutdown __P((void *)); 272 273 void sip_reset __P((struct sip_softc *)); 274 int sip_init __P((struct sip_softc *)); 275 void sip_stop __P((struct sip_softc *, int)); 276 void sip_rxdrain __P((struct sip_softc *)); 277 int sip_add_rxbuf __P((struct sip_softc *, int)); 278 void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *)); 279 void sip_set_filter __P((struct sip_softc *)); 280 void sip_tick __P((void *)); 281 282 int sip_intr __P((void *)); 283 void sip_txintr __P((struct sip_softc *)); 284 void sip_rxintr __P((struct sip_softc *)); 285 286 int sip_mii_readreg __P((struct device *, int, int)); 287 void sip_mii_writereg __P((struct device *, int, int, int)); 288 void sip_mii_statchg __P((struct device *)); 289 290 int sip_mediachange __P((struct ifnet *)); 291 void sip_mediastatus __P((struct ifnet *, struct ifmediareq *)); 292 293 int sip_match __P((struct device *, struct cfdata *, void *)); 294 void sip_attach __P((struct device *, struct device *, void *)); 295 296 int sip_copy_small = 0; 297 298 struct cfattach sip_ca = { 299 sizeof(struct sip_softc), sip_match, sip_attach, 300 }; 301 302 const struct sip_product *sip_lookup __P((const struct pci_attach_args *)); 303 304 const struct sip_product * 305 sip_lookup(pa) 306 const struct pci_attach_args *pa; 307 { 308 const struct sip_product *sip; 309 310 for (sip = sip_products; sip->sip_name != NULL; sip++) { 311 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 312 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 313 return (sip); 314 } 315 return (NULL); 316 } 317 318 int 319 sip_match(parent, cf, aux) 320 struct device *parent; 321 struct cfdata *cf; 322 void *aux; 323 { 324 struct pci_attach_args *pa = aux; 325 326 if (sip_lookup(pa) != NULL) 327 return (1); 328 329 return (0); 330 } 331 332 void 333 sip_attach(parent, self, aux) 334 struct device *parent, *self; 335 void *aux; 336 { 337 struct sip_softc *sc = (struct sip_softc *) self; 338 struct pci_attach_args *pa = aux; 339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 340 pci_chipset_tag_t pc = pa->pa_pc; 341 pci_intr_handle_t ih; 342 const char *intrstr = NULL; 343 bus_space_tag_t iot, memt; 344 bus_space_handle_t ioh, memh; 345 bus_dma_segment_t seg; 346 int ioh_valid, memh_valid; 347 int i, rseg, error; 348 const struct sip_product *sip; 349 pcireg_t pmode; 350 u_int16_t enaddr[ETHER_ADDR_LEN / 2]; 351 int pmreg; 352 353 callout_init(&sc->sc_tick_ch); 354 355 sip = sip_lookup(pa); 356 if (sip == NULL) { 357 printf("\n"); 358 panic("sip_attach: impossible"); 359 } 360 361 printf(": %s\n", sip->sip_name); 362 363 sc->sc_model = PCI_PRODUCT(pa->pa_id); 364 365 /* 366 * Map the device. 367 */ 368 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 369 PCI_MAPREG_TYPE_IO, 0, 370 &iot, &ioh, NULL, NULL) == 0); 371 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 372 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 373 &memt, &memh, NULL, NULL) == 0); 374 375 if (memh_valid) { 376 sc->sc_st = memt; 377 sc->sc_sh = memh; 378 } else if (ioh_valid) { 379 sc->sc_st = iot; 380 sc->sc_sh = ioh; 381 } else { 382 printf("%s: unable to map device registers\n", 383 sc->sc_dev.dv_xname); 384 return; 385 } 386 387 sc->sc_dmat = pa->pa_dmat; 388 389 /* Enable bus mastering. */ 390 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 391 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 392 PCI_COMMAND_MASTER_ENABLE); 393 394 /* Get it out of power save mode if needed. */ 395 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 396 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 397 if (pmode == 3) { 398 /* 399 * The card has lost all configuration data in 400 * this state, so punt. 401 */ 402 printf("%s: unable to wake up from power state D3\n", 403 sc->sc_dev.dv_xname); 404 return; 405 } 406 if (pmode != 0) { 407 printf("%s: waking up from power state D%d\n", 408 sc->sc_dev.dv_xname, pmode); 409 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 410 } 411 } 412 413 /* 414 * Map and establish our interrupt. 415 */ 416 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 417 pa->pa_intrline, &ih)) { 418 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 419 return; 420 } 421 intrstr = pci_intr_string(pc, ih); 422 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 423 if (sc->sc_ih == NULL) { 424 printf("%s: unable to establish interrupt", 425 sc->sc_dev.dv_xname); 426 if (intrstr != NULL) 427 printf(" at %s", intrstr); 428 printf("\n"); 429 return; 430 } 431 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 432 433 SIMPLEQ_INIT(&sc->sc_txfreeq); 434 SIMPLEQ_INIT(&sc->sc_txdirtyq); 435 436 /* 437 * Allocate the control data structures, and create and load the 438 * DMA map for it. 439 */ 440 if ((error = bus_dmamem_alloc(sc->sc_dmat, 441 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 442 0)) != 0) { 443 printf("%s: unable to allocate control data, error = %d\n", 444 sc->sc_dev.dv_xname, error); 445 goto fail_0; 446 } 447 448 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 449 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 450 BUS_DMA_COHERENT)) != 0) { 451 printf("%s: unable to map control data, error = %d\n", 452 sc->sc_dev.dv_xname, error); 453 goto fail_1; 454 } 455 456 if ((error = bus_dmamap_create(sc->sc_dmat, 457 sizeof(struct sip_control_data), 1, 458 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 459 printf("%s: unable to create control data DMA map, " 460 "error = %d\n", sc->sc_dev.dv_xname, error); 461 goto fail_2; 462 } 463 464 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 465 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 466 0)) != 0) { 467 printf("%s: unable to load control data DMA map, error = %d\n", 468 sc->sc_dev.dv_xname, error); 469 goto fail_3; 470 } 471 472 /* 473 * Create the transmit buffer DMA maps. 474 */ 475 for (i = 0; i < SIP_TXQUEUELEN; i++) { 476 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 477 SIP_NTXSEGS, MCLBYTES, 0, 0, 478 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 479 printf("%s: unable to create tx DMA map %d, " 480 "error = %d\n", sc->sc_dev.dv_xname, i, error); 481 goto fail_4; 482 } 483 } 484 485 /* 486 * Create the receive buffer DMA maps. 487 */ 488 for (i = 0; i < SIP_NRXDESC; i++) { 489 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 490 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 491 printf("%s: unable to create rx DMA map %d, " 492 "error = %d\n", sc->sc_dev.dv_xname, i, error); 493 goto fail_5; 494 } 495 sc->sc_rxsoft[i].rxs_mbuf = NULL; 496 } 497 498 /* 499 * Reset the chip to a known state. 500 */ 501 sip_reset(sc); 502 503 /* 504 * Read the Ethernet address from the EEPROM. 505 */ 506 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 507 sizeof(enaddr) / sizeof(enaddr[0]), enaddr); 508 509 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 510 ether_sprintf((u_int8_t *)enaddr)); 511 512 /* 513 * Initialize our media structures and probe the MII. 514 */ 515 sc->sc_mii.mii_ifp = ifp; 516 sc->sc_mii.mii_readreg = sip_mii_readreg; 517 sc->sc_mii.mii_writereg = sip_mii_writereg; 518 sc->sc_mii.mii_statchg = sip_mii_statchg; 519 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 520 sip_mediastatus); 521 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 522 MII_OFFSET_ANY, 0); 523 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 524 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 525 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 526 } else 527 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 528 529 ifp = &sc->sc_ethercom.ec_if; 530 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 531 ifp->if_softc = sc; 532 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 533 ifp->if_ioctl = sip_ioctl; 534 ifp->if_start = sip_start; 535 ifp->if_watchdog = sip_watchdog; 536 537 /* 538 * Attach the interface. 539 */ 540 if_attach(ifp); 541 ether_ifattach(ifp, (u_int8_t *)enaddr); 542 #if NBPFILTER > 0 543 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 544 sizeof(struct ether_header)); 545 #endif 546 547 /* 548 * Make sure the interface is shutdown during reboot. 549 */ 550 sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc); 551 if (sc->sc_sdhook == NULL) 552 printf("%s: WARNING: unable to establish shutdown hook\n", 553 sc->sc_dev.dv_xname); 554 return; 555 556 /* 557 * Free any resources we've allocated during the failed attach 558 * attempt. Do this in reverse order and fall through. 559 */ 560 fail_5: 561 for (i = 0; i < SIP_NRXDESC; i++) { 562 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 563 bus_dmamap_destroy(sc->sc_dmat, 564 sc->sc_rxsoft[i].rxs_dmamap); 565 } 566 fail_4: 567 for (i = 0; i < SIP_TXQUEUELEN; i++) { 568 if (sc->sc_txsoft[i].txs_dmamap != NULL) 569 bus_dmamap_destroy(sc->sc_dmat, 570 sc->sc_txsoft[i].txs_dmamap); 571 } 572 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 573 fail_3: 574 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 575 fail_2: 576 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 577 sizeof(struct sip_control_data)); 578 fail_1: 579 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 580 fail_0: 581 return; 582 } 583 584 /* 585 * sip_shutdown: 586 * 587 * Make sure the interface is stopped at reboot time. 588 */ 589 void 590 sip_shutdown(arg) 591 void *arg; 592 { 593 struct sip_softc *sc = arg; 594 595 sip_stop(sc, 1); 596 } 597 598 /* 599 * sip_start: [ifnet interface function] 600 * 601 * Start packet transmission on the interface. 602 */ 603 void 604 sip_start(ifp) 605 struct ifnet *ifp; 606 { 607 struct sip_softc *sc = ifp->if_softc; 608 struct mbuf *m0, *m; 609 struct sip_txsoft *txs; 610 bus_dmamap_t dmamap; 611 int error, firsttx, nexttx, lasttx, ofree, seg; 612 613 /* 614 * If we've been told to pause, don't transmit any more packets. 615 */ 616 if (sc->sc_flags & SIPF_PAUSED) 617 ifp->if_flags |= IFF_OACTIVE; 618 619 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 620 return; 621 622 /* 623 * Remember the previous number of free descriptors and 624 * the first descriptor we'll use. 625 */ 626 ofree = sc->sc_txfree; 627 firsttx = sc->sc_txnext; 628 629 /* 630 * Loop through the send queue, setting up transmit descriptors 631 * until we drain the queue, or use up all available transmit 632 * descriptors. 633 */ 634 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 635 sc->sc_txfree != 0) { 636 /* 637 * Grab a packet off the queue. 638 */ 639 IF_DEQUEUE(&ifp->if_snd, m0); 640 if (m0 == NULL) 641 break; 642 643 dmamap = txs->txs_dmamap; 644 645 /* 646 * Load the DMA map. If this fails, the packet either 647 * didn't fit in the alloted number of segments, or we 648 * were short on resources. In this case, we'll copy 649 * and try again. 650 */ 651 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 652 BUS_DMA_NOWAIT) != 0) { 653 MGETHDR(m, M_DONTWAIT, MT_DATA); 654 if (m == NULL) { 655 printf("%s: unable to allocate Tx mbuf\n", 656 sc->sc_dev.dv_xname); 657 IF_PREPEND(&ifp->if_snd, m0); 658 break; 659 } 660 if (m0->m_pkthdr.len > MHLEN) { 661 MCLGET(m, M_DONTWAIT); 662 if ((m->m_flags & M_EXT) == 0) { 663 printf("%s: unable to allocate Tx " 664 "cluster\n", sc->sc_dev.dv_xname); 665 m_freem(m); 666 IF_PREPEND(&ifp->if_snd, m0); 667 break; 668 } 669 } 670 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 671 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 672 m_freem(m0); 673 m0 = m; 674 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 675 m0, BUS_DMA_NOWAIT); 676 if (error) { 677 printf("%s: unable to load Tx buffer, " 678 "error = %d\n", sc->sc_dev.dv_xname, error); 679 IF_PREPEND(&ifp->if_snd, m0); 680 break; 681 } 682 } 683 684 /* 685 * Ensure we have enough descriptors free to describe 686 * the packet. 687 */ 688 if (dmamap->dm_nsegs > sc->sc_txfree) { 689 /* 690 * Not enough free descriptors to transmit this 691 * packet. We haven't committed anything yet, 692 * so just unload the DMA map, put the packet 693 * back on the queue, and punt. Notify the upper 694 * layer that there are not more slots left. 695 * 696 * XXX We could allocate an mbuf and copy, but 697 * XXX is it worth it? 698 */ 699 ifp->if_flags |= IFF_OACTIVE; 700 bus_dmamap_unload(sc->sc_dmat, dmamap); 701 IF_PREPEND(&ifp->if_snd, m0); 702 break; 703 } 704 705 /* 706 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 707 */ 708 709 /* Sync the DMA map. */ 710 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 711 BUS_DMASYNC_PREWRITE); 712 713 /* 714 * Initialize the transmit descriptors. 715 */ 716 for (nexttx = sc->sc_txnext, seg = 0; 717 seg < dmamap->dm_nsegs; 718 seg++, nexttx = SIP_NEXTTX(nexttx)) { 719 /* 720 * If this is the first descriptor we're 721 * enqueueing, don't set the OWN bit just 722 * yet. That could cause a race condition. 723 * We'll do it below. 724 */ 725 sc->sc_txdescs[nexttx].sipd_bufptr = 726 dmamap->dm_segs[seg].ds_addr; 727 sc->sc_txdescs[nexttx].sipd_cmdsts = 728 (nexttx == firsttx ? 0 : CMDSTS_OWN) | 729 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len; 730 lasttx = nexttx; 731 } 732 733 /* Clear the MORE bit on the last segment. */ 734 sc->sc_txdescs[lasttx].sipd_cmdsts &= ~CMDSTS_MORE; 735 736 /* Sync the descriptors we're using. */ 737 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 738 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 739 740 /* 741 * Store a pointer to the packet so we can free it later, 742 * and remember what txdirty will be once the packet is 743 * done. 744 */ 745 txs->txs_mbuf = m0; 746 txs->txs_firstdesc = sc->sc_txnext; 747 txs->txs_lastdesc = lasttx; 748 749 /* Advance the tx pointer. */ 750 sc->sc_txfree -= dmamap->dm_nsegs; 751 sc->sc_txnext = nexttx; 752 753 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 754 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 755 756 #if NBPFILTER > 0 757 /* 758 * Pass the packet to any BPF listeners. 759 */ 760 if (ifp->if_bpf) 761 bpf_mtap(ifp->if_bpf, m0); 762 #endif /* NBPFILTER > 0 */ 763 } 764 765 if (txs == NULL || sc->sc_txfree == 0) { 766 /* No more slots left; notify upper layer. */ 767 ifp->if_flags |= IFF_OACTIVE; 768 } 769 770 if (sc->sc_txfree != ofree) { 771 /* 772 * Cause a descriptor interrupt to happen on the 773 * last packet we enqueued. 774 */ 775 sc->sc_txdescs[lasttx].sipd_cmdsts |= CMDSTS_INTR; 776 SIP_CDTXSYNC(sc, lasttx, 1, 777 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 778 779 /* 780 * The entire packet chain is set up. Give the 781 * first descrptor to the chip now. 782 */ 783 sc->sc_txdescs[firsttx].sipd_cmdsts |= CMDSTS_OWN; 784 SIP_CDTXSYNC(sc, firsttx, 1, 785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 786 787 /* Start the transmit process. */ 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 789 CR_TXE) == 0) { 790 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 791 SIP_CDTXADDR(sc, firsttx)); 792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 793 } 794 795 /* Set a watchdog timer in case the chip flakes out. */ 796 ifp->if_timer = 5; 797 } 798 } 799 800 /* 801 * sip_watchdog: [ifnet interface function] 802 * 803 * Watchdog timer handler. 804 */ 805 void 806 sip_watchdog(ifp) 807 struct ifnet *ifp; 808 { 809 struct sip_softc *sc = ifp->if_softc; 810 811 /* 812 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 813 * If we get a timeout, try and sweep up transmit descriptors. 814 * If we manage to sweep them all up, ignore the lack of 815 * interrupt. 816 */ 817 sip_txintr(sc); 818 819 if (sc->sc_txfree != SIP_NTXDESC) { 820 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 821 ifp->if_oerrors++; 822 823 /* Reset the interface. */ 824 (void) sip_init(sc); 825 } else if (ifp->if_flags & IFF_DEBUG) 826 printf("%s: recovered from device timeout\n", 827 sc->sc_dev.dv_xname); 828 829 /* Try to get more packets going. */ 830 sip_start(ifp); 831 } 832 833 /* 834 * sip_ioctl: [ifnet interface function] 835 * 836 * Handle control requests from the operator. 837 */ 838 int 839 sip_ioctl(ifp, cmd, data) 840 struct ifnet *ifp; 841 u_long cmd; 842 caddr_t data; 843 { 844 struct sip_softc *sc = ifp->if_softc; 845 struct ifreq *ifr = (struct ifreq *)data; 846 struct ifaddr *ifa = (struct ifaddr *)data; 847 int s, error = 0; 848 849 s = splnet(); 850 851 switch (cmd) { 852 case SIOCSIFADDR: 853 ifp->if_flags |= IFF_UP; 854 855 switch (ifa->ifa_addr->sa_family) { 856 #ifdef INET 857 case AF_INET: 858 if ((error = sip_init(sc)) != 0) 859 break; 860 arp_ifinit(ifp, ifa); 861 break; 862 #endif /* INET */ 863 #ifdef NS 864 case AF_NS: 865 { 866 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 867 868 if (ns_nullhost(*ina)) 869 ina->x_host = *(union ns_host *) 870 LLADDR(ifp->if_sadl); 871 else 872 memcpy(LLADDR(ifp->if_sadl), 873 ina->x_host.c_host, ifp->if_addrlen); 874 error = sip_init(sc); 875 break; 876 } 877 #endif /* NS */ 878 default: 879 error = sip_init(sc); 880 break; 881 } 882 break; 883 884 case SIOCSIFMTU: 885 if (ifr->ifr_mtu > ETHERMTU) 886 error = EINVAL; 887 else 888 ifp->if_mtu = ifr->ifr_mtu; 889 break; 890 891 case SIOCSIFFLAGS: 892 if ((ifp->if_flags & IFF_UP) == 0 && 893 (ifp->if_flags & IFF_RUNNING) != 0) { 894 /* 895 * If interface is marked down and it is running, then 896 * stop it. 897 */ 898 sip_stop(sc, 1); 899 } else if ((ifp->if_flags & IFF_UP) != 0 && 900 (ifp->if_flags & IFF_RUNNING) == 0) { 901 /* 902 * If interfase it marked up and it is stopped, then 903 * start it. 904 */ 905 error = sip_init(sc); 906 } else if ((ifp->if_flags & IFF_UP) != 0) { 907 /* 908 * Reset the interface to pick up changes in any other 909 * flags that affect the hardware state. 910 */ 911 error = sip_init(sc); 912 } 913 break; 914 915 case SIOCADDMULTI: 916 case SIOCDELMULTI: 917 error = (cmd == SIOCADDMULTI) ? 918 ether_addmulti(ifr, &sc->sc_ethercom) : 919 ether_delmulti(ifr, &sc->sc_ethercom); 920 921 if (error == ENETRESET) { 922 /* 923 * Multicast list has changed; set the hardware filter 924 * accordingly. 925 */ 926 sip_set_filter(sc); 927 error = 0; 928 } 929 break; 930 931 case SIOCSIFMEDIA: 932 case SIOCGIFMEDIA: 933 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 934 break; 935 936 default: 937 error = EINVAL; 938 break; 939 } 940 941 /* Try to get more packets going. */ 942 sip_start(ifp); 943 944 splx(s); 945 return (error); 946 } 947 948 /* 949 * sip_intr: 950 * 951 * Interrupt service routine. 952 */ 953 int 954 sip_intr(arg) 955 void *arg; 956 { 957 struct sip_softc *sc = arg; 958 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 959 u_int32_t isr; 960 int handled = 0; 961 962 for (;;) { 963 /* Reading clears interrupt. */ 964 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 965 if ((isr & sc->sc_imr) == 0) 966 break; 967 968 handled = 1; 969 970 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 971 /* Grab any new packets. */ 972 sip_rxintr(sc); 973 974 if (isr & ISR_RXORN) { 975 printf("%s: receive FIFO overrun\n", 976 sc->sc_dev.dv_xname); 977 978 /* XXX adjust rx_drain_thresh? */ 979 } 980 981 if (isr & ISR_RXIDLE) { 982 printf("%s: receive ring overrun\n", 983 sc->sc_dev.dv_xname); 984 985 /* Get the receive process going again. */ 986 bus_space_write_4(sc->sc_st, sc->sc_sh, 987 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 988 bus_space_write_4(sc->sc_st, sc->sc_sh, 989 SIP_CR, CR_RXE); 990 } 991 } 992 993 if (isr & (ISR_TXURN|ISR_TXDESC)) { 994 /* Sweep up transmit descriptors. */ 995 sip_txintr(sc); 996 997 if (isr & ISR_TXURN) { 998 u_int32_t thresh; 999 1000 printf("%s: transmit FIFO underrun", 1001 sc->sc_dev.dv_xname); 1002 1003 thresh = sc->sc_tx_drain_thresh + 1; 1004 if (thresh <= TXCFG_DRTH && 1005 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1006 (sc->sc_tx_fill_thresh * 32))) { 1007 printf("; increasing Tx drain " 1008 "threshold to %u bytes\n", 1009 thresh * 32); 1010 sc->sc_tx_drain_thresh = thresh; 1011 (void) sip_init(sc); 1012 } else { 1013 (void) sip_init(sc); 1014 printf("\n"); 1015 } 1016 } 1017 } 1018 1019 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1020 if (isr & ISR_PAUSE_ST) { 1021 sc->sc_flags |= SIPF_PAUSED; 1022 ifp->if_flags |= IFF_OACTIVE; 1023 } 1024 if (isr & ISR_PAUSE_END) { 1025 sc->sc_flags &= ~SIPF_PAUSED; 1026 ifp->if_flags &= ~IFF_OACTIVE; 1027 } 1028 } 1029 1030 if (isr & ISR_HIBERR) { 1031 #define PRINTERR(bit, str) \ 1032 if (isr & (bit)) \ 1033 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1034 PRINTERR(ISR_DPERR, "parity error"); 1035 PRINTERR(ISR_SSERR, "system error"); 1036 PRINTERR(ISR_RMABT, "master abort"); 1037 PRINTERR(ISR_RTABT, "target abort"); 1038 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1039 (void) sip_init(sc); 1040 #undef PRINTERR 1041 } 1042 } 1043 1044 /* Try to get more packets going. */ 1045 sip_start(ifp); 1046 1047 return (handled); 1048 } 1049 1050 /* 1051 * sip_txintr: 1052 * 1053 * Helper; handle transmit interrupts. 1054 */ 1055 void 1056 sip_txintr(sc) 1057 struct sip_softc *sc; 1058 { 1059 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1060 struct sip_txsoft *txs; 1061 u_int32_t cmdsts; 1062 1063 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 /* 1067 * Go through our Tx list and free mbufs for those 1068 * frames which have been transmitted. 1069 */ 1070 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1071 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1072 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1073 1074 cmdsts = sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1075 if (cmdsts & CMDSTS_OWN) 1076 break; 1077 1078 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1079 1080 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1081 1082 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1083 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1084 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1085 m_freem(txs->txs_mbuf); 1086 txs->txs_mbuf = NULL; 1087 1088 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1089 1090 /* 1091 * Check for errors and collisions. 1092 */ 1093 if (cmdsts & 1094 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1095 if (ifp->if_flags & IFF_DEBUG) { 1096 if (CMDSTS_Tx_ED) 1097 printf("%s: excessive deferral\n", 1098 sc->sc_dev.dv_xname); 1099 if (CMDSTS_Tx_EC) { 1100 printf("%s: excessive collisions\n", 1101 sc->sc_dev.dv_xname); 1102 ifp->if_collisions += 16; 1103 } 1104 } 1105 } else { 1106 /* Packet was transmitted successfully. */ 1107 ifp->if_opackets++; 1108 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1109 } 1110 } 1111 1112 /* 1113 * If there are no more pending transmissions, cancel the watchdog 1114 * timer. 1115 */ 1116 if (txs == NULL) 1117 ifp->if_timer = 0; 1118 } 1119 1120 /* 1121 * sip_rxintr: 1122 * 1123 * Helper; handle receive interrupts. 1124 */ 1125 void 1126 sip_rxintr(sc) 1127 struct sip_softc *sc; 1128 { 1129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1130 struct ether_header *eh; 1131 struct sip_rxsoft *rxs; 1132 struct mbuf *m; 1133 u_int32_t cmdsts; 1134 int i, len; 1135 1136 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1137 rxs = &sc->sc_rxsoft[i]; 1138 1139 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1140 1141 cmdsts = sc->sc_rxdescs[i].sipd_cmdsts; 1142 1143 /* 1144 * NOTE: OWN is set if owned by _consumer_. We're the 1145 * consumer of the receive ring, so if the bit is clear, 1146 * we have processed all of the packets. 1147 */ 1148 if ((cmdsts & CMDSTS_OWN) == 0) { 1149 /* 1150 * We have processed all of the receive buffers. 1151 */ 1152 break; 1153 } 1154 1155 /* 1156 * If any collisions were seen on the wire, count one. 1157 */ 1158 if (cmdsts & CMDSTS_Rx_COL) 1159 ifp->if_collisions++; 1160 1161 /* 1162 * If an error occurred, update stats, clear the status 1163 * word, and leave the packet buffer in place. It will 1164 * simply be reused the next time the ring comes around. 1165 */ 1166 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1167 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1168 ifp->if_ierrors++; 1169 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1170 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1171 /* Receive overrun handled elsewhere. */ 1172 printf("%s: receive descriptor error\n", 1173 sc->sc_dev.dv_xname); 1174 } 1175 #define PRINTERR(bit, str) \ 1176 if (cmdsts & (bit)) \ 1177 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1178 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1179 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1180 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1181 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1182 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1183 #undef PRINTERR 1184 SIP_INIT_RXDESC(sc, i); 1185 continue; 1186 } 1187 1188 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1189 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1190 1191 /* 1192 * No errors; receive the packet. Note, the SiS 900 1193 * includes the CRC with every packet; trim it. 1194 */ 1195 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 1196 1197 #ifdef __NO_STRICT_ALIGNMENT 1198 /* 1199 * If the packet is small enough to fit in a 1200 * single header mbuf, allocate one and copy 1201 * the data into it. This greatly reduces 1202 * memory consumption when we receive lots 1203 * of small packets. 1204 * 1205 * Otherwise, we add a new buffer to the receive 1206 * chain. If this fails, we drop the packet and 1207 * recycle the old buffer. 1208 */ 1209 if (sip_copy_small != 0 && len <= MHLEN) { 1210 MGETHDR(m, M_DONTWAIT, MT_DATA); 1211 if (m == NULL) 1212 goto dropit; 1213 memcpy(mtod(m, caddr_t), 1214 mtod(rxs->rxs_mbuf, caddr_t), len); 1215 SIP_INIT_RXDESC(sc, i); 1216 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1217 rxs->rxs_dmamap->dm_mapsize, 1218 BUS_DMASYNC_PREREAD); 1219 } else { 1220 m = rxs->rxs_mbuf; 1221 if (sip_add_rxbuf(sc, i) != 0) { 1222 dropit: 1223 ifp->if_ierrors++; 1224 SIP_INIT_RXDESC(sc, i); 1225 bus_dmamap_sync(sc->sc_dmat, 1226 rxs->rxs_dmamap, 0, 1227 rxs->rxs_dmamap->dm_mapsize, 1228 BUS_DMASYNC_PREREAD); 1229 continue; 1230 } 1231 } 1232 #else 1233 /* 1234 * The SiS 900's receive buffers must be 4-byte aligned. 1235 * But this means that the data after the Ethernet header 1236 * is misaligned. We must allocate a new buffer and 1237 * copy the data, shifted forward 2 bytes. 1238 */ 1239 MGETHDR(m, M_DONTWAIT, MT_DATA); 1240 if (m == NULL) { 1241 dropit: 1242 ifp->if_ierrors++; 1243 SIP_INIT_RXDESC(sc, i); 1244 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1245 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1246 continue; 1247 } 1248 if (len > (MHLEN - 2)) { 1249 MCLGET(m, M_DONTWAIT); 1250 if ((m->m_flags & M_EXT) == 0) { 1251 m_freem(m); 1252 goto dropit; 1253 } 1254 } 1255 m->m_data += 2; 1256 1257 /* 1258 * Note that we use clusters for incoming frames, so the 1259 * buffer is virtually contiguous. 1260 */ 1261 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1262 1263 /* Allow the receive descriptor to continue using its mbuf. */ 1264 SIP_INIT_RXDESC(sc, i); 1265 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1266 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1267 #endif /* __NO_STRICT_ALIGNMENT */ 1268 1269 ifp->if_ipackets++; 1270 eh = mtod(m, struct ether_header *); 1271 m->m_pkthdr.rcvif = ifp; 1272 m->m_pkthdr.len = m->m_len = len; 1273 1274 #if NBPFILTER > 0 1275 /* 1276 * Pass this up to any BPF listeners, but only 1277 * pass if up the stack if it's for us. 1278 */ 1279 if (ifp->if_bpf) { 1280 bpf_mtap(ifp->if_bpf, m); 1281 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1282 (cmdsts & CMDSTS_Rx_DEST) == CMDSTS_Rx_DEST_REJ) { 1283 m_freem(m); 1284 continue; 1285 } 1286 } 1287 #endif /* NBPFILTER > 0 */ 1288 1289 /* Pass it on. */ 1290 (*ifp->if_input)(ifp, m); 1291 } 1292 1293 /* Update the receive pointer. */ 1294 sc->sc_rxptr = i; 1295 } 1296 1297 /* 1298 * sip_tick: 1299 * 1300 * One second timer, used to tick the MII. 1301 */ 1302 void 1303 sip_tick(arg) 1304 void *arg; 1305 { 1306 struct sip_softc *sc = arg; 1307 int s; 1308 1309 s = splnet(); 1310 mii_tick(&sc->sc_mii); 1311 splx(s); 1312 1313 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1314 } 1315 1316 /* 1317 * sip_reset: 1318 * 1319 * Perform a soft reset on the SiS 900. 1320 */ 1321 void 1322 sip_reset(sc) 1323 struct sip_softc *sc; 1324 { 1325 bus_space_tag_t st = sc->sc_st; 1326 bus_space_handle_t sh = sc->sc_sh; 1327 int i; 1328 1329 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1330 1331 for (i = 0; i < 1000; i++) { 1332 if ((bus_space_read_4(st, sh, SIP_ISR) & 1333 (ISR_TXRCMP|ISR_RXRCMP)) == (ISR_TXRCMP|ISR_RXRCMP)) 1334 return; 1335 delay(2); 1336 } 1337 1338 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1339 } 1340 1341 /* 1342 * sip_init: 1343 * 1344 * Initialize the interface. Must be called at splnet(). 1345 */ 1346 int 1347 sip_init(sc) 1348 struct sip_softc *sc; 1349 { 1350 bus_space_tag_t st = sc->sc_st; 1351 bus_space_handle_t sh = sc->sc_sh; 1352 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1353 struct sip_txsoft *txs; 1354 struct sip_rxsoft *rxs; 1355 struct sip_desc *sipd; 1356 u_int32_t cfg; 1357 int i, error = 0; 1358 1359 /* 1360 * Cancel any pending I/O. 1361 */ 1362 sip_stop(sc, 0); 1363 1364 /* 1365 * Reset the chip to a known state. 1366 */ 1367 sip_reset(sc); 1368 1369 /* 1370 * Initialize the transmit descriptor ring. 1371 */ 1372 for (i = 0; i < SIP_NTXDESC; i++) { 1373 sipd = &sc->sc_txdescs[i]; 1374 memset(sipd, 0, sizeof(struct sip_desc)); 1375 sipd->sipd_link = SIP_CDTXADDR(sc, SIP_NEXTTX(i)); 1376 } 1377 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1378 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1379 sc->sc_txfree = SIP_NTXDESC; 1380 sc->sc_txnext = 0; 1381 1382 /* 1383 * Initialize the transmit job descriptors. 1384 */ 1385 SIMPLEQ_INIT(&sc->sc_txfreeq); 1386 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1387 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1388 txs = &sc->sc_txsoft[i]; 1389 txs->txs_mbuf = NULL; 1390 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1391 } 1392 1393 /* 1394 * Initialize the receive descriptor and receive job 1395 * descriptor rings. 1396 */ 1397 for (i = 0; i < SIP_NRXDESC; i++) { 1398 rxs = &sc->sc_rxsoft[i]; 1399 if (rxs->rxs_mbuf == NULL) { 1400 if ((error = sip_add_rxbuf(sc, i)) != 0) { 1401 printf("%s: unable to allocate or map rx " 1402 "buffer %d, error = %d\n", 1403 sc->sc_dev.dv_xname, i, error); 1404 /* 1405 * XXX Should attempt to run with fewer receive 1406 * XXX buffers instead of just failing. 1407 */ 1408 sip_rxdrain(sc); 1409 goto out; 1410 } 1411 } 1412 } 1413 sc->sc_rxptr = 0; 1414 1415 /* 1416 * Initialize the configuration register: aggressive PCI 1417 * bus request algorithm, default backoff, default OW timer, 1418 * default parity error detection. 1419 */ 1420 cfg = 0; 1421 #if BYTE_ORDER == BIG_ENDIAN 1422 /* 1423 * ...descriptors in big-endian mode. 1424 */ 1425 cfg |= CFG_BEM; 1426 #endif 1427 bus_space_write_4(st, sh, SIP_CFG, cfg); 1428 1429 /* 1430 * Initialize the transmit fill and drain thresholds if 1431 * we have never done so. 1432 */ 1433 if (sc->sc_tx_fill_thresh == 0) { 1434 /* 1435 * XXX This value should be tuned. This is the 1436 * minimum (32 bytes), and we may be able to 1437 * improve performance by increasing it. 1438 */ 1439 sc->sc_tx_fill_thresh = 1; 1440 } 1441 if (sc->sc_tx_drain_thresh == 0) { 1442 /* 1443 * Start at a drain threshold of 128 bytes. We will 1444 * increase it if a DMA underrun occurs. 1445 * 1446 * XXX The minimum value of this variable should be 1447 * tuned. We may be able to improve performance 1448 * by starting with a lower value. That, however, 1449 * may trash the first few outgoing packets if the 1450 * PCI bus is saturated. 1451 */ 1452 sc->sc_tx_drain_thresh = 4; 1453 } 1454 1455 /* 1456 * Initialize the prototype TXCFG register. 1457 */ 1458 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1459 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1460 sc->sc_tx_drain_thresh; 1461 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1462 1463 /* 1464 * Initialize the receive drain threshold if we have never 1465 * done so. 1466 */ 1467 if (sc->sc_rx_drain_thresh == 0) { 1468 /* 1469 * XXX This value should be tuned. This is set to the 1470 * maximum of 248 bytes, and we may be able to improve 1471 * performance by decreasing it (although we should never 1472 * set this value lower than 2; 14 bytes are required to 1473 * filter the packet). 1474 */ 1475 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1476 } 1477 1478 /* 1479 * Initialize the prototype RXCFG register. 1480 */ 1481 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1482 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1483 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1484 1485 /* Set up the receive filter. */ 1486 sip_set_filter(sc); 1487 1488 /* 1489 * Give the transmit and receive rings to the chip. 1490 */ 1491 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1492 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1493 1494 /* 1495 * Initialize the interrupt mask. 1496 */ 1497 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1498 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1499 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1500 1501 /* 1502 * Set the current media. Do this after initializing the prototype 1503 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1504 * control. 1505 */ 1506 mii_mediachg(&sc->sc_mii); 1507 1508 /* 1509 * Enable interrupts. 1510 */ 1511 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1512 1513 /* 1514 * Start the transmit and receive processes. 1515 */ 1516 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1517 1518 /* 1519 * Start the one second MII clock. 1520 */ 1521 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1522 1523 /* 1524 * ...all done! 1525 */ 1526 ifp->if_flags |= IFF_RUNNING; 1527 ifp->if_flags &= ~IFF_OACTIVE; 1528 1529 out: 1530 if (error) 1531 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1532 return (error); 1533 } 1534 1535 /* 1536 * sip_drain: 1537 * 1538 * Drain the receive queue. 1539 */ 1540 void 1541 sip_rxdrain(sc) 1542 struct sip_softc *sc; 1543 { 1544 struct sip_rxsoft *rxs; 1545 int i; 1546 1547 for (i = 0; i < SIP_NRXDESC; i++) { 1548 rxs = &sc->sc_rxsoft[i]; 1549 if (rxs->rxs_mbuf != NULL) { 1550 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1551 m_freem(rxs->rxs_mbuf); 1552 rxs->rxs_mbuf = NULL; 1553 } 1554 } 1555 } 1556 1557 /* 1558 * sip_stop: 1559 * 1560 * Stop transmission on the interface. 1561 */ 1562 void 1563 sip_stop(sc, drain) 1564 struct sip_softc *sc; 1565 { 1566 bus_space_tag_t st = sc->sc_st; 1567 bus_space_handle_t sh = sc->sc_sh; 1568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1569 struct sip_txsoft *txs; 1570 u_int32_t cmdsts = 0; /* DEBUG */ 1571 1572 /* 1573 * Stop the one second clock. 1574 */ 1575 callout_stop(&sc->sc_tick_ch); 1576 1577 /* Down the MII. */ 1578 mii_down(&sc->sc_mii); 1579 1580 /* 1581 * Disable interrupts. 1582 */ 1583 bus_space_write_4(st, sh, SIP_IER, 0); 1584 1585 /* 1586 * Stop receiver and transmitter. 1587 */ 1588 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1589 1590 /* 1591 * Release any queued transmit buffers. 1592 */ 1593 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1594 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1595 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1596 (sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts & 1597 CMDSTS_INTR) == 0) 1598 printf("%s: sip_stop: last descriptor does not " 1599 "have INTR bit set\n", sc->sc_dev.dv_xname); 1600 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1601 #ifdef DIAGNOSTIC 1602 if (txs->txs_mbuf == NULL) { 1603 printf("%s: dirty txsoft with no mbuf chain\n", 1604 sc->sc_dev.dv_xname); 1605 panic("sip_stop"); 1606 } 1607 #endif 1608 cmdsts |= /* DEBUG */ 1609 sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1610 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1611 m_freem(txs->txs_mbuf); 1612 txs->txs_mbuf = NULL; 1613 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1614 } 1615 1616 if (drain) { 1617 /* 1618 * Release the receive buffers. 1619 */ 1620 sip_rxdrain(sc); 1621 } 1622 1623 /* 1624 * Mark the interface down and cancel the watchdog timer. 1625 */ 1626 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1627 ifp->if_timer = 0; 1628 1629 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1630 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1631 printf("%s: sip_stop: no INTR bits set in dirty tx " 1632 "descriptors\n", sc->sc_dev.dv_xname); 1633 } 1634 1635 /* 1636 * sip_read_eeprom: 1637 * 1638 * Read data from the serial EEPROM. 1639 */ 1640 void 1641 sip_read_eeprom(sc, word, wordcnt, data) 1642 struct sip_softc *sc; 1643 int word, wordcnt; 1644 u_int16_t *data; 1645 { 1646 bus_space_tag_t st = sc->sc_st; 1647 bus_space_handle_t sh = sc->sc_sh; 1648 u_int16_t reg; 1649 int i, x; 1650 1651 for (i = 0; i < wordcnt; i++) { 1652 /* Send CHIP SELECT. */ 1653 reg = EROMAR_EECS; 1654 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1655 1656 /* Shift in the READ opcode. */ 1657 for (x = 3; x > 0; x--) { 1658 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1659 reg |= EROMAR_EEDI; 1660 else 1661 reg &= ~EROMAR_EEDI; 1662 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1663 bus_space_write_4(st, sh, SIP_EROMAR, 1664 reg | EROMAR_EESK); 1665 delay(4); 1666 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1667 delay(4); 1668 } 1669 1670 /* Shift in address. */ 1671 for (x = 6; x > 0; x--) { 1672 if ((word + i) & (1 << (x - 1))) 1673 reg |= EROMAR_EEDI; 1674 else 1675 reg &= ~EROMAR_EEDI; 1676 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1677 bus_space_write_4(st, sh, SIP_EROMAR, 1678 reg | EROMAR_EESK); 1679 delay(4); 1680 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1681 delay(4); 1682 } 1683 1684 /* Shift out data. */ 1685 reg = EROMAR_EECS; 1686 data[i] = 0; 1687 for (x = 16; x > 0; x--) { 1688 bus_space_write_4(st, sh, SIP_EROMAR, 1689 reg | EROMAR_EESK); 1690 delay(4); 1691 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1692 data[i] |= (1 << (x - 1)); 1693 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1694 } 1695 1696 /* Clear CHIP SELECT. */ 1697 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1698 delay(4); 1699 } 1700 } 1701 1702 /* 1703 * sip_add_rxbuf: 1704 * 1705 * Add a receive buffer to the indicated descriptor. 1706 */ 1707 int 1708 sip_add_rxbuf(sc, idx) 1709 struct sip_softc *sc; 1710 int idx; 1711 { 1712 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1713 struct mbuf *m; 1714 int error; 1715 1716 MGETHDR(m, M_DONTWAIT, MT_DATA); 1717 if (m == NULL) 1718 return (ENOBUFS); 1719 1720 MCLGET(m, M_DONTWAIT); 1721 if ((m->m_flags & M_EXT) == 0) { 1722 m_freem(m); 1723 return (ENOBUFS); 1724 } 1725 1726 if (rxs->rxs_mbuf != NULL) 1727 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1728 1729 rxs->rxs_mbuf = m; 1730 1731 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1732 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1733 if (error) { 1734 printf("%s: can't load rx DMA map %d, error = %d\n", 1735 sc->sc_dev.dv_xname, idx, error); 1736 panic("sip_add_rxbuf"); /* XXX */ 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1740 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1741 1742 SIP_INIT_RXDESC(sc, idx); 1743 1744 return (0); 1745 } 1746 1747 /* 1748 * sip_set_filter: 1749 * 1750 * Set up the receive filter. 1751 */ 1752 void 1753 sip_set_filter(sc) 1754 struct sip_softc *sc; 1755 { 1756 bus_space_tag_t st = sc->sc_st; 1757 bus_space_handle_t sh = sc->sc_sh; 1758 struct ethercom *ec = &sc->sc_ethercom; 1759 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1760 struct ether_multi *enm; 1761 u_int8_t *cp; 1762 struct ether_multistep step; 1763 u_int32_t crc, mchash[8]; 1764 1765 /* 1766 * Initialize the prototype RFCR. 1767 */ 1768 sc->sc_rfcr = RFCR_RFEN; 1769 if (ifp->if_flags & IFF_BROADCAST) 1770 sc->sc_rfcr |= RFCR_AAB; 1771 if (ifp->if_flags & IFF_PROMISC) { 1772 sc->sc_rfcr |= RFCR_AAP; 1773 goto allmulti; 1774 } 1775 1776 /* 1777 * Set up the multicast address filter by passing all multicast 1778 * addresses through a CRC generator, and then using the high-order 1779 * 6 bits as an index into the 128 bit multicast hash table (only 1780 * the lower 16 bits of each 32 bit multicast hash register are 1781 * valid). The high order bits select the register, while the 1782 * rest of the bits select the bit within the register. 1783 */ 1784 1785 memset(mchash, 0, sizeof(mchash)); 1786 1787 ETHER_FIRST_MULTI(step, ec, enm); 1788 while (enm != NULL) { 1789 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1790 /* 1791 * We must listen to a range of multicast addresses. 1792 * For now, just accept all multicasts, rather than 1793 * trying to set only those filter bits needed to match 1794 * the range. (At this time, the only use of address 1795 * ranges is for IP multicast routing, for which the 1796 * range is big enough to require all bits set.) 1797 */ 1798 goto allmulti; 1799 } 1800 1801 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1802 1803 /* Just want the 7 most significant bits. */ 1804 crc >>= 25; 1805 1806 /* Set the corresponding bit in the hash table. */ 1807 mchash[crc >> 4] |= 1 << (crc & 0xf); 1808 1809 ETHER_NEXT_MULTI(step, enm); 1810 } 1811 1812 ifp->if_flags &= ~IFF_ALLMULTI; 1813 goto setit; 1814 1815 allmulti: 1816 ifp->if_flags |= IFF_ALLMULTI; 1817 sc->sc_rfcr |= RFCR_AAM; 1818 1819 setit: 1820 #define FILTER_EMIT(addr, data) \ 1821 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1822 bus_space_write_4(st, sh, SIP_RFDR, (data)) 1823 1824 /* 1825 * Disable receive filter, and program the node address. 1826 */ 1827 cp = LLADDR(ifp->if_sadl); 1828 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1829 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1830 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1831 1832 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1833 /* 1834 * Program the multicast hash table. 1835 */ 1836 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1837 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1838 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1839 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1840 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1841 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1842 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1843 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1844 } 1845 #undef FILTER_EMIT 1846 1847 /* 1848 * Re-enable the receiver filter. 1849 */ 1850 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1851 } 1852 1853 /* 1854 * sip_mii_readreg: [mii interface function] 1855 * 1856 * Read a PHY register on the MII. 1857 */ 1858 int 1859 sip_mii_readreg(self, phy, reg) 1860 struct device *self; 1861 int phy, reg; 1862 { 1863 struct sip_softc *sc = (struct sip_softc *) self; 1864 u_int32_t enphy; 1865 1866 /* 1867 * The SiS 900 has only an internal PHY on the MII. Only allow 1868 * MII address 0. 1869 */ 1870 if (sc->sc_model == PCI_PRODUCT_SIS_900 && phy != 0) 1871 return (0); 1872 1873 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1874 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 1875 ENPHY_RWCMD | ENPHY_ACCESS); 1876 do { 1877 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1878 } while (enphy & ENPHY_ACCESS); 1879 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 1880 } 1881 1882 /* 1883 * sip_mii_writereg: [mii interface function] 1884 * 1885 * Write a PHY register on the MII. 1886 */ 1887 void 1888 sip_mii_writereg(self, phy, reg, val) 1889 struct device *self; 1890 int phy, reg, val; 1891 { 1892 struct sip_softc *sc = (struct sip_softc *) self; 1893 u_int32_t enphy; 1894 1895 /* 1896 * The SiS 900 has only an internal PHY on the MII. Only allow 1897 * MII address 0. 1898 */ 1899 if (sc->sc_model == PCI_PRODUCT_SIS_900 && phy != 0) 1900 return; 1901 1902 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1903 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 1904 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 1905 do { 1906 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1907 } while (enphy & ENPHY_ACCESS); 1908 } 1909 1910 /* 1911 * sip_mii_statchg: [mii interface function] 1912 * 1913 * Callback from MII layer when media changes. 1914 */ 1915 void 1916 sip_mii_statchg(self) 1917 struct device *self; 1918 { 1919 struct sip_softc *sc = (struct sip_softc *) self; 1920 u_int32_t flowctl; 1921 1922 /* 1923 * Update TXCFG for full-duplex operation. 1924 */ 1925 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1926 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 1927 else 1928 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 1929 1930 /* 1931 * Update RXCFG for full-duplex or loopback. 1932 */ 1933 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 1934 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 1935 sc->sc_rxcfg |= RXCFG_ATX; 1936 else 1937 sc->sc_rxcfg &= ~RXCFG_ATX; 1938 1939 /* 1940 * Update IMR for use of 802.3x flow control. 1941 */ 1942 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 1943 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 1944 flowctl = FLOWCTL_FLOWEN; 1945 } else { 1946 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 1947 flowctl = 0; 1948 } 1949 1950 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 1951 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 1952 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 1953 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 1954 } 1955 1956 /* 1957 * sip_mediastatus: [ifmedia interface function] 1958 * 1959 * Get the current interface media status. 1960 */ 1961 void 1962 sip_mediastatus(ifp, ifmr) 1963 struct ifnet *ifp; 1964 struct ifmediareq *ifmr; 1965 { 1966 struct sip_softc *sc = ifp->if_softc; 1967 1968 mii_pollstat(&sc->sc_mii); 1969 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1970 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1971 } 1972 1973 /* 1974 * sip_mediachange: [ifmedia interface function] 1975 * 1976 * Set hardware to newly-selected media. 1977 */ 1978 int 1979 sip_mediachange(ifp) 1980 struct ifnet *ifp; 1981 { 1982 struct sip_softc *sc = ifp->if_softc; 1983 1984 if (ifp->if_flags & IFF_UP) 1985 mii_mediachg(&sc->sc_mii); 1986 return (0); 1987 } 1988