1 /* $NetBSD: if_sip.c,v 1.2 1999/08/03 17:25:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Silicon Integrated Systems SiS900 10/100 PCI 34 * Ethernet controller. 35 * 36 * Written by Jason R. Thorpe for Network Computer, Inc. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/queue.h> 53 54 #include <vm/vm.h> /* for PAGE_SIZE */ 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #endif 69 70 #ifdef NS 71 #include <netns/ns.h> 72 #include <netns/ns_if.h> 73 #endif 74 75 #include <machine/bus.h> 76 #include <machine/intr.h> 77 78 #include <dev/mii/miivar.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_sipreg.h> 85 86 /* 87 * Devices supported by this driver. 88 */ 89 const struct sip_product { 90 pci_vendor_id_t sip_vendor; 91 pci_product_id_t sip_product; 92 const char *sip_name; 93 } sip_products[] = { 94 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 95 "SiS 900 10/100 Ethernet" }, 96 97 { 0, 0, 98 NULL }, 99 }; 100 101 /* 102 * Transmit descriptor list size. This is arbitrary, but allocate 103 * enough descriptors for 64 pending transmissions, and 16 segments 104 * per packet. This MUST work out to a power of 2. 105 */ 106 #define SIP_NTXSEGS 16 107 108 #define SIP_TXQUEUELEN 64 109 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 110 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 111 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 112 113 /* 114 * Receive descriptor list size. We have one Rx buffer per incoming 115 * packet, so this logic is a little simpler. 116 */ 117 #define SIP_NRXDESC 64 118 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 119 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 120 121 /* 122 * Control structures are DMA'd to the SiS900 chip. We allocate them in 123 * a single clump that maps to a single DMA segment to make several things 124 * easier. 125 */ 126 struct sip_control_data { 127 /* 128 * The transmit descriptors. 129 */ 130 struct sip_desc scd_txdescs[SIP_NTXDESC]; 131 132 /* 133 * The receive descriptors. 134 */ 135 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 136 }; 137 138 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 139 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 140 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 141 142 /* 143 * Software state for transmit jobs. 144 */ 145 struct sip_txsoft { 146 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 147 bus_dmamap_t txs_dmamap; /* our DMA map */ 148 int txs_firstdesc; /* first descriptor in packet */ 149 int txs_lastdesc; /* last descriptor in packet */ 150 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 151 }; 152 153 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 154 155 /* 156 * Software state for receive jobs. 157 */ 158 struct sip_rxsoft { 159 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 160 bus_dmamap_t rxs_dmamap; /* our DMA map */ 161 }; 162 163 /* 164 * Software state per device. 165 */ 166 struct sip_softc { 167 struct device sc_dev; /* generic device information */ 168 bus_space_tag_t sc_st; /* bus space tag */ 169 bus_space_handle_t sc_sh; /* bus space handle */ 170 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 171 struct ethercom sc_ethercom; /* ethernet common data */ 172 void *sc_sdhook; /* shutdown hook */ 173 174 void *sc_ih; /* interrupt cookie */ 175 176 struct mii_data sc_mii; /* MII/media information */ 177 178 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 179 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 180 181 /* 182 * Software state for transmit and receive descriptors. 183 */ 184 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 185 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 186 187 /* 188 * Control data structures. 189 */ 190 struct sip_control_data *sc_control_data; 191 #define sc_txdescs sc_control_data->scd_txdescs 192 #define sc_rxdescs sc_control_data->scd_rxdescs 193 194 u_int32_t sc_txcfg; /* prototype TXCFG register */ 195 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 196 u_int32_t sc_imr; /* prototype IMR register */ 197 u_int32_t sc_rfcr; /* prototype RFCR register */ 198 199 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 200 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 201 202 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 203 204 int sc_flags; /* misc. flags; see below */ 205 206 int sc_txfree; /* number of free Tx descriptors */ 207 int sc_txnext; /* next ready Tx descriptor */ 208 209 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 210 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 211 212 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 213 }; 214 215 /* sc_flags */ 216 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 217 218 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 219 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 220 221 #define SIP_CDTXSYNC(sc, x, n, ops) \ 222 do { \ 223 int __x, __n; \ 224 \ 225 __x = (x); \ 226 __n = (n); \ 227 \ 228 /* If it will wrap around, sync to the end of the ring. */ \ 229 if ((__x + __n) > SIP_NTXDESC) { \ 230 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 231 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 232 (SIP_NTXDESC - __x), (ops)); \ 233 __n -= (SIP_NTXDESC - __x); \ 234 __x = 0; \ 235 } \ 236 \ 237 /* Now sync whatever is left. */ \ 238 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 239 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 240 } while (0) 241 242 #define SIP_CDRXSYNC(sc, x, ops) \ 243 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 244 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 245 246 /* 247 * Note we rely on MCLBYTES being a power of two below. 248 */ 249 #define SIP_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 252 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 253 \ 254 __sipd->sipd_link = SIP_CDRXADDR((sc), SIP_NEXTRX((x))); \ 255 __sipd->sipd_bufptr = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 256 __sipd->sipd_cmdsts = CMDSTS_INTR | \ 257 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK); \ 258 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 259 } while (0) 260 261 void sip_start __P((struct ifnet *)); 262 void sip_watchdog __P((struct ifnet *)); 263 int sip_ioctl __P((struct ifnet *, u_long, caddr_t)); 264 265 void sip_shutdown __P((void *)); 266 267 void sip_reset __P((struct sip_softc *)); 268 int sip_init __P((struct sip_softc *)); 269 void sip_stop __P((struct sip_softc *, int)); 270 void sip_rxdrain __P((struct sip_softc *)); 271 int sip_add_rxbuf __P((struct sip_softc *, int)); 272 void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *)); 273 void sip_set_filter __P((struct sip_softc *)); 274 void sip_tick __P((void *)); 275 276 int sip_intr __P((void *)); 277 void sip_txintr __P((struct sip_softc *)); 278 void sip_rxintr __P((struct sip_softc *)); 279 280 int sip_mii_readreg __P((struct device *, int, int)); 281 void sip_mii_writereg __P((struct device *, int, int, int)); 282 void sip_mii_statchg __P((struct device *)); 283 284 int sip_mediachange __P((struct ifnet *)); 285 void sip_mediastatus __P((struct ifnet *, struct ifmediareq *)); 286 287 int sip_match __P((struct device *, struct cfdata *, void *)); 288 void sip_attach __P((struct device *, struct device *, void *)); 289 290 int sip_copy_small = 0; 291 292 struct cfattach sip_ca = { 293 sizeof(struct sip_softc), sip_match, sip_attach, 294 }; 295 296 const struct sip_product *sip_lookup __P((const struct pci_attach_args *)); 297 298 const struct sip_product * 299 sip_lookup(pa) 300 const struct pci_attach_args *pa; 301 { 302 const struct sip_product *sip; 303 304 for (sip = sip_products; sip->sip_name != NULL; sip++) { 305 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 306 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 307 return (sip); 308 } 309 return (NULL); 310 } 311 312 int 313 sip_match(parent, cf, aux) 314 struct device *parent; 315 struct cfdata *cf; 316 void *aux; 317 { 318 struct pci_attach_args *pa = aux; 319 320 if (sip_lookup(pa) != NULL) 321 return (1); 322 323 return (0); 324 } 325 326 void 327 sip_attach(parent, self, aux) 328 struct device *parent, *self; 329 void *aux; 330 { 331 struct sip_softc *sc = (struct sip_softc *) self; 332 struct pci_attach_args *pa = aux; 333 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 334 pci_chipset_tag_t pc = pa->pa_pc; 335 pci_intr_handle_t ih; 336 const char *intrstr = NULL; 337 bus_space_tag_t iot, memt; 338 bus_space_handle_t ioh, memh; 339 bus_dma_segment_t seg; 340 int ioh_valid, memh_valid; 341 int i, rseg, error; 342 const struct sip_product *sip; 343 pcireg_t pmode; 344 u_int16_t enaddr[ETHER_ADDR_LEN / 2]; 345 346 sip = sip_lookup(pa); 347 if (sip == NULL) { 348 printf("\n"); 349 panic("sip_attach: impossible"); 350 } 351 352 printf(": %s\n", sip->sip_name); 353 354 /* 355 * Map the device. 356 */ 357 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 358 PCI_MAPREG_TYPE_IO, 0, 359 &iot, &ioh, NULL, NULL) == 0); 360 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 361 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 362 &memt, &memh, NULL, NULL) == 0); 363 364 if (memh_valid) { 365 sc->sc_st = memt; 366 sc->sc_sh = memh; 367 } else if (ioh_valid) { 368 sc->sc_st = iot; 369 sc->sc_sh = ioh; 370 } else { 371 printf("%s: unable to map device registers\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } 375 376 sc->sc_dmat = pa->pa_dmat; 377 378 /* Enable bus mastering. */ 379 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 380 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 381 PCI_COMMAND_MASTER_ENABLE); 382 383 /* Get it out of power save mode if needed. */ 384 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 0, 0)) { 385 pmode = pci_conf_read(pc, pa->pa_tag, SIP_PCI_CFGPMCSR) & 0x3; 386 if (pmode == 3) { 387 /* 388 * The card has lost all configuration data in 389 * this state, so punt. 390 */ 391 printf("%s: unable to wake up from power state D3\n", 392 sc->sc_dev.dv_xname); 393 return; 394 } 395 if (pmode != 0) { 396 printf("%s: waking up from power state D%d\n", 397 sc->sc_dev.dv_xname, pmode); 398 pci_conf_write(pc, pa->pa_tag, SIP_PCI_CFGPMCSR, 0); 399 } 400 } 401 402 /* 403 * Map and establish our interrupt. 404 */ 405 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 406 pa->pa_intrline, &ih)) { 407 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 408 return; 409 } 410 intrstr = pci_intr_string(pc, ih); 411 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 412 if (sc->sc_ih == NULL) { 413 printf("%s: unable to establish interrupt", 414 sc->sc_dev.dv_xname); 415 if (intrstr != NULL) 416 printf(" at %s", intrstr); 417 printf("\n"); 418 return; 419 } 420 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 421 422 SIMPLEQ_INIT(&sc->sc_txfreeq); 423 SIMPLEQ_INIT(&sc->sc_txdirtyq); 424 425 /* 426 * Allocate the control data structures, and create and load the 427 * DMA map for it. 428 */ 429 if ((error = bus_dmamem_alloc(sc->sc_dmat, 430 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 431 0)) != 0) { 432 printf("%s: unable to allocate control data, error = %d\n", 433 sc->sc_dev.dv_xname, error); 434 goto fail_0; 435 } 436 437 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 438 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 439 BUS_DMA_COHERENT)) != 0) { 440 printf("%s: unable to map control data, error = %d\n", 441 sc->sc_dev.dv_xname, error); 442 goto fail_1; 443 } 444 445 if ((error = bus_dmamap_create(sc->sc_dmat, 446 sizeof(struct sip_control_data), 1, 447 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 448 printf("%s: unable to create control data DMA map, " 449 "error = %d\n", sc->sc_dev.dv_xname, error); 450 goto fail_2; 451 } 452 453 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 454 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 455 0)) != 0) { 456 printf("%s: unable to load control data DMA map, error = %d\n", 457 sc->sc_dev.dv_xname, error); 458 goto fail_3; 459 } 460 461 /* 462 * Create the transmit buffer DMA maps. 463 */ 464 for (i = 0; i < SIP_TXQUEUELEN; i++) { 465 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 466 SIP_NTXSEGS, MCLBYTES, 0, 0, 467 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 468 printf("%s: unable to create tx DMA map %d, " 469 "error = %d\n", sc->sc_dev.dv_xname, i, error); 470 goto fail_4; 471 } 472 } 473 474 /* 475 * Create the receive buffer DMA maps. 476 */ 477 for (i = 0; i < SIP_NRXDESC; i++) { 478 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 479 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 480 printf("%s: unable to create rx DMA map %d, " 481 "error = %d\n", sc->sc_dev.dv_xname, i, error); 482 goto fail_5; 483 } 484 sc->sc_rxsoft[i].rxs_mbuf = NULL; 485 } 486 487 /* 488 * Reset the chip to a known state. 489 */ 490 sip_reset(sc); 491 492 /* 493 * Read the Ethernet address from the EEPROM. 494 */ 495 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 496 sizeof(enaddr) / sizeof(enaddr[0]), enaddr); 497 498 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 499 ether_sprintf((u_int8_t *)enaddr)); 500 501 /* 502 * Initialize our media structures and probe the MII. 503 */ 504 sc->sc_mii.mii_ifp = ifp; 505 sc->sc_mii.mii_readreg = sip_mii_readreg; 506 sc->sc_mii.mii_writereg = sip_mii_writereg; 507 sc->sc_mii.mii_statchg = sip_mii_statchg; 508 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 509 sip_mediastatus); 510 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 511 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 512 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 513 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 514 } else 515 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 516 517 ifp = &sc->sc_ethercom.ec_if; 518 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 519 ifp->if_softc = sc; 520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 521 ifp->if_ioctl = sip_ioctl; 522 ifp->if_start = sip_start; 523 ifp->if_watchdog = sip_watchdog; 524 525 /* 526 * Attach the interface. 527 */ 528 if_attach(ifp); 529 ether_ifattach(ifp, (u_int8_t *)enaddr); 530 #if NBPFILTER > 0 531 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 532 sizeof(struct ether_header)); 533 #endif 534 535 /* 536 * Make sure the interface is shutdown during reboot. 537 */ 538 sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc); 539 if (sc->sc_sdhook == NULL) 540 printf("%s: WARNING: unable to establish shutdown hook\n", 541 sc->sc_dev.dv_xname); 542 return; 543 544 /* 545 * Free any resources we've allocated during the failed attach 546 * attempt. Do this in reverse order and fall through. 547 */ 548 fail_5: 549 for (i = 0; i < SIP_NRXDESC; i++) { 550 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 551 bus_dmamap_destroy(sc->sc_dmat, 552 sc->sc_rxsoft[i].rxs_dmamap); 553 } 554 fail_4: 555 for (i = 0; i < SIP_TXQUEUELEN; i++) { 556 if (sc->sc_txsoft[i].txs_dmamap != NULL) 557 bus_dmamap_destroy(sc->sc_dmat, 558 sc->sc_txsoft[i].txs_dmamap); 559 } 560 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 561 fail_3: 562 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 563 fail_2: 564 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 565 sizeof(struct sip_control_data)); 566 fail_1: 567 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 568 fail_0: 569 return; 570 } 571 572 /* 573 * sip_shutdown: 574 * 575 * Make sure the interface is stopped at reboot time. 576 */ 577 void 578 sip_shutdown(arg) 579 void *arg; 580 { 581 struct sip_softc *sc = arg; 582 583 sip_stop(sc, 1); 584 } 585 586 /* 587 * sip_start: [ifnet interface function] 588 * 589 * Start packet transmission on the interface. 590 */ 591 void 592 sip_start(ifp) 593 struct ifnet *ifp; 594 { 595 struct sip_softc *sc = ifp->if_softc; 596 struct mbuf *m0, *m; 597 struct sip_txsoft *txs; 598 bus_dmamap_t dmamap; 599 int error, firsttx, nexttx, lasttx, ofree, seg; 600 601 /* 602 * If we've been told to pause, don't transmit any more packets. 603 */ 604 if (sc->sc_flags & SIPF_PAUSED) 605 ifp->if_flags |= IFF_OACTIVE; 606 607 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 608 return; 609 610 /* 611 * Remember the previous number of free descriptors and 612 * the first descriptor we'll use. 613 */ 614 ofree = sc->sc_txfree; 615 firsttx = sc->sc_txnext; 616 617 /* 618 * Loop through the send queue, setting up transmit descriptors 619 * until we drain the queue, or use up all available transmit 620 * descriptors. 621 */ 622 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 623 sc->sc_txfree != 0) { 624 /* 625 * Grab a packet off the queue. 626 */ 627 IF_DEQUEUE(&ifp->if_snd, m0); 628 if (m0 == NULL) 629 break; 630 631 dmamap = txs->txs_dmamap; 632 633 /* 634 * Load the DMA map. If this fails, the packet either 635 * didn't fit in the alloted number of segments, or we 636 * were short on resources. In this case, we'll copy 637 * and try again. 638 */ 639 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 640 BUS_DMA_NOWAIT) != 0) { 641 MGETHDR(m, M_DONTWAIT, MT_DATA); 642 if (m == NULL) { 643 printf("%s: unable to allocate Tx mbuf\n", 644 sc->sc_dev.dv_xname); 645 IF_PREPEND(&ifp->if_snd, m0); 646 break; 647 } 648 if (m0->m_pkthdr.len > MHLEN) { 649 MCLGET(m, M_DONTWAIT); 650 if ((m->m_flags & M_EXT) == 0) { 651 printf("%s: unable to allocate Tx " 652 "cluster\n", sc->sc_dev.dv_xname); 653 m_freem(m); 654 IF_PREPEND(&ifp->if_snd, m0); 655 break; 656 } 657 } 658 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 659 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 660 m_freem(m0); 661 m0 = m; 662 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 663 m0, BUS_DMA_NOWAIT); 664 if (error) { 665 printf("%s: unable to load Tx buffer, " 666 "error = %d\n", sc->sc_dev.dv_xname, error); 667 IF_PREPEND(&ifp->if_snd, m0); 668 break; 669 } 670 } 671 672 /* 673 * Ensure we have enough descriptors free to describe 674 * the packet. 675 */ 676 if (dmamap->dm_nsegs > sc->sc_txfree) { 677 /* 678 * Not enough free descriptors to transmit this 679 * packet. We haven't committed anything yet, 680 * so just unload the DMA map, put the packet 681 * back on the queue, and punt. Notify the upper 682 * layer that there are not more slots left. 683 * 684 * XXX We could allocate an mbuf and copy, but 685 * XXX is it worth it? 686 */ 687 ifp->if_flags |= IFF_OACTIVE; 688 bus_dmamap_unload(sc->sc_dmat, dmamap); 689 IF_PREPEND(&ifp->if_snd, m0); 690 break; 691 } 692 693 /* 694 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 695 */ 696 697 /* Sync the DMA map. */ 698 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 699 BUS_DMASYNC_PREWRITE); 700 701 /* 702 * Initialize the transmit descriptors. 703 */ 704 for (nexttx = sc->sc_txnext, seg = 0; 705 seg < dmamap->dm_nsegs; 706 seg++, nexttx = SIP_NEXTTX(nexttx)) { 707 /* 708 * If this is the first descriptor we're 709 * enqueueing, don't set the OWN bit just 710 * yet. That could cause a race condition. 711 * We'll do it below. 712 */ 713 sc->sc_txdescs[nexttx].sipd_bufptr = 714 dmamap->dm_segs[seg].ds_addr; 715 sc->sc_txdescs[nexttx].sipd_cmdsts = 716 (nexttx == firsttx ? 0 : CMDSTS_OWN) | 717 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len; 718 lasttx = nexttx; 719 } 720 721 /* Clear the MORE bit on the last segment. */ 722 sc->sc_txdescs[lasttx].sipd_cmdsts &= ~CMDSTS_MORE; 723 724 /* Sync the descriptors we're using. */ 725 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 726 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 727 728 /* 729 * Store a pointer to the packet so we can free it later, 730 * and remember what txdirty will be once the packet is 731 * done. 732 */ 733 txs->txs_mbuf = m0; 734 txs->txs_firstdesc = sc->sc_txnext; 735 txs->txs_lastdesc = lasttx; 736 737 /* Advance the tx pointer. */ 738 sc->sc_txfree -= dmamap->dm_nsegs; 739 sc->sc_txnext = nexttx; 740 741 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 742 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 743 744 #if NBPFILTER > 0 745 /* 746 * Pass the packet to any BPF listeners. 747 */ 748 if (ifp->if_bpf) 749 bpf_mtap(ifp->if_bpf, m0); 750 #endif /* NBPFILTER > 0 */ 751 } 752 753 if (txs == NULL || sc->sc_txfree == 0) { 754 /* No more slots left; notify upper layer. */ 755 ifp->if_flags |= IFF_OACTIVE; 756 } 757 758 if (sc->sc_txfree != ofree) { 759 /* 760 * Cause a descriptor interrupt to happen on the 761 * last packet we enqueued. 762 */ 763 sc->sc_txdescs[lasttx].sipd_cmdsts |= CMDSTS_INTR; 764 SIP_CDTXSYNC(sc, lasttx, 1, 765 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 766 767 /* 768 * The entire packet chain is set up. Give the 769 * first descrptor to the chip now. 770 */ 771 sc->sc_txdescs[firsttx].sipd_cmdsts |= CMDSTS_OWN; 772 SIP_CDTXSYNC(sc, firsttx, 1, 773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 774 775 /* Start the transmit process. */ 776 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 777 CR_TXE) == 0) { 778 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 779 SIP_CDTXADDR(sc, firsttx)); 780 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 781 } 782 783 /* Set a watchdog timer in case the chip flakes out. */ 784 ifp->if_timer = 5; 785 } 786 } 787 788 /* 789 * sip_watchdog: [ifnet interface function] 790 * 791 * Watchdog timer handler. 792 */ 793 void 794 sip_watchdog(ifp) 795 struct ifnet *ifp; 796 { 797 struct sip_softc *sc = ifp->if_softc; 798 799 /* 800 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 801 * If we get a timeout, try and sweep up transmit descriptors. 802 * If we manage to sweep them all up, ignore the lack of 803 * interrupt. 804 */ 805 sip_txintr(sc); 806 807 if (sc->sc_txfree != SIP_NTXDESC) { 808 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 809 ifp->if_oerrors++; 810 811 /* Reset the interface. */ 812 (void) sip_init(sc); 813 } else if (ifp->if_flags & IFF_DEBUG) 814 printf("%s: recovered from device timeout\n", 815 sc->sc_dev.dv_xname); 816 817 /* Try to get more packets going. */ 818 sip_start(ifp); 819 } 820 821 /* 822 * sip_ioctl: [ifnet interface function] 823 * 824 * Handle control requests from the operator. 825 */ 826 int 827 sip_ioctl(ifp, cmd, data) 828 struct ifnet *ifp; 829 u_long cmd; 830 caddr_t data; 831 { 832 struct sip_softc *sc = ifp->if_softc; 833 struct ifreq *ifr = (struct ifreq *)data; 834 struct ifaddr *ifa = (struct ifaddr *)data; 835 int s, error = 0; 836 837 s = splnet(); 838 839 switch (cmd) { 840 case SIOCSIFADDR: 841 ifp->if_flags |= IFF_UP; 842 843 switch (ifa->ifa_addr->sa_family) { 844 #ifdef INET 845 case AF_INET: 846 if ((error = sip_init(sc)) != 0) 847 break; 848 arp_ifinit(ifp, ifa); 849 break; 850 #endif /* INET */ 851 #ifdef NS 852 case AF_NS: 853 { 854 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 855 856 if (ns_nullhost(*ina)) 857 ina->x_host = *(union ns_host *) 858 LLADDR(ifp->if_sadl); 859 else 860 memcpy(LLADDR(ifp->if_sadl), 861 ina->x_host.c_host, ifp->if_addrlen); 862 error = sip_init(sc); 863 break; 864 } 865 #endif /* NS */ 866 default: 867 error = sip_init(sc); 868 break; 869 } 870 break; 871 872 case SIOCSIFMTU: 873 if (ifr->ifr_mtu > ETHERMTU) 874 error = EINVAL; 875 else 876 ifp->if_mtu = ifr->ifr_mtu; 877 break; 878 879 case SIOCSIFFLAGS: 880 if ((ifp->if_flags & IFF_UP) == 0 && 881 (ifp->if_flags & IFF_RUNNING) != 0) { 882 /* 883 * If interface is marked down and it is running, then 884 * stop it. 885 */ 886 sip_stop(sc, 1); 887 } else if ((ifp->if_flags & IFF_UP) != 0 && 888 (ifp->if_flags & IFF_RUNNING) == 0) { 889 /* 890 * If interfase it marked up and it is stopped, then 891 * start it. 892 */ 893 error = sip_init(sc); 894 } else if ((ifp->if_flags & IFF_UP) != 0) { 895 /* 896 * Reset the interface to pick up changes in any other 897 * flags that affect the hardware state. 898 */ 899 error = sip_init(sc); 900 } 901 break; 902 903 case SIOCADDMULTI: 904 case SIOCDELMULTI: 905 error = (cmd == SIOCADDMULTI) ? 906 ether_addmulti(ifr, &sc->sc_ethercom) : 907 ether_delmulti(ifr, &sc->sc_ethercom); 908 909 if (error == ENETRESET) { 910 /* 911 * Multicast list has changed; set the hardware filter 912 * accordingly. 913 */ 914 sip_set_filter(sc); 915 error = 0; 916 } 917 break; 918 919 case SIOCSIFMEDIA: 920 case SIOCGIFMEDIA: 921 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 922 break; 923 924 default: 925 error = EINVAL; 926 break; 927 } 928 929 /* Try to get more packets going. */ 930 sip_start(ifp); 931 932 splx(s); 933 return (error); 934 } 935 936 /* 937 * sip_intr: 938 * 939 * Interrupt service routine. 940 */ 941 int 942 sip_intr(arg) 943 void *arg; 944 { 945 struct sip_softc *sc = arg; 946 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 947 u_int32_t isr; 948 int handled = 0; 949 950 for (;;) { 951 /* Reading clears interrupt. */ 952 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 953 if ((isr & sc->sc_imr) == 0) 954 break; 955 956 handled = 1; 957 958 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 959 /* Grab any new packets. */ 960 sip_rxintr(sc); 961 962 if (isr & ISR_RXORN) { 963 printf("%s: receive FIFO overrun\n", 964 sc->sc_dev.dv_xname); 965 966 /* XXX adjust rx_drain_thresh? */ 967 } 968 969 if (isr & ISR_RXIDLE) { 970 printf("%s: receive ring overrun\n", 971 sc->sc_dev.dv_xname); 972 973 /* Get the receive process going again. */ 974 bus_space_write_4(sc->sc_st, sc->sc_sh, 975 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 976 bus_space_write_4(sc->sc_st, sc->sc_sh, 977 SIP_CR, CR_RXE); 978 } 979 } 980 981 if (isr & (ISR_TXURN|ISR_TXDESC)) { 982 /* Sweep up transmit descriptors. */ 983 sip_txintr(sc); 984 985 if (isr & ISR_TXURN) { 986 u_int32_t thresh; 987 988 printf("%s: transmit FIFO underrun", 989 sc->sc_dev.dv_xname); 990 991 thresh = sc->sc_tx_drain_thresh + 1; 992 if (thresh <= TXCFG_DRTH && 993 (thresh * 32) <= (SIP_TXFIFO_SIZE - 994 (sc->sc_tx_fill_thresh * 32))) { 995 printf("; increasing Tx drain " 996 "threshold to %u bytes\n", 997 thresh * 32); 998 sc->sc_tx_drain_thresh = thresh; 999 (void) sip_init(sc); 1000 } else { 1001 (void) sip_init(sc); 1002 printf("\n"); 1003 } 1004 } 1005 } 1006 1007 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1008 if (isr & ISR_PAUSE_ST) { 1009 sc->sc_flags |= SIPF_PAUSED; 1010 ifp->if_flags |= IFF_OACTIVE; 1011 } 1012 if (isr & ISR_PAUSE_END) { 1013 sc->sc_flags &= ~SIPF_PAUSED; 1014 ifp->if_flags &= ~IFF_OACTIVE; 1015 } 1016 } 1017 1018 if (isr & ISR_HIBERR) { 1019 #define PRINTERR(bit, str) \ 1020 if (isr & (bit)) \ 1021 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1022 PRINTERR(ISR_DPERR, "parity error"); 1023 PRINTERR(ISR_SSERR, "system error"); 1024 PRINTERR(ISR_RMABT, "master abort"); 1025 PRINTERR(ISR_RTABT, "target abort"); 1026 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1027 (void) sip_init(sc); 1028 #undef PRINTERR 1029 } 1030 } 1031 1032 /* Try to get more packets going. */ 1033 sip_start(ifp); 1034 1035 return (handled); 1036 } 1037 1038 /* 1039 * sip_txintr: 1040 * 1041 * Helper; handle transmit interrupts. 1042 */ 1043 void 1044 sip_txintr(sc) 1045 struct sip_softc *sc; 1046 { 1047 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1048 struct sip_txsoft *txs; 1049 u_int32_t cmdsts; 1050 1051 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1052 ifp->if_flags &= ~IFF_OACTIVE; 1053 1054 /* 1055 * Go through our Tx list and free mbufs for those 1056 * frames which have been transmitted. 1057 */ 1058 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1059 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1060 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1061 1062 cmdsts = sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1063 if (cmdsts & CMDSTS_OWN) 1064 break; 1065 1066 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1067 1068 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1069 1070 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1071 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1072 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1073 m_freem(txs->txs_mbuf); 1074 txs->txs_mbuf = NULL; 1075 1076 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1077 1078 /* 1079 * Check for errors and collisions. 1080 */ 1081 if (cmdsts & 1082 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1083 if (ifp->if_flags & IFF_DEBUG) { 1084 if (CMDSTS_Tx_ED) 1085 printf("%s: excessive deferral\n", 1086 sc->sc_dev.dv_xname); 1087 if (CMDSTS_Tx_EC) { 1088 printf("%s: excessive collisions\n", 1089 sc->sc_dev.dv_xname); 1090 ifp->if_collisions += 16; 1091 } 1092 } 1093 } else { 1094 /* Packet was transmitted successfully. */ 1095 ifp->if_opackets++; 1096 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1097 } 1098 } 1099 1100 /* 1101 * If there are no more pending transmissions, cancel the watchdog 1102 * timer. 1103 */ 1104 if (txs == NULL) 1105 ifp->if_timer = 0; 1106 } 1107 1108 /* 1109 * sip_rxintr: 1110 * 1111 * Helper; handle receive interrupts. 1112 */ 1113 void 1114 sip_rxintr(sc) 1115 struct sip_softc *sc; 1116 { 1117 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1118 struct ether_header *eh; 1119 struct sip_rxsoft *rxs; 1120 struct mbuf *m; 1121 u_int32_t cmdsts; 1122 int i, len; 1123 1124 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1125 rxs = &sc->sc_rxsoft[i]; 1126 1127 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1128 1129 cmdsts = sc->sc_rxdescs[i].sipd_cmdsts; 1130 1131 /* 1132 * NOTE: OWN is set if owned by _consumer_. We're the 1133 * consumer of the receive ring, so if the bit is clear, 1134 * we have processed all of the packets. 1135 */ 1136 if ((cmdsts & CMDSTS_OWN) == 0) { 1137 /* 1138 * We have processed all of the receive buffers. 1139 */ 1140 break; 1141 } 1142 1143 /* 1144 * If any collisions were seen on the wire, count one. 1145 */ 1146 if (cmdsts & CMDSTS_Rx_COL) 1147 ifp->if_collisions++; 1148 1149 /* 1150 * If an error occurred, update stats, clear the status 1151 * word, and leave the packet buffer in place. It will 1152 * simply be reused the next time the ring comes around. 1153 */ 1154 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1155 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1156 ifp->if_ierrors++; 1157 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1158 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1159 /* Receive overrun handled elsewhere. */ 1160 printf("%s: receive descriptor error\n", 1161 sc->sc_dev.dv_xname); 1162 } 1163 #define PRINTERR(bit, str) \ 1164 if (cmdsts & (bit)) \ 1165 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1166 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1167 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1168 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1169 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1170 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1171 #undef PRINTERR 1172 SIP_INIT_RXDESC(sc, i); 1173 continue; 1174 } 1175 1176 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1177 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1178 1179 /* 1180 * No errors; receive the packet. Note, the SiS 900 1181 * includes the CRC with every packet; trim it. 1182 */ 1183 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 1184 1185 #ifdef __NO_STRICT_ALIGNMENT 1186 /* 1187 * If the packet is small enough to fit in a 1188 * single header mbuf, allocate one and copy 1189 * the data into it. This greatly reduces 1190 * memory consumption when we receive lots 1191 * of small packets. 1192 * 1193 * Otherwise, we add a new buffer to the receive 1194 * chain. If this fails, we drop the packet and 1195 * recycle the old buffer. 1196 */ 1197 if (sip_copy_small != 0 && len <= MHLEN) { 1198 MGETHDR(m, M_DONTWAIT, MT_DATA); 1199 if (m == NULL) 1200 goto dropit; 1201 memcpy(mtod(m, caddr_t), 1202 mtod(rxs->rxs_mbuf, caddr_t), len); 1203 SIP_INIT_RXDESC(sc, i); 1204 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1205 rxs->rxs_dmamap->dm_mapsize, 1206 BUS_DMASYNC_PREREAD); 1207 } else { 1208 m = rxs->rxs_mbuf; 1209 if (sip_add_rxbuf(sc, i) != 0) { 1210 dropit: 1211 ifp->if_ierrors++; 1212 SIP_INIT_RXDESC(sc, i); 1213 bus_dmamap_sync(sc->sc_dmat, 1214 rxs->rxs_dmamap, 0, 1215 rxs->rxs_dmamap->dm_mapsize, 1216 BUS_DMASYNC_PREREAD); 1217 continue; 1218 } 1219 } 1220 #else 1221 /* 1222 * The SiS 900's receive buffers must be 4-byte aligned. 1223 * But this means that the data after the Ethernet header 1224 * is misaligned. We must allocate a new buffer and 1225 * copy the data, shifted forward 2 bytes. 1226 */ 1227 MGETHDR(m, M_DONTWAIT, MT_DATA); 1228 if (m == NULL) { 1229 dropit: 1230 ifp->if_ierrors++; 1231 SIP_INIT_RXDESC(sc, i); 1232 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1233 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1234 continue; 1235 } 1236 if (len > (MHLEN - 2)) { 1237 MCLGET(m, M_DONTWAIT); 1238 if ((m->m_flags & M_EXT) == 0) { 1239 m_freem(m); 1240 goto dropit; 1241 } 1242 } 1243 m->m_data += 2; 1244 1245 /* 1246 * Note that we use clusters for incoming frames, so the 1247 * buffer is virtually contiguous. 1248 */ 1249 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1250 1251 /* Allow the receive descriptor to continue using its mbuf. */ 1252 SIP_INIT_RXDESC(sc, i); 1253 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1254 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1255 #endif /* __NO_STRICT_ALIGNMENT */ 1256 1257 ifp->if_ipackets++; 1258 eh = mtod(m, struct ether_header *); 1259 m->m_pkthdr.rcvif = ifp; 1260 m->m_pkthdr.len = m->m_len = len; 1261 1262 #if NBPFILTER > 0 1263 /* 1264 * Pass this up to any BPF listeners, but only 1265 * pass if up the stack if it's for us. 1266 */ 1267 if (ifp->if_bpf) { 1268 bpf_mtap(ifp->if_bpf, m); 1269 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1270 (cmdsts & CMDSTS_Rx_DEST) == CMDSTS_Rx_DEST_REJ) { 1271 m_freem(m); 1272 continue; 1273 } 1274 } 1275 #endif /* NBPFILTER > 0 */ 1276 1277 /* Pass it on. */ 1278 (*ifp->if_input)(ifp, m); 1279 } 1280 1281 /* Update the receive pointer. */ 1282 sc->sc_rxptr = i; 1283 } 1284 1285 /* 1286 * sip_tick: 1287 * 1288 * One second timer, used to tick the MII. 1289 */ 1290 void 1291 sip_tick(arg) 1292 void *arg; 1293 { 1294 struct sip_softc *sc = arg; 1295 int s; 1296 1297 s = splnet(); 1298 mii_tick(&sc->sc_mii); 1299 splx(s); 1300 1301 timeout(sip_tick, sc, hz); 1302 } 1303 1304 /* 1305 * sip_reset: 1306 * 1307 * Perform a soft reset on the SiS 900. 1308 */ 1309 void 1310 sip_reset(sc) 1311 struct sip_softc *sc; 1312 { 1313 bus_space_tag_t st = sc->sc_st; 1314 bus_space_handle_t sh = sc->sc_sh; 1315 int i; 1316 1317 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1318 1319 for (i = 0; i < 1000; i++) { 1320 if ((bus_space_read_4(st, sh, SIP_ISR) & 1321 (ISR_TXRCMP|ISR_RXRCMP)) == (ISR_TXRCMP|ISR_RXRCMP)) 1322 return; 1323 delay(2); 1324 } 1325 1326 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1327 } 1328 1329 /* 1330 * sip_init: 1331 * 1332 * Initialize the interface. Must be called at splnet(). 1333 */ 1334 int 1335 sip_init(sc) 1336 struct sip_softc *sc; 1337 { 1338 bus_space_tag_t st = sc->sc_st; 1339 bus_space_handle_t sh = sc->sc_sh; 1340 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1341 struct sip_txsoft *txs; 1342 struct sip_rxsoft *rxs; 1343 struct sip_desc *sipd; 1344 u_int32_t cfg; 1345 int i, error = 0; 1346 1347 /* 1348 * Cancel any pending I/O. 1349 */ 1350 sip_stop(sc, 0); 1351 1352 /* 1353 * Reset the chip to a known state. 1354 */ 1355 sip_reset(sc); 1356 1357 /* 1358 * Initialize the transmit descriptor ring. 1359 */ 1360 for (i = 0; i < SIP_NTXDESC; i++) { 1361 sipd = &sc->sc_txdescs[i]; 1362 memset(sipd, 0, sizeof(struct sip_desc)); 1363 sipd->sipd_link = SIP_CDTXADDR(sc, SIP_NEXTTX(i)); 1364 } 1365 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1366 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1367 sc->sc_txfree = SIP_NTXDESC; 1368 sc->sc_txnext = 0; 1369 1370 /* 1371 * Initialize the transmit job descriptors. 1372 */ 1373 SIMPLEQ_INIT(&sc->sc_txfreeq); 1374 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1375 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1376 txs = &sc->sc_txsoft[i]; 1377 txs->txs_mbuf = NULL; 1378 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1379 } 1380 1381 /* 1382 * Initialize the receive descriptor and receive job 1383 * descriptor rings. 1384 */ 1385 for (i = 0; i < SIP_NRXDESC; i++) { 1386 rxs = &sc->sc_rxsoft[i]; 1387 if (rxs->rxs_mbuf == NULL) { 1388 if ((error = sip_add_rxbuf(sc, i)) != 0) { 1389 printf("%s: unable to allocate or map rx " 1390 "buffer %d, error = %d\n", 1391 sc->sc_dev.dv_xname, i, error); 1392 /* 1393 * XXX Should attempt to run with fewer receive 1394 * XXX buffers instead of just failing. 1395 */ 1396 sip_rxdrain(sc); 1397 goto out; 1398 } 1399 } 1400 } 1401 sc->sc_rxptr = 0; 1402 1403 /* 1404 * Initialize the configuration register: aggressive PCI 1405 * bus request algorithm, default backoff, default OW timer, 1406 * default parity error detection. 1407 */ 1408 cfg = 0; 1409 #if BYTE_ORDER == BIG_ENDIAN 1410 /* 1411 * ...descriptors in big-endian mode. 1412 */ 1413 cfg |= CFG_BEM; 1414 #endif 1415 bus_space_write_4(st, sh, SIP_CFG, cfg); 1416 1417 /* 1418 * Initialize the transmit fill and drain thresholds if 1419 * we have never done so. 1420 */ 1421 if (sc->sc_tx_fill_thresh == 0) { 1422 /* 1423 * XXX This value should be tuned. This is the 1424 * minimum (32 bytes), and we may be able to 1425 * improve performance by increasing it. 1426 */ 1427 sc->sc_tx_fill_thresh = 1; 1428 } 1429 if (sc->sc_tx_drain_thresh == 0) { 1430 /* 1431 * Start at a drain threshold of 128 bytes. We will 1432 * increase it if a DMA underrun occurs. 1433 * 1434 * XXX The minimum value of this variable should be 1435 * tuned. We may be able to improve performance 1436 * by starting with a lower value. That, however, 1437 * may trash the first few outgoing packets if the 1438 * PCI bus is saturated. 1439 */ 1440 sc->sc_tx_drain_thresh = 4; 1441 } 1442 1443 /* 1444 * Initialize the prototype TXCFG register. 1445 */ 1446 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1447 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1448 sc->sc_tx_drain_thresh; 1449 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1450 1451 /* 1452 * Initialize the receive drain threshold if we have never 1453 * done so. 1454 */ 1455 if (sc->sc_rx_drain_thresh == 0) { 1456 /* 1457 * XXX This value should be tuned. This is set to the 1458 * maximum of 248 bytes, and we may be able to improve 1459 * performance by decreasing it (although we should never 1460 * set this value lower than 2; 14 bytes are required to 1461 * filter the packet). 1462 */ 1463 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1464 } 1465 1466 /* 1467 * Initialize the prototype RXCFG register. 1468 */ 1469 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1470 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1471 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1472 1473 /* Set up the receive filter. */ 1474 sip_set_filter(sc); 1475 1476 /* 1477 * Give the transmit and receive rings to the chip. 1478 */ 1479 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1480 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1481 1482 /* 1483 * Initialize the interrupt mask. 1484 */ 1485 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1486 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1487 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1488 1489 /* 1490 * Set the current media. Do this after initializing the prototype 1491 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1492 * control. 1493 */ 1494 mii_mediachg(&sc->sc_mii); 1495 1496 /* 1497 * Enable interrupts. 1498 */ 1499 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1500 1501 /* 1502 * Start the transmit and receive processes. 1503 */ 1504 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1505 1506 /* 1507 * Start the one second MII clock. 1508 */ 1509 timeout(sip_tick, sc, hz); 1510 1511 /* 1512 * ...all done! 1513 */ 1514 ifp->if_flags |= IFF_RUNNING; 1515 ifp->if_flags &= ~IFF_OACTIVE; 1516 1517 out: 1518 if (error) 1519 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1520 return (error); 1521 } 1522 1523 /* 1524 * sip_drain: 1525 * 1526 * Drain the receive queue. 1527 */ 1528 void 1529 sip_rxdrain(sc) 1530 struct sip_softc *sc; 1531 { 1532 struct sip_rxsoft *rxs; 1533 int i; 1534 1535 for (i = 0; i < SIP_NRXDESC; i++) { 1536 rxs = &sc->sc_rxsoft[i]; 1537 if (rxs->rxs_mbuf != NULL) { 1538 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1539 m_freem(rxs->rxs_mbuf); 1540 rxs->rxs_mbuf = NULL; 1541 } 1542 } 1543 } 1544 1545 /* 1546 * sip_stop: 1547 * 1548 * Stop transmission on the interface. 1549 */ 1550 void 1551 sip_stop(sc, drain) 1552 struct sip_softc *sc; 1553 { 1554 bus_space_tag_t st = sc->sc_st; 1555 bus_space_handle_t sh = sc->sc_sh; 1556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1557 struct sip_txsoft *txs; 1558 u_int32_t cmdsts = 0; /* DEBUG */ 1559 1560 /* 1561 * Stop the one second clock. 1562 */ 1563 untimeout(sip_tick, sc); 1564 1565 /* 1566 * Disable interrupts. 1567 */ 1568 bus_space_write_4(st, sh, SIP_IER, 0); 1569 1570 /* 1571 * Stop receiver and transmitter. 1572 */ 1573 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1574 1575 /* 1576 * Release any queued transmit buffers. 1577 */ 1578 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1579 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1580 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1581 (sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts & 1582 CMDSTS_INTR) == 0) 1583 printf("%s: sip_stop: last descriptor does not " 1584 "have INTR bit set\n", sc->sc_dev.dv_xname); 1585 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1586 #ifdef DIAGNOSTIC 1587 if (txs->txs_mbuf == NULL) { 1588 printf("%s: dirty txsoft with no mbuf chain\n", 1589 sc->sc_dev.dv_xname); 1590 panic("sip_stop"); 1591 } 1592 #endif 1593 cmdsts |= /* DEBUG */ 1594 sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts; 1595 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1596 m_freem(txs->txs_mbuf); 1597 txs->txs_mbuf = NULL; 1598 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1599 } 1600 1601 if (drain) { 1602 /* 1603 * Release the receive buffers. 1604 */ 1605 sip_rxdrain(sc); 1606 } 1607 1608 /* 1609 * Mark the interface down and cancel the watchdog timer. 1610 */ 1611 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1612 ifp->if_timer = 0; 1613 1614 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1615 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1616 printf("%s: sip_stop: no INTR bits set in dirty tx " 1617 "descriptors\n", sc->sc_dev.dv_xname); 1618 } 1619 1620 /* 1621 * sip_read_eeprom: 1622 * 1623 * Read data from the serial EEPROM. 1624 */ 1625 void 1626 sip_read_eeprom(sc, word, wordcnt, data) 1627 struct sip_softc *sc; 1628 int word, wordcnt; 1629 u_int16_t *data; 1630 { 1631 bus_space_tag_t st = sc->sc_st; 1632 bus_space_handle_t sh = sc->sc_sh; 1633 u_int16_t reg; 1634 int i, x; 1635 1636 for (i = 0; i < wordcnt; i++) { 1637 /* Send CHIP SELECT. */ 1638 reg = EROMAR_EECS; 1639 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1640 1641 /* Shift in the READ opcode. */ 1642 for (x = 3; x > 0; x--) { 1643 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1644 reg |= EROMAR_EEDI; 1645 else 1646 reg &= ~EROMAR_EEDI; 1647 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1648 bus_space_write_4(st, sh, SIP_EROMAR, 1649 reg | EROMAR_EESK); 1650 delay(4); 1651 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1652 delay(4); 1653 } 1654 1655 /* Shift in address. */ 1656 for (x = 6; x > 0; x--) { 1657 if ((word + i) & (1 << (x - 1))) 1658 reg |= EROMAR_EEDI; 1659 else 1660 reg &= ~EROMAR_EEDI; 1661 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1662 bus_space_write_4(st, sh, SIP_EROMAR, 1663 reg | EROMAR_EESK); 1664 delay(4); 1665 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1666 delay(4); 1667 } 1668 1669 /* Shift out data. */ 1670 reg = EROMAR_EECS; 1671 data[i] = 0; 1672 for (x = 16; x > 0; x--) { 1673 bus_space_write_4(st, sh, SIP_EROMAR, 1674 reg | EROMAR_EESK); 1675 delay(4); 1676 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1677 data[i] |= (1 << (x - 1)); 1678 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1679 } 1680 1681 /* Clear CHIP SELECT. */ 1682 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1683 delay(4); 1684 } 1685 } 1686 1687 /* 1688 * sip_add_rxbuf: 1689 * 1690 * Add a receive buffer to the indicated descriptor. 1691 */ 1692 int 1693 sip_add_rxbuf(sc, idx) 1694 struct sip_softc *sc; 1695 int idx; 1696 { 1697 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1698 struct mbuf *m; 1699 int error; 1700 1701 MGETHDR(m, M_DONTWAIT, MT_DATA); 1702 if (m == NULL) 1703 return (ENOBUFS); 1704 1705 MCLGET(m, M_DONTWAIT); 1706 if ((m->m_flags & M_EXT) == 0) { 1707 m_freem(m); 1708 return (ENOBUFS); 1709 } 1710 1711 if (rxs->rxs_mbuf != NULL) 1712 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1713 1714 rxs->rxs_mbuf = m; 1715 1716 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1717 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1718 if (error) { 1719 printf("%s: can't load rx DMA map %d, error = %d\n", 1720 sc->sc_dev.dv_xname, idx, error); 1721 panic("sip_add_rxbuf"); /* XXX */ 1722 } 1723 1724 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1725 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1726 1727 SIP_INIT_RXDESC(sc, idx); 1728 1729 return (0); 1730 } 1731 1732 /* 1733 * sip_set_filter: 1734 * 1735 * Set up the receive filter. 1736 */ 1737 void 1738 sip_set_filter(sc) 1739 struct sip_softc *sc; 1740 { 1741 bus_space_tag_t st = sc->sc_st; 1742 bus_space_handle_t sh = sc->sc_sh; 1743 struct ethercom *ec = &sc->sc_ethercom; 1744 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1745 struct ether_multi *enm; 1746 struct ether_multistep step; 1747 u_int8_t *cp; 1748 u_int32_t crc, mchash[8]; 1749 int len; 1750 static const u_int32_t crctab[] = { 1751 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 1752 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 1753 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 1754 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c 1755 }; 1756 1757 /* 1758 * Initialize the prototype RFCR. 1759 */ 1760 sc->sc_rfcr = RFCR_RFEN; 1761 if (ifp->if_flags & IFF_BROADCAST) 1762 sc->sc_rfcr |= RFCR_AAB; 1763 if (ifp->if_flags & IFF_PROMISC) { 1764 sc->sc_rfcr |= RFCR_AAP; 1765 goto allmulti; 1766 } 1767 1768 /* 1769 * Set up the multicast address filter by passing all multicast 1770 * addresses through a CRC generator, and then using the high-order 1771 * 6 bits as an index into the 128 bit multicast hash table (only 1772 * the lower 16 bits of each 32 bit multicast hash register are 1773 * valid). The high order bits select the register, while the 1774 * rest of the bits select the bit within the register. 1775 */ 1776 1777 memset(mchash, 0, sizeof(mchash)); 1778 1779 ETHER_FIRST_MULTI(step, ec, enm); 1780 while (enm != NULL) { 1781 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1782 /* 1783 * We must listen to a range of multicast addresses. 1784 * For now, just accept all multicasts, rather than 1785 * trying to set only those filter bits needed to match 1786 * the range. (At this time, the only use of address 1787 * ranges is for IP multicast routing, for which the 1788 * range is big enough to require all bits set.) 1789 */ 1790 goto allmulti; 1791 } 1792 1793 cp = enm->enm_addrlo; 1794 crc = 0xffffffff; 1795 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1796 crc ^= *cp++; 1797 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1798 crc = (crc >> 4) ^ crctab[crc & 0xf]; 1799 } 1800 /* Just want the 7 most significant bits. */ 1801 crc >>= 25; 1802 1803 /* Set the corresponding bit in the hash table. */ 1804 mchash[crc >> 4] |= 1 << (crc & 0xf); 1805 1806 ETHER_NEXT_MULTI(step, enm); 1807 } 1808 1809 ifp->if_flags &= ~IFF_ALLMULTI; 1810 goto setit; 1811 1812 allmulti: 1813 ifp->if_flags |= IFF_ALLMULTI; 1814 sc->sc_rfcr |= RFCR_AAM; 1815 1816 setit: 1817 #define FILTER_EMIT(addr, data) \ 1818 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1819 bus_space_write_4(st, sh, SIP_RFDR, (data)) 1820 1821 /* 1822 * Disable receive filter, and program the node address. 1823 */ 1824 cp = LLADDR(ifp->if_sadl); 1825 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1826 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1827 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1828 1829 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1830 /* 1831 * Program the multicast hash table. 1832 */ 1833 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1834 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1835 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1836 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1837 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1838 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1839 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1840 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1841 } 1842 #undef FILTER_EMIT 1843 1844 /* 1845 * Re-enable the receiver filter. 1846 */ 1847 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1848 } 1849 1850 /* 1851 * sip_mii_readreg: [mii interface function] 1852 * 1853 * Read a PHY register on the MII. 1854 */ 1855 int 1856 sip_mii_readreg(self, phy, reg) 1857 struct device *self; 1858 int phy, reg; 1859 { 1860 struct sip_softc *sc = (struct sip_softc *) self; 1861 u_int32_t enphy; 1862 1863 /* 1864 * The SiS 900 has only an internal PHY on the MII. Only allow 1865 * MII address 0. 1866 */ 1867 if (phy != 0) 1868 return (0); 1869 1870 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1871 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_RWCMD | ENPHY_ACCESS); 1872 do { 1873 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1874 } while (enphy & ENPHY_ACCESS); 1875 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 1876 } 1877 1878 /* 1879 * sip_mii_writereg: [mii interface function] 1880 * 1881 * Write a PHY register on the MII. 1882 */ 1883 void 1884 sip_mii_writereg(self, phy, reg, val) 1885 struct device *self; 1886 int phy, reg, val; 1887 { 1888 struct sip_softc *sc = (struct sip_softc *) self; 1889 u_int32_t enphy; 1890 1891 /* 1892 * The SiS 900 has only an internal PHY on the MII. Only allow 1893 * MII address 0. 1894 */ 1895 if (phy != 0) 1896 return; 1897 1898 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1899 (val << ENPHY_DATA_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 1900 ENPHY_ACCESS); 1901 do { 1902 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1903 } while (enphy & ENPHY_ACCESS); 1904 } 1905 1906 /* 1907 * sip_mii_statchg: [mii interface function] 1908 * 1909 * Callback from MII layer when media changes. 1910 */ 1911 void 1912 sip_mii_statchg(self) 1913 struct device *self; 1914 { 1915 struct sip_softc *sc = (struct sip_softc *) self; 1916 u_int32_t flowctl; 1917 1918 /* 1919 * Update TXCFG for full-duplex operation. 1920 */ 1921 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1922 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 1923 else 1924 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 1925 1926 /* 1927 * Update RXCFG for full-duplex or loopback. 1928 */ 1929 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 1930 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 1931 sc->sc_rxcfg |= RXCFG_ATX; 1932 else 1933 sc->sc_rxcfg &= ~RXCFG_ATX; 1934 1935 /* 1936 * Update IMR for use of 802.3x flow control. 1937 */ 1938 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 1939 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 1940 flowctl = FLOWCTL_FLOWEN; 1941 } else { 1942 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 1943 flowctl = 0; 1944 } 1945 1946 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 1947 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 1948 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 1949 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 1950 1951 /* XXX Update ifp->if_baudrate */ 1952 } 1953 1954 /* 1955 * sip_mediastatus: [ifmedia interface function] 1956 * 1957 * Get the current interface media status. 1958 */ 1959 void 1960 sip_mediastatus(ifp, ifmr) 1961 struct ifnet *ifp; 1962 struct ifmediareq *ifmr; 1963 { 1964 struct sip_softc *sc = ifp->if_softc; 1965 1966 mii_pollstat(&sc->sc_mii); 1967 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1968 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1969 } 1970 1971 /* 1972 * sip_mediachange: [ifmedia interface function] 1973 * 1974 * Set hardware to newly-selected media. 1975 */ 1976 int 1977 sip_mediachange(ifp) 1978 struct ifnet *ifp; 1979 { 1980 struct sip_softc *sc = ifp->if_softc; 1981 1982 if (ifp->if_flags & IFF_UP) 1983 mii_mediachg(&sc->sc_mii); 1984 return (0); 1985 } 1986