1 /* $NetBSD: if_pcn.c,v 1.29 2006/02/22 02:57:26 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include "opt_pcn.h" 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.29 2006/02/22 02:57:26 garbled Exp $"); 71 72 #include "bpfilter.h" 73 #include "rnd.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/callout.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/ioctl.h> 83 #include <sys/errno.h> 84 #include <sys/device.h> 85 #include <sys/queue.h> 86 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #endif 101 102 #include <machine/bus.h> 103 #include <machine/intr.h> 104 #include <machine/endian.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/ic/am79900reg.h> 110 #include <dev/ic/lancereg.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/pci/if_pcnreg.h> 117 118 /* 119 * Transmit descriptor list size. This is arbitrary, but allocate 120 * enough descriptors for 128 pending transmissions, and 4 segments 121 * per packet. This MUST work out to a power of 2. 122 * 123 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 124 * 125 * So we play a little trick here. We give each packet up to 16 126 * DMA segments, but only allocate the max of 512 descriptors. The 127 * transmit logic can deal with this, we just are hoping to sneak by. 128 */ 129 #define PCN_NTXSEGS 16 130 131 #define PCN_TXQUEUELEN 128 132 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 133 #define PCN_NTXDESC 512 134 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 135 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 136 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 137 138 /* Tx interrupt every N + 1 packets. */ 139 #define PCN_TXINTR_MASK 7 140 141 /* 142 * Receive descriptor list size. We have one Rx buffer per incoming 143 * packet, so this logic is a little simpler. 144 */ 145 #define PCN_NRXDESC 128 146 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 147 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 148 149 /* 150 * Control structures are DMA'd to the PCnet chip. We allocate them in 151 * a single clump that maps to a single DMA segment to make several things 152 * easier. 153 */ 154 struct pcn_control_data { 155 /* The transmit descriptors. */ 156 struct letmd pcd_txdescs[PCN_NTXDESC]; 157 158 /* The receive descriptors. */ 159 struct lermd pcd_rxdescs[PCN_NRXDESC]; 160 161 /* The init block. */ 162 struct leinit pcd_initblock; 163 }; 164 165 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 166 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 167 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 168 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 169 170 /* 171 * Software state for transmit jobs. 172 */ 173 struct pcn_txsoft { 174 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t txs_dmamap; /* our DMA map */ 176 int txs_firstdesc; /* first descriptor in packet */ 177 int txs_lastdesc; /* last descriptor in packet */ 178 }; 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct pcn_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 /* 189 * Description of Rx FIFO watermarks for various revisions. 190 */ 191 static const char * const pcn_79c970_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "128 bytes", 195 NULL, 196 }; 197 198 static const char * const pcn_79c971_rcvfw[] = { 199 "16 bytes", 200 "64 bytes", 201 "112 bytes", 202 NULL, 203 }; 204 205 /* 206 * Description of Tx start points for various revisions. 207 */ 208 static const char * const pcn_79c970_xmtsp[] = { 209 "8 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 static const char * const pcn_79c971_xmtsp[] = { 216 "20 bytes", 217 "64 bytes", 218 "128 bytes", 219 "248 bytes", 220 }; 221 222 static const char * const pcn_79c971_xmtsp_sram[] = { 223 "44 bytes", 224 "64 bytes", 225 "128 bytes", 226 "store-and-forward", 227 }; 228 229 /* 230 * Description of Tx FIFO watermarks for various revisions. 231 */ 232 static const char * const pcn_79c970_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "128 bytes", 236 NULL, 237 }; 238 239 static const char * const pcn_79c971_xmtfw[] = { 240 "16 bytes", 241 "64 bytes", 242 "108 bytes", 243 NULL, 244 }; 245 246 /* 247 * Software state per device. 248 */ 249 struct pcn_softc { 250 struct device sc_dev; /* generic device information */ 251 bus_space_tag_t sc_st; /* bus space tag */ 252 bus_space_handle_t sc_sh; /* bus space handle */ 253 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 254 struct ethercom sc_ethercom; /* Ethernet common data */ 255 void *sc_sdhook; /* shutdown hook */ 256 257 /* Points to our media routines, etc. */ 258 const struct pcn_variant *sc_variant; 259 260 void *sc_ih; /* interrupt cookie */ 261 262 struct mii_data sc_mii; /* MII/media information */ 263 264 struct callout sc_tick_ch; /* tick callout */ 265 266 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 267 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 268 269 /* Software state for transmit and receive descriptors. */ 270 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 271 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 272 273 /* Control data structures */ 274 struct pcn_control_data *sc_control_data; 275 #define sc_txdescs sc_control_data->pcd_txdescs 276 #define sc_rxdescs sc_control_data->pcd_rxdescs 277 #define sc_initblock sc_control_data->pcd_initblock 278 279 #ifdef PCN_EVENT_COUNTERS 280 /* Event counters. */ 281 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 282 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 283 struct evcnt sc_ev_txintr; /* Tx interrupts */ 284 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 285 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 286 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 287 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 288 289 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 290 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 291 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 292 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 293 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 294 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 295 struct evcnt sc_ev_txcopy; /* Tx copies required */ 296 #endif /* PCN_EVENT_COUNTERS */ 297 298 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 299 int sc_rcvfw; 300 301 const char * const *sc_xmtsp_desc; /* Tx start point info */ 302 int sc_xmtsp; 303 304 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 305 int sc_xmtfw; 306 307 int sc_flags; /* misc. flags; see below */ 308 int sc_swstyle; /* the software style in use */ 309 310 int sc_txfree; /* number of free Tx descriptors */ 311 int sc_txnext; /* next ready Tx descriptor */ 312 313 int sc_txsfree; /* number of free Tx jobs */ 314 int sc_txsnext; /* next free Tx job */ 315 int sc_txsdirty; /* dirty Tx jobs */ 316 317 int sc_rxptr; /* next ready Rx descriptor/job */ 318 319 uint32_t sc_csr5; /* prototype CSR5 register */ 320 uint32_t sc_mode; /* prototype MODE register */ 321 322 #if NRND > 0 323 rndsource_element_t rnd_source; /* random source */ 324 #endif 325 }; 326 327 /* sc_flags */ 328 #define PCN_F_HAS_MII 0x0001 /* has MII */ 329 330 #ifdef PCN_EVENT_COUNTERS 331 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 332 #else 333 #define PCN_EVCNT_INCR(ev) /* nothing */ 334 #endif 335 336 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 337 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 338 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 339 340 #define PCN_CDTXSYNC(sc, x, n, ops) \ 341 do { \ 342 int __x, __n; \ 343 \ 344 __x = (x); \ 345 __n = (n); \ 346 \ 347 /* If it will wrap around, sync to the end of the ring. */ \ 348 if ((__x + __n) > PCN_NTXDESC) { \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 351 (PCN_NTXDESC - __x), (ops)); \ 352 __n -= (PCN_NTXDESC - __x); \ 353 __x = 0; \ 354 } \ 355 \ 356 /* Now sync whatever is left. */ \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 359 } while (/*CONSTCOND*/0) 360 361 #define PCN_CDRXSYNC(sc, x, ops) \ 362 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 363 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 364 365 #define PCN_CDINITSYNC(sc, ops) \ 366 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 367 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 368 369 #define PCN_INIT_RXDESC(sc, x) \ 370 do { \ 371 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 372 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 373 struct mbuf *__m = __rxs->rxs_mbuf; \ 374 \ 375 /* \ 376 * Note: We scoot the packet forward 2 bytes in the buffer \ 377 * so that the payload after the Ethernet header is aligned \ 378 * to a 4-byte boundary. \ 379 */ \ 380 __m->m_data = __m->m_ext.ext_buf + 2; \ 381 \ 382 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 383 __rmd->rmd2 = \ 384 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 385 __rmd->rmd0 = 0; \ 386 } else { \ 387 __rmd->rmd2 = 0; \ 388 __rmd->rmd0 = \ 389 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 390 } \ 391 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 392 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 393 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 394 } while(/*CONSTCOND*/0) 395 396 static void pcn_start(struct ifnet *); 397 static void pcn_watchdog(struct ifnet *); 398 static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 399 static int pcn_init(struct ifnet *); 400 static void pcn_stop(struct ifnet *, int); 401 402 static void pcn_shutdown(void *); 403 404 static void pcn_reset(struct pcn_softc *); 405 static void pcn_rxdrain(struct pcn_softc *); 406 static int pcn_add_rxbuf(struct pcn_softc *, int); 407 static void pcn_tick(void *); 408 409 static void pcn_spnd(struct pcn_softc *); 410 411 static void pcn_set_filter(struct pcn_softc *); 412 413 static int pcn_intr(void *); 414 static void pcn_txintr(struct pcn_softc *); 415 static int pcn_rxintr(struct pcn_softc *); 416 417 static int pcn_mii_readreg(struct device *, int, int); 418 static void pcn_mii_writereg(struct device *, int, int, int); 419 static void pcn_mii_statchg(struct device *); 420 421 static void pcn_79c970_mediainit(struct pcn_softc *); 422 static int pcn_79c970_mediachange(struct ifnet *); 423 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 424 425 static void pcn_79c971_mediainit(struct pcn_softc *); 426 static int pcn_79c971_mediachange(struct ifnet *); 427 static void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 428 429 /* 430 * Description of a PCnet-PCI variant. Used to select media access 431 * method, mostly, and to print a nice description of the chip. 432 */ 433 static const struct pcn_variant { 434 const char *pcv_desc; 435 void (*pcv_mediainit)(struct pcn_softc *); 436 uint16_t pcv_chipid; 437 } pcn_variants[] = { 438 { "Am79c970 PCnet-PCI", 439 pcn_79c970_mediainit, 440 PARTID_Am79c970 }, 441 442 { "Am79c970A PCnet-PCI II", 443 pcn_79c970_mediainit, 444 PARTID_Am79c970A }, 445 446 { "Am79c971 PCnet-FAST", 447 pcn_79c971_mediainit, 448 PARTID_Am79c971 }, 449 450 { "Am79c972 PCnet-FAST+", 451 pcn_79c971_mediainit, 452 PARTID_Am79c972 }, 453 454 { "Am79c973 PCnet-FAST III", 455 pcn_79c971_mediainit, 456 PARTID_Am79c973 }, 457 458 { "Am79c975 PCnet-FAST III", 459 pcn_79c971_mediainit, 460 PARTID_Am79c975 }, 461 462 { "Unknown PCnet-PCI variant", 463 pcn_79c971_mediainit, 464 0 }, 465 }; 466 467 int pcn_copy_small = 0; 468 469 static int pcn_match(struct device *, struct cfdata *, void *); 470 static void pcn_attach(struct device *, struct device *, void *); 471 472 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 473 pcn_match, pcn_attach, NULL, NULL); 474 475 /* 476 * Routines to read and write the PCnet-PCI CSR/BCR space. 477 */ 478 479 static inline uint32_t 480 pcn_csr_read(struct pcn_softc *sc, int reg) 481 { 482 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 484 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 485 } 486 487 static inline void 488 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 489 { 490 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 493 } 494 495 static inline uint32_t 496 pcn_bcr_read(struct pcn_softc *sc, int reg) 497 { 498 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 500 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 501 } 502 503 static inline void 504 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 505 { 506 507 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 508 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 509 } 510 511 static const struct pcn_variant * 512 pcn_lookup_variant(uint16_t chipid) 513 { 514 const struct pcn_variant *pcv; 515 516 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 517 if (chipid == pcv->pcv_chipid) 518 return (pcv); 519 } 520 521 /* 522 * This covers unknown chips, which we simply treat like 523 * a generic PCnet-FAST. 524 */ 525 return (pcv); 526 } 527 528 static int 529 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 530 { 531 struct pci_attach_args *pa = aux; 532 533 /* 534 * IBM Makes a PCI variant of this card which shows up as a 535 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 536 * this card is truly a pcn card, so we have a special case match for 537 * it 538 */ 539 540 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 541 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 542 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 543 return(1); 544 545 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 546 return (0); 547 548 switch (PCI_PRODUCT(pa->pa_id)) { 549 case PCI_PRODUCT_AMD_PCNET_PCI: 550 /* Beat if_le_pci.c */ 551 return (10); 552 } 553 554 return (0); 555 } 556 557 static void 558 pcn_attach(struct device *parent, struct device *self, void *aux) 559 { 560 struct pcn_softc *sc = (struct pcn_softc *) self; 561 struct pci_attach_args *pa = aux; 562 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 563 pci_chipset_tag_t pc = pa->pa_pc; 564 pci_intr_handle_t ih; 565 const char *intrstr = NULL; 566 bus_space_tag_t iot, memt; 567 bus_space_handle_t ioh, memh; 568 bus_dma_segment_t seg; 569 int ioh_valid, memh_valid; 570 int i, rseg, error; 571 pcireg_t pmode; 572 uint32_t chipid, reg; 573 uint8_t enaddr[ETHER_ADDR_LEN]; 574 int pmreg; 575 576 callout_init(&sc->sc_tick_ch); 577 578 printf(": AMD PCnet-PCI Ethernet\n"); 579 580 /* 581 * Map the device. 582 */ 583 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 584 &iot, &ioh, NULL, NULL) == 0); 585 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 586 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 587 &memt, &memh, NULL, NULL) == 0); 588 589 if (memh_valid) { 590 sc->sc_st = memt; 591 sc->sc_sh = memh; 592 } else if (ioh_valid) { 593 sc->sc_st = iot; 594 sc->sc_sh = ioh; 595 } else { 596 printf("%s: unable to map device registers\n", 597 sc->sc_dev.dv_xname); 598 return; 599 } 600 601 sc->sc_dmat = pa->pa_dmat; 602 603 /* Make sure bus mastering is enabled. */ 604 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 605 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 606 PCI_COMMAND_MASTER_ENABLE); 607 608 /* Get it out of power save mode, if needed. */ 609 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 610 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 611 PCI_PMCSR_STATE_MASK; 612 if (pmode == PCI_PMCSR_STATE_D3) { 613 /* 614 * The card has lost all configuration data in 615 * this state, so punt. 616 */ 617 printf("%s: unable to wake from power state D3\n", 618 sc->sc_dev.dv_xname); 619 return; 620 } 621 if (pmode != PCI_PMCSR_STATE_D0) { 622 printf("%s: waking up from power date D%d\n", 623 sc->sc_dev.dv_xname, pmode); 624 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 625 PCI_PMCSR_STATE_D0); 626 } 627 } 628 629 /* 630 * Reset the chip to a known state. This also puts the 631 * chip into 32-bit mode. 632 */ 633 pcn_reset(sc); 634 635 #if !defined(PCN_NO_PROM) 636 637 /* 638 * Read the Ethernet address from the EEPROM. 639 */ 640 for (i = 0; i < ETHER_ADDR_LEN; i++) 641 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 642 PCN32_APROM + i); 643 #else 644 /* 645 * The PROM is not used; instead we assume that the MAC address 646 * has been programmed into the device's physical address 647 * registers by the boot firmware 648 */ 649 650 for (i=0; i < 3; i++) { 651 uint32_t val; 652 val = pcn_csr_read(sc, LE_CSR12 + i); 653 enaddr[2*i] = val & 0x0ff; 654 enaddr[2*i+1] = (val >> 8) & 0x0ff; 655 } 656 #endif 657 658 /* 659 * Now that the device is mapped, attempt to figure out what 660 * kind of chip we have. Note that IDL has all 32 bits of 661 * the chip ID when we're in 32-bit mode. 662 */ 663 chipid = pcn_csr_read(sc, LE_CSR88); 664 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 665 666 printf("%s: %s rev %d, Ethernet address %s\n", 667 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 668 ether_sprintf(enaddr)); 669 670 /* 671 * Map and establish our interrupt. 672 */ 673 if (pci_intr_map(pa, &ih)) { 674 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 675 return; 676 } 677 intrstr = pci_intr_string(pc, ih); 678 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 679 if (sc->sc_ih == NULL) { 680 printf("%s: unable to establish interrupt", 681 sc->sc_dev.dv_xname); 682 if (intrstr != NULL) 683 printf(" at %s", intrstr); 684 printf("\n"); 685 return; 686 } 687 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 688 689 /* 690 * Allocate the control data structures, and create and load the 691 * DMA map for it. 692 */ 693 if ((error = bus_dmamem_alloc(sc->sc_dmat, 694 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 695 0)) != 0) { 696 printf("%s: unable to allocate control data, error = %d\n", 697 sc->sc_dev.dv_xname, error); 698 goto fail_0; 699 } 700 701 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 702 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 703 BUS_DMA_COHERENT)) != 0) { 704 printf("%s: unable to map control data, error = %d\n", 705 sc->sc_dev.dv_xname, error); 706 goto fail_1; 707 } 708 709 if ((error = bus_dmamap_create(sc->sc_dmat, 710 sizeof(struct pcn_control_data), 1, 711 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 712 printf("%s: unable to create control data DMA map, " 713 "error = %d\n", sc->sc_dev.dv_xname, error); 714 goto fail_2; 715 } 716 717 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 718 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 719 0)) != 0) { 720 printf("%s: unable to load control data DMA map, error = %d\n", 721 sc->sc_dev.dv_xname, error); 722 goto fail_3; 723 } 724 725 /* Create the transmit buffer DMA maps. */ 726 for (i = 0; i < PCN_TXQUEUELEN; i++) { 727 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 728 PCN_NTXSEGS, MCLBYTES, 0, 0, 729 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 730 printf("%s: unable to create tx DMA map %d, " 731 "error = %d\n", sc->sc_dev.dv_xname, i, error); 732 goto fail_4; 733 } 734 } 735 736 /* Create the receive buffer DMA maps. */ 737 for (i = 0; i < PCN_NRXDESC; i++) { 738 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 739 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 740 printf("%s: unable to create rx DMA map %d, " 741 "error = %d\n", sc->sc_dev.dv_xname, i, error); 742 goto fail_5; 743 } 744 sc->sc_rxsoft[i].rxs_mbuf = NULL; 745 } 746 747 /* Initialize our media structures. */ 748 (*sc->sc_variant->pcv_mediainit)(sc); 749 750 /* 751 * Initialize FIFO watermark info. 752 */ 753 switch (sc->sc_variant->pcv_chipid) { 754 case PARTID_Am79c970: 755 case PARTID_Am79c970A: 756 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 757 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 758 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 759 break; 760 761 default: 762 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 763 /* 764 * Read BCR25 to determine how much SRAM is 765 * on the board. If > 0, then we the chip 766 * uses different Start Point thresholds. 767 * 768 * Note BCR25 and BCR26 are loaded from the 769 * EEPROM on RST, and unaffected by S_RESET, 770 * so we don't really have to worry about 771 * them except for this. 772 */ 773 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 774 if (reg != 0) 775 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 776 else 777 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 778 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 779 break; 780 } 781 782 /* 783 * Set up defaults -- see the tables above for what these 784 * values mean. 785 * 786 * XXX How should we tune RCVFW and XMTFW? 787 */ 788 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 789 sc->sc_xmtsp = 1; 790 sc->sc_xmtfw = 0; 791 792 ifp = &sc->sc_ethercom.ec_if; 793 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 794 ifp->if_softc = sc; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = pcn_ioctl; 797 ifp->if_start = pcn_start; 798 ifp->if_watchdog = pcn_watchdog; 799 ifp->if_init = pcn_init; 800 ifp->if_stop = pcn_stop; 801 IFQ_SET_READY(&ifp->if_snd); 802 803 /* Attach the interface. */ 804 if_attach(ifp); 805 ether_ifattach(ifp, enaddr); 806 #if NRND > 0 807 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 808 RND_TYPE_NET, 0); 809 #endif 810 811 #ifdef PCN_EVENT_COUNTERS 812 /* Attach event counters. */ 813 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 814 NULL, sc->sc_dev.dv_xname, "txsstall"); 815 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 816 NULL, sc->sc_dev.dv_xname, "txdstall"); 817 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 818 NULL, sc->sc_dev.dv_xname, "txintr"); 819 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 820 NULL, sc->sc_dev.dv_xname, "rxintr"); 821 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 822 NULL, sc->sc_dev.dv_xname, "babl"); 823 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 824 NULL, sc->sc_dev.dv_xname, "miss"); 825 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 826 NULL, sc->sc_dev.dv_xname, "merr"); 827 828 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 829 NULL, sc->sc_dev.dv_xname, "txseg1"); 830 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 831 NULL, sc->sc_dev.dv_xname, "txseg2"); 832 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 833 NULL, sc->sc_dev.dv_xname, "txseg3"); 834 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 835 NULL, sc->sc_dev.dv_xname, "txseg4"); 836 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 837 NULL, sc->sc_dev.dv_xname, "txseg5"); 838 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 839 NULL, sc->sc_dev.dv_xname, "txsegmore"); 840 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 841 NULL, sc->sc_dev.dv_xname, "txcopy"); 842 #endif /* PCN_EVENT_COUNTERS */ 843 844 /* Make sure the interface is shutdown during reboot. */ 845 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 846 if (sc->sc_sdhook == NULL) 847 printf("%s: WARNING: unable to establish shutdown hook\n", 848 sc->sc_dev.dv_xname); 849 return; 850 851 /* 852 * Free any resources we've allocated during the failed attach 853 * attempt. Do this in reverse order and fall through. 854 */ 855 fail_5: 856 for (i = 0; i < PCN_NRXDESC; i++) { 857 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 858 bus_dmamap_destroy(sc->sc_dmat, 859 sc->sc_rxsoft[i].rxs_dmamap); 860 } 861 fail_4: 862 for (i = 0; i < PCN_TXQUEUELEN; i++) { 863 if (sc->sc_txsoft[i].txs_dmamap != NULL) 864 bus_dmamap_destroy(sc->sc_dmat, 865 sc->sc_txsoft[i].txs_dmamap); 866 } 867 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 868 fail_3: 869 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 870 fail_2: 871 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 872 sizeof(struct pcn_control_data)); 873 fail_1: 874 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 875 fail_0: 876 return; 877 } 878 879 /* 880 * pcn_shutdown: 881 * 882 * Make sure the interface is stopped at reboot time. 883 */ 884 static void 885 pcn_shutdown(void *arg) 886 { 887 struct pcn_softc *sc = arg; 888 889 pcn_stop(&sc->sc_ethercom.ec_if, 1); 890 } 891 892 /* 893 * pcn_start: [ifnet interface function] 894 * 895 * Start packet transmission on the interface. 896 */ 897 static void 898 pcn_start(struct ifnet *ifp) 899 { 900 struct pcn_softc *sc = ifp->if_softc; 901 struct mbuf *m0, *m; 902 struct pcn_txsoft *txs; 903 bus_dmamap_t dmamap; 904 int error, nexttx, lasttx = -1, ofree, seg; 905 906 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 907 return; 908 909 /* 910 * Remember the previous number of free descriptors and 911 * the first descriptor we'll use. 912 */ 913 ofree = sc->sc_txfree; 914 915 /* 916 * Loop through the send queue, setting up transmit descriptors 917 * until we drain the queue, or use up all available transmit 918 * descriptors. 919 */ 920 for (;;) { 921 /* Grab a packet off the queue. */ 922 IFQ_POLL(&ifp->if_snd, m0); 923 if (m0 == NULL) 924 break; 925 m = NULL; 926 927 /* Get a work queue entry. */ 928 if (sc->sc_txsfree == 0) { 929 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 930 break; 931 } 932 933 txs = &sc->sc_txsoft[sc->sc_txsnext]; 934 dmamap = txs->txs_dmamap; 935 936 /* 937 * Load the DMA map. If this fails, the packet either 938 * didn't fit in the alloted number of segments, or we 939 * were short on resources. In this case, we'll copy 940 * and try again. 941 */ 942 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 943 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 944 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 945 MGETHDR(m, M_DONTWAIT, MT_DATA); 946 if (m == NULL) { 947 printf("%s: unable to allocate Tx mbuf\n", 948 sc->sc_dev.dv_xname); 949 break; 950 } 951 if (m0->m_pkthdr.len > MHLEN) { 952 MCLGET(m, M_DONTWAIT); 953 if ((m->m_flags & M_EXT) == 0) { 954 printf("%s: unable to allocate Tx " 955 "cluster\n", sc->sc_dev.dv_xname); 956 m_freem(m); 957 break; 958 } 959 } 960 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 961 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 962 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 963 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 964 if (error) { 965 printf("%s: unable to load Tx buffer, " 966 "error = %d\n", sc->sc_dev.dv_xname, error); 967 break; 968 } 969 } 970 971 /* 972 * Ensure we have enough descriptors free to describe 973 * the packet. Note, we always reserve one descriptor 974 * at the end of the ring as a termination point, to 975 * prevent wrap-around. 976 */ 977 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 978 /* 979 * Not enough free descriptors to transmit this 980 * packet. We haven't committed anything yet, 981 * so just unload the DMA map, put the packet 982 * back on the queue, and punt. Notify the upper 983 * layer that there are not more slots left. 984 * 985 * XXX We could allocate an mbuf and copy, but 986 * XXX is it worth it? 987 */ 988 ifp->if_flags |= IFF_OACTIVE; 989 bus_dmamap_unload(sc->sc_dmat, dmamap); 990 if (m != NULL) 991 m_freem(m); 992 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 993 break; 994 } 995 996 IFQ_DEQUEUE(&ifp->if_snd, m0); 997 if (m != NULL) { 998 m_freem(m0); 999 m0 = m; 1000 } 1001 1002 /* 1003 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1004 */ 1005 1006 /* Sync the DMA map. */ 1007 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1008 BUS_DMASYNC_PREWRITE); 1009 1010 #ifdef PCN_EVENT_COUNTERS 1011 switch (dmamap->dm_nsegs) { 1012 case 1: 1013 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1014 break; 1015 case 2: 1016 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1017 break; 1018 case 3: 1019 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1020 break; 1021 case 4: 1022 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1023 break; 1024 case 5: 1025 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1026 break; 1027 default: 1028 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1029 break; 1030 } 1031 #endif /* PCN_EVENT_COUNTERS */ 1032 1033 /* 1034 * Initialize the transmit descriptors. 1035 */ 1036 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1037 for (nexttx = sc->sc_txnext, seg = 0; 1038 seg < dmamap->dm_nsegs; 1039 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1040 /* 1041 * If this is the first descriptor we're 1042 * enqueueing, don't set the OWN bit just 1043 * yet. That could cause a race condition. 1044 * We'll do it below. 1045 */ 1046 sc->sc_txdescs[nexttx].tmd0 = 0; 1047 sc->sc_txdescs[nexttx].tmd2 = 1048 htole32(dmamap->dm_segs[seg].ds_addr); 1049 sc->sc_txdescs[nexttx].tmd1 = 1050 htole32(LE_T1_ONES | 1051 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1052 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1053 LE_T1_BCNT_MASK)); 1054 lasttx = nexttx; 1055 } 1056 } else { 1057 for (nexttx = sc->sc_txnext, seg = 0; 1058 seg < dmamap->dm_nsegs; 1059 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1060 /* 1061 * If this is the first descriptor we're 1062 * enqueueing, don't set the OWN bit just 1063 * yet. That could cause a race condition. 1064 * We'll do it below. 1065 */ 1066 sc->sc_txdescs[nexttx].tmd0 = 1067 htole32(dmamap->dm_segs[seg].ds_addr); 1068 sc->sc_txdescs[nexttx].tmd2 = 0; 1069 sc->sc_txdescs[nexttx].tmd1 = 1070 htole32(LE_T1_ONES | 1071 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1072 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1073 LE_T1_BCNT_MASK)); 1074 lasttx = nexttx; 1075 } 1076 } 1077 1078 KASSERT(lasttx != -1); 1079 /* Interrupt on the packet, if appropriate. */ 1080 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1081 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1082 1083 /* Set `start of packet' and `end of packet' appropriately. */ 1084 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1085 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1086 htole32(LE_T1_OWN|LE_T1_STP); 1087 1088 /* Sync the descriptors we're using. */ 1089 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1091 1092 /* Kick the transmitter. */ 1093 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1094 1095 /* 1096 * Store a pointer to the packet so we can free it later, 1097 * and remember what txdirty will be once the packet is 1098 * done. 1099 */ 1100 txs->txs_mbuf = m0; 1101 txs->txs_firstdesc = sc->sc_txnext; 1102 txs->txs_lastdesc = lasttx; 1103 1104 /* Advance the tx pointer. */ 1105 sc->sc_txfree -= dmamap->dm_nsegs; 1106 sc->sc_txnext = nexttx; 1107 1108 sc->sc_txsfree--; 1109 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1110 1111 #if NBPFILTER > 0 1112 /* Pass the packet to any BPF listeners. */ 1113 if (ifp->if_bpf) 1114 bpf_mtap(ifp->if_bpf, m0); 1115 #endif /* NBPFILTER > 0 */ 1116 } 1117 1118 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1119 /* No more slots left; notify upper layer. */ 1120 ifp->if_flags |= IFF_OACTIVE; 1121 } 1122 1123 if (sc->sc_txfree != ofree) { 1124 /* Set a watchdog timer in case the chip flakes out. */ 1125 ifp->if_timer = 5; 1126 } 1127 } 1128 1129 /* 1130 * pcn_watchdog: [ifnet interface function] 1131 * 1132 * Watchdog timer handler. 1133 */ 1134 static void 1135 pcn_watchdog(struct ifnet *ifp) 1136 { 1137 struct pcn_softc *sc = ifp->if_softc; 1138 1139 /* 1140 * Since we're not interrupting every packet, sweep 1141 * up before we report an error. 1142 */ 1143 pcn_txintr(sc); 1144 1145 if (sc->sc_txfree != PCN_NTXDESC) { 1146 printf("%s: device timeout (txfree %d txsfree %d)\n", 1147 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1148 ifp->if_oerrors++; 1149 1150 /* Reset the interface. */ 1151 (void) pcn_init(ifp); 1152 } 1153 1154 /* Try to get more packets going. */ 1155 pcn_start(ifp); 1156 } 1157 1158 /* 1159 * pcn_ioctl: [ifnet interface function] 1160 * 1161 * Handle control requests from the operator. 1162 */ 1163 static int 1164 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1165 { 1166 struct pcn_softc *sc = ifp->if_softc; 1167 struct ifreq *ifr = (struct ifreq *) data; 1168 int s, error; 1169 1170 s = splnet(); 1171 1172 switch (cmd) { 1173 case SIOCSIFMEDIA: 1174 case SIOCGIFMEDIA: 1175 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1176 break; 1177 1178 default: 1179 error = ether_ioctl(ifp, cmd, data); 1180 if (error == ENETRESET) { 1181 /* 1182 * Multicast list has changed; set the hardware filter 1183 * accordingly. 1184 */ 1185 if (ifp->if_flags & IFF_RUNNING) 1186 error = pcn_init(ifp); 1187 else 1188 error = 0; 1189 } 1190 break; 1191 } 1192 1193 /* Try to get more packets going. */ 1194 pcn_start(ifp); 1195 1196 splx(s); 1197 return (error); 1198 } 1199 1200 /* 1201 * pcn_intr: 1202 * 1203 * Interrupt service routine. 1204 */ 1205 static int 1206 pcn_intr(void *arg) 1207 { 1208 struct pcn_softc *sc = arg; 1209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1210 uint32_t csr0; 1211 int wantinit, handled = 0; 1212 1213 for (wantinit = 0; wantinit == 0;) { 1214 csr0 = pcn_csr_read(sc, LE_CSR0); 1215 if ((csr0 & LE_C0_INTR) == 0) 1216 break; 1217 1218 #if NRND > 0 1219 if (RND_ENABLED(&sc->rnd_source)) 1220 rnd_add_uint32(&sc->rnd_source, csr0); 1221 #endif 1222 1223 /* ACK the bits and re-enable interrupts. */ 1224 pcn_csr_write(sc, LE_CSR0, csr0 & 1225 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1226 LE_C0_TINT|LE_C0_IDON)); 1227 1228 handled = 1; 1229 1230 if (csr0 & LE_C0_RINT) { 1231 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1232 wantinit = pcn_rxintr(sc); 1233 } 1234 1235 if (csr0 & LE_C0_TINT) { 1236 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1237 pcn_txintr(sc); 1238 } 1239 1240 if (csr0 & LE_C0_ERR) { 1241 if (csr0 & LE_C0_BABL) { 1242 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1243 ifp->if_oerrors++; 1244 } 1245 if (csr0 & LE_C0_MISS) { 1246 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1247 ifp->if_ierrors++; 1248 } 1249 if (csr0 & LE_C0_MERR) { 1250 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1251 printf("%s: memory error\n", 1252 sc->sc_dev.dv_xname); 1253 wantinit = 1; 1254 break; 1255 } 1256 } 1257 1258 if ((csr0 & LE_C0_RXON) == 0) { 1259 printf("%s: receiver disabled\n", 1260 sc->sc_dev.dv_xname); 1261 ifp->if_ierrors++; 1262 wantinit = 1; 1263 } 1264 1265 if ((csr0 & LE_C0_TXON) == 0) { 1266 printf("%s: transmitter disabled\n", 1267 sc->sc_dev.dv_xname); 1268 ifp->if_oerrors++; 1269 wantinit = 1; 1270 } 1271 } 1272 1273 if (handled) { 1274 if (wantinit) 1275 pcn_init(ifp); 1276 1277 /* Try to get more packets going. */ 1278 pcn_start(ifp); 1279 } 1280 1281 return (handled); 1282 } 1283 1284 /* 1285 * pcn_spnd: 1286 * 1287 * Suspend the chip. 1288 */ 1289 static void 1290 pcn_spnd(struct pcn_softc *sc) 1291 { 1292 int i; 1293 1294 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1295 1296 for (i = 0; i < 10000; i++) { 1297 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1298 return; 1299 delay(5); 1300 } 1301 1302 printf("%s: WARNING: chip failed to enter suspended state\n", 1303 sc->sc_dev.dv_xname); 1304 } 1305 1306 /* 1307 * pcn_txintr: 1308 * 1309 * Helper; handle transmit interrupts. 1310 */ 1311 static void 1312 pcn_txintr(struct pcn_softc *sc) 1313 { 1314 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1315 struct pcn_txsoft *txs; 1316 uint32_t tmd1, tmd2, tmd; 1317 int i, j; 1318 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 /* 1322 * Go through our Tx list and free mbufs for those 1323 * frames which have been transmitted. 1324 */ 1325 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1326 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1327 txs = &sc->sc_txsoft[i]; 1328 1329 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1330 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1331 1332 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1333 if (tmd1 & LE_T1_OWN) 1334 break; 1335 1336 /* 1337 * Slightly annoying -- we have to loop through the 1338 * descriptors we've used looking for ERR, since it 1339 * can appear on any descriptor in the chain. 1340 */ 1341 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1342 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1343 if (tmd & LE_T1_ERR) { 1344 ifp->if_oerrors++; 1345 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1346 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1347 else 1348 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1349 if (tmd2 & LE_T2_UFLO) { 1350 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1351 sc->sc_xmtsp++; 1352 printf("%s: transmit " 1353 "underrun; new threshold: " 1354 "%s\n", 1355 sc->sc_dev.dv_xname, 1356 sc->sc_xmtsp_desc[ 1357 sc->sc_xmtsp]); 1358 pcn_spnd(sc); 1359 pcn_csr_write(sc, LE_CSR80, 1360 LE_C80_RCVFW(sc->sc_rcvfw) | 1361 LE_C80_XMTSP(sc->sc_xmtsp) | 1362 LE_C80_XMTFW(sc->sc_xmtfw)); 1363 pcn_csr_write(sc, LE_CSR5, 1364 sc->sc_csr5); 1365 } else { 1366 printf("%s: transmit " 1367 "underrun\n", 1368 sc->sc_dev.dv_xname); 1369 } 1370 } else if (tmd2 & LE_T2_BUFF) { 1371 printf("%s: transmit buffer error\n", 1372 sc->sc_dev.dv_xname); 1373 } 1374 if (tmd2 & LE_T2_LCOL) 1375 ifp->if_collisions++; 1376 if (tmd2 & LE_T2_RTRY) 1377 ifp->if_collisions += 16; 1378 goto next_packet; 1379 } 1380 if (j == txs->txs_lastdesc) 1381 break; 1382 } 1383 if (tmd1 & LE_T1_ONE) 1384 ifp->if_collisions++; 1385 else if (tmd & LE_T1_MORE) { 1386 /* Real number is unknown. */ 1387 ifp->if_collisions += 2; 1388 } 1389 ifp->if_opackets++; 1390 next_packet: 1391 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1392 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1393 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1394 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1395 m_freem(txs->txs_mbuf); 1396 txs->txs_mbuf = NULL; 1397 } 1398 1399 /* Update the dirty transmit buffer pointer. */ 1400 sc->sc_txsdirty = i; 1401 1402 /* 1403 * If there are no more pending transmissions, cancel the watchdog 1404 * timer. 1405 */ 1406 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1407 ifp->if_timer = 0; 1408 } 1409 1410 /* 1411 * pcn_rxintr: 1412 * 1413 * Helper; handle receive interrupts. 1414 */ 1415 static int 1416 pcn_rxintr(struct pcn_softc *sc) 1417 { 1418 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1419 struct pcn_rxsoft *rxs; 1420 struct mbuf *m; 1421 uint32_t rmd1; 1422 int i, len; 1423 1424 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1425 rxs = &sc->sc_rxsoft[i]; 1426 1427 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1428 1429 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1430 1431 if (rmd1 & LE_R1_OWN) 1432 break; 1433 1434 /* 1435 * Check for errors and make sure the packet fit into 1436 * a single buffer. We have structured this block of 1437 * code the way it is in order to compress it into 1438 * one test in the common case (no error). 1439 */ 1440 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1441 (LE_R1_STP|LE_R1_ENP))) { 1442 /* Make sure the packet is in a single buffer. */ 1443 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1444 (LE_R1_STP|LE_R1_ENP)) { 1445 printf("%s: packet spilled into next buffer\n", 1446 sc->sc_dev.dv_xname); 1447 return (1); /* pcn_intr() will re-init */ 1448 } 1449 1450 /* 1451 * If the packet had an error, simple recycle the 1452 * buffer. 1453 */ 1454 if (rmd1 & LE_R1_ERR) { 1455 ifp->if_ierrors++; 1456 /* 1457 * If we got an overflow error, chances 1458 * are there will be a CRC error. In 1459 * this case, just print the overflow 1460 * error, and skip the others. 1461 */ 1462 if (rmd1 & LE_R1_OFLO) 1463 printf("%s: overflow error\n", 1464 sc->sc_dev.dv_xname); 1465 else { 1466 #define PRINTIT(x, str) \ 1467 if (rmd1 & (x)) \ 1468 printf("%s: %s\n", \ 1469 sc->sc_dev.dv_xname, str); 1470 PRINTIT(LE_R1_FRAM, "framing error"); 1471 PRINTIT(LE_R1_CRC, "CRC error"); 1472 PRINTIT(LE_R1_BUFF, "buffer error"); 1473 } 1474 #undef PRINTIT 1475 PCN_INIT_RXDESC(sc, i); 1476 continue; 1477 } 1478 } 1479 1480 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1481 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1482 1483 /* 1484 * No errors; receive the packet. 1485 */ 1486 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1487 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1488 else 1489 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1490 1491 /* 1492 * The LANCE family includes the CRC with every packet; 1493 * trim it off here. 1494 */ 1495 len -= ETHER_CRC_LEN; 1496 1497 /* 1498 * If the packet is small enough to fit in a 1499 * single header mbuf, allocate one and copy 1500 * the data into it. This greatly reduces 1501 * memory consumption when we receive lots 1502 * of small packets. 1503 * 1504 * Otherwise, we add a new buffer to the receive 1505 * chain. If this fails, we drop the packet and 1506 * recycle the old buffer. 1507 */ 1508 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1509 MGETHDR(m, M_DONTWAIT, MT_DATA); 1510 if (m == NULL) 1511 goto dropit; 1512 m->m_data += 2; 1513 memcpy(mtod(m, caddr_t), 1514 mtod(rxs->rxs_mbuf, caddr_t), len); 1515 PCN_INIT_RXDESC(sc, i); 1516 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1517 rxs->rxs_dmamap->dm_mapsize, 1518 BUS_DMASYNC_PREREAD); 1519 } else { 1520 m = rxs->rxs_mbuf; 1521 if (pcn_add_rxbuf(sc, i) != 0) { 1522 dropit: 1523 ifp->if_ierrors++; 1524 PCN_INIT_RXDESC(sc, i); 1525 bus_dmamap_sync(sc->sc_dmat, 1526 rxs->rxs_dmamap, 0, 1527 rxs->rxs_dmamap->dm_mapsize, 1528 BUS_DMASYNC_PREREAD); 1529 continue; 1530 } 1531 } 1532 1533 m->m_pkthdr.rcvif = ifp; 1534 m->m_pkthdr.len = m->m_len = len; 1535 1536 #if NBPFILTER > 0 1537 /* Pass this up to any BPF listeners. */ 1538 if (ifp->if_bpf) 1539 bpf_mtap(ifp->if_bpf, m); 1540 #endif /* NBPFILTER > 0 */ 1541 1542 /* Pass it on. */ 1543 (*ifp->if_input)(ifp, m); 1544 ifp->if_ipackets++; 1545 } 1546 1547 /* Update the receive pointer. */ 1548 sc->sc_rxptr = i; 1549 return (0); 1550 } 1551 1552 /* 1553 * pcn_tick: 1554 * 1555 * One second timer, used to tick the MII. 1556 */ 1557 static void 1558 pcn_tick(void *arg) 1559 { 1560 struct pcn_softc *sc = arg; 1561 int s; 1562 1563 s = splnet(); 1564 mii_tick(&sc->sc_mii); 1565 splx(s); 1566 1567 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1568 } 1569 1570 /* 1571 * pcn_reset: 1572 * 1573 * Perform a soft reset on the PCnet-PCI. 1574 */ 1575 static void 1576 pcn_reset(struct pcn_softc *sc) 1577 { 1578 1579 /* 1580 * The PCnet-PCI chip is reset by reading from the 1581 * RESET register. Note that while the NE2100 LANCE 1582 * boards require a write after the read, the PCnet-PCI 1583 * chips do not require this. 1584 * 1585 * Since we don't know if we're in 16-bit or 32-bit 1586 * mode right now, issue both (it's safe) in the 1587 * hopes that one will succeed. 1588 */ 1589 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1590 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1591 1592 /* Wait 1ms for it to finish. */ 1593 delay(1000); 1594 1595 /* 1596 * Select 32-bit I/O mode by issuing a 32-bit write to the 1597 * RDP. Since the RAP is 0 after a reset, writing a 0 1598 * to RDP is safe (since it simply clears CSR0). 1599 */ 1600 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1601 } 1602 1603 /* 1604 * pcn_init: [ifnet interface function] 1605 * 1606 * Initialize the interface. Must be called at splnet(). 1607 */ 1608 static int 1609 pcn_init(struct ifnet *ifp) 1610 { 1611 struct pcn_softc *sc = ifp->if_softc; 1612 struct pcn_rxsoft *rxs; 1613 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1614 int i, error = 0; 1615 uint32_t reg; 1616 1617 /* Cancel any pending I/O. */ 1618 pcn_stop(ifp, 0); 1619 1620 /* Reset the chip to a known state. */ 1621 pcn_reset(sc); 1622 1623 /* 1624 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1625 * else. 1626 * 1627 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1628 * because the structure layout is compatible with ILACC, 1629 * but the burst mode is only available in SSTYLE 3, and 1630 * burst mode should provide some performance enhancement. 1631 */ 1632 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1633 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1634 else 1635 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1636 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1637 1638 /* Initialize the transmit descriptor ring. */ 1639 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1640 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1641 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1642 sc->sc_txfree = PCN_NTXDESC; 1643 sc->sc_txnext = 0; 1644 1645 /* Initialize the transmit job descriptors. */ 1646 for (i = 0; i < PCN_TXQUEUELEN; i++) 1647 sc->sc_txsoft[i].txs_mbuf = NULL; 1648 sc->sc_txsfree = PCN_TXQUEUELEN; 1649 sc->sc_txsnext = 0; 1650 sc->sc_txsdirty = 0; 1651 1652 /* 1653 * Initialize the receive descriptor and receive job 1654 * descriptor rings. 1655 */ 1656 for (i = 0; i < PCN_NRXDESC; i++) { 1657 rxs = &sc->sc_rxsoft[i]; 1658 if (rxs->rxs_mbuf == NULL) { 1659 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1660 printf("%s: unable to allocate or map rx " 1661 "buffer %d, error = %d\n", 1662 sc->sc_dev.dv_xname, i, error); 1663 /* 1664 * XXX Should attempt to run with fewer receive 1665 * XXX buffers instead of just failing. 1666 */ 1667 pcn_rxdrain(sc); 1668 goto out; 1669 } 1670 } else 1671 PCN_INIT_RXDESC(sc, i); 1672 } 1673 sc->sc_rxptr = 0; 1674 1675 /* Initialize MODE for the initialization block. */ 1676 sc->sc_mode = 0; 1677 if (ifp->if_flags & IFF_PROMISC) 1678 sc->sc_mode |= LE_C15_PROM; 1679 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1680 sc->sc_mode |= LE_C15_DRCVBC; 1681 1682 /* 1683 * If we have MII, simply select MII in the MODE register, 1684 * and clear ASEL. Otherwise, let ASEL stand (for now), 1685 * and leave PORTSEL alone (it is ignored with ASEL is set). 1686 */ 1687 if (sc->sc_flags & PCN_F_HAS_MII) { 1688 pcn_bcr_write(sc, LE_BCR2, 1689 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1690 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1691 1692 /* 1693 * Disable MII auto-negotiation. We handle that in 1694 * our own MII layer. 1695 */ 1696 pcn_bcr_write(sc, LE_BCR32, 1697 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1698 } 1699 1700 /* 1701 * Set the Tx and Rx descriptor ring addresses in the init 1702 * block, the TLEN and RLEN other fields of the init block 1703 * MODE register. 1704 */ 1705 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1706 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1707 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1708 ((ffs(PCN_NTXDESC) - 1) << 28) | 1709 ((ffs(PCN_NRXDESC) - 1) << 20)); 1710 1711 /* Set the station address in the init block. */ 1712 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1713 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1714 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1715 (enaddr[5] << 8)); 1716 1717 /* Set the multicast filter in the init block. */ 1718 pcn_set_filter(sc); 1719 1720 /* Initialize CSR3. */ 1721 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1722 1723 /* Initialize CSR4. */ 1724 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1725 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1726 1727 /* Initialize CSR5. */ 1728 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1729 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1730 1731 /* 1732 * If we have an Am79c971 or greater, initialize CSR7. 1733 * 1734 * XXX Might be nice to use the MII auto-poll interrupt someday. 1735 */ 1736 switch (sc->sc_variant->pcv_chipid) { 1737 case PARTID_Am79c970: 1738 case PARTID_Am79c970A: 1739 /* Not available on these chips. */ 1740 break; 1741 1742 default: 1743 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1744 break; 1745 } 1746 1747 /* 1748 * On the Am79c970A and greater, initialize BCR18 to 1749 * enable burst mode. 1750 * 1751 * Also enable the "no underflow" option on the Am79c971 and 1752 * higher, which prevents the chip from generating transmit 1753 * underflows, yet sill provides decent performance. Note if 1754 * chip is not connected to external SRAM, then we still have 1755 * to handle underflow errors (the NOUFLO bit is ignored in 1756 * that case). 1757 */ 1758 reg = pcn_bcr_read(sc, LE_BCR18); 1759 switch (sc->sc_variant->pcv_chipid) { 1760 case PARTID_Am79c970: 1761 break; 1762 1763 case PARTID_Am79c970A: 1764 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1765 break; 1766 1767 default: 1768 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1769 break; 1770 } 1771 pcn_bcr_write(sc, LE_BCR18, reg); 1772 1773 /* 1774 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1775 */ 1776 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1777 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1778 1779 /* 1780 * Send the init block to the chip, and wait for it 1781 * to be processed. 1782 */ 1783 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1784 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1785 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1786 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1787 delay(100); 1788 for (i = 0; i < 10000; i++) { 1789 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1790 break; 1791 delay(10); 1792 } 1793 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1794 if (i == 10000) { 1795 printf("%s: timeout processing init block\n", 1796 sc->sc_dev.dv_xname); 1797 error = EIO; 1798 goto out; 1799 } 1800 1801 /* Set the media. */ 1802 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1803 1804 /* Enable interrupts and external activity (and ACK IDON). */ 1805 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1806 1807 if (sc->sc_flags & PCN_F_HAS_MII) { 1808 /* Start the one second MII clock. */ 1809 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1810 } 1811 1812 /* ...all done! */ 1813 ifp->if_flags |= IFF_RUNNING; 1814 ifp->if_flags &= ~IFF_OACTIVE; 1815 1816 out: 1817 if (error) 1818 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1819 return (error); 1820 } 1821 1822 /* 1823 * pcn_rxdrain: 1824 * 1825 * Drain the receive queue. 1826 */ 1827 static void 1828 pcn_rxdrain(struct pcn_softc *sc) 1829 { 1830 struct pcn_rxsoft *rxs; 1831 int i; 1832 1833 for (i = 0; i < PCN_NRXDESC; i++) { 1834 rxs = &sc->sc_rxsoft[i]; 1835 if (rxs->rxs_mbuf != NULL) { 1836 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1837 m_freem(rxs->rxs_mbuf); 1838 rxs->rxs_mbuf = NULL; 1839 } 1840 } 1841 } 1842 1843 /* 1844 * pcn_stop: [ifnet interface function] 1845 * 1846 * Stop transmission on the interface. 1847 */ 1848 static void 1849 pcn_stop(struct ifnet *ifp, int disable) 1850 { 1851 struct pcn_softc *sc = ifp->if_softc; 1852 struct pcn_txsoft *txs; 1853 int i; 1854 1855 if (sc->sc_flags & PCN_F_HAS_MII) { 1856 /* Stop the one second clock. */ 1857 callout_stop(&sc->sc_tick_ch); 1858 1859 /* Down the MII. */ 1860 mii_down(&sc->sc_mii); 1861 } 1862 1863 /* Stop the chip. */ 1864 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1865 1866 /* Release any queued transmit buffers. */ 1867 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1868 txs = &sc->sc_txsoft[i]; 1869 if (txs->txs_mbuf != NULL) { 1870 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1871 m_freem(txs->txs_mbuf); 1872 txs->txs_mbuf = NULL; 1873 } 1874 } 1875 1876 if (disable) 1877 pcn_rxdrain(sc); 1878 1879 /* Mark the interface as down and cancel the watchdog timer. */ 1880 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1881 ifp->if_timer = 0; 1882 } 1883 1884 /* 1885 * pcn_add_rxbuf: 1886 * 1887 * Add a receive buffer to the indicated descriptor. 1888 */ 1889 static int 1890 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1891 { 1892 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1893 struct mbuf *m; 1894 int error; 1895 1896 MGETHDR(m, M_DONTWAIT, MT_DATA); 1897 if (m == NULL) 1898 return (ENOBUFS); 1899 1900 MCLGET(m, M_DONTWAIT); 1901 if ((m->m_flags & M_EXT) == 0) { 1902 m_freem(m); 1903 return (ENOBUFS); 1904 } 1905 1906 if (rxs->rxs_mbuf != NULL) 1907 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1908 1909 rxs->rxs_mbuf = m; 1910 1911 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1912 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1913 BUS_DMA_READ|BUS_DMA_NOWAIT); 1914 if (error) { 1915 printf("%s: can't load rx DMA map %d, error = %d\n", 1916 sc->sc_dev.dv_xname, idx, error); 1917 panic("pcn_add_rxbuf"); 1918 } 1919 1920 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1921 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1922 1923 PCN_INIT_RXDESC(sc, idx); 1924 1925 return (0); 1926 } 1927 1928 /* 1929 * pcn_set_filter: 1930 * 1931 * Set up the receive filter. 1932 */ 1933 static void 1934 pcn_set_filter(struct pcn_softc *sc) 1935 { 1936 struct ethercom *ec = &sc->sc_ethercom; 1937 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1938 struct ether_multi *enm; 1939 struct ether_multistep step; 1940 uint32_t crc; 1941 1942 /* 1943 * Set up the multicast address filter by passing all multicast 1944 * addresses through a CRC generator, and then using the high 1945 * order 6 bits as an index into the 64-bit logical address 1946 * filter. The high order bits select the word, while the rest 1947 * of the bits select the bit within the word. 1948 */ 1949 1950 if (ifp->if_flags & IFF_PROMISC) 1951 goto allmulti; 1952 1953 sc->sc_initblock.init_ladrf[0] = 1954 sc->sc_initblock.init_ladrf[1] = 1955 sc->sc_initblock.init_ladrf[2] = 1956 sc->sc_initblock.init_ladrf[3] = 0; 1957 1958 ETHER_FIRST_MULTI(step, ec, enm); 1959 while (enm != NULL) { 1960 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1961 /* 1962 * We must listen to a range of multicast addresses. 1963 * For now, just accept all multicasts, rather than 1964 * trying to set only those filter bits needed to match 1965 * the range. (At this time, the only use of address 1966 * ranges is for IP multicast routing, for which the 1967 * range is big enough to require all bits set.) 1968 */ 1969 goto allmulti; 1970 } 1971 1972 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1973 1974 /* Just want the 6 most significant bits. */ 1975 crc >>= 26; 1976 1977 /* Set the corresponding bit in the filter. */ 1978 sc->sc_initblock.init_ladrf[crc >> 4] |= 1979 htole16(1 << (crc & 0xf)); 1980 1981 ETHER_NEXT_MULTI(step, enm); 1982 } 1983 1984 ifp->if_flags &= ~IFF_ALLMULTI; 1985 return; 1986 1987 allmulti: 1988 ifp->if_flags |= IFF_ALLMULTI; 1989 sc->sc_initblock.init_ladrf[0] = 1990 sc->sc_initblock.init_ladrf[1] = 1991 sc->sc_initblock.init_ladrf[2] = 1992 sc->sc_initblock.init_ladrf[3] = 0xffff; 1993 } 1994 1995 /* 1996 * pcn_79c970_mediainit: 1997 * 1998 * Initialize media for the Am79c970. 1999 */ 2000 static void 2001 pcn_79c970_mediainit(struct pcn_softc *sc) 2002 { 2003 const char *sep = ""; 2004 2005 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2006 pcn_79c970_mediastatus); 2007 2008 #define ADD(str, m, d) \ 2009 do { \ 2010 printf("%s%s", sep, str); \ 2011 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2012 sep = ", "; \ 2013 } while (/*CONSTCOND*/0) 2014 2015 printf("%s: ", sc->sc_dev.dv_xname); 2016 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2017 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2018 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2019 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2020 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2021 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2022 ADD("auto", IFM_AUTO, 0); 2023 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2024 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2025 printf("\n"); 2026 2027 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2028 } 2029 2030 /* 2031 * pcn_79c970_mediastatus: [ifmedia interface function] 2032 * 2033 * Get the current interface media status (Am79c970 version). 2034 */ 2035 static void 2036 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2037 { 2038 struct pcn_softc *sc = ifp->if_softc; 2039 2040 /* 2041 * The currently selected media is always the active media. 2042 * Note: We have no way to determine what media the AUTO 2043 * process picked. 2044 */ 2045 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2046 } 2047 2048 /* 2049 * pcn_79c970_mediachange: [ifmedia interface function] 2050 * 2051 * Set hardware to newly-selected media (Am79c970 version). 2052 */ 2053 static int 2054 pcn_79c970_mediachange(struct ifnet *ifp) 2055 { 2056 struct pcn_softc *sc = ifp->if_softc; 2057 uint32_t reg; 2058 2059 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2060 /* 2061 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2062 */ 2063 reg = pcn_bcr_read(sc, LE_BCR2); 2064 reg |= LE_B2_ASEL; 2065 pcn_bcr_write(sc, LE_BCR2, reg); 2066 } else { 2067 /* 2068 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2069 */ 2070 reg = pcn_bcr_read(sc, LE_BCR2); 2071 reg &= ~LE_B2_ASEL; 2072 pcn_bcr_write(sc, LE_BCR2, reg); 2073 2074 reg = pcn_csr_read(sc, LE_CSR15); 2075 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2076 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2077 pcn_csr_write(sc, LE_CSR15, reg); 2078 } 2079 2080 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2081 reg = LE_B9_FDEN; 2082 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2083 reg |= LE_B9_AUIFD; 2084 pcn_bcr_write(sc, LE_BCR9, reg); 2085 } else 2086 pcn_bcr_write(sc, LE_BCR9, 0); 2087 2088 return (0); 2089 } 2090 2091 /* 2092 * pcn_79c971_mediainit: 2093 * 2094 * Initialize media for the Am79c971. 2095 */ 2096 static void 2097 pcn_79c971_mediainit(struct pcn_softc *sc) 2098 { 2099 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2100 2101 /* We have MII. */ 2102 sc->sc_flags |= PCN_F_HAS_MII; 2103 2104 /* 2105 * The built-in 10BASE-T interface is mapped to the MII 2106 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2107 * word that tells us which PHY to use. 2108 * This driver used to ignore all but the first PHY to 2109 * answer, but this code was removed to support multiple 2110 * external PHYs. As the default instance will be the first 2111 * one to answer, no harm is done by letting the possibly 2112 * non-connected internal PHY show up. 2113 */ 2114 2115 /* Initialize our media structures and probe the MII. */ 2116 sc->sc_mii.mii_ifp = ifp; 2117 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2118 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2119 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2120 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2121 pcn_79c971_mediastatus); 2122 2123 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2124 MII_OFFSET_ANY, 0); 2125 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2126 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2127 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2128 } else 2129 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2130 } 2131 2132 /* 2133 * pcn_79c971_mediastatus: [ifmedia interface function] 2134 * 2135 * Get the current interface media status (Am79c971 version). 2136 */ 2137 static void 2138 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2139 { 2140 struct pcn_softc *sc = ifp->if_softc; 2141 2142 mii_pollstat(&sc->sc_mii); 2143 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2144 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2145 } 2146 2147 /* 2148 * pcn_79c971_mediachange: [ifmedia interface function] 2149 * 2150 * Set hardware to newly-selected media (Am79c971 version). 2151 */ 2152 static int 2153 pcn_79c971_mediachange(struct ifnet *ifp) 2154 { 2155 struct pcn_softc *sc = ifp->if_softc; 2156 2157 if (ifp->if_flags & IFF_UP) 2158 mii_mediachg(&sc->sc_mii); 2159 return (0); 2160 } 2161 2162 /* 2163 * pcn_mii_readreg: [mii interface function] 2164 * 2165 * Read a PHY register on the MII. 2166 */ 2167 static int 2168 pcn_mii_readreg(struct device *self, int phy, int reg) 2169 { 2170 struct pcn_softc *sc = (void *) self; 2171 uint32_t rv; 2172 2173 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2174 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2175 if (rv == 0xffff) 2176 return (0); 2177 2178 return (rv); 2179 } 2180 2181 /* 2182 * pcn_mii_writereg: [mii interface function] 2183 * 2184 * Write a PHY register on the MII. 2185 */ 2186 static void 2187 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2188 { 2189 struct pcn_softc *sc = (void *) self; 2190 2191 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2192 pcn_bcr_write(sc, LE_BCR34, val); 2193 } 2194 2195 /* 2196 * pcn_mii_statchg: [mii interface function] 2197 * 2198 * Callback from MII layer when media changes. 2199 */ 2200 static void 2201 pcn_mii_statchg(struct device *self) 2202 { 2203 struct pcn_softc *sc = (void *) self; 2204 2205 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2206 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2207 else 2208 pcn_bcr_write(sc, LE_BCR9, 0); 2209 } 2210