1 /* $NetBSD: if_pcn.c,v 1.47 2009/05/06 10:34:32 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.47 2009/05/06 10:34:32 cegger Exp $"); 69 70 #include "bpfilter.h" 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/callout.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/ioctl.h> 81 #include <sys/errno.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #include <sys/bus.h> 101 #include <sys/intr.h> 102 #include <machine/endian.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/ic/am79900reg.h> 108 #include <dev/ic/lancereg.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/pci/if_pcnreg.h> 115 116 /* 117 * Transmit descriptor list size. This is arbitrary, but allocate 118 * enough descriptors for 128 pending transmissions, and 4 segments 119 * per packet. This MUST work out to a power of 2. 120 * 121 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 122 * 123 * So we play a little trick here. We give each packet up to 16 124 * DMA segments, but only allocate the max of 512 descriptors. The 125 * transmit logic can deal with this, we just are hoping to sneak by. 126 */ 127 #define PCN_NTXSEGS 16 128 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 129 130 #define PCN_TXQUEUELEN 128 131 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 132 #define PCN_NTXDESC 512 133 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 134 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 135 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 136 137 /* Tx interrupt every N + 1 packets. */ 138 #define PCN_TXINTR_MASK 7 139 140 /* 141 * Receive descriptor list size. We have one Rx buffer per incoming 142 * packet, so this logic is a little simpler. 143 */ 144 #define PCN_NRXDESC 128 145 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 146 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 147 148 /* 149 * Control structures are DMA'd to the PCnet chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct pcn_control_data { 154 /* The transmit descriptors. */ 155 struct letmd pcd_txdescs[PCN_NTXDESC]; 156 157 /* The receive descriptors. */ 158 struct lermd pcd_rxdescs[PCN_NRXDESC]; 159 160 /* The init block. */ 161 struct leinit pcd_initblock; 162 }; 163 164 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 165 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 166 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 167 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct pcn_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 }; 178 179 /* 180 * Software state for receive jobs. 181 */ 182 struct pcn_rxsoft { 183 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t rxs_dmamap; /* our DMA map */ 185 }; 186 187 /* 188 * Description of Rx FIFO watermarks for various revisions. 189 */ 190 static const char * const pcn_79c970_rcvfw[] = { 191 "16 bytes", 192 "64 bytes", 193 "128 bytes", 194 NULL, 195 }; 196 197 static const char * const pcn_79c971_rcvfw[] = { 198 "16 bytes", 199 "64 bytes", 200 "112 bytes", 201 NULL, 202 }; 203 204 /* 205 * Description of Tx start points for various revisions. 206 */ 207 static const char * const pcn_79c970_xmtsp[] = { 208 "8 bytes", 209 "64 bytes", 210 "128 bytes", 211 "248 bytes", 212 }; 213 214 static const char * const pcn_79c971_xmtsp[] = { 215 "20 bytes", 216 "64 bytes", 217 "128 bytes", 218 "248 bytes", 219 }; 220 221 static const char * const pcn_79c971_xmtsp_sram[] = { 222 "44 bytes", 223 "64 bytes", 224 "128 bytes", 225 "store-and-forward", 226 }; 227 228 /* 229 * Description of Tx FIFO watermarks for various revisions. 230 */ 231 static const char * const pcn_79c970_xmtfw[] = { 232 "16 bytes", 233 "64 bytes", 234 "128 bytes", 235 NULL, 236 }; 237 238 static const char * const pcn_79c971_xmtfw[] = { 239 "16 bytes", 240 "64 bytes", 241 "108 bytes", 242 NULL, 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct pcn_softc { 249 device_t sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* Ethernet common data */ 254 void *sc_sdhook; /* shutdown hook */ 255 256 /* Points to our media routines, etc. */ 257 const struct pcn_variant *sc_variant; 258 259 void *sc_ih; /* interrupt cookie */ 260 261 struct mii_data sc_mii; /* MII/media information */ 262 263 callout_t sc_tick_ch; /* tick callout */ 264 265 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 266 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 267 268 /* Software state for transmit and receive descriptors. */ 269 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 270 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 271 272 /* Control data structures */ 273 struct pcn_control_data *sc_control_data; 274 #define sc_txdescs sc_control_data->pcd_txdescs 275 #define sc_rxdescs sc_control_data->pcd_rxdescs 276 #define sc_initblock sc_control_data->pcd_initblock 277 278 #ifdef PCN_EVENT_COUNTERS 279 /* Event counters. */ 280 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 281 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 282 struct evcnt sc_ev_txintr; /* Tx interrupts */ 283 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 284 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 285 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 286 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 287 288 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 289 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 290 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 291 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 292 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 293 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 294 struct evcnt sc_ev_txcopy; /* Tx copies required */ 295 #endif /* PCN_EVENT_COUNTERS */ 296 297 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 298 int sc_rcvfw; 299 300 const char * const *sc_xmtsp_desc; /* Tx start point info */ 301 int sc_xmtsp; 302 303 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 304 int sc_xmtfw; 305 306 int sc_flags; /* misc. flags; see below */ 307 int sc_swstyle; /* the software style in use */ 308 309 int sc_txfree; /* number of free Tx descriptors */ 310 int sc_txnext; /* next ready Tx descriptor */ 311 312 int sc_txsfree; /* number of free Tx jobs */ 313 int sc_txsnext; /* next free Tx job */ 314 int sc_txsdirty; /* dirty Tx jobs */ 315 316 int sc_rxptr; /* next ready Rx descriptor/job */ 317 318 uint32_t sc_csr5; /* prototype CSR5 register */ 319 uint32_t sc_mode; /* prototype MODE register */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 /* sc_flags */ 327 #define PCN_F_HAS_MII 0x0001 /* has MII */ 328 329 #ifdef PCN_EVENT_COUNTERS 330 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 331 #else 332 #define PCN_EVCNT_INCR(ev) /* nothing */ 333 #endif 334 335 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 336 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 337 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 338 339 #define PCN_CDTXSYNC(sc, x, n, ops) \ 340 do { \ 341 int __x, __n; \ 342 \ 343 __x = (x); \ 344 __n = (n); \ 345 \ 346 /* If it will wrap around, sync to the end of the ring. */ \ 347 if ((__x + __n) > PCN_NTXDESC) { \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 350 (PCN_NTXDESC - __x), (ops)); \ 351 __n -= (PCN_NTXDESC - __x); \ 352 __x = 0; \ 353 } \ 354 \ 355 /* Now sync whatever is left. */ \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 358 } while (/*CONSTCOND*/0) 359 360 #define PCN_CDRXSYNC(sc, x, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 363 364 #define PCN_CDINITSYNC(sc, ops) \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 367 368 #define PCN_INIT_RXDESC(sc, x) \ 369 do { \ 370 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 371 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 372 struct mbuf *__m = __rxs->rxs_mbuf; \ 373 \ 374 /* \ 375 * Note: We scoot the packet forward 2 bytes in the buffer \ 376 * so that the payload after the Ethernet header is aligned \ 377 * to a 4-byte boundary. \ 378 */ \ 379 __m->m_data = __m->m_ext.ext_buf + 2; \ 380 \ 381 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 382 __rmd->rmd2 = \ 383 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 384 __rmd->rmd0 = 0; \ 385 } else { \ 386 __rmd->rmd2 = 0; \ 387 __rmd->rmd0 = \ 388 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 389 } \ 390 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 391 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 392 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 393 } while(/*CONSTCOND*/0) 394 395 static void pcn_start(struct ifnet *); 396 static void pcn_watchdog(struct ifnet *); 397 static int pcn_ioctl(struct ifnet *, u_long, void *); 398 static int pcn_init(struct ifnet *); 399 static void pcn_stop(struct ifnet *, int); 400 401 static void pcn_shutdown(void *); 402 403 static void pcn_reset(struct pcn_softc *); 404 static void pcn_rxdrain(struct pcn_softc *); 405 static int pcn_add_rxbuf(struct pcn_softc *, int); 406 static void pcn_tick(void *); 407 408 static void pcn_spnd(struct pcn_softc *); 409 410 static void pcn_set_filter(struct pcn_softc *); 411 412 static int pcn_intr(void *); 413 static void pcn_txintr(struct pcn_softc *); 414 static int pcn_rxintr(struct pcn_softc *); 415 416 static int pcn_mii_readreg(device_t, int, int); 417 static void pcn_mii_writereg(device_t, int, int, int); 418 static void pcn_mii_statchg(device_t); 419 420 static void pcn_79c970_mediainit(struct pcn_softc *); 421 static int pcn_79c970_mediachange(struct ifnet *); 422 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 423 424 static void pcn_79c971_mediainit(struct pcn_softc *); 425 426 /* 427 * Description of a PCnet-PCI variant. Used to select media access 428 * method, mostly, and to print a nice description of the chip. 429 */ 430 static const struct pcn_variant { 431 const char *pcv_desc; 432 void (*pcv_mediainit)(struct pcn_softc *); 433 uint16_t pcv_chipid; 434 } pcn_variants[] = { 435 { "Am79c970 PCnet-PCI", 436 pcn_79c970_mediainit, 437 PARTID_Am79c970 }, 438 439 { "Am79c970A PCnet-PCI II", 440 pcn_79c970_mediainit, 441 PARTID_Am79c970A }, 442 443 { "Am79c971 PCnet-FAST", 444 pcn_79c971_mediainit, 445 PARTID_Am79c971 }, 446 447 { "Am79c972 PCnet-FAST+", 448 pcn_79c971_mediainit, 449 PARTID_Am79c972 }, 450 451 { "Am79c973 PCnet-FAST III", 452 pcn_79c971_mediainit, 453 PARTID_Am79c973 }, 454 455 { "Am79c975 PCnet-FAST III", 456 pcn_79c971_mediainit, 457 PARTID_Am79c975 }, 458 459 { "Unknown PCnet-PCI variant", 460 pcn_79c971_mediainit, 461 0 }, 462 }; 463 464 int pcn_copy_small = 0; 465 466 static int pcn_match(device_t, cfdata_t, void *); 467 static void pcn_attach(device_t, device_t, void *); 468 469 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 470 pcn_match, pcn_attach, NULL, NULL); 471 472 /* 473 * Routines to read and write the PCnet-PCI CSR/BCR space. 474 */ 475 476 static inline uint32_t 477 pcn_csr_read(struct pcn_softc *sc, int reg) 478 { 479 480 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 481 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 482 } 483 484 static inline void 485 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 486 { 487 488 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 489 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 490 } 491 492 static inline uint32_t 493 pcn_bcr_read(struct pcn_softc *sc, int reg) 494 { 495 496 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 497 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 498 } 499 500 static inline void 501 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 502 { 503 504 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 505 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 506 } 507 508 static bool 509 pcn_is_vmware(const char *enaddr) 510 { 511 512 /* 513 * VMware uses the OUI 00:0c:29 for auto-generated MAC 514 * addresses. 515 */ 516 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 517 return (TRUE); 518 519 /* 520 * VMware uses the OUI 00:50:56 for manually-set MAC 521 * addresses (and some auto-generated ones). 522 */ 523 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 524 return (TRUE); 525 526 return (FALSE); 527 } 528 529 static const struct pcn_variant * 530 pcn_lookup_variant(uint16_t chipid) 531 { 532 const struct pcn_variant *pcv; 533 534 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 535 if (chipid == pcv->pcv_chipid) 536 return (pcv); 537 } 538 539 /* 540 * This covers unknown chips, which we simply treat like 541 * a generic PCnet-FAST. 542 */ 543 return (pcv); 544 } 545 546 static int 547 pcn_match(device_t parent, cfdata_t cf, void *aux) 548 { 549 struct pci_attach_args *pa = aux; 550 551 /* 552 * IBM Makes a PCI variant of this card which shows up as a 553 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 554 * this card is truly a pcn card, so we have a special case match for 555 * it 556 */ 557 558 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 559 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 560 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 561 return(1); 562 563 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 564 return (0); 565 566 switch (PCI_PRODUCT(pa->pa_id)) { 567 case PCI_PRODUCT_AMD_PCNET_PCI: 568 /* Beat if_le_pci.c */ 569 return (10); 570 } 571 572 return (0); 573 } 574 575 static void 576 pcn_attach(device_t parent, device_t self, void *aux) 577 { 578 struct pcn_softc *sc = device_private(self); 579 struct pci_attach_args *pa = aux; 580 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 581 pci_chipset_tag_t pc = pa->pa_pc; 582 pci_intr_handle_t ih; 583 const char *intrstr = NULL; 584 bus_space_tag_t iot, memt; 585 bus_space_handle_t ioh, memh; 586 bus_dma_segment_t seg; 587 int ioh_valid, memh_valid; 588 int ntxsegs, i, rseg, error; 589 uint32_t chipid, reg; 590 uint8_t enaddr[ETHER_ADDR_LEN]; 591 prop_object_t obj; 592 bool is_vmware; 593 594 sc->sc_dev = self; 595 callout_init(&sc->sc_tick_ch, 0); 596 597 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 598 599 /* 600 * Map the device. 601 */ 602 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 603 &iot, &ioh, NULL, NULL) == 0); 604 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 605 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 606 &memt, &memh, NULL, NULL) == 0); 607 608 if (memh_valid) { 609 sc->sc_st = memt; 610 sc->sc_sh = memh; 611 } else if (ioh_valid) { 612 sc->sc_st = iot; 613 sc->sc_sh = ioh; 614 } else { 615 aprint_error_dev(self, "unable to map device registers\n"); 616 return; 617 } 618 619 sc->sc_dmat = pa->pa_dmat; 620 621 /* Make sure bus mastering is enabled. */ 622 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 623 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 624 PCI_COMMAND_MASTER_ENABLE); 625 626 /* power up chip */ 627 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 628 NULL)) && error != EOPNOTSUPP) { 629 aprint_error_dev(self, "cannot activate %d\n", error); 630 return; 631 } 632 633 /* 634 * Reset the chip to a known state. This also puts the 635 * chip into 32-bit mode. 636 */ 637 pcn_reset(sc); 638 639 /* 640 * On some systems with the chip is an on-board device, the 641 * EEPROM is not used. Handle this by reading the MAC address 642 * from the CSRs (assuming that boot firmware has written 643 * it there). 644 */ 645 obj = prop_dictionary_get(device_properties(sc->sc_dev), 646 "am79c970-no-eeprom"); 647 if (prop_bool_true(obj)) { 648 for (i = 0; i < 3; i++) { 649 uint32_t val; 650 val = pcn_csr_read(sc, LE_CSR12 + i); 651 enaddr[2 * i] = val & 0xff; 652 enaddr[2 * i + 1] = (val >> 8) & 0xff; 653 } 654 } else { 655 for (i = 0; i < ETHER_ADDR_LEN; i++) { 656 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 657 PCN32_APROM + i); 658 } 659 } 660 661 /* Check to see if this is a VMware emulated network interface. */ 662 is_vmware = pcn_is_vmware(enaddr); 663 664 /* 665 * Now that the device is mapped, attempt to figure out what 666 * kind of chip we have. Note that IDL has all 32 bits of 667 * the chip ID when we're in 32-bit mode. 668 */ 669 chipid = pcn_csr_read(sc, LE_CSR88); 670 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 671 672 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 673 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 674 ether_sprintf(enaddr)); 675 676 /* 677 * VMware has a bug in its network interface emulation; we must 678 * limit the number of Tx segments. 679 */ 680 if (is_vmware) { 681 ntxsegs = PCN_NTXSEGS_VMWARE; 682 prop_dictionary_set_bool(device_properties(sc->sc_dev), 683 "am79c970-vmware-tx-bug", TRUE); 684 aprint_verbose_dev(self, 685 "VMware Tx segment count bug detected\n"); 686 } else { 687 ntxsegs = PCN_NTXSEGS; 688 } 689 690 /* 691 * Map and establish our interrupt. 692 */ 693 if (pci_intr_map(pa, &ih)) { 694 aprint_error_dev(self, "unable to map interrupt\n"); 695 return; 696 } 697 intrstr = pci_intr_string(pc, ih); 698 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 699 if (sc->sc_ih == NULL) { 700 aprint_error_dev(self, "unable to establish interrupt"); 701 if (intrstr != NULL) 702 aprint_error(" at %s", intrstr); 703 aprint_error("\n"); 704 return; 705 } 706 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 707 708 /* 709 * Allocate the control data structures, and create and load the 710 * DMA map for it. 711 */ 712 if ((error = bus_dmamem_alloc(sc->sc_dmat, 713 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 714 0)) != 0) { 715 aprint_error_dev(self, "unable to allocate control data, " 716 "error = %d\n", error); 717 goto fail_0; 718 } 719 720 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 721 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 722 BUS_DMA_COHERENT)) != 0) { 723 aprint_error_dev(self, "unable to map control data, " 724 "error = %d\n", error); 725 goto fail_1; 726 } 727 728 if ((error = bus_dmamap_create(sc->sc_dmat, 729 sizeof(struct pcn_control_data), 1, 730 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 731 aprint_error_dev(self, "unable to create control data DMA map, " 732 "error = %d\n", error); 733 goto fail_2; 734 } 735 736 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 737 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 738 0)) != 0) { 739 aprint_error_dev(self, 740 "unable to load control data DMA map, error = %d\n", error); 741 goto fail_3; 742 } 743 744 /* Create the transmit buffer DMA maps. */ 745 for (i = 0; i < PCN_TXQUEUELEN; i++) { 746 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 747 ntxsegs, MCLBYTES, 0, 0, 748 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 749 aprint_error_dev(self, 750 "unable to create tx DMA map %d, error = %d\n", 751 i, error); 752 goto fail_4; 753 } 754 } 755 756 /* Create the receive buffer DMA maps. */ 757 for (i = 0; i < PCN_NRXDESC; i++) { 758 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 759 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 760 aprint_error_dev(self, 761 "unable to create rx DMA map %d, error = %d\n", 762 i, error); 763 goto fail_5; 764 } 765 sc->sc_rxsoft[i].rxs_mbuf = NULL; 766 } 767 768 /* Initialize our media structures. */ 769 (*sc->sc_variant->pcv_mediainit)(sc); 770 771 /* 772 * Initialize FIFO watermark info. 773 */ 774 switch (sc->sc_variant->pcv_chipid) { 775 case PARTID_Am79c970: 776 case PARTID_Am79c970A: 777 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 778 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 779 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 780 break; 781 782 default: 783 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 784 /* 785 * Read BCR25 to determine how much SRAM is 786 * on the board. If > 0, then we the chip 787 * uses different Start Point thresholds. 788 * 789 * Note BCR25 and BCR26 are loaded from the 790 * EEPROM on RST, and unaffected by S_RESET, 791 * so we don't really have to worry about 792 * them except for this. 793 */ 794 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 795 if (reg != 0) 796 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 797 else 798 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 799 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 800 break; 801 } 802 803 /* 804 * Set up defaults -- see the tables above for what these 805 * values mean. 806 * 807 * XXX How should we tune RCVFW and XMTFW? 808 */ 809 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 810 sc->sc_xmtsp = 1; 811 sc->sc_xmtfw = 0; 812 813 ifp = &sc->sc_ethercom.ec_if; 814 strcpy(ifp->if_xname, device_xname(self)); 815 ifp->if_softc = sc; 816 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 817 ifp->if_ioctl = pcn_ioctl; 818 ifp->if_start = pcn_start; 819 ifp->if_watchdog = pcn_watchdog; 820 ifp->if_init = pcn_init; 821 ifp->if_stop = pcn_stop; 822 IFQ_SET_READY(&ifp->if_snd); 823 824 /* Attach the interface. */ 825 if_attach(ifp); 826 ether_ifattach(ifp, enaddr); 827 #if NRND > 0 828 rnd_attach_source(&sc->rnd_source, device_xname(self), 829 RND_TYPE_NET, 0); 830 #endif 831 832 #ifdef PCN_EVENT_COUNTERS 833 /* Attach event counters. */ 834 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 835 NULL, device_xname(self), "txsstall"); 836 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 837 NULL, device_xname(self), "txdstall"); 838 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 839 NULL, device_xname(self), "txintr"); 840 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 841 NULL, device_xname(self), "rxintr"); 842 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 843 NULL, device_xname(self), "babl"); 844 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 845 NULL, device_xname(self), "miss"); 846 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 847 NULL, device_xname(self), "merr"); 848 849 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 850 NULL, device_xname(self), "txseg1"); 851 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 852 NULL, device_xname(self), "txseg2"); 853 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 854 NULL, device_xname(self), "txseg3"); 855 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 856 NULL, device_xname(self), "txseg4"); 857 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 858 NULL, device_xname(self), "txseg5"); 859 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 860 NULL, device_xname(self), "txsegmore"); 861 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 862 NULL, device_xname(self), "txcopy"); 863 #endif /* PCN_EVENT_COUNTERS */ 864 865 /* Make sure the interface is shutdown during reboot. */ 866 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 867 if (sc->sc_sdhook == NULL) 868 aprint_error_dev(self, 869 "WARNING: unable to establish shutdown hook\n"); 870 return; 871 872 /* 873 * Free any resources we've allocated during the failed attach 874 * attempt. Do this in reverse order and fall through. 875 */ 876 fail_5: 877 for (i = 0; i < PCN_NRXDESC; i++) { 878 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 879 bus_dmamap_destroy(sc->sc_dmat, 880 sc->sc_rxsoft[i].rxs_dmamap); 881 } 882 fail_4: 883 for (i = 0; i < PCN_TXQUEUELEN; i++) { 884 if (sc->sc_txsoft[i].txs_dmamap != NULL) 885 bus_dmamap_destroy(sc->sc_dmat, 886 sc->sc_txsoft[i].txs_dmamap); 887 } 888 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 889 fail_3: 890 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 891 fail_2: 892 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 893 sizeof(struct pcn_control_data)); 894 fail_1: 895 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 896 fail_0: 897 return; 898 } 899 900 /* 901 * pcn_shutdown: 902 * 903 * Make sure the interface is stopped at reboot time. 904 */ 905 static void 906 pcn_shutdown(void *arg) 907 { 908 struct pcn_softc *sc = arg; 909 910 pcn_stop(&sc->sc_ethercom.ec_if, 1); 911 /* explicitly reset the chip for some onboard one with lazy firmware */ 912 pcn_reset(sc); 913 } 914 915 /* 916 * pcn_start: [ifnet interface function] 917 * 918 * Start packet transmission on the interface. 919 */ 920 static void 921 pcn_start(struct ifnet *ifp) 922 { 923 struct pcn_softc *sc = ifp->if_softc; 924 struct mbuf *m0, *m; 925 struct pcn_txsoft *txs; 926 bus_dmamap_t dmamap; 927 int error, nexttx, lasttx = -1, ofree, seg; 928 929 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 930 return; 931 932 /* 933 * Remember the previous number of free descriptors and 934 * the first descriptor we'll use. 935 */ 936 ofree = sc->sc_txfree; 937 938 /* 939 * Loop through the send queue, setting up transmit descriptors 940 * until we drain the queue, or use up all available transmit 941 * descriptors. 942 */ 943 for (;;) { 944 /* Grab a packet off the queue. */ 945 IFQ_POLL(&ifp->if_snd, m0); 946 if (m0 == NULL) 947 break; 948 m = NULL; 949 950 /* Get a work queue entry. */ 951 if (sc->sc_txsfree == 0) { 952 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 953 break; 954 } 955 956 txs = &sc->sc_txsoft[sc->sc_txsnext]; 957 dmamap = txs->txs_dmamap; 958 959 /* 960 * Load the DMA map. If this fails, the packet either 961 * didn't fit in the alloted number of segments, or we 962 * were short on resources. In this case, we'll copy 963 * and try again. 964 */ 965 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 966 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 967 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 968 MGETHDR(m, M_DONTWAIT, MT_DATA); 969 if (m == NULL) { 970 printf("%s: unable to allocate Tx mbuf\n", 971 device_xname(sc->sc_dev)); 972 break; 973 } 974 if (m0->m_pkthdr.len > MHLEN) { 975 MCLGET(m, M_DONTWAIT); 976 if ((m->m_flags & M_EXT) == 0) { 977 printf("%s: unable to allocate Tx " 978 "cluster\n", 979 device_xname(sc->sc_dev)); 980 m_freem(m); 981 break; 982 } 983 } 984 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 985 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 986 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 987 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 988 if (error) { 989 printf("%s: unable to load Tx buffer, " 990 "error = %d\n", device_xname(sc->sc_dev), 991 error); 992 break; 993 } 994 } 995 996 /* 997 * Ensure we have enough descriptors free to describe 998 * the packet. Note, we always reserve one descriptor 999 * at the end of the ring as a termination point, to 1000 * prevent wrap-around. 1001 */ 1002 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1003 /* 1004 * Not enough free descriptors to transmit this 1005 * packet. We haven't committed anything yet, 1006 * so just unload the DMA map, put the packet 1007 * back on the queue, and punt. Notify the upper 1008 * layer that there are not more slots left. 1009 * 1010 * XXX We could allocate an mbuf and copy, but 1011 * XXX is it worth it? 1012 */ 1013 ifp->if_flags |= IFF_OACTIVE; 1014 bus_dmamap_unload(sc->sc_dmat, dmamap); 1015 if (m != NULL) 1016 m_freem(m); 1017 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1018 break; 1019 } 1020 1021 IFQ_DEQUEUE(&ifp->if_snd, m0); 1022 if (m != NULL) { 1023 m_freem(m0); 1024 m0 = m; 1025 } 1026 1027 /* 1028 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1029 */ 1030 1031 /* Sync the DMA map. */ 1032 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1033 BUS_DMASYNC_PREWRITE); 1034 1035 #ifdef PCN_EVENT_COUNTERS 1036 switch (dmamap->dm_nsegs) { 1037 case 1: 1038 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1039 break; 1040 case 2: 1041 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1042 break; 1043 case 3: 1044 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1045 break; 1046 case 4: 1047 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1048 break; 1049 case 5: 1050 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1051 break; 1052 default: 1053 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1054 break; 1055 } 1056 #endif /* PCN_EVENT_COUNTERS */ 1057 1058 /* 1059 * Initialize the transmit descriptors. 1060 */ 1061 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1062 for (nexttx = sc->sc_txnext, seg = 0; 1063 seg < dmamap->dm_nsegs; 1064 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1065 /* 1066 * If this is the first descriptor we're 1067 * enqueueing, don't set the OWN bit just 1068 * yet. That could cause a race condition. 1069 * We'll do it below. 1070 */ 1071 sc->sc_txdescs[nexttx].tmd0 = 0; 1072 sc->sc_txdescs[nexttx].tmd2 = 1073 htole32(dmamap->dm_segs[seg].ds_addr); 1074 sc->sc_txdescs[nexttx].tmd1 = 1075 htole32(LE_T1_ONES | 1076 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1077 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1078 LE_T1_BCNT_MASK)); 1079 lasttx = nexttx; 1080 } 1081 } else { 1082 for (nexttx = sc->sc_txnext, seg = 0; 1083 seg < dmamap->dm_nsegs; 1084 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1085 /* 1086 * If this is the first descriptor we're 1087 * enqueueing, don't set the OWN bit just 1088 * yet. That could cause a race condition. 1089 * We'll do it below. 1090 */ 1091 sc->sc_txdescs[nexttx].tmd0 = 1092 htole32(dmamap->dm_segs[seg].ds_addr); 1093 sc->sc_txdescs[nexttx].tmd2 = 0; 1094 sc->sc_txdescs[nexttx].tmd1 = 1095 htole32(LE_T1_ONES | 1096 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1097 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1098 LE_T1_BCNT_MASK)); 1099 lasttx = nexttx; 1100 } 1101 } 1102 1103 KASSERT(lasttx != -1); 1104 /* Interrupt on the packet, if appropriate. */ 1105 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1106 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1107 1108 /* Set `start of packet' and `end of packet' appropriately. */ 1109 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1110 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1111 htole32(LE_T1_OWN|LE_T1_STP); 1112 1113 /* Sync the descriptors we're using. */ 1114 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1116 1117 /* Kick the transmitter. */ 1118 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1119 1120 /* 1121 * Store a pointer to the packet so we can free it later, 1122 * and remember what txdirty will be once the packet is 1123 * done. 1124 */ 1125 txs->txs_mbuf = m0; 1126 txs->txs_firstdesc = sc->sc_txnext; 1127 txs->txs_lastdesc = lasttx; 1128 1129 /* Advance the tx pointer. */ 1130 sc->sc_txfree -= dmamap->dm_nsegs; 1131 sc->sc_txnext = nexttx; 1132 1133 sc->sc_txsfree--; 1134 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1135 1136 #if NBPFILTER > 0 1137 /* Pass the packet to any BPF listeners. */ 1138 if (ifp->if_bpf) 1139 bpf_mtap(ifp->if_bpf, m0); 1140 #endif /* NBPFILTER > 0 */ 1141 } 1142 1143 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1144 /* No more slots left; notify upper layer. */ 1145 ifp->if_flags |= IFF_OACTIVE; 1146 } 1147 1148 if (sc->sc_txfree != ofree) { 1149 /* Set a watchdog timer in case the chip flakes out. */ 1150 ifp->if_timer = 5; 1151 } 1152 } 1153 1154 /* 1155 * pcn_watchdog: [ifnet interface function] 1156 * 1157 * Watchdog timer handler. 1158 */ 1159 static void 1160 pcn_watchdog(struct ifnet *ifp) 1161 { 1162 struct pcn_softc *sc = ifp->if_softc; 1163 1164 /* 1165 * Since we're not interrupting every packet, sweep 1166 * up before we report an error. 1167 */ 1168 pcn_txintr(sc); 1169 1170 if (sc->sc_txfree != PCN_NTXDESC) { 1171 printf("%s: device timeout (txfree %d txsfree %d)\n", 1172 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1173 ifp->if_oerrors++; 1174 1175 /* Reset the interface. */ 1176 (void) pcn_init(ifp); 1177 } 1178 1179 /* Try to get more packets going. */ 1180 pcn_start(ifp); 1181 } 1182 1183 /* 1184 * pcn_ioctl: [ifnet interface function] 1185 * 1186 * Handle control requests from the operator. 1187 */ 1188 static int 1189 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1190 { 1191 struct pcn_softc *sc = ifp->if_softc; 1192 struct ifreq *ifr = (struct ifreq *) data; 1193 int s, error; 1194 1195 s = splnet(); 1196 1197 switch (cmd) { 1198 case SIOCSIFMEDIA: 1199 case SIOCGIFMEDIA: 1200 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1201 break; 1202 1203 default: 1204 error = ether_ioctl(ifp, cmd, data); 1205 if (error == ENETRESET) { 1206 /* 1207 * Multicast list has changed; set the hardware filter 1208 * accordingly. 1209 */ 1210 if (ifp->if_flags & IFF_RUNNING) 1211 error = pcn_init(ifp); 1212 else 1213 error = 0; 1214 } 1215 break; 1216 } 1217 1218 /* Try to get more packets going. */ 1219 pcn_start(ifp); 1220 1221 splx(s); 1222 return (error); 1223 } 1224 1225 /* 1226 * pcn_intr: 1227 * 1228 * Interrupt service routine. 1229 */ 1230 static int 1231 pcn_intr(void *arg) 1232 { 1233 struct pcn_softc *sc = arg; 1234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1235 uint32_t csr0; 1236 int wantinit, handled = 0; 1237 1238 for (wantinit = 0; wantinit == 0;) { 1239 csr0 = pcn_csr_read(sc, LE_CSR0); 1240 if ((csr0 & LE_C0_INTR) == 0) 1241 break; 1242 1243 #if NRND > 0 1244 if (RND_ENABLED(&sc->rnd_source)) 1245 rnd_add_uint32(&sc->rnd_source, csr0); 1246 #endif 1247 1248 /* ACK the bits and re-enable interrupts. */ 1249 pcn_csr_write(sc, LE_CSR0, csr0 & 1250 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1251 LE_C0_TINT|LE_C0_IDON)); 1252 1253 handled = 1; 1254 1255 if (csr0 & LE_C0_RINT) { 1256 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1257 wantinit = pcn_rxintr(sc); 1258 } 1259 1260 if (csr0 & LE_C0_TINT) { 1261 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1262 pcn_txintr(sc); 1263 } 1264 1265 if (csr0 & LE_C0_ERR) { 1266 if (csr0 & LE_C0_BABL) { 1267 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1268 ifp->if_oerrors++; 1269 } 1270 if (csr0 & LE_C0_MISS) { 1271 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1272 ifp->if_ierrors++; 1273 } 1274 if (csr0 & LE_C0_MERR) { 1275 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1276 printf("%s: memory error\n", 1277 device_xname(sc->sc_dev)); 1278 wantinit = 1; 1279 break; 1280 } 1281 } 1282 1283 if ((csr0 & LE_C0_RXON) == 0) { 1284 printf("%s: receiver disabled\n", 1285 device_xname(sc->sc_dev)); 1286 ifp->if_ierrors++; 1287 wantinit = 1; 1288 } 1289 1290 if ((csr0 & LE_C0_TXON) == 0) { 1291 printf("%s: transmitter disabled\n", 1292 device_xname(sc->sc_dev)); 1293 ifp->if_oerrors++; 1294 wantinit = 1; 1295 } 1296 } 1297 1298 if (handled) { 1299 if (wantinit) 1300 pcn_init(ifp); 1301 1302 /* Try to get more packets going. */ 1303 pcn_start(ifp); 1304 } 1305 1306 return (handled); 1307 } 1308 1309 /* 1310 * pcn_spnd: 1311 * 1312 * Suspend the chip. 1313 */ 1314 static void 1315 pcn_spnd(struct pcn_softc *sc) 1316 { 1317 int i; 1318 1319 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1320 1321 for (i = 0; i < 10000; i++) { 1322 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1323 return; 1324 delay(5); 1325 } 1326 1327 printf("%s: WARNING: chip failed to enter suspended state\n", 1328 device_xname(sc->sc_dev)); 1329 } 1330 1331 /* 1332 * pcn_txintr: 1333 * 1334 * Helper; handle transmit interrupts. 1335 */ 1336 static void 1337 pcn_txintr(struct pcn_softc *sc) 1338 { 1339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1340 struct pcn_txsoft *txs; 1341 uint32_t tmd1, tmd2, tmd; 1342 int i, j; 1343 1344 ifp->if_flags &= ~IFF_OACTIVE; 1345 1346 /* 1347 * Go through our Tx list and free mbufs for those 1348 * frames which have been transmitted. 1349 */ 1350 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1351 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1352 txs = &sc->sc_txsoft[i]; 1353 1354 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1355 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1356 1357 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1358 if (tmd1 & LE_T1_OWN) 1359 break; 1360 1361 /* 1362 * Slightly annoying -- we have to loop through the 1363 * descriptors we've used looking for ERR, since it 1364 * can appear on any descriptor in the chain. 1365 */ 1366 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1367 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1368 if (tmd & LE_T1_ERR) { 1369 ifp->if_oerrors++; 1370 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1371 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1372 else 1373 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1374 if (tmd2 & LE_T2_UFLO) { 1375 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1376 sc->sc_xmtsp++; 1377 printf("%s: transmit " 1378 "underrun; new threshold: " 1379 "%s\n", 1380 device_xname(sc->sc_dev), 1381 sc->sc_xmtsp_desc[ 1382 sc->sc_xmtsp]); 1383 pcn_spnd(sc); 1384 pcn_csr_write(sc, LE_CSR80, 1385 LE_C80_RCVFW(sc->sc_rcvfw) | 1386 LE_C80_XMTSP(sc->sc_xmtsp) | 1387 LE_C80_XMTFW(sc->sc_xmtfw)); 1388 pcn_csr_write(sc, LE_CSR5, 1389 sc->sc_csr5); 1390 } else { 1391 printf("%s: transmit " 1392 "underrun\n", 1393 device_xname(sc->sc_dev)); 1394 } 1395 } else if (tmd2 & LE_T2_BUFF) { 1396 printf("%s: transmit buffer error\n", 1397 device_xname(sc->sc_dev)); 1398 } 1399 if (tmd2 & LE_T2_LCOL) 1400 ifp->if_collisions++; 1401 if (tmd2 & LE_T2_RTRY) 1402 ifp->if_collisions += 16; 1403 goto next_packet; 1404 } 1405 if (j == txs->txs_lastdesc) 1406 break; 1407 } 1408 if (tmd1 & LE_T1_ONE) 1409 ifp->if_collisions++; 1410 else if (tmd & LE_T1_MORE) { 1411 /* Real number is unknown. */ 1412 ifp->if_collisions += 2; 1413 } 1414 ifp->if_opackets++; 1415 next_packet: 1416 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1417 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1418 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1419 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1420 m_freem(txs->txs_mbuf); 1421 txs->txs_mbuf = NULL; 1422 } 1423 1424 /* Update the dirty transmit buffer pointer. */ 1425 sc->sc_txsdirty = i; 1426 1427 /* 1428 * If there are no more pending transmissions, cancel the watchdog 1429 * timer. 1430 */ 1431 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1432 ifp->if_timer = 0; 1433 } 1434 1435 /* 1436 * pcn_rxintr: 1437 * 1438 * Helper; handle receive interrupts. 1439 */ 1440 static int 1441 pcn_rxintr(struct pcn_softc *sc) 1442 { 1443 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1444 struct pcn_rxsoft *rxs; 1445 struct mbuf *m; 1446 uint32_t rmd1; 1447 int i, len; 1448 1449 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1450 rxs = &sc->sc_rxsoft[i]; 1451 1452 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1453 1454 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1455 1456 if (rmd1 & LE_R1_OWN) 1457 break; 1458 1459 /* 1460 * Check for errors and make sure the packet fit into 1461 * a single buffer. We have structured this block of 1462 * code the way it is in order to compress it into 1463 * one test in the common case (no error). 1464 */ 1465 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1466 (LE_R1_STP|LE_R1_ENP))) { 1467 /* Make sure the packet is in a single buffer. */ 1468 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1469 (LE_R1_STP|LE_R1_ENP)) { 1470 printf("%s: packet spilled into next buffer\n", 1471 device_xname(sc->sc_dev)); 1472 return (1); /* pcn_intr() will re-init */ 1473 } 1474 1475 /* 1476 * If the packet had an error, simple recycle the 1477 * buffer. 1478 */ 1479 if (rmd1 & LE_R1_ERR) { 1480 ifp->if_ierrors++; 1481 /* 1482 * If we got an overflow error, chances 1483 * are there will be a CRC error. In 1484 * this case, just print the overflow 1485 * error, and skip the others. 1486 */ 1487 if (rmd1 & LE_R1_OFLO) 1488 printf("%s: overflow error\n", 1489 device_xname(sc->sc_dev)); 1490 else { 1491 #define PRINTIT(x, str) \ 1492 if (rmd1 & (x)) \ 1493 printf("%s: %s\n", \ 1494 device_xname(sc->sc_dev), \ 1495 str); 1496 PRINTIT(LE_R1_FRAM, "framing error"); 1497 PRINTIT(LE_R1_CRC, "CRC error"); 1498 PRINTIT(LE_R1_BUFF, "buffer error"); 1499 } 1500 #undef PRINTIT 1501 PCN_INIT_RXDESC(sc, i); 1502 continue; 1503 } 1504 } 1505 1506 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1507 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1508 1509 /* 1510 * No errors; receive the packet. 1511 */ 1512 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1513 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1514 else 1515 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1516 1517 /* 1518 * The LANCE family includes the CRC with every packet; 1519 * trim it off here. 1520 */ 1521 len -= ETHER_CRC_LEN; 1522 1523 /* 1524 * If the packet is small enough to fit in a 1525 * single header mbuf, allocate one and copy 1526 * the data into it. This greatly reduces 1527 * memory consumption when we receive lots 1528 * of small packets. 1529 * 1530 * Otherwise, we add a new buffer to the receive 1531 * chain. If this fails, we drop the packet and 1532 * recycle the old buffer. 1533 */ 1534 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1535 MGETHDR(m, M_DONTWAIT, MT_DATA); 1536 if (m == NULL) 1537 goto dropit; 1538 m->m_data += 2; 1539 memcpy(mtod(m, void *), 1540 mtod(rxs->rxs_mbuf, void *), len); 1541 PCN_INIT_RXDESC(sc, i); 1542 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1543 rxs->rxs_dmamap->dm_mapsize, 1544 BUS_DMASYNC_PREREAD); 1545 } else { 1546 m = rxs->rxs_mbuf; 1547 if (pcn_add_rxbuf(sc, i) != 0) { 1548 dropit: 1549 ifp->if_ierrors++; 1550 PCN_INIT_RXDESC(sc, i); 1551 bus_dmamap_sync(sc->sc_dmat, 1552 rxs->rxs_dmamap, 0, 1553 rxs->rxs_dmamap->dm_mapsize, 1554 BUS_DMASYNC_PREREAD); 1555 continue; 1556 } 1557 } 1558 1559 m->m_pkthdr.rcvif = ifp; 1560 m->m_pkthdr.len = m->m_len = len; 1561 1562 #if NBPFILTER > 0 1563 /* Pass this up to any BPF listeners. */ 1564 if (ifp->if_bpf) 1565 bpf_mtap(ifp->if_bpf, m); 1566 #endif /* NBPFILTER > 0 */ 1567 1568 /* Pass it on. */ 1569 (*ifp->if_input)(ifp, m); 1570 ifp->if_ipackets++; 1571 } 1572 1573 /* Update the receive pointer. */ 1574 sc->sc_rxptr = i; 1575 return (0); 1576 } 1577 1578 /* 1579 * pcn_tick: 1580 * 1581 * One second timer, used to tick the MII. 1582 */ 1583 static void 1584 pcn_tick(void *arg) 1585 { 1586 struct pcn_softc *sc = arg; 1587 int s; 1588 1589 s = splnet(); 1590 mii_tick(&sc->sc_mii); 1591 splx(s); 1592 1593 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1594 } 1595 1596 /* 1597 * pcn_reset: 1598 * 1599 * Perform a soft reset on the PCnet-PCI. 1600 */ 1601 static void 1602 pcn_reset(struct pcn_softc *sc) 1603 { 1604 1605 /* 1606 * The PCnet-PCI chip is reset by reading from the 1607 * RESET register. Note that while the NE2100 LANCE 1608 * boards require a write after the read, the PCnet-PCI 1609 * chips do not require this. 1610 * 1611 * Since we don't know if we're in 16-bit or 32-bit 1612 * mode right now, issue both (it's safe) in the 1613 * hopes that one will succeed. 1614 */ 1615 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1616 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1617 1618 /* Wait 1ms for it to finish. */ 1619 delay(1000); 1620 1621 /* 1622 * Select 32-bit I/O mode by issuing a 32-bit write to the 1623 * RDP. Since the RAP is 0 after a reset, writing a 0 1624 * to RDP is safe (since it simply clears CSR0). 1625 */ 1626 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1627 } 1628 1629 /* 1630 * pcn_init: [ifnet interface function] 1631 * 1632 * Initialize the interface. Must be called at splnet(). 1633 */ 1634 static int 1635 pcn_init(struct ifnet *ifp) 1636 { 1637 struct pcn_softc *sc = ifp->if_softc; 1638 struct pcn_rxsoft *rxs; 1639 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1640 int i, error = 0; 1641 uint32_t reg; 1642 1643 /* Cancel any pending I/O. */ 1644 pcn_stop(ifp, 0); 1645 1646 /* Reset the chip to a known state. */ 1647 pcn_reset(sc); 1648 1649 /* 1650 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1651 * else. 1652 * 1653 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1654 * because the structure layout is compatible with ILACC, 1655 * but the burst mode is only available in SSTYLE 3, and 1656 * burst mode should provide some performance enhancement. 1657 */ 1658 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1659 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1660 else 1661 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1662 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1663 1664 /* Initialize the transmit descriptor ring. */ 1665 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1666 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1667 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1668 sc->sc_txfree = PCN_NTXDESC; 1669 sc->sc_txnext = 0; 1670 1671 /* Initialize the transmit job descriptors. */ 1672 for (i = 0; i < PCN_TXQUEUELEN; i++) 1673 sc->sc_txsoft[i].txs_mbuf = NULL; 1674 sc->sc_txsfree = PCN_TXQUEUELEN; 1675 sc->sc_txsnext = 0; 1676 sc->sc_txsdirty = 0; 1677 1678 /* 1679 * Initialize the receive descriptor and receive job 1680 * descriptor rings. 1681 */ 1682 for (i = 0; i < PCN_NRXDESC; i++) { 1683 rxs = &sc->sc_rxsoft[i]; 1684 if (rxs->rxs_mbuf == NULL) { 1685 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1686 printf("%s: unable to allocate or map rx " 1687 "buffer %d, error = %d\n", 1688 device_xname(sc->sc_dev), i, error); 1689 /* 1690 * XXX Should attempt to run with fewer receive 1691 * XXX buffers instead of just failing. 1692 */ 1693 pcn_rxdrain(sc); 1694 goto out; 1695 } 1696 } else 1697 PCN_INIT_RXDESC(sc, i); 1698 } 1699 sc->sc_rxptr = 0; 1700 1701 /* Initialize MODE for the initialization block. */ 1702 sc->sc_mode = 0; 1703 if (ifp->if_flags & IFF_PROMISC) 1704 sc->sc_mode |= LE_C15_PROM; 1705 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1706 sc->sc_mode |= LE_C15_DRCVBC; 1707 1708 /* 1709 * If we have MII, simply select MII in the MODE register, 1710 * and clear ASEL. Otherwise, let ASEL stand (for now), 1711 * and leave PORTSEL alone (it is ignored with ASEL is set). 1712 */ 1713 if (sc->sc_flags & PCN_F_HAS_MII) { 1714 pcn_bcr_write(sc, LE_BCR2, 1715 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1716 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1717 1718 /* 1719 * Disable MII auto-negotiation. We handle that in 1720 * our own MII layer. 1721 */ 1722 pcn_bcr_write(sc, LE_BCR32, 1723 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1724 } 1725 1726 /* 1727 * Set the Tx and Rx descriptor ring addresses in the init 1728 * block, the TLEN and RLEN other fields of the init block 1729 * MODE register. 1730 */ 1731 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1732 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1733 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1734 ((ffs(PCN_NTXDESC) - 1) << 28) | 1735 ((ffs(PCN_NRXDESC) - 1) << 20)); 1736 1737 /* Set the station address in the init block. */ 1738 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1739 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1740 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1741 (enaddr[5] << 8)); 1742 1743 /* Set the multicast filter in the init block. */ 1744 pcn_set_filter(sc); 1745 1746 /* Initialize CSR3. */ 1747 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1748 1749 /* Initialize CSR4. */ 1750 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1751 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1752 1753 /* Initialize CSR5. */ 1754 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1755 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1756 1757 /* 1758 * If we have an Am79c971 or greater, initialize CSR7. 1759 * 1760 * XXX Might be nice to use the MII auto-poll interrupt someday. 1761 */ 1762 switch (sc->sc_variant->pcv_chipid) { 1763 case PARTID_Am79c970: 1764 case PARTID_Am79c970A: 1765 /* Not available on these chips. */ 1766 break; 1767 1768 default: 1769 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1770 break; 1771 } 1772 1773 /* 1774 * On the Am79c970A and greater, initialize BCR18 to 1775 * enable burst mode. 1776 * 1777 * Also enable the "no underflow" option on the Am79c971 and 1778 * higher, which prevents the chip from generating transmit 1779 * underflows, yet sill provides decent performance. Note if 1780 * chip is not connected to external SRAM, then we still have 1781 * to handle underflow errors (the NOUFLO bit is ignored in 1782 * that case). 1783 */ 1784 reg = pcn_bcr_read(sc, LE_BCR18); 1785 switch (sc->sc_variant->pcv_chipid) { 1786 case PARTID_Am79c970: 1787 break; 1788 1789 case PARTID_Am79c970A: 1790 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1791 break; 1792 1793 default: 1794 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1795 break; 1796 } 1797 pcn_bcr_write(sc, LE_BCR18, reg); 1798 1799 /* 1800 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1801 */ 1802 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1803 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1804 1805 /* 1806 * Send the init block to the chip, and wait for it 1807 * to be processed. 1808 */ 1809 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1810 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1811 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1812 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1813 delay(100); 1814 for (i = 0; i < 10000; i++) { 1815 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1816 break; 1817 delay(10); 1818 } 1819 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1820 if (i == 10000) { 1821 printf("%s: timeout processing init block\n", 1822 device_xname(sc->sc_dev)); 1823 error = EIO; 1824 goto out; 1825 } 1826 1827 /* Set the media. */ 1828 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1829 goto out; 1830 1831 /* Enable interrupts and external activity (and ACK IDON). */ 1832 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1833 1834 if (sc->sc_flags & PCN_F_HAS_MII) { 1835 /* Start the one second MII clock. */ 1836 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1837 } 1838 1839 /* ...all done! */ 1840 ifp->if_flags |= IFF_RUNNING; 1841 ifp->if_flags &= ~IFF_OACTIVE; 1842 1843 out: 1844 if (error) 1845 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1846 return (error); 1847 } 1848 1849 /* 1850 * pcn_rxdrain: 1851 * 1852 * Drain the receive queue. 1853 */ 1854 static void 1855 pcn_rxdrain(struct pcn_softc *sc) 1856 { 1857 struct pcn_rxsoft *rxs; 1858 int i; 1859 1860 for (i = 0; i < PCN_NRXDESC; i++) { 1861 rxs = &sc->sc_rxsoft[i]; 1862 if (rxs->rxs_mbuf != NULL) { 1863 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1864 m_freem(rxs->rxs_mbuf); 1865 rxs->rxs_mbuf = NULL; 1866 } 1867 } 1868 } 1869 1870 /* 1871 * pcn_stop: [ifnet interface function] 1872 * 1873 * Stop transmission on the interface. 1874 */ 1875 static void 1876 pcn_stop(struct ifnet *ifp, int disable) 1877 { 1878 struct pcn_softc *sc = ifp->if_softc; 1879 struct pcn_txsoft *txs; 1880 int i; 1881 1882 if (sc->sc_flags & PCN_F_HAS_MII) { 1883 /* Stop the one second clock. */ 1884 callout_stop(&sc->sc_tick_ch); 1885 1886 /* Down the MII. */ 1887 mii_down(&sc->sc_mii); 1888 } 1889 1890 /* Stop the chip. */ 1891 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1892 1893 /* Release any queued transmit buffers. */ 1894 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1895 txs = &sc->sc_txsoft[i]; 1896 if (txs->txs_mbuf != NULL) { 1897 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1898 m_freem(txs->txs_mbuf); 1899 txs->txs_mbuf = NULL; 1900 } 1901 } 1902 1903 /* Mark the interface as down and cancel the watchdog timer. */ 1904 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1905 ifp->if_timer = 0; 1906 1907 if (disable) 1908 pcn_rxdrain(sc); 1909 } 1910 1911 /* 1912 * pcn_add_rxbuf: 1913 * 1914 * Add a receive buffer to the indicated descriptor. 1915 */ 1916 static int 1917 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1918 { 1919 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1920 struct mbuf *m; 1921 int error; 1922 1923 MGETHDR(m, M_DONTWAIT, MT_DATA); 1924 if (m == NULL) 1925 return (ENOBUFS); 1926 1927 MCLGET(m, M_DONTWAIT); 1928 if ((m->m_flags & M_EXT) == 0) { 1929 m_freem(m); 1930 return (ENOBUFS); 1931 } 1932 1933 if (rxs->rxs_mbuf != NULL) 1934 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1935 1936 rxs->rxs_mbuf = m; 1937 1938 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1939 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1940 BUS_DMA_READ|BUS_DMA_NOWAIT); 1941 if (error) { 1942 printf("%s: can't load rx DMA map %d, error = %d\n", 1943 device_xname(sc->sc_dev), idx, error); 1944 panic("pcn_add_rxbuf"); 1945 } 1946 1947 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1948 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1949 1950 PCN_INIT_RXDESC(sc, idx); 1951 1952 return (0); 1953 } 1954 1955 /* 1956 * pcn_set_filter: 1957 * 1958 * Set up the receive filter. 1959 */ 1960 static void 1961 pcn_set_filter(struct pcn_softc *sc) 1962 { 1963 struct ethercom *ec = &sc->sc_ethercom; 1964 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1965 struct ether_multi *enm; 1966 struct ether_multistep step; 1967 uint32_t crc; 1968 1969 /* 1970 * Set up the multicast address filter by passing all multicast 1971 * addresses through a CRC generator, and then using the high 1972 * order 6 bits as an index into the 64-bit logical address 1973 * filter. The high order bits select the word, while the rest 1974 * of the bits select the bit within the word. 1975 */ 1976 1977 if (ifp->if_flags & IFF_PROMISC) 1978 goto allmulti; 1979 1980 sc->sc_initblock.init_ladrf[0] = 1981 sc->sc_initblock.init_ladrf[1] = 1982 sc->sc_initblock.init_ladrf[2] = 1983 sc->sc_initblock.init_ladrf[3] = 0; 1984 1985 ETHER_FIRST_MULTI(step, ec, enm); 1986 while (enm != NULL) { 1987 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1988 /* 1989 * We must listen to a range of multicast addresses. 1990 * For now, just accept all multicasts, rather than 1991 * trying to set only those filter bits needed to match 1992 * the range. (At this time, the only use of address 1993 * ranges is for IP multicast routing, for which the 1994 * range is big enough to require all bits set.) 1995 */ 1996 goto allmulti; 1997 } 1998 1999 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2000 2001 /* Just want the 6 most significant bits. */ 2002 crc >>= 26; 2003 2004 /* Set the corresponding bit in the filter. */ 2005 sc->sc_initblock.init_ladrf[crc >> 4] |= 2006 htole16(1 << (crc & 0xf)); 2007 2008 ETHER_NEXT_MULTI(step, enm); 2009 } 2010 2011 ifp->if_flags &= ~IFF_ALLMULTI; 2012 return; 2013 2014 allmulti: 2015 ifp->if_flags |= IFF_ALLMULTI; 2016 sc->sc_initblock.init_ladrf[0] = 2017 sc->sc_initblock.init_ladrf[1] = 2018 sc->sc_initblock.init_ladrf[2] = 2019 sc->sc_initblock.init_ladrf[3] = 0xffff; 2020 } 2021 2022 /* 2023 * pcn_79c970_mediainit: 2024 * 2025 * Initialize media for the Am79c970. 2026 */ 2027 static void 2028 pcn_79c970_mediainit(struct pcn_softc *sc) 2029 { 2030 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2031 const char *sep = ""; 2032 2033 sc->sc_mii.mii_ifp = ifp; 2034 2035 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2036 pcn_79c970_mediastatus); 2037 2038 #define ADD(str, m, d) \ 2039 do { \ 2040 printf("%s%s", sep, str); \ 2041 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2042 sep = ", "; \ 2043 } while (/*CONSTCOND*/0) 2044 2045 printf("%s: ", device_xname(sc->sc_dev)); 2046 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2047 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2048 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2049 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2050 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2051 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2052 ADD("auto", IFM_AUTO, 0); 2053 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2054 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2055 printf("\n"); 2056 2057 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2058 } 2059 2060 /* 2061 * pcn_79c970_mediastatus: [ifmedia interface function] 2062 * 2063 * Get the current interface media status (Am79c970 version). 2064 */ 2065 static void 2066 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2067 { 2068 struct pcn_softc *sc = ifp->if_softc; 2069 2070 /* 2071 * The currently selected media is always the active media. 2072 * Note: We have no way to determine what media the AUTO 2073 * process picked. 2074 */ 2075 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2076 } 2077 2078 /* 2079 * pcn_79c970_mediachange: [ifmedia interface function] 2080 * 2081 * Set hardware to newly-selected media (Am79c970 version). 2082 */ 2083 static int 2084 pcn_79c970_mediachange(struct ifnet *ifp) 2085 { 2086 struct pcn_softc *sc = ifp->if_softc; 2087 uint32_t reg; 2088 2089 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2090 /* 2091 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2092 */ 2093 reg = pcn_bcr_read(sc, LE_BCR2); 2094 reg |= LE_B2_ASEL; 2095 pcn_bcr_write(sc, LE_BCR2, reg); 2096 } else { 2097 /* 2098 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2099 */ 2100 reg = pcn_bcr_read(sc, LE_BCR2); 2101 reg &= ~LE_B2_ASEL; 2102 pcn_bcr_write(sc, LE_BCR2, reg); 2103 2104 reg = pcn_csr_read(sc, LE_CSR15); 2105 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2106 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2107 pcn_csr_write(sc, LE_CSR15, reg); 2108 } 2109 2110 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2111 reg = LE_B9_FDEN; 2112 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2113 reg |= LE_B9_AUIFD; 2114 pcn_bcr_write(sc, LE_BCR9, reg); 2115 } else 2116 pcn_bcr_write(sc, LE_BCR9, 0); 2117 2118 return (0); 2119 } 2120 2121 /* 2122 * pcn_79c971_mediainit: 2123 * 2124 * Initialize media for the Am79c971. 2125 */ 2126 static void 2127 pcn_79c971_mediainit(struct pcn_softc *sc) 2128 { 2129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2130 2131 /* We have MII. */ 2132 sc->sc_flags |= PCN_F_HAS_MII; 2133 2134 /* 2135 * The built-in 10BASE-T interface is mapped to the MII 2136 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2137 * word that tells us which PHY to use. 2138 * This driver used to ignore all but the first PHY to 2139 * answer, but this code was removed to support multiple 2140 * external PHYs. As the default instance will be the first 2141 * one to answer, no harm is done by letting the possibly 2142 * non-connected internal PHY show up. 2143 */ 2144 2145 /* Initialize our media structures and probe the MII. */ 2146 sc->sc_mii.mii_ifp = ifp; 2147 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2148 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2149 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2150 2151 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2152 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2153 ether_mediastatus); 2154 2155 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2156 MII_OFFSET_ANY, 0); 2157 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2158 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2159 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2160 } else 2161 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2162 } 2163 2164 /* 2165 * pcn_mii_readreg: [mii interface function] 2166 * 2167 * Read a PHY register on the MII. 2168 */ 2169 static int 2170 pcn_mii_readreg(device_t self, int phy, int reg) 2171 { 2172 struct pcn_softc *sc = device_private(self); 2173 uint32_t rv; 2174 2175 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2176 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2177 if (rv == 0xffff) 2178 return (0); 2179 2180 return (rv); 2181 } 2182 2183 /* 2184 * pcn_mii_writereg: [mii interface function] 2185 * 2186 * Write a PHY register on the MII. 2187 */ 2188 static void 2189 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2190 { 2191 struct pcn_softc *sc = device_private(self); 2192 2193 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2194 pcn_bcr_write(sc, LE_BCR34, val); 2195 } 2196 2197 /* 2198 * pcn_mii_statchg: [mii interface function] 2199 * 2200 * Callback from MII layer when media changes. 2201 */ 2202 static void 2203 pcn_mii_statchg(device_t self) 2204 { 2205 struct pcn_softc *sc = device_private(self); 2206 2207 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2208 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2209 else 2210 pcn_bcr_write(sc, LE_BCR9, 0); 2211 } 2212