1 /* $NetBSD: if_pcn.c,v 1.55 2012/07/22 14:33:03 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.55 2012/07/22 14:33:03 matt Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rnd.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txintr; /* Tx interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 275 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 276 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 277 278 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 279 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 280 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 281 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 282 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 283 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 284 struct evcnt sc_ev_txcopy; /* Tx copies required */ 285 #endif /* PCN_EVENT_COUNTERS */ 286 287 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 288 int sc_rcvfw; 289 290 const char * const *sc_xmtsp_desc; /* Tx start point info */ 291 int sc_xmtsp; 292 293 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 294 int sc_xmtfw; 295 296 int sc_flags; /* misc. flags; see below */ 297 int sc_swstyle; /* the software style in use */ 298 299 int sc_txfree; /* number of free Tx descriptors */ 300 int sc_txnext; /* next ready Tx descriptor */ 301 302 int sc_txsfree; /* number of free Tx jobs */ 303 int sc_txsnext; /* next free Tx job */ 304 int sc_txsdirty; /* dirty Tx jobs */ 305 306 int sc_rxptr; /* next ready Rx descriptor/job */ 307 308 uint32_t sc_csr5; /* prototype CSR5 register */ 309 uint32_t sc_mode; /* prototype MODE register */ 310 311 krndsource_t rnd_source; /* random source */ 312 }; 313 314 /* sc_flags */ 315 #define PCN_F_HAS_MII 0x0001 /* has MII */ 316 317 #ifdef PCN_EVENT_COUNTERS 318 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 319 #else 320 #define PCN_EVCNT_INCR(ev) /* nothing */ 321 #endif 322 323 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 324 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 325 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 326 327 #define PCN_CDTXSYNC(sc, x, n, ops) \ 328 do { \ 329 int __x, __n; \ 330 \ 331 __x = (x); \ 332 __n = (n); \ 333 \ 334 /* If it will wrap around, sync to the end of the ring. */ \ 335 if ((__x + __n) > PCN_NTXDESC) { \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 338 (PCN_NTXDESC - __x), (ops)); \ 339 __n -= (PCN_NTXDESC - __x); \ 340 __x = 0; \ 341 } \ 342 \ 343 /* Now sync whatever is left. */ \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 346 } while (/*CONSTCOND*/0) 347 348 #define PCN_CDRXSYNC(sc, x, ops) \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 351 352 #define PCN_CDINITSYNC(sc, ops) \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 355 356 #define PCN_INIT_RXDESC(sc, x) \ 357 do { \ 358 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 359 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 360 struct mbuf *__m = __rxs->rxs_mbuf; \ 361 \ 362 /* \ 363 * Note: We scoot the packet forward 2 bytes in the buffer \ 364 * so that the payload after the Ethernet header is aligned \ 365 * to a 4-byte boundary. \ 366 */ \ 367 __m->m_data = __m->m_ext.ext_buf + 2; \ 368 \ 369 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 370 __rmd->rmd2 = \ 371 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 372 __rmd->rmd0 = 0; \ 373 } else { \ 374 __rmd->rmd2 = 0; \ 375 __rmd->rmd0 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 } \ 378 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 379 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 380 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 381 } while(/*CONSTCOND*/0) 382 383 static void pcn_start(struct ifnet *); 384 static void pcn_watchdog(struct ifnet *); 385 static int pcn_ioctl(struct ifnet *, u_long, void *); 386 static int pcn_init(struct ifnet *); 387 static void pcn_stop(struct ifnet *, int); 388 389 static bool pcn_shutdown(device_t, int); 390 391 static void pcn_reset(struct pcn_softc *); 392 static void pcn_rxdrain(struct pcn_softc *); 393 static int pcn_add_rxbuf(struct pcn_softc *, int); 394 static void pcn_tick(void *); 395 396 static void pcn_spnd(struct pcn_softc *); 397 398 static void pcn_set_filter(struct pcn_softc *); 399 400 static int pcn_intr(void *); 401 static void pcn_txintr(struct pcn_softc *); 402 static int pcn_rxintr(struct pcn_softc *); 403 404 static int pcn_mii_readreg(device_t, int, int); 405 static void pcn_mii_writereg(device_t, int, int, int); 406 static void pcn_mii_statchg(struct ifnet *); 407 408 static void pcn_79c970_mediainit(struct pcn_softc *); 409 static int pcn_79c970_mediachange(struct ifnet *); 410 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 411 412 static void pcn_79c971_mediainit(struct pcn_softc *); 413 414 /* 415 * Description of a PCnet-PCI variant. Used to select media access 416 * method, mostly, and to print a nice description of the chip. 417 */ 418 static const struct pcn_variant { 419 const char *pcv_desc; 420 void (*pcv_mediainit)(struct pcn_softc *); 421 uint16_t pcv_chipid; 422 } pcn_variants[] = { 423 { "Am79c970 PCnet-PCI", 424 pcn_79c970_mediainit, 425 PARTID_Am79c970 }, 426 427 { "Am79c970A PCnet-PCI II", 428 pcn_79c970_mediainit, 429 PARTID_Am79c970A }, 430 431 { "Am79c971 PCnet-FAST", 432 pcn_79c971_mediainit, 433 PARTID_Am79c971 }, 434 435 { "Am79c972 PCnet-FAST+", 436 pcn_79c971_mediainit, 437 PARTID_Am79c972 }, 438 439 { "Am79c973 PCnet-FAST III", 440 pcn_79c971_mediainit, 441 PARTID_Am79c973 }, 442 443 { "Am79c975 PCnet-FAST III", 444 pcn_79c971_mediainit, 445 PARTID_Am79c975 }, 446 447 { "Unknown PCnet-PCI variant", 448 pcn_79c971_mediainit, 449 0 }, 450 }; 451 452 int pcn_copy_small = 0; 453 454 static int pcn_match(device_t, cfdata_t, void *); 455 static void pcn_attach(device_t, device_t, void *); 456 457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 458 pcn_match, pcn_attach, NULL, NULL); 459 460 /* 461 * Routines to read and write the PCnet-PCI CSR/BCR space. 462 */ 463 464 static inline uint32_t 465 pcn_csr_read(struct pcn_softc *sc, int reg) 466 { 467 468 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 469 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 470 } 471 472 static inline void 473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 478 } 479 480 static inline uint32_t 481 pcn_bcr_read(struct pcn_softc *sc, int reg) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 486 } 487 488 static inline void 489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 494 } 495 496 static bool 497 pcn_is_vmware(const char *enaddr) 498 { 499 500 /* 501 * VMware uses the OUI 00:0c:29 for auto-generated MAC 502 * addresses. 503 */ 504 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 505 return (TRUE); 506 507 /* 508 * VMware uses the OUI 00:50:56 for manually-set MAC 509 * addresses (and some auto-generated ones). 510 */ 511 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 512 return (TRUE); 513 514 return (FALSE); 515 } 516 517 static const struct pcn_variant * 518 pcn_lookup_variant(uint16_t chipid) 519 { 520 const struct pcn_variant *pcv; 521 522 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 523 if (chipid == pcv->pcv_chipid) 524 return (pcv); 525 } 526 527 /* 528 * This covers unknown chips, which we simply treat like 529 * a generic PCnet-FAST. 530 */ 531 return (pcv); 532 } 533 534 static int 535 pcn_match(device_t parent, cfdata_t cf, void *aux) 536 { 537 struct pci_attach_args *pa = aux; 538 539 /* 540 * IBM Makes a PCI variant of this card which shows up as a 541 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 542 * this card is truly a pcn card, so we have a special case match for 543 * it 544 */ 545 546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 548 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 549 return(1); 550 551 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 552 return (0); 553 554 switch (PCI_PRODUCT(pa->pa_id)) { 555 case PCI_PRODUCT_AMD_PCNET_PCI: 556 /* Beat if_le_pci.c */ 557 return (10); 558 } 559 560 return (0); 561 } 562 563 static void 564 pcn_attach(device_t parent, device_t self, void *aux) 565 { 566 struct pcn_softc *sc = device_private(self); 567 struct pci_attach_args *pa = aux; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 pci_intr_handle_t ih; 571 const char *intrstr = NULL; 572 bus_space_tag_t iot, memt; 573 bus_space_handle_t ioh, memh; 574 bus_dma_segment_t seg; 575 int ioh_valid, memh_valid; 576 int ntxsegs, i, rseg, error; 577 uint32_t chipid, reg; 578 uint8_t enaddr[ETHER_ADDR_LEN]; 579 prop_object_t obj; 580 bool is_vmware; 581 582 sc->sc_dev = self; 583 callout_init(&sc->sc_tick_ch, 0); 584 585 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 586 587 /* 588 * Map the device. 589 */ 590 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 591 &iot, &ioh, NULL, NULL) == 0); 592 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 593 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 594 &memt, &memh, NULL, NULL) == 0); 595 596 if (memh_valid) { 597 sc->sc_st = memt; 598 sc->sc_sh = memh; 599 } else if (ioh_valid) { 600 sc->sc_st = iot; 601 sc->sc_sh = ioh; 602 } else { 603 aprint_error_dev(self, "unable to map device registers\n"); 604 return; 605 } 606 607 sc->sc_dmat = pa->pa_dmat; 608 609 /* Make sure bus mastering is enabled. */ 610 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 611 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 612 PCI_COMMAND_MASTER_ENABLE); 613 614 /* power up chip */ 615 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 616 NULL)) && error != EOPNOTSUPP) { 617 aprint_error_dev(self, "cannot activate %d\n", error); 618 return; 619 } 620 621 /* 622 * Reset the chip to a known state. This also puts the 623 * chip into 32-bit mode. 624 */ 625 pcn_reset(sc); 626 627 /* 628 * On some systems with the chip is an on-board device, the 629 * EEPROM is not used. Handle this by reading the MAC address 630 * from the CSRs (assuming that boot firmware has written 631 * it there). 632 */ 633 obj = prop_dictionary_get(device_properties(sc->sc_dev), 634 "am79c970-no-eeprom"); 635 if (prop_bool_true(obj)) { 636 for (i = 0; i < 3; i++) { 637 uint32_t val; 638 val = pcn_csr_read(sc, LE_CSR12 + i); 639 enaddr[2 * i] = val & 0xff; 640 enaddr[2 * i + 1] = (val >> 8) & 0xff; 641 } 642 } else { 643 for (i = 0; i < ETHER_ADDR_LEN; i++) { 644 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 645 PCN32_APROM + i); 646 } 647 } 648 649 /* Check to see if this is a VMware emulated network interface. */ 650 is_vmware = pcn_is_vmware(enaddr); 651 652 /* 653 * Now that the device is mapped, attempt to figure out what 654 * kind of chip we have. Note that IDL has all 32 bits of 655 * the chip ID when we're in 32-bit mode. 656 */ 657 chipid = pcn_csr_read(sc, LE_CSR88); 658 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 659 660 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 661 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 662 ether_sprintf(enaddr)); 663 664 /* 665 * VMware has a bug in its network interface emulation; we must 666 * limit the number of Tx segments. 667 */ 668 if (is_vmware) { 669 ntxsegs = PCN_NTXSEGS_VMWARE; 670 prop_dictionary_set_bool(device_properties(sc->sc_dev), 671 "am79c970-vmware-tx-bug", TRUE); 672 aprint_verbose_dev(self, 673 "VMware Tx segment count bug detected\n"); 674 } else { 675 ntxsegs = PCN_NTXSEGS; 676 } 677 678 /* 679 * Map and establish our interrupt. 680 */ 681 if (pci_intr_map(pa, &ih)) { 682 aprint_error_dev(self, "unable to map interrupt\n"); 683 return; 684 } 685 intrstr = pci_intr_string(pc, ih); 686 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 687 if (sc->sc_ih == NULL) { 688 aprint_error_dev(self, "unable to establish interrupt"); 689 if (intrstr != NULL) 690 aprint_error(" at %s", intrstr); 691 aprint_error("\n"); 692 return; 693 } 694 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 695 696 /* 697 * Allocate the control data structures, and create and load the 698 * DMA map for it. 699 */ 700 if ((error = bus_dmamem_alloc(sc->sc_dmat, 701 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 702 0)) != 0) { 703 aprint_error_dev(self, "unable to allocate control data, " 704 "error = %d\n", error); 705 goto fail_0; 706 } 707 708 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 709 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 710 BUS_DMA_COHERENT)) != 0) { 711 aprint_error_dev(self, "unable to map control data, " 712 "error = %d\n", error); 713 goto fail_1; 714 } 715 716 if ((error = bus_dmamap_create(sc->sc_dmat, 717 sizeof(struct pcn_control_data), 1, 718 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 719 aprint_error_dev(self, "unable to create control data DMA map, " 720 "error = %d\n", error); 721 goto fail_2; 722 } 723 724 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 725 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 726 0)) != 0) { 727 aprint_error_dev(self, 728 "unable to load control data DMA map, error = %d\n", error); 729 goto fail_3; 730 } 731 732 /* Create the transmit buffer DMA maps. */ 733 for (i = 0; i < PCN_TXQUEUELEN; i++) { 734 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 735 ntxsegs, MCLBYTES, 0, 0, 736 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 737 aprint_error_dev(self, 738 "unable to create tx DMA map %d, error = %d\n", 739 i, error); 740 goto fail_4; 741 } 742 } 743 744 /* Create the receive buffer DMA maps. */ 745 for (i = 0; i < PCN_NRXDESC; i++) { 746 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 747 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 748 aprint_error_dev(self, 749 "unable to create rx DMA map %d, error = %d\n", 750 i, error); 751 goto fail_5; 752 } 753 sc->sc_rxsoft[i].rxs_mbuf = NULL; 754 } 755 756 /* Initialize our media structures. */ 757 (*sc->sc_variant->pcv_mediainit)(sc); 758 759 /* 760 * Initialize FIFO watermark info. 761 */ 762 switch (sc->sc_variant->pcv_chipid) { 763 case PARTID_Am79c970: 764 case PARTID_Am79c970A: 765 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 766 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 767 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 768 break; 769 770 default: 771 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 772 /* 773 * Read BCR25 to determine how much SRAM is 774 * on the board. If > 0, then we the chip 775 * uses different Start Point thresholds. 776 * 777 * Note BCR25 and BCR26 are loaded from the 778 * EEPROM on RST, and unaffected by S_RESET, 779 * so we don't really have to worry about 780 * them except for this. 781 */ 782 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 783 if (reg != 0) 784 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 785 else 786 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 787 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 788 break; 789 } 790 791 /* 792 * Set up defaults -- see the tables above for what these 793 * values mean. 794 * 795 * XXX How should we tune RCVFW and XMTFW? 796 */ 797 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 798 sc->sc_xmtsp = 1; 799 sc->sc_xmtfw = 0; 800 801 ifp = &sc->sc_ethercom.ec_if; 802 strcpy(ifp->if_xname, device_xname(self)); 803 ifp->if_softc = sc; 804 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 805 ifp->if_ioctl = pcn_ioctl; 806 ifp->if_start = pcn_start; 807 ifp->if_watchdog = pcn_watchdog; 808 ifp->if_init = pcn_init; 809 ifp->if_stop = pcn_stop; 810 IFQ_SET_READY(&ifp->if_snd); 811 812 /* Attach the interface. */ 813 if_attach(ifp); 814 ether_ifattach(ifp, enaddr); 815 rnd_attach_source(&sc->rnd_source, device_xname(self), 816 RND_TYPE_NET, 0); 817 818 #ifdef PCN_EVENT_COUNTERS 819 /* Attach event counters. */ 820 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 821 NULL, device_xname(self), "txsstall"); 822 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 823 NULL, device_xname(self), "txdstall"); 824 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 825 NULL, device_xname(self), "txintr"); 826 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 827 NULL, device_xname(self), "rxintr"); 828 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 829 NULL, device_xname(self), "babl"); 830 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 831 NULL, device_xname(self), "miss"); 832 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 833 NULL, device_xname(self), "merr"); 834 835 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 836 NULL, device_xname(self), "txseg1"); 837 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 838 NULL, device_xname(self), "txseg2"); 839 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 840 NULL, device_xname(self), "txseg3"); 841 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 842 NULL, device_xname(self), "txseg4"); 843 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txseg5"); 845 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txsegmore"); 847 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txcopy"); 849 #endif /* PCN_EVENT_COUNTERS */ 850 851 /* 852 * Establish power handler with shutdown hook, to make sure 853 * the interface is shutdown during reboot. 854 */ 855 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 856 pmf_class_network_register(self, ifp); 857 else 858 aprint_error_dev(self, "couldn't establish power handler\n"); 859 860 return; 861 862 /* 863 * Free any resources we've allocated during the failed attach 864 * attempt. Do this in reverse order and fall through. 865 */ 866 fail_5: 867 for (i = 0; i < PCN_NRXDESC; i++) { 868 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 869 bus_dmamap_destroy(sc->sc_dmat, 870 sc->sc_rxsoft[i].rxs_dmamap); 871 } 872 fail_4: 873 for (i = 0; i < PCN_TXQUEUELEN; i++) { 874 if (sc->sc_txsoft[i].txs_dmamap != NULL) 875 bus_dmamap_destroy(sc->sc_dmat, 876 sc->sc_txsoft[i].txs_dmamap); 877 } 878 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 879 fail_3: 880 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 881 fail_2: 882 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 883 sizeof(struct pcn_control_data)); 884 fail_1: 885 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 886 fail_0: 887 return; 888 } 889 890 /* 891 * pcn_shutdown: 892 * 893 * Make sure the interface is stopped at reboot time. 894 */ 895 static bool 896 pcn_shutdown(device_t self, int howto) 897 { 898 struct pcn_softc *sc = device_private(self); 899 900 pcn_stop(&sc->sc_ethercom.ec_if, 1); 901 /* explicitly reset the chip for some onboard one with lazy firmware */ 902 pcn_reset(sc); 903 904 return true; 905 } 906 907 /* 908 * pcn_start: [ifnet interface function] 909 * 910 * Start packet transmission on the interface. 911 */ 912 static void 913 pcn_start(struct ifnet *ifp) 914 { 915 struct pcn_softc *sc = ifp->if_softc; 916 struct mbuf *m0, *m; 917 struct pcn_txsoft *txs; 918 bus_dmamap_t dmamap; 919 int error, nexttx, lasttx = -1, ofree, seg; 920 921 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 922 return; 923 924 /* 925 * Remember the previous number of free descriptors and 926 * the first descriptor we'll use. 927 */ 928 ofree = sc->sc_txfree; 929 930 /* 931 * Loop through the send queue, setting up transmit descriptors 932 * until we drain the queue, or use up all available transmit 933 * descriptors. 934 */ 935 for (;;) { 936 /* Grab a packet off the queue. */ 937 IFQ_POLL(&ifp->if_snd, m0); 938 if (m0 == NULL) 939 break; 940 m = NULL; 941 942 /* Get a work queue entry. */ 943 if (sc->sc_txsfree == 0) { 944 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 945 break; 946 } 947 948 txs = &sc->sc_txsoft[sc->sc_txsnext]; 949 dmamap = txs->txs_dmamap; 950 951 /* 952 * Load the DMA map. If this fails, the packet either 953 * didn't fit in the alloted number of segments, or we 954 * were short on resources. In this case, we'll copy 955 * and try again. 956 */ 957 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 958 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 959 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 960 MGETHDR(m, M_DONTWAIT, MT_DATA); 961 if (m == NULL) { 962 printf("%s: unable to allocate Tx mbuf\n", 963 device_xname(sc->sc_dev)); 964 break; 965 } 966 if (m0->m_pkthdr.len > MHLEN) { 967 MCLGET(m, M_DONTWAIT); 968 if ((m->m_flags & M_EXT) == 0) { 969 printf("%s: unable to allocate Tx " 970 "cluster\n", 971 device_xname(sc->sc_dev)); 972 m_freem(m); 973 break; 974 } 975 } 976 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 977 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 978 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 979 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 980 if (error) { 981 printf("%s: unable to load Tx buffer, " 982 "error = %d\n", device_xname(sc->sc_dev), 983 error); 984 break; 985 } 986 } 987 988 /* 989 * Ensure we have enough descriptors free to describe 990 * the packet. Note, we always reserve one descriptor 991 * at the end of the ring as a termination point, to 992 * prevent wrap-around. 993 */ 994 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 995 /* 996 * Not enough free descriptors to transmit this 997 * packet. We haven't committed anything yet, 998 * so just unload the DMA map, put the packet 999 * back on the queue, and punt. Notify the upper 1000 * layer that there are not more slots left. 1001 * 1002 * XXX We could allocate an mbuf and copy, but 1003 * XXX is it worth it? 1004 */ 1005 ifp->if_flags |= IFF_OACTIVE; 1006 bus_dmamap_unload(sc->sc_dmat, dmamap); 1007 if (m != NULL) 1008 m_freem(m); 1009 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1010 break; 1011 } 1012 1013 IFQ_DEQUEUE(&ifp->if_snd, m0); 1014 if (m != NULL) { 1015 m_freem(m0); 1016 m0 = m; 1017 } 1018 1019 /* 1020 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1021 */ 1022 1023 /* Sync the DMA map. */ 1024 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1025 BUS_DMASYNC_PREWRITE); 1026 1027 #ifdef PCN_EVENT_COUNTERS 1028 switch (dmamap->dm_nsegs) { 1029 case 1: 1030 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1031 break; 1032 case 2: 1033 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1034 break; 1035 case 3: 1036 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1037 break; 1038 case 4: 1039 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1040 break; 1041 case 5: 1042 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1043 break; 1044 default: 1045 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1046 break; 1047 } 1048 #endif /* PCN_EVENT_COUNTERS */ 1049 1050 /* 1051 * Initialize the transmit descriptors. 1052 */ 1053 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1054 for (nexttx = sc->sc_txnext, seg = 0; 1055 seg < dmamap->dm_nsegs; 1056 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1057 /* 1058 * If this is the first descriptor we're 1059 * enqueueing, don't set the OWN bit just 1060 * yet. That could cause a race condition. 1061 * We'll do it below. 1062 */ 1063 sc->sc_txdescs[nexttx].tmd0 = 0; 1064 sc->sc_txdescs[nexttx].tmd2 = 1065 htole32(dmamap->dm_segs[seg].ds_addr); 1066 sc->sc_txdescs[nexttx].tmd1 = 1067 htole32(LE_T1_ONES | 1068 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1069 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1070 LE_T1_BCNT_MASK)); 1071 lasttx = nexttx; 1072 } 1073 } else { 1074 for (nexttx = sc->sc_txnext, seg = 0; 1075 seg < dmamap->dm_nsegs; 1076 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1077 /* 1078 * If this is the first descriptor we're 1079 * enqueueing, don't set the OWN bit just 1080 * yet. That could cause a race condition. 1081 * We'll do it below. 1082 */ 1083 sc->sc_txdescs[nexttx].tmd0 = 1084 htole32(dmamap->dm_segs[seg].ds_addr); 1085 sc->sc_txdescs[nexttx].tmd2 = 0; 1086 sc->sc_txdescs[nexttx].tmd1 = 1087 htole32(LE_T1_ONES | 1088 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1089 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1090 LE_T1_BCNT_MASK)); 1091 lasttx = nexttx; 1092 } 1093 } 1094 1095 KASSERT(lasttx != -1); 1096 /* Interrupt on the packet, if appropriate. */ 1097 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1098 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1099 1100 /* Set `start of packet' and `end of packet' appropriately. */ 1101 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1102 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1103 htole32(LE_T1_OWN|LE_T1_STP); 1104 1105 /* Sync the descriptors we're using. */ 1106 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1107 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1108 1109 /* Kick the transmitter. */ 1110 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1111 1112 /* 1113 * Store a pointer to the packet so we can free it later, 1114 * and remember what txdirty will be once the packet is 1115 * done. 1116 */ 1117 txs->txs_mbuf = m0; 1118 txs->txs_firstdesc = sc->sc_txnext; 1119 txs->txs_lastdesc = lasttx; 1120 1121 /* Advance the tx pointer. */ 1122 sc->sc_txfree -= dmamap->dm_nsegs; 1123 sc->sc_txnext = nexttx; 1124 1125 sc->sc_txsfree--; 1126 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1127 1128 /* Pass the packet to any BPF listeners. */ 1129 bpf_mtap(ifp, m0); 1130 } 1131 1132 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1133 /* No more slots left; notify upper layer. */ 1134 ifp->if_flags |= IFF_OACTIVE; 1135 } 1136 1137 if (sc->sc_txfree != ofree) { 1138 /* Set a watchdog timer in case the chip flakes out. */ 1139 ifp->if_timer = 5; 1140 } 1141 } 1142 1143 /* 1144 * pcn_watchdog: [ifnet interface function] 1145 * 1146 * Watchdog timer handler. 1147 */ 1148 static void 1149 pcn_watchdog(struct ifnet *ifp) 1150 { 1151 struct pcn_softc *sc = ifp->if_softc; 1152 1153 /* 1154 * Since we're not interrupting every packet, sweep 1155 * up before we report an error. 1156 */ 1157 pcn_txintr(sc); 1158 1159 if (sc->sc_txfree != PCN_NTXDESC) { 1160 printf("%s: device timeout (txfree %d txsfree %d)\n", 1161 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1162 ifp->if_oerrors++; 1163 1164 /* Reset the interface. */ 1165 (void) pcn_init(ifp); 1166 } 1167 1168 /* Try to get more packets going. */ 1169 pcn_start(ifp); 1170 } 1171 1172 /* 1173 * pcn_ioctl: [ifnet interface function] 1174 * 1175 * Handle control requests from the operator. 1176 */ 1177 static int 1178 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1179 { 1180 struct pcn_softc *sc = ifp->if_softc; 1181 struct ifreq *ifr = (struct ifreq *) data; 1182 int s, error; 1183 1184 s = splnet(); 1185 1186 switch (cmd) { 1187 case SIOCSIFMEDIA: 1188 case SIOCGIFMEDIA: 1189 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1190 break; 1191 1192 default: 1193 error = ether_ioctl(ifp, cmd, data); 1194 if (error == ENETRESET) { 1195 /* 1196 * Multicast list has changed; set the hardware filter 1197 * accordingly. 1198 */ 1199 if (ifp->if_flags & IFF_RUNNING) 1200 error = pcn_init(ifp); 1201 else 1202 error = 0; 1203 } 1204 break; 1205 } 1206 1207 /* Try to get more packets going. */ 1208 pcn_start(ifp); 1209 1210 splx(s); 1211 return (error); 1212 } 1213 1214 /* 1215 * pcn_intr: 1216 * 1217 * Interrupt service routine. 1218 */ 1219 static int 1220 pcn_intr(void *arg) 1221 { 1222 struct pcn_softc *sc = arg; 1223 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1224 uint32_t csr0; 1225 int wantinit, handled = 0; 1226 1227 for (wantinit = 0; wantinit == 0;) { 1228 csr0 = pcn_csr_read(sc, LE_CSR0); 1229 if ((csr0 & LE_C0_INTR) == 0) 1230 break; 1231 1232 rnd_add_uint32(&sc->rnd_source, csr0); 1233 1234 /* ACK the bits and re-enable interrupts. */ 1235 pcn_csr_write(sc, LE_CSR0, csr0 & 1236 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1237 LE_C0_TINT|LE_C0_IDON)); 1238 1239 handled = 1; 1240 1241 if (csr0 & LE_C0_RINT) { 1242 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1243 wantinit = pcn_rxintr(sc); 1244 } 1245 1246 if (csr0 & LE_C0_TINT) { 1247 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1248 pcn_txintr(sc); 1249 } 1250 1251 if (csr0 & LE_C0_ERR) { 1252 if (csr0 & LE_C0_BABL) { 1253 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1254 ifp->if_oerrors++; 1255 } 1256 if (csr0 & LE_C0_MISS) { 1257 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1258 ifp->if_ierrors++; 1259 } 1260 if (csr0 & LE_C0_MERR) { 1261 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1262 printf("%s: memory error\n", 1263 device_xname(sc->sc_dev)); 1264 wantinit = 1; 1265 break; 1266 } 1267 } 1268 1269 if ((csr0 & LE_C0_RXON) == 0) { 1270 printf("%s: receiver disabled\n", 1271 device_xname(sc->sc_dev)); 1272 ifp->if_ierrors++; 1273 wantinit = 1; 1274 } 1275 1276 if ((csr0 & LE_C0_TXON) == 0) { 1277 printf("%s: transmitter disabled\n", 1278 device_xname(sc->sc_dev)); 1279 ifp->if_oerrors++; 1280 wantinit = 1; 1281 } 1282 } 1283 1284 if (handled) { 1285 if (wantinit) 1286 pcn_init(ifp); 1287 1288 /* Try to get more packets going. */ 1289 pcn_start(ifp); 1290 } 1291 1292 return (handled); 1293 } 1294 1295 /* 1296 * pcn_spnd: 1297 * 1298 * Suspend the chip. 1299 */ 1300 static void 1301 pcn_spnd(struct pcn_softc *sc) 1302 { 1303 int i; 1304 1305 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1306 1307 for (i = 0; i < 10000; i++) { 1308 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1309 return; 1310 delay(5); 1311 } 1312 1313 printf("%s: WARNING: chip failed to enter suspended state\n", 1314 device_xname(sc->sc_dev)); 1315 } 1316 1317 /* 1318 * pcn_txintr: 1319 * 1320 * Helper; handle transmit interrupts. 1321 */ 1322 static void 1323 pcn_txintr(struct pcn_softc *sc) 1324 { 1325 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1326 struct pcn_txsoft *txs; 1327 uint32_t tmd1, tmd2, tmd; 1328 int i, j; 1329 1330 ifp->if_flags &= ~IFF_OACTIVE; 1331 1332 /* 1333 * Go through our Tx list and free mbufs for those 1334 * frames which have been transmitted. 1335 */ 1336 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1337 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1338 txs = &sc->sc_txsoft[i]; 1339 1340 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1341 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1342 1343 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1344 if (tmd1 & LE_T1_OWN) 1345 break; 1346 1347 /* 1348 * Slightly annoying -- we have to loop through the 1349 * descriptors we've used looking for ERR, since it 1350 * can appear on any descriptor in the chain. 1351 */ 1352 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1353 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1354 if (tmd & LE_T1_ERR) { 1355 ifp->if_oerrors++; 1356 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1357 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1358 else 1359 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1360 if (tmd2 & LE_T2_UFLO) { 1361 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1362 sc->sc_xmtsp++; 1363 printf("%s: transmit " 1364 "underrun; new threshold: " 1365 "%s\n", 1366 device_xname(sc->sc_dev), 1367 sc->sc_xmtsp_desc[ 1368 sc->sc_xmtsp]); 1369 pcn_spnd(sc); 1370 pcn_csr_write(sc, LE_CSR80, 1371 LE_C80_RCVFW(sc->sc_rcvfw) | 1372 LE_C80_XMTSP(sc->sc_xmtsp) | 1373 LE_C80_XMTFW(sc->sc_xmtfw)); 1374 pcn_csr_write(sc, LE_CSR5, 1375 sc->sc_csr5); 1376 } else { 1377 printf("%s: transmit " 1378 "underrun\n", 1379 device_xname(sc->sc_dev)); 1380 } 1381 } else if (tmd2 & LE_T2_BUFF) { 1382 printf("%s: transmit buffer error\n", 1383 device_xname(sc->sc_dev)); 1384 } 1385 if (tmd2 & LE_T2_LCOL) 1386 ifp->if_collisions++; 1387 if (tmd2 & LE_T2_RTRY) 1388 ifp->if_collisions += 16; 1389 goto next_packet; 1390 } 1391 if (j == txs->txs_lastdesc) 1392 break; 1393 } 1394 if (tmd1 & LE_T1_ONE) 1395 ifp->if_collisions++; 1396 else if (tmd & LE_T1_MORE) { 1397 /* Real number is unknown. */ 1398 ifp->if_collisions += 2; 1399 } 1400 ifp->if_opackets++; 1401 next_packet: 1402 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1403 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1404 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1405 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1406 m_freem(txs->txs_mbuf); 1407 txs->txs_mbuf = NULL; 1408 } 1409 1410 /* Update the dirty transmit buffer pointer. */ 1411 sc->sc_txsdirty = i; 1412 1413 /* 1414 * If there are no more pending transmissions, cancel the watchdog 1415 * timer. 1416 */ 1417 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1418 ifp->if_timer = 0; 1419 } 1420 1421 /* 1422 * pcn_rxintr: 1423 * 1424 * Helper; handle receive interrupts. 1425 */ 1426 static int 1427 pcn_rxintr(struct pcn_softc *sc) 1428 { 1429 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1430 struct pcn_rxsoft *rxs; 1431 struct mbuf *m; 1432 uint32_t rmd1; 1433 int i, len; 1434 1435 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1436 rxs = &sc->sc_rxsoft[i]; 1437 1438 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1439 1440 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1441 1442 if (rmd1 & LE_R1_OWN) 1443 break; 1444 1445 /* 1446 * Check for errors and make sure the packet fit into 1447 * a single buffer. We have structured this block of 1448 * code the way it is in order to compress it into 1449 * one test in the common case (no error). 1450 */ 1451 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1452 (LE_R1_STP|LE_R1_ENP))) { 1453 /* Make sure the packet is in a single buffer. */ 1454 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1455 (LE_R1_STP|LE_R1_ENP)) { 1456 printf("%s: packet spilled into next buffer\n", 1457 device_xname(sc->sc_dev)); 1458 return (1); /* pcn_intr() will re-init */ 1459 } 1460 1461 /* 1462 * If the packet had an error, simple recycle the 1463 * buffer. 1464 */ 1465 if (rmd1 & LE_R1_ERR) { 1466 ifp->if_ierrors++; 1467 /* 1468 * If we got an overflow error, chances 1469 * are there will be a CRC error. In 1470 * this case, just print the overflow 1471 * error, and skip the others. 1472 */ 1473 if (rmd1 & LE_R1_OFLO) 1474 printf("%s: overflow error\n", 1475 device_xname(sc->sc_dev)); 1476 else { 1477 #define PRINTIT(x, str) \ 1478 if (rmd1 & (x)) \ 1479 printf("%s: %s\n", \ 1480 device_xname(sc->sc_dev), \ 1481 str); 1482 PRINTIT(LE_R1_FRAM, "framing error"); 1483 PRINTIT(LE_R1_CRC, "CRC error"); 1484 PRINTIT(LE_R1_BUFF, "buffer error"); 1485 } 1486 #undef PRINTIT 1487 PCN_INIT_RXDESC(sc, i); 1488 continue; 1489 } 1490 } 1491 1492 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1493 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1494 1495 /* 1496 * No errors; receive the packet. 1497 */ 1498 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1499 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1500 else 1501 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1502 1503 /* 1504 * The LANCE family includes the CRC with every packet; 1505 * trim it off here. 1506 */ 1507 len -= ETHER_CRC_LEN; 1508 1509 /* 1510 * If the packet is small enough to fit in a 1511 * single header mbuf, allocate one and copy 1512 * the data into it. This greatly reduces 1513 * memory consumption when we receive lots 1514 * of small packets. 1515 * 1516 * Otherwise, we add a new buffer to the receive 1517 * chain. If this fails, we drop the packet and 1518 * recycle the old buffer. 1519 */ 1520 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1521 MGETHDR(m, M_DONTWAIT, MT_DATA); 1522 if (m == NULL) 1523 goto dropit; 1524 m->m_data += 2; 1525 memcpy(mtod(m, void *), 1526 mtod(rxs->rxs_mbuf, void *), len); 1527 PCN_INIT_RXDESC(sc, i); 1528 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1529 rxs->rxs_dmamap->dm_mapsize, 1530 BUS_DMASYNC_PREREAD); 1531 } else { 1532 m = rxs->rxs_mbuf; 1533 if (pcn_add_rxbuf(sc, i) != 0) { 1534 dropit: 1535 ifp->if_ierrors++; 1536 PCN_INIT_RXDESC(sc, i); 1537 bus_dmamap_sync(sc->sc_dmat, 1538 rxs->rxs_dmamap, 0, 1539 rxs->rxs_dmamap->dm_mapsize, 1540 BUS_DMASYNC_PREREAD); 1541 continue; 1542 } 1543 } 1544 1545 m->m_pkthdr.rcvif = ifp; 1546 m->m_pkthdr.len = m->m_len = len; 1547 1548 /* Pass this up to any BPF listeners. */ 1549 bpf_mtap(ifp, m); 1550 1551 /* Pass it on. */ 1552 (*ifp->if_input)(ifp, m); 1553 ifp->if_ipackets++; 1554 } 1555 1556 /* Update the receive pointer. */ 1557 sc->sc_rxptr = i; 1558 return (0); 1559 } 1560 1561 /* 1562 * pcn_tick: 1563 * 1564 * One second timer, used to tick the MII. 1565 */ 1566 static void 1567 pcn_tick(void *arg) 1568 { 1569 struct pcn_softc *sc = arg; 1570 int s; 1571 1572 s = splnet(); 1573 mii_tick(&sc->sc_mii); 1574 splx(s); 1575 1576 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1577 } 1578 1579 /* 1580 * pcn_reset: 1581 * 1582 * Perform a soft reset on the PCnet-PCI. 1583 */ 1584 static void 1585 pcn_reset(struct pcn_softc *sc) 1586 { 1587 1588 /* 1589 * The PCnet-PCI chip is reset by reading from the 1590 * RESET register. Note that while the NE2100 LANCE 1591 * boards require a write after the read, the PCnet-PCI 1592 * chips do not require this. 1593 * 1594 * Since we don't know if we're in 16-bit or 32-bit 1595 * mode right now, issue both (it's safe) in the 1596 * hopes that one will succeed. 1597 */ 1598 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1599 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1600 1601 /* Wait 1ms for it to finish. */ 1602 delay(1000); 1603 1604 /* 1605 * Select 32-bit I/O mode by issuing a 32-bit write to the 1606 * RDP. Since the RAP is 0 after a reset, writing a 0 1607 * to RDP is safe (since it simply clears CSR0). 1608 */ 1609 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1610 } 1611 1612 /* 1613 * pcn_init: [ifnet interface function] 1614 * 1615 * Initialize the interface. Must be called at splnet(). 1616 */ 1617 static int 1618 pcn_init(struct ifnet *ifp) 1619 { 1620 struct pcn_softc *sc = ifp->if_softc; 1621 struct pcn_rxsoft *rxs; 1622 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1623 int i, error = 0; 1624 uint32_t reg; 1625 1626 /* Cancel any pending I/O. */ 1627 pcn_stop(ifp, 0); 1628 1629 /* Reset the chip to a known state. */ 1630 pcn_reset(sc); 1631 1632 /* 1633 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1634 * else. 1635 * 1636 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1637 * because the structure layout is compatible with ILACC, 1638 * but the burst mode is only available in SSTYLE 3, and 1639 * burst mode should provide some performance enhancement. 1640 */ 1641 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1642 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1643 else 1644 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1645 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1646 1647 /* Initialize the transmit descriptor ring. */ 1648 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1649 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1650 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1651 sc->sc_txfree = PCN_NTXDESC; 1652 sc->sc_txnext = 0; 1653 1654 /* Initialize the transmit job descriptors. */ 1655 for (i = 0; i < PCN_TXQUEUELEN; i++) 1656 sc->sc_txsoft[i].txs_mbuf = NULL; 1657 sc->sc_txsfree = PCN_TXQUEUELEN; 1658 sc->sc_txsnext = 0; 1659 sc->sc_txsdirty = 0; 1660 1661 /* 1662 * Initialize the receive descriptor and receive job 1663 * descriptor rings. 1664 */ 1665 for (i = 0; i < PCN_NRXDESC; i++) { 1666 rxs = &sc->sc_rxsoft[i]; 1667 if (rxs->rxs_mbuf == NULL) { 1668 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1669 printf("%s: unable to allocate or map rx " 1670 "buffer %d, error = %d\n", 1671 device_xname(sc->sc_dev), i, error); 1672 /* 1673 * XXX Should attempt to run with fewer receive 1674 * XXX buffers instead of just failing. 1675 */ 1676 pcn_rxdrain(sc); 1677 goto out; 1678 } 1679 } else 1680 PCN_INIT_RXDESC(sc, i); 1681 } 1682 sc->sc_rxptr = 0; 1683 1684 /* Initialize MODE for the initialization block. */ 1685 sc->sc_mode = 0; 1686 if (ifp->if_flags & IFF_PROMISC) 1687 sc->sc_mode |= LE_C15_PROM; 1688 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1689 sc->sc_mode |= LE_C15_DRCVBC; 1690 1691 /* 1692 * If we have MII, simply select MII in the MODE register, 1693 * and clear ASEL. Otherwise, let ASEL stand (for now), 1694 * and leave PORTSEL alone (it is ignored with ASEL is set). 1695 */ 1696 if (sc->sc_flags & PCN_F_HAS_MII) { 1697 pcn_bcr_write(sc, LE_BCR2, 1698 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1699 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1700 1701 /* 1702 * Disable MII auto-negotiation. We handle that in 1703 * our own MII layer. 1704 */ 1705 pcn_bcr_write(sc, LE_BCR32, 1706 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1707 } 1708 1709 /* 1710 * Set the Tx and Rx descriptor ring addresses in the init 1711 * block, the TLEN and RLEN other fields of the init block 1712 * MODE register. 1713 */ 1714 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1715 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1716 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1717 ((ffs(PCN_NTXDESC) - 1) << 28) | 1718 ((ffs(PCN_NRXDESC) - 1) << 20)); 1719 1720 /* Set the station address in the init block. */ 1721 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1722 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1723 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1724 (enaddr[5] << 8)); 1725 1726 /* Set the multicast filter in the init block. */ 1727 pcn_set_filter(sc); 1728 1729 /* Initialize CSR3. */ 1730 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1731 1732 /* Initialize CSR4. */ 1733 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1734 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1735 1736 /* Initialize CSR5. */ 1737 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1738 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1739 1740 /* 1741 * If we have an Am79c971 or greater, initialize CSR7. 1742 * 1743 * XXX Might be nice to use the MII auto-poll interrupt someday. 1744 */ 1745 switch (sc->sc_variant->pcv_chipid) { 1746 case PARTID_Am79c970: 1747 case PARTID_Am79c970A: 1748 /* Not available on these chips. */ 1749 break; 1750 1751 default: 1752 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1753 break; 1754 } 1755 1756 /* 1757 * On the Am79c970A and greater, initialize BCR18 to 1758 * enable burst mode. 1759 * 1760 * Also enable the "no underflow" option on the Am79c971 and 1761 * higher, which prevents the chip from generating transmit 1762 * underflows, yet sill provides decent performance. Note if 1763 * chip is not connected to external SRAM, then we still have 1764 * to handle underflow errors (the NOUFLO bit is ignored in 1765 * that case). 1766 */ 1767 reg = pcn_bcr_read(sc, LE_BCR18); 1768 switch (sc->sc_variant->pcv_chipid) { 1769 case PARTID_Am79c970: 1770 break; 1771 1772 case PARTID_Am79c970A: 1773 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1774 break; 1775 1776 default: 1777 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1778 break; 1779 } 1780 pcn_bcr_write(sc, LE_BCR18, reg); 1781 1782 /* 1783 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1784 */ 1785 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1786 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1787 1788 /* 1789 * Send the init block to the chip, and wait for it 1790 * to be processed. 1791 */ 1792 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1793 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1794 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1795 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1796 delay(100); 1797 for (i = 0; i < 10000; i++) { 1798 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1799 break; 1800 delay(10); 1801 } 1802 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1803 if (i == 10000) { 1804 printf("%s: timeout processing init block\n", 1805 device_xname(sc->sc_dev)); 1806 error = EIO; 1807 goto out; 1808 } 1809 1810 /* Set the media. */ 1811 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1812 goto out; 1813 1814 /* Enable interrupts and external activity (and ACK IDON). */ 1815 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1816 1817 if (sc->sc_flags & PCN_F_HAS_MII) { 1818 /* Start the one second MII clock. */ 1819 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1820 } 1821 1822 /* ...all done! */ 1823 ifp->if_flags |= IFF_RUNNING; 1824 ifp->if_flags &= ~IFF_OACTIVE; 1825 1826 out: 1827 if (error) 1828 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1829 return (error); 1830 } 1831 1832 /* 1833 * pcn_rxdrain: 1834 * 1835 * Drain the receive queue. 1836 */ 1837 static void 1838 pcn_rxdrain(struct pcn_softc *sc) 1839 { 1840 struct pcn_rxsoft *rxs; 1841 int i; 1842 1843 for (i = 0; i < PCN_NRXDESC; i++) { 1844 rxs = &sc->sc_rxsoft[i]; 1845 if (rxs->rxs_mbuf != NULL) { 1846 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1847 m_freem(rxs->rxs_mbuf); 1848 rxs->rxs_mbuf = NULL; 1849 } 1850 } 1851 } 1852 1853 /* 1854 * pcn_stop: [ifnet interface function] 1855 * 1856 * Stop transmission on the interface. 1857 */ 1858 static void 1859 pcn_stop(struct ifnet *ifp, int disable) 1860 { 1861 struct pcn_softc *sc = ifp->if_softc; 1862 struct pcn_txsoft *txs; 1863 int i; 1864 1865 if (sc->sc_flags & PCN_F_HAS_MII) { 1866 /* Stop the one second clock. */ 1867 callout_stop(&sc->sc_tick_ch); 1868 1869 /* Down the MII. */ 1870 mii_down(&sc->sc_mii); 1871 } 1872 1873 /* Stop the chip. */ 1874 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1875 1876 /* Release any queued transmit buffers. */ 1877 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1878 txs = &sc->sc_txsoft[i]; 1879 if (txs->txs_mbuf != NULL) { 1880 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1881 m_freem(txs->txs_mbuf); 1882 txs->txs_mbuf = NULL; 1883 } 1884 } 1885 1886 /* Mark the interface as down and cancel the watchdog timer. */ 1887 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1888 ifp->if_timer = 0; 1889 1890 if (disable) 1891 pcn_rxdrain(sc); 1892 } 1893 1894 /* 1895 * pcn_add_rxbuf: 1896 * 1897 * Add a receive buffer to the indicated descriptor. 1898 */ 1899 static int 1900 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1901 { 1902 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1903 struct mbuf *m; 1904 int error; 1905 1906 MGETHDR(m, M_DONTWAIT, MT_DATA); 1907 if (m == NULL) 1908 return (ENOBUFS); 1909 1910 MCLGET(m, M_DONTWAIT); 1911 if ((m->m_flags & M_EXT) == 0) { 1912 m_freem(m); 1913 return (ENOBUFS); 1914 } 1915 1916 if (rxs->rxs_mbuf != NULL) 1917 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1918 1919 rxs->rxs_mbuf = m; 1920 1921 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1922 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1923 BUS_DMA_READ|BUS_DMA_NOWAIT); 1924 if (error) { 1925 printf("%s: can't load rx DMA map %d, error = %d\n", 1926 device_xname(sc->sc_dev), idx, error); 1927 panic("pcn_add_rxbuf"); 1928 } 1929 1930 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1931 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1932 1933 PCN_INIT_RXDESC(sc, idx); 1934 1935 return (0); 1936 } 1937 1938 /* 1939 * pcn_set_filter: 1940 * 1941 * Set up the receive filter. 1942 */ 1943 static void 1944 pcn_set_filter(struct pcn_softc *sc) 1945 { 1946 struct ethercom *ec = &sc->sc_ethercom; 1947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1948 struct ether_multi *enm; 1949 struct ether_multistep step; 1950 uint32_t crc; 1951 1952 /* 1953 * Set up the multicast address filter by passing all multicast 1954 * addresses through a CRC generator, and then using the high 1955 * order 6 bits as an index into the 64-bit logical address 1956 * filter. The high order bits select the word, while the rest 1957 * of the bits select the bit within the word. 1958 */ 1959 1960 if (ifp->if_flags & IFF_PROMISC) 1961 goto allmulti; 1962 1963 sc->sc_initblock.init_ladrf[0] = 1964 sc->sc_initblock.init_ladrf[1] = 1965 sc->sc_initblock.init_ladrf[2] = 1966 sc->sc_initblock.init_ladrf[3] = 0; 1967 1968 ETHER_FIRST_MULTI(step, ec, enm); 1969 while (enm != NULL) { 1970 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1971 /* 1972 * We must listen to a range of multicast addresses. 1973 * For now, just accept all multicasts, rather than 1974 * trying to set only those filter bits needed to match 1975 * the range. (At this time, the only use of address 1976 * ranges is for IP multicast routing, for which the 1977 * range is big enough to require all bits set.) 1978 */ 1979 goto allmulti; 1980 } 1981 1982 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1983 1984 /* Just want the 6 most significant bits. */ 1985 crc >>= 26; 1986 1987 /* Set the corresponding bit in the filter. */ 1988 sc->sc_initblock.init_ladrf[crc >> 4] |= 1989 htole16(1 << (crc & 0xf)); 1990 1991 ETHER_NEXT_MULTI(step, enm); 1992 } 1993 1994 ifp->if_flags &= ~IFF_ALLMULTI; 1995 return; 1996 1997 allmulti: 1998 ifp->if_flags |= IFF_ALLMULTI; 1999 sc->sc_initblock.init_ladrf[0] = 2000 sc->sc_initblock.init_ladrf[1] = 2001 sc->sc_initblock.init_ladrf[2] = 2002 sc->sc_initblock.init_ladrf[3] = 0xffff; 2003 } 2004 2005 /* 2006 * pcn_79c970_mediainit: 2007 * 2008 * Initialize media for the Am79c970. 2009 */ 2010 static void 2011 pcn_79c970_mediainit(struct pcn_softc *sc) 2012 { 2013 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2014 const char *sep = ""; 2015 2016 sc->sc_mii.mii_ifp = ifp; 2017 2018 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2019 pcn_79c970_mediastatus); 2020 2021 #define ADD(str, m, d) \ 2022 do { \ 2023 aprint_normal("%s%s", sep, str); \ 2024 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2025 sep = ", "; \ 2026 } while (/*CONSTCOND*/0) 2027 2028 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2029 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2030 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2031 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2032 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2033 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2034 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2035 ADD("auto", IFM_AUTO, 0); 2036 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2037 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2038 aprint_normal("\n"); 2039 2040 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2041 } 2042 2043 /* 2044 * pcn_79c970_mediastatus: [ifmedia interface function] 2045 * 2046 * Get the current interface media status (Am79c970 version). 2047 */ 2048 static void 2049 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2050 { 2051 struct pcn_softc *sc = ifp->if_softc; 2052 2053 /* 2054 * The currently selected media is always the active media. 2055 * Note: We have no way to determine what media the AUTO 2056 * process picked. 2057 */ 2058 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2059 } 2060 2061 /* 2062 * pcn_79c970_mediachange: [ifmedia interface function] 2063 * 2064 * Set hardware to newly-selected media (Am79c970 version). 2065 */ 2066 static int 2067 pcn_79c970_mediachange(struct ifnet *ifp) 2068 { 2069 struct pcn_softc *sc = ifp->if_softc; 2070 uint32_t reg; 2071 2072 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2073 /* 2074 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2075 */ 2076 reg = pcn_bcr_read(sc, LE_BCR2); 2077 reg |= LE_B2_ASEL; 2078 pcn_bcr_write(sc, LE_BCR2, reg); 2079 } else { 2080 /* 2081 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2082 */ 2083 reg = pcn_bcr_read(sc, LE_BCR2); 2084 reg &= ~LE_B2_ASEL; 2085 pcn_bcr_write(sc, LE_BCR2, reg); 2086 2087 reg = pcn_csr_read(sc, LE_CSR15); 2088 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2089 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2090 pcn_csr_write(sc, LE_CSR15, reg); 2091 } 2092 2093 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2094 reg = LE_B9_FDEN; 2095 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2096 reg |= LE_B9_AUIFD; 2097 pcn_bcr_write(sc, LE_BCR9, reg); 2098 } else 2099 pcn_bcr_write(sc, LE_BCR9, 0); 2100 2101 return (0); 2102 } 2103 2104 /* 2105 * pcn_79c971_mediainit: 2106 * 2107 * Initialize media for the Am79c971. 2108 */ 2109 static void 2110 pcn_79c971_mediainit(struct pcn_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2113 2114 /* We have MII. */ 2115 sc->sc_flags |= PCN_F_HAS_MII; 2116 2117 /* 2118 * The built-in 10BASE-T interface is mapped to the MII 2119 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2120 * word that tells us which PHY to use. 2121 * This driver used to ignore all but the first PHY to 2122 * answer, but this code was removed to support multiple 2123 * external PHYs. As the default instance will be the first 2124 * one to answer, no harm is done by letting the possibly 2125 * non-connected internal PHY show up. 2126 */ 2127 2128 /* Initialize our media structures and probe the MII. */ 2129 sc->sc_mii.mii_ifp = ifp; 2130 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2131 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2132 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2133 2134 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2135 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2136 ether_mediastatus); 2137 2138 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2139 MII_OFFSET_ANY, 0); 2140 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2141 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2142 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2143 } else 2144 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2145 } 2146 2147 /* 2148 * pcn_mii_readreg: [mii interface function] 2149 * 2150 * Read a PHY register on the MII. 2151 */ 2152 static int 2153 pcn_mii_readreg(device_t self, int phy, int reg) 2154 { 2155 struct pcn_softc *sc = device_private(self); 2156 uint32_t rv; 2157 2158 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2159 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2160 if (rv == 0xffff) 2161 return (0); 2162 2163 return (rv); 2164 } 2165 2166 /* 2167 * pcn_mii_writereg: [mii interface function] 2168 * 2169 * Write a PHY register on the MII. 2170 */ 2171 static void 2172 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2173 { 2174 struct pcn_softc *sc = device_private(self); 2175 2176 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2177 pcn_bcr_write(sc, LE_BCR34, val); 2178 } 2179 2180 /* 2181 * pcn_mii_statchg: [mii interface function] 2182 * 2183 * Callback from MII layer when media changes. 2184 */ 2185 static void 2186 pcn_mii_statchg(struct ifnet *ifp) 2187 { 2188 struct pcn_softc *sc = ifp->if_softc; 2189 2190 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2191 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2192 else 2193 pcn_bcr_write(sc, LE_BCR9, 0); 2194 } 2195