1 /* $NetBSD: if_pcn.c,v 1.51 2010/04/30 21:17:19 hubertf Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.51 2010/04/30 21:17:19 hubertf Exp $"); 69 70 #include "rnd.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/if_ether.h> 94 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/ic/am79900reg.h> 105 #include <dev/ic/lancereg.h> 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/pci/if_pcnreg.h> 112 113 /* 114 * Transmit descriptor list size. This is arbitrary, but allocate 115 * enough descriptors for 128 pending transmissions, and 4 segments 116 * per packet. This MUST work out to a power of 2. 117 * 118 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 119 * 120 * So we play a little trick here. We give each packet up to 16 121 * DMA segments, but only allocate the max of 512 descriptors. The 122 * transmit logic can deal with this, we just are hoping to sneak by. 123 */ 124 #define PCN_NTXSEGS 16 125 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 126 127 #define PCN_TXQUEUELEN 128 128 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 129 #define PCN_NTXDESC 512 130 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 131 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 132 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 133 134 /* Tx interrupt every N + 1 packets. */ 135 #define PCN_TXINTR_MASK 7 136 137 /* 138 * Receive descriptor list size. We have one Rx buffer per incoming 139 * packet, so this logic is a little simpler. 140 */ 141 #define PCN_NRXDESC 128 142 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 143 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 144 145 /* 146 * Control structures are DMA'd to the PCnet chip. We allocate them in 147 * a single clump that maps to a single DMA segment to make several things 148 * easier. 149 */ 150 struct pcn_control_data { 151 /* The transmit descriptors. */ 152 struct letmd pcd_txdescs[PCN_NTXDESC]; 153 154 /* The receive descriptors. */ 155 struct lermd pcd_rxdescs[PCN_NRXDESC]; 156 157 /* The init block. */ 158 struct leinit pcd_initblock; 159 }; 160 161 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 162 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 163 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 164 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 165 166 /* 167 * Software state for transmit jobs. 168 */ 169 struct pcn_txsoft { 170 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 171 bus_dmamap_t txs_dmamap; /* our DMA map */ 172 int txs_firstdesc; /* first descriptor in packet */ 173 int txs_lastdesc; /* last descriptor in packet */ 174 }; 175 176 /* 177 * Software state for receive jobs. 178 */ 179 struct pcn_rxsoft { 180 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 181 bus_dmamap_t rxs_dmamap; /* our DMA map */ 182 }; 183 184 /* 185 * Description of Rx FIFO watermarks for various revisions. 186 */ 187 static const char * const pcn_79c970_rcvfw[] = { 188 "16 bytes", 189 "64 bytes", 190 "128 bytes", 191 NULL, 192 }; 193 194 static const char * const pcn_79c971_rcvfw[] = { 195 "16 bytes", 196 "64 bytes", 197 "112 bytes", 198 NULL, 199 }; 200 201 /* 202 * Description of Tx start points for various revisions. 203 */ 204 static const char * const pcn_79c970_xmtsp[] = { 205 "8 bytes", 206 "64 bytes", 207 "128 bytes", 208 "248 bytes", 209 }; 210 211 static const char * const pcn_79c971_xmtsp[] = { 212 "20 bytes", 213 "64 bytes", 214 "128 bytes", 215 "248 bytes", 216 }; 217 218 static const char * const pcn_79c971_xmtsp_sram[] = { 219 "44 bytes", 220 "64 bytes", 221 "128 bytes", 222 "store-and-forward", 223 }; 224 225 /* 226 * Description of Tx FIFO watermarks for various revisions. 227 */ 228 static const char * const pcn_79c970_xmtfw[] = { 229 "16 bytes", 230 "64 bytes", 231 "128 bytes", 232 NULL, 233 }; 234 235 static const char * const pcn_79c971_xmtfw[] = { 236 "16 bytes", 237 "64 bytes", 238 "108 bytes", 239 NULL, 240 }; 241 242 /* 243 * Software state per device. 244 */ 245 struct pcn_softc { 246 device_t sc_dev; /* generic device information */ 247 bus_space_tag_t sc_st; /* bus space tag */ 248 bus_space_handle_t sc_sh; /* bus space handle */ 249 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 250 struct ethercom sc_ethercom; /* Ethernet common data */ 251 252 /* Points to our media routines, etc. */ 253 const struct pcn_variant *sc_variant; 254 255 void *sc_ih; /* interrupt cookie */ 256 257 struct mii_data sc_mii; /* MII/media information */ 258 259 callout_t sc_tick_ch; /* tick callout */ 260 261 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 262 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 263 264 /* Software state for transmit and receive descriptors. */ 265 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 266 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 267 268 /* Control data structures */ 269 struct pcn_control_data *sc_control_data; 270 #define sc_txdescs sc_control_data->pcd_txdescs 271 #define sc_rxdescs sc_control_data->pcd_rxdescs 272 #define sc_initblock sc_control_data->pcd_initblock 273 274 #ifdef PCN_EVENT_COUNTERS 275 /* Event counters. */ 276 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 277 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 278 struct evcnt sc_ev_txintr; /* Tx interrupts */ 279 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 280 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 281 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 282 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 283 284 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 285 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 286 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 287 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 288 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 289 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 290 struct evcnt sc_ev_txcopy; /* Tx copies required */ 291 #endif /* PCN_EVENT_COUNTERS */ 292 293 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 294 int sc_rcvfw; 295 296 const char * const *sc_xmtsp_desc; /* Tx start point info */ 297 int sc_xmtsp; 298 299 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 300 int sc_xmtfw; 301 302 int sc_flags; /* misc. flags; see below */ 303 int sc_swstyle; /* the software style in use */ 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 308 int sc_txsfree; /* number of free Tx jobs */ 309 int sc_txsnext; /* next free Tx job */ 310 int sc_txsdirty; /* dirty Tx jobs */ 311 312 int sc_rxptr; /* next ready Rx descriptor/job */ 313 314 uint32_t sc_csr5; /* prototype CSR5 register */ 315 uint32_t sc_mode; /* prototype MODE register */ 316 317 #if NRND > 0 318 rndsource_element_t rnd_source; /* random source */ 319 #endif 320 }; 321 322 /* sc_flags */ 323 #define PCN_F_HAS_MII 0x0001 /* has MII */ 324 325 #ifdef PCN_EVENT_COUNTERS 326 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 327 #else 328 #define PCN_EVCNT_INCR(ev) /* nothing */ 329 #endif 330 331 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 332 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 333 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 334 335 #define PCN_CDTXSYNC(sc, x, n, ops) \ 336 do { \ 337 int __x, __n; \ 338 \ 339 __x = (x); \ 340 __n = (n); \ 341 \ 342 /* If it will wrap around, sync to the end of the ring. */ \ 343 if ((__x + __n) > PCN_NTXDESC) { \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 346 (PCN_NTXDESC - __x), (ops)); \ 347 __n -= (PCN_NTXDESC - __x); \ 348 __x = 0; \ 349 } \ 350 \ 351 /* Now sync whatever is left. */ \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 354 } while (/*CONSTCOND*/0) 355 356 #define PCN_CDRXSYNC(sc, x, ops) \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 359 360 #define PCN_CDINITSYNC(sc, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 363 364 #define PCN_INIT_RXDESC(sc, x) \ 365 do { \ 366 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 367 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 368 struct mbuf *__m = __rxs->rxs_mbuf; \ 369 \ 370 /* \ 371 * Note: We scoot the packet forward 2 bytes in the buffer \ 372 * so that the payload after the Ethernet header is aligned \ 373 * to a 4-byte boundary. \ 374 */ \ 375 __m->m_data = __m->m_ext.ext_buf + 2; \ 376 \ 377 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 378 __rmd->rmd2 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 __rmd->rmd0 = 0; \ 381 } else { \ 382 __rmd->rmd2 = 0; \ 383 __rmd->rmd0 = \ 384 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 385 } \ 386 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 387 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 388 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 389 } while(/*CONSTCOND*/0) 390 391 static void pcn_start(struct ifnet *); 392 static void pcn_watchdog(struct ifnet *); 393 static int pcn_ioctl(struct ifnet *, u_long, void *); 394 static int pcn_init(struct ifnet *); 395 static void pcn_stop(struct ifnet *, int); 396 397 static bool pcn_shutdown(device_t, int); 398 399 static void pcn_reset(struct pcn_softc *); 400 static void pcn_rxdrain(struct pcn_softc *); 401 static int pcn_add_rxbuf(struct pcn_softc *, int); 402 static void pcn_tick(void *); 403 404 static void pcn_spnd(struct pcn_softc *); 405 406 static void pcn_set_filter(struct pcn_softc *); 407 408 static int pcn_intr(void *); 409 static void pcn_txintr(struct pcn_softc *); 410 static int pcn_rxintr(struct pcn_softc *); 411 412 static int pcn_mii_readreg(device_t, int, int); 413 static void pcn_mii_writereg(device_t, int, int, int); 414 static void pcn_mii_statchg(device_t); 415 416 static void pcn_79c970_mediainit(struct pcn_softc *); 417 static int pcn_79c970_mediachange(struct ifnet *); 418 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 419 420 static void pcn_79c971_mediainit(struct pcn_softc *); 421 422 /* 423 * Description of a PCnet-PCI variant. Used to select media access 424 * method, mostly, and to print a nice description of the chip. 425 */ 426 static const struct pcn_variant { 427 const char *pcv_desc; 428 void (*pcv_mediainit)(struct pcn_softc *); 429 uint16_t pcv_chipid; 430 } pcn_variants[] = { 431 { "Am79c970 PCnet-PCI", 432 pcn_79c970_mediainit, 433 PARTID_Am79c970 }, 434 435 { "Am79c970A PCnet-PCI II", 436 pcn_79c970_mediainit, 437 PARTID_Am79c970A }, 438 439 { "Am79c971 PCnet-FAST", 440 pcn_79c971_mediainit, 441 PARTID_Am79c971 }, 442 443 { "Am79c972 PCnet-FAST+", 444 pcn_79c971_mediainit, 445 PARTID_Am79c972 }, 446 447 { "Am79c973 PCnet-FAST III", 448 pcn_79c971_mediainit, 449 PARTID_Am79c973 }, 450 451 { "Am79c975 PCnet-FAST III", 452 pcn_79c971_mediainit, 453 PARTID_Am79c975 }, 454 455 { "Unknown PCnet-PCI variant", 456 pcn_79c971_mediainit, 457 0 }, 458 }; 459 460 int pcn_copy_small = 0; 461 462 static int pcn_match(device_t, cfdata_t, void *); 463 static void pcn_attach(device_t, device_t, void *); 464 465 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 466 pcn_match, pcn_attach, NULL, NULL); 467 468 /* 469 * Routines to read and write the PCnet-PCI CSR/BCR space. 470 */ 471 472 static inline uint32_t 473 pcn_csr_read(struct pcn_softc *sc, int reg) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 478 } 479 480 static inline void 481 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 486 } 487 488 static inline uint32_t 489 pcn_bcr_read(struct pcn_softc *sc, int reg) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 494 } 495 496 static inline void 497 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 498 { 499 500 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 501 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 502 } 503 504 static bool 505 pcn_is_vmware(const char *enaddr) 506 { 507 508 /* 509 * VMware uses the OUI 00:0c:29 for auto-generated MAC 510 * addresses. 511 */ 512 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 513 return (TRUE); 514 515 /* 516 * VMware uses the OUI 00:50:56 for manually-set MAC 517 * addresses (and some auto-generated ones). 518 */ 519 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 520 return (TRUE); 521 522 return (FALSE); 523 } 524 525 static const struct pcn_variant * 526 pcn_lookup_variant(uint16_t chipid) 527 { 528 const struct pcn_variant *pcv; 529 530 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 531 if (chipid == pcv->pcv_chipid) 532 return (pcv); 533 } 534 535 /* 536 * This covers unknown chips, which we simply treat like 537 * a generic PCnet-FAST. 538 */ 539 return (pcv); 540 } 541 542 static int 543 pcn_match(device_t parent, cfdata_t cf, void *aux) 544 { 545 struct pci_attach_args *pa = aux; 546 547 /* 548 * IBM Makes a PCI variant of this card which shows up as a 549 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 550 * this card is truly a pcn card, so we have a special case match for 551 * it 552 */ 553 554 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 555 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 556 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 557 return(1); 558 559 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 560 return (0); 561 562 switch (PCI_PRODUCT(pa->pa_id)) { 563 case PCI_PRODUCT_AMD_PCNET_PCI: 564 /* Beat if_le_pci.c */ 565 return (10); 566 } 567 568 return (0); 569 } 570 571 static void 572 pcn_attach(device_t parent, device_t self, void *aux) 573 { 574 struct pcn_softc *sc = device_private(self); 575 struct pci_attach_args *pa = aux; 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 pci_chipset_tag_t pc = pa->pa_pc; 578 pci_intr_handle_t ih; 579 const char *intrstr = NULL; 580 bus_space_tag_t iot, memt; 581 bus_space_handle_t ioh, memh; 582 bus_dma_segment_t seg; 583 int ioh_valid, memh_valid; 584 int ntxsegs, i, rseg, error; 585 uint32_t chipid, reg; 586 uint8_t enaddr[ETHER_ADDR_LEN]; 587 prop_object_t obj; 588 bool is_vmware; 589 590 sc->sc_dev = self; 591 callout_init(&sc->sc_tick_ch, 0); 592 593 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 594 595 /* 596 * Map the device. 597 */ 598 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 599 &iot, &ioh, NULL, NULL) == 0); 600 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 601 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 602 &memt, &memh, NULL, NULL) == 0); 603 604 if (memh_valid) { 605 sc->sc_st = memt; 606 sc->sc_sh = memh; 607 } else if (ioh_valid) { 608 sc->sc_st = iot; 609 sc->sc_sh = ioh; 610 } else { 611 aprint_error_dev(self, "unable to map device registers\n"); 612 return; 613 } 614 615 sc->sc_dmat = pa->pa_dmat; 616 617 /* Make sure bus mastering is enabled. */ 618 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 619 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 620 PCI_COMMAND_MASTER_ENABLE); 621 622 /* power up chip */ 623 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 624 NULL)) && error != EOPNOTSUPP) { 625 aprint_error_dev(self, "cannot activate %d\n", error); 626 return; 627 } 628 629 /* 630 * Reset the chip to a known state. This also puts the 631 * chip into 32-bit mode. 632 */ 633 pcn_reset(sc); 634 635 /* 636 * On some systems with the chip is an on-board device, the 637 * EEPROM is not used. Handle this by reading the MAC address 638 * from the CSRs (assuming that boot firmware has written 639 * it there). 640 */ 641 obj = prop_dictionary_get(device_properties(sc->sc_dev), 642 "am79c970-no-eeprom"); 643 if (prop_bool_true(obj)) { 644 for (i = 0; i < 3; i++) { 645 uint32_t val; 646 val = pcn_csr_read(sc, LE_CSR12 + i); 647 enaddr[2 * i] = val & 0xff; 648 enaddr[2 * i + 1] = (val >> 8) & 0xff; 649 } 650 } else { 651 for (i = 0; i < ETHER_ADDR_LEN; i++) { 652 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 653 PCN32_APROM + i); 654 } 655 } 656 657 /* Check to see if this is a VMware emulated network interface. */ 658 is_vmware = pcn_is_vmware(enaddr); 659 660 /* 661 * Now that the device is mapped, attempt to figure out what 662 * kind of chip we have. Note that IDL has all 32 bits of 663 * the chip ID when we're in 32-bit mode. 664 */ 665 chipid = pcn_csr_read(sc, LE_CSR88); 666 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 667 668 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 669 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 670 ether_sprintf(enaddr)); 671 672 /* 673 * VMware has a bug in its network interface emulation; we must 674 * limit the number of Tx segments. 675 */ 676 if (is_vmware) { 677 ntxsegs = PCN_NTXSEGS_VMWARE; 678 prop_dictionary_set_bool(device_properties(sc->sc_dev), 679 "am79c970-vmware-tx-bug", TRUE); 680 aprint_verbose_dev(self, 681 "VMware Tx segment count bug detected\n"); 682 } else { 683 ntxsegs = PCN_NTXSEGS; 684 } 685 686 /* 687 * Map and establish our interrupt. 688 */ 689 if (pci_intr_map(pa, &ih)) { 690 aprint_error_dev(self, "unable to map interrupt\n"); 691 return; 692 } 693 intrstr = pci_intr_string(pc, ih); 694 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 695 if (sc->sc_ih == NULL) { 696 aprint_error_dev(self, "unable to establish interrupt"); 697 if (intrstr != NULL) 698 aprint_error(" at %s", intrstr); 699 aprint_error("\n"); 700 return; 701 } 702 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 703 704 /* 705 * Allocate the control data structures, and create and load the 706 * DMA map for it. 707 */ 708 if ((error = bus_dmamem_alloc(sc->sc_dmat, 709 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 710 0)) != 0) { 711 aprint_error_dev(self, "unable to allocate control data, " 712 "error = %d\n", error); 713 goto fail_0; 714 } 715 716 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 717 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 718 BUS_DMA_COHERENT)) != 0) { 719 aprint_error_dev(self, "unable to map control data, " 720 "error = %d\n", error); 721 goto fail_1; 722 } 723 724 if ((error = bus_dmamap_create(sc->sc_dmat, 725 sizeof(struct pcn_control_data), 1, 726 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 727 aprint_error_dev(self, "unable to create control data DMA map, " 728 "error = %d\n", error); 729 goto fail_2; 730 } 731 732 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 733 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 734 0)) != 0) { 735 aprint_error_dev(self, 736 "unable to load control data DMA map, error = %d\n", error); 737 goto fail_3; 738 } 739 740 /* Create the transmit buffer DMA maps. */ 741 for (i = 0; i < PCN_TXQUEUELEN; i++) { 742 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 743 ntxsegs, MCLBYTES, 0, 0, 744 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 745 aprint_error_dev(self, 746 "unable to create tx DMA map %d, error = %d\n", 747 i, error); 748 goto fail_4; 749 } 750 } 751 752 /* Create the receive buffer DMA maps. */ 753 for (i = 0; i < PCN_NRXDESC; i++) { 754 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 755 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 756 aprint_error_dev(self, 757 "unable to create rx DMA map %d, error = %d\n", 758 i, error); 759 goto fail_5; 760 } 761 sc->sc_rxsoft[i].rxs_mbuf = NULL; 762 } 763 764 /* Initialize our media structures. */ 765 (*sc->sc_variant->pcv_mediainit)(sc); 766 767 /* 768 * Initialize FIFO watermark info. 769 */ 770 switch (sc->sc_variant->pcv_chipid) { 771 case PARTID_Am79c970: 772 case PARTID_Am79c970A: 773 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 774 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 775 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 776 break; 777 778 default: 779 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 780 /* 781 * Read BCR25 to determine how much SRAM is 782 * on the board. If > 0, then we the chip 783 * uses different Start Point thresholds. 784 * 785 * Note BCR25 and BCR26 are loaded from the 786 * EEPROM on RST, and unaffected by S_RESET, 787 * so we don't really have to worry about 788 * them except for this. 789 */ 790 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 791 if (reg != 0) 792 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 793 else 794 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 795 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 796 break; 797 } 798 799 /* 800 * Set up defaults -- see the tables above for what these 801 * values mean. 802 * 803 * XXX How should we tune RCVFW and XMTFW? 804 */ 805 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 806 sc->sc_xmtsp = 1; 807 sc->sc_xmtfw = 0; 808 809 ifp = &sc->sc_ethercom.ec_if; 810 strcpy(ifp->if_xname, device_xname(self)); 811 ifp->if_softc = sc; 812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 813 ifp->if_ioctl = pcn_ioctl; 814 ifp->if_start = pcn_start; 815 ifp->if_watchdog = pcn_watchdog; 816 ifp->if_init = pcn_init; 817 ifp->if_stop = pcn_stop; 818 IFQ_SET_READY(&ifp->if_snd); 819 820 /* Attach the interface. */ 821 if_attach(ifp); 822 ether_ifattach(ifp, enaddr); 823 #if NRND > 0 824 rnd_attach_source(&sc->rnd_source, device_xname(self), 825 RND_TYPE_NET, 0); 826 #endif 827 828 #ifdef PCN_EVENT_COUNTERS 829 /* Attach event counters. */ 830 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 831 NULL, device_xname(self), "txsstall"); 832 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 833 NULL, device_xname(self), "txdstall"); 834 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 835 NULL, device_xname(self), "txintr"); 836 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 837 NULL, device_xname(self), "rxintr"); 838 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 839 NULL, device_xname(self), "babl"); 840 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 841 NULL, device_xname(self), "miss"); 842 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 843 NULL, device_xname(self), "merr"); 844 845 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txseg1"); 847 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txseg2"); 849 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 850 NULL, device_xname(self), "txseg3"); 851 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 852 NULL, device_xname(self), "txseg4"); 853 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 854 NULL, device_xname(self), "txseg5"); 855 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 856 NULL, device_xname(self), "txsegmore"); 857 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 858 NULL, device_xname(self), "txcopy"); 859 #endif /* PCN_EVENT_COUNTERS */ 860 861 /* 862 * Establish power handler with shutdown hook, to make sure 863 * the interface is shutdown during reboot. 864 */ 865 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 866 pmf_class_network_register(self, ifp); 867 else 868 aprint_error_dev(self, "couldn't establish power handler\n"); 869 870 return; 871 872 /* 873 * Free any resources we've allocated during the failed attach 874 * attempt. Do this in reverse order and fall through. 875 */ 876 fail_5: 877 for (i = 0; i < PCN_NRXDESC; i++) { 878 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 879 bus_dmamap_destroy(sc->sc_dmat, 880 sc->sc_rxsoft[i].rxs_dmamap); 881 } 882 fail_4: 883 for (i = 0; i < PCN_TXQUEUELEN; i++) { 884 if (sc->sc_txsoft[i].txs_dmamap != NULL) 885 bus_dmamap_destroy(sc->sc_dmat, 886 sc->sc_txsoft[i].txs_dmamap); 887 } 888 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 889 fail_3: 890 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 891 fail_2: 892 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 893 sizeof(struct pcn_control_data)); 894 fail_1: 895 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 896 fail_0: 897 return; 898 } 899 900 /* 901 * pcn_shutdown: 902 * 903 * Make sure the interface is stopped at reboot time. 904 */ 905 static bool 906 pcn_shutdown(device_t self, int howto) 907 { 908 struct pcn_softc *sc = device_private(self); 909 910 pcn_stop(&sc->sc_ethercom.ec_if, 1); 911 /* explicitly reset the chip for some onboard one with lazy firmware */ 912 pcn_reset(sc); 913 914 return true; 915 } 916 917 /* 918 * pcn_start: [ifnet interface function] 919 * 920 * Start packet transmission on the interface. 921 */ 922 static void 923 pcn_start(struct ifnet *ifp) 924 { 925 struct pcn_softc *sc = ifp->if_softc; 926 struct mbuf *m0, *m; 927 struct pcn_txsoft *txs; 928 bus_dmamap_t dmamap; 929 int error, nexttx, lasttx = -1, ofree, seg; 930 931 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 932 return; 933 934 /* 935 * Remember the previous number of free descriptors and 936 * the first descriptor we'll use. 937 */ 938 ofree = sc->sc_txfree; 939 940 /* 941 * Loop through the send queue, setting up transmit descriptors 942 * until we drain the queue, or use up all available transmit 943 * descriptors. 944 */ 945 for (;;) { 946 /* Grab a packet off the queue. */ 947 IFQ_POLL(&ifp->if_snd, m0); 948 if (m0 == NULL) 949 break; 950 m = NULL; 951 952 /* Get a work queue entry. */ 953 if (sc->sc_txsfree == 0) { 954 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 955 break; 956 } 957 958 txs = &sc->sc_txsoft[sc->sc_txsnext]; 959 dmamap = txs->txs_dmamap; 960 961 /* 962 * Load the DMA map. If this fails, the packet either 963 * didn't fit in the alloted number of segments, or we 964 * were short on resources. In this case, we'll copy 965 * and try again. 966 */ 967 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 968 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 969 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 970 MGETHDR(m, M_DONTWAIT, MT_DATA); 971 if (m == NULL) { 972 printf("%s: unable to allocate Tx mbuf\n", 973 device_xname(sc->sc_dev)); 974 break; 975 } 976 if (m0->m_pkthdr.len > MHLEN) { 977 MCLGET(m, M_DONTWAIT); 978 if ((m->m_flags & M_EXT) == 0) { 979 printf("%s: unable to allocate Tx " 980 "cluster\n", 981 device_xname(sc->sc_dev)); 982 m_freem(m); 983 break; 984 } 985 } 986 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 987 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 988 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 989 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 990 if (error) { 991 printf("%s: unable to load Tx buffer, " 992 "error = %d\n", device_xname(sc->sc_dev), 993 error); 994 break; 995 } 996 } 997 998 /* 999 * Ensure we have enough descriptors free to describe 1000 * the packet. Note, we always reserve one descriptor 1001 * at the end of the ring as a termination point, to 1002 * prevent wrap-around. 1003 */ 1004 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1005 /* 1006 * Not enough free descriptors to transmit this 1007 * packet. We haven't committed anything yet, 1008 * so just unload the DMA map, put the packet 1009 * back on the queue, and punt. Notify the upper 1010 * layer that there are not more slots left. 1011 * 1012 * XXX We could allocate an mbuf and copy, but 1013 * XXX is it worth it? 1014 */ 1015 ifp->if_flags |= IFF_OACTIVE; 1016 bus_dmamap_unload(sc->sc_dmat, dmamap); 1017 if (m != NULL) 1018 m_freem(m); 1019 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1020 break; 1021 } 1022 1023 IFQ_DEQUEUE(&ifp->if_snd, m0); 1024 if (m != NULL) { 1025 m_freem(m0); 1026 m0 = m; 1027 } 1028 1029 /* 1030 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1031 */ 1032 1033 /* Sync the DMA map. */ 1034 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1035 BUS_DMASYNC_PREWRITE); 1036 1037 #ifdef PCN_EVENT_COUNTERS 1038 switch (dmamap->dm_nsegs) { 1039 case 1: 1040 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1041 break; 1042 case 2: 1043 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1044 break; 1045 case 3: 1046 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1047 break; 1048 case 4: 1049 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1050 break; 1051 case 5: 1052 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1053 break; 1054 default: 1055 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1056 break; 1057 } 1058 #endif /* PCN_EVENT_COUNTERS */ 1059 1060 /* 1061 * Initialize the transmit descriptors. 1062 */ 1063 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1064 for (nexttx = sc->sc_txnext, seg = 0; 1065 seg < dmamap->dm_nsegs; 1066 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1067 /* 1068 * If this is the first descriptor we're 1069 * enqueueing, don't set the OWN bit just 1070 * yet. That could cause a race condition. 1071 * We'll do it below. 1072 */ 1073 sc->sc_txdescs[nexttx].tmd0 = 0; 1074 sc->sc_txdescs[nexttx].tmd2 = 1075 htole32(dmamap->dm_segs[seg].ds_addr); 1076 sc->sc_txdescs[nexttx].tmd1 = 1077 htole32(LE_T1_ONES | 1078 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1079 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1080 LE_T1_BCNT_MASK)); 1081 lasttx = nexttx; 1082 } 1083 } else { 1084 for (nexttx = sc->sc_txnext, seg = 0; 1085 seg < dmamap->dm_nsegs; 1086 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1087 /* 1088 * If this is the first descriptor we're 1089 * enqueueing, don't set the OWN bit just 1090 * yet. That could cause a race condition. 1091 * We'll do it below. 1092 */ 1093 sc->sc_txdescs[nexttx].tmd0 = 1094 htole32(dmamap->dm_segs[seg].ds_addr); 1095 sc->sc_txdescs[nexttx].tmd2 = 0; 1096 sc->sc_txdescs[nexttx].tmd1 = 1097 htole32(LE_T1_ONES | 1098 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1099 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1100 LE_T1_BCNT_MASK)); 1101 lasttx = nexttx; 1102 } 1103 } 1104 1105 KASSERT(lasttx != -1); 1106 /* Interrupt on the packet, if appropriate. */ 1107 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1108 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1109 1110 /* Set `start of packet' and `end of packet' appropriately. */ 1111 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1112 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1113 htole32(LE_T1_OWN|LE_T1_STP); 1114 1115 /* Sync the descriptors we're using. */ 1116 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1117 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1118 1119 /* Kick the transmitter. */ 1120 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1121 1122 /* 1123 * Store a pointer to the packet so we can free it later, 1124 * and remember what txdirty will be once the packet is 1125 * done. 1126 */ 1127 txs->txs_mbuf = m0; 1128 txs->txs_firstdesc = sc->sc_txnext; 1129 txs->txs_lastdesc = lasttx; 1130 1131 /* Advance the tx pointer. */ 1132 sc->sc_txfree -= dmamap->dm_nsegs; 1133 sc->sc_txnext = nexttx; 1134 1135 sc->sc_txsfree--; 1136 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1137 1138 /* Pass the packet to any BPF listeners. */ 1139 bpf_mtap(ifp, m0); 1140 } 1141 1142 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1143 /* No more slots left; notify upper layer. */ 1144 ifp->if_flags |= IFF_OACTIVE; 1145 } 1146 1147 if (sc->sc_txfree != ofree) { 1148 /* Set a watchdog timer in case the chip flakes out. */ 1149 ifp->if_timer = 5; 1150 } 1151 } 1152 1153 /* 1154 * pcn_watchdog: [ifnet interface function] 1155 * 1156 * Watchdog timer handler. 1157 */ 1158 static void 1159 pcn_watchdog(struct ifnet *ifp) 1160 { 1161 struct pcn_softc *sc = ifp->if_softc; 1162 1163 /* 1164 * Since we're not interrupting every packet, sweep 1165 * up before we report an error. 1166 */ 1167 pcn_txintr(sc); 1168 1169 if (sc->sc_txfree != PCN_NTXDESC) { 1170 printf("%s: device timeout (txfree %d txsfree %d)\n", 1171 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1172 ifp->if_oerrors++; 1173 1174 /* Reset the interface. */ 1175 (void) pcn_init(ifp); 1176 } 1177 1178 /* Try to get more packets going. */ 1179 pcn_start(ifp); 1180 } 1181 1182 /* 1183 * pcn_ioctl: [ifnet interface function] 1184 * 1185 * Handle control requests from the operator. 1186 */ 1187 static int 1188 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1189 { 1190 struct pcn_softc *sc = ifp->if_softc; 1191 struct ifreq *ifr = (struct ifreq *) data; 1192 int s, error; 1193 1194 s = splnet(); 1195 1196 switch (cmd) { 1197 case SIOCSIFMEDIA: 1198 case SIOCGIFMEDIA: 1199 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1200 break; 1201 1202 default: 1203 error = ether_ioctl(ifp, cmd, data); 1204 if (error == ENETRESET) { 1205 /* 1206 * Multicast list has changed; set the hardware filter 1207 * accordingly. 1208 */ 1209 if (ifp->if_flags & IFF_RUNNING) 1210 error = pcn_init(ifp); 1211 else 1212 error = 0; 1213 } 1214 break; 1215 } 1216 1217 /* Try to get more packets going. */ 1218 pcn_start(ifp); 1219 1220 splx(s); 1221 return (error); 1222 } 1223 1224 /* 1225 * pcn_intr: 1226 * 1227 * Interrupt service routine. 1228 */ 1229 static int 1230 pcn_intr(void *arg) 1231 { 1232 struct pcn_softc *sc = arg; 1233 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1234 uint32_t csr0; 1235 int wantinit, handled = 0; 1236 1237 for (wantinit = 0; wantinit == 0;) { 1238 csr0 = pcn_csr_read(sc, LE_CSR0); 1239 if ((csr0 & LE_C0_INTR) == 0) 1240 break; 1241 1242 #if NRND > 0 1243 if (RND_ENABLED(&sc->rnd_source)) 1244 rnd_add_uint32(&sc->rnd_source, csr0); 1245 #endif 1246 1247 /* ACK the bits and re-enable interrupts. */ 1248 pcn_csr_write(sc, LE_CSR0, csr0 & 1249 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1250 LE_C0_TINT|LE_C0_IDON)); 1251 1252 handled = 1; 1253 1254 if (csr0 & LE_C0_RINT) { 1255 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1256 wantinit = pcn_rxintr(sc); 1257 } 1258 1259 if (csr0 & LE_C0_TINT) { 1260 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1261 pcn_txintr(sc); 1262 } 1263 1264 if (csr0 & LE_C0_ERR) { 1265 if (csr0 & LE_C0_BABL) { 1266 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1267 ifp->if_oerrors++; 1268 } 1269 if (csr0 & LE_C0_MISS) { 1270 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1271 ifp->if_ierrors++; 1272 } 1273 if (csr0 & LE_C0_MERR) { 1274 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1275 printf("%s: memory error\n", 1276 device_xname(sc->sc_dev)); 1277 wantinit = 1; 1278 break; 1279 } 1280 } 1281 1282 if ((csr0 & LE_C0_RXON) == 0) { 1283 printf("%s: receiver disabled\n", 1284 device_xname(sc->sc_dev)); 1285 ifp->if_ierrors++; 1286 wantinit = 1; 1287 } 1288 1289 if ((csr0 & LE_C0_TXON) == 0) { 1290 printf("%s: transmitter disabled\n", 1291 device_xname(sc->sc_dev)); 1292 ifp->if_oerrors++; 1293 wantinit = 1; 1294 } 1295 } 1296 1297 if (handled) { 1298 if (wantinit) 1299 pcn_init(ifp); 1300 1301 /* Try to get more packets going. */ 1302 pcn_start(ifp); 1303 } 1304 1305 return (handled); 1306 } 1307 1308 /* 1309 * pcn_spnd: 1310 * 1311 * Suspend the chip. 1312 */ 1313 static void 1314 pcn_spnd(struct pcn_softc *sc) 1315 { 1316 int i; 1317 1318 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1319 1320 for (i = 0; i < 10000; i++) { 1321 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1322 return; 1323 delay(5); 1324 } 1325 1326 printf("%s: WARNING: chip failed to enter suspended state\n", 1327 device_xname(sc->sc_dev)); 1328 } 1329 1330 /* 1331 * pcn_txintr: 1332 * 1333 * Helper; handle transmit interrupts. 1334 */ 1335 static void 1336 pcn_txintr(struct pcn_softc *sc) 1337 { 1338 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1339 struct pcn_txsoft *txs; 1340 uint32_t tmd1, tmd2, tmd; 1341 int i, j; 1342 1343 ifp->if_flags &= ~IFF_OACTIVE; 1344 1345 /* 1346 * Go through our Tx list and free mbufs for those 1347 * frames which have been transmitted. 1348 */ 1349 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1350 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1351 txs = &sc->sc_txsoft[i]; 1352 1353 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1354 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1355 1356 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1357 if (tmd1 & LE_T1_OWN) 1358 break; 1359 1360 /* 1361 * Slightly annoying -- we have to loop through the 1362 * descriptors we've used looking for ERR, since it 1363 * can appear on any descriptor in the chain. 1364 */ 1365 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1366 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1367 if (tmd & LE_T1_ERR) { 1368 ifp->if_oerrors++; 1369 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1370 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1371 else 1372 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1373 if (tmd2 & LE_T2_UFLO) { 1374 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1375 sc->sc_xmtsp++; 1376 printf("%s: transmit " 1377 "underrun; new threshold: " 1378 "%s\n", 1379 device_xname(sc->sc_dev), 1380 sc->sc_xmtsp_desc[ 1381 sc->sc_xmtsp]); 1382 pcn_spnd(sc); 1383 pcn_csr_write(sc, LE_CSR80, 1384 LE_C80_RCVFW(sc->sc_rcvfw) | 1385 LE_C80_XMTSP(sc->sc_xmtsp) | 1386 LE_C80_XMTFW(sc->sc_xmtfw)); 1387 pcn_csr_write(sc, LE_CSR5, 1388 sc->sc_csr5); 1389 } else { 1390 printf("%s: transmit " 1391 "underrun\n", 1392 device_xname(sc->sc_dev)); 1393 } 1394 } else if (tmd2 & LE_T2_BUFF) { 1395 printf("%s: transmit buffer error\n", 1396 device_xname(sc->sc_dev)); 1397 } 1398 if (tmd2 & LE_T2_LCOL) 1399 ifp->if_collisions++; 1400 if (tmd2 & LE_T2_RTRY) 1401 ifp->if_collisions += 16; 1402 goto next_packet; 1403 } 1404 if (j == txs->txs_lastdesc) 1405 break; 1406 } 1407 if (tmd1 & LE_T1_ONE) 1408 ifp->if_collisions++; 1409 else if (tmd & LE_T1_MORE) { 1410 /* Real number is unknown. */ 1411 ifp->if_collisions += 2; 1412 } 1413 ifp->if_opackets++; 1414 next_packet: 1415 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1416 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1417 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1418 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1419 m_freem(txs->txs_mbuf); 1420 txs->txs_mbuf = NULL; 1421 } 1422 1423 /* Update the dirty transmit buffer pointer. */ 1424 sc->sc_txsdirty = i; 1425 1426 /* 1427 * If there are no more pending transmissions, cancel the watchdog 1428 * timer. 1429 */ 1430 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1431 ifp->if_timer = 0; 1432 } 1433 1434 /* 1435 * pcn_rxintr: 1436 * 1437 * Helper; handle receive interrupts. 1438 */ 1439 static int 1440 pcn_rxintr(struct pcn_softc *sc) 1441 { 1442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1443 struct pcn_rxsoft *rxs; 1444 struct mbuf *m; 1445 uint32_t rmd1; 1446 int i, len; 1447 1448 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1449 rxs = &sc->sc_rxsoft[i]; 1450 1451 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1452 1453 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1454 1455 if (rmd1 & LE_R1_OWN) 1456 break; 1457 1458 /* 1459 * Check for errors and make sure the packet fit into 1460 * a single buffer. We have structured this block of 1461 * code the way it is in order to compress it into 1462 * one test in the common case (no error). 1463 */ 1464 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1465 (LE_R1_STP|LE_R1_ENP))) { 1466 /* Make sure the packet is in a single buffer. */ 1467 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1468 (LE_R1_STP|LE_R1_ENP)) { 1469 printf("%s: packet spilled into next buffer\n", 1470 device_xname(sc->sc_dev)); 1471 return (1); /* pcn_intr() will re-init */ 1472 } 1473 1474 /* 1475 * If the packet had an error, simple recycle the 1476 * buffer. 1477 */ 1478 if (rmd1 & LE_R1_ERR) { 1479 ifp->if_ierrors++; 1480 /* 1481 * If we got an overflow error, chances 1482 * are there will be a CRC error. In 1483 * this case, just print the overflow 1484 * error, and skip the others. 1485 */ 1486 if (rmd1 & LE_R1_OFLO) 1487 printf("%s: overflow error\n", 1488 device_xname(sc->sc_dev)); 1489 else { 1490 #define PRINTIT(x, str) \ 1491 if (rmd1 & (x)) \ 1492 printf("%s: %s\n", \ 1493 device_xname(sc->sc_dev), \ 1494 str); 1495 PRINTIT(LE_R1_FRAM, "framing error"); 1496 PRINTIT(LE_R1_CRC, "CRC error"); 1497 PRINTIT(LE_R1_BUFF, "buffer error"); 1498 } 1499 #undef PRINTIT 1500 PCN_INIT_RXDESC(sc, i); 1501 continue; 1502 } 1503 } 1504 1505 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1506 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1507 1508 /* 1509 * No errors; receive the packet. 1510 */ 1511 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1512 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1513 else 1514 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1515 1516 /* 1517 * The LANCE family includes the CRC with every packet; 1518 * trim it off here. 1519 */ 1520 len -= ETHER_CRC_LEN; 1521 1522 /* 1523 * If the packet is small enough to fit in a 1524 * single header mbuf, allocate one and copy 1525 * the data into it. This greatly reduces 1526 * memory consumption when we receive lots 1527 * of small packets. 1528 * 1529 * Otherwise, we add a new buffer to the receive 1530 * chain. If this fails, we drop the packet and 1531 * recycle the old buffer. 1532 */ 1533 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1534 MGETHDR(m, M_DONTWAIT, MT_DATA); 1535 if (m == NULL) 1536 goto dropit; 1537 m->m_data += 2; 1538 memcpy(mtod(m, void *), 1539 mtod(rxs->rxs_mbuf, void *), len); 1540 PCN_INIT_RXDESC(sc, i); 1541 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1542 rxs->rxs_dmamap->dm_mapsize, 1543 BUS_DMASYNC_PREREAD); 1544 } else { 1545 m = rxs->rxs_mbuf; 1546 if (pcn_add_rxbuf(sc, i) != 0) { 1547 dropit: 1548 ifp->if_ierrors++; 1549 PCN_INIT_RXDESC(sc, i); 1550 bus_dmamap_sync(sc->sc_dmat, 1551 rxs->rxs_dmamap, 0, 1552 rxs->rxs_dmamap->dm_mapsize, 1553 BUS_DMASYNC_PREREAD); 1554 continue; 1555 } 1556 } 1557 1558 m->m_pkthdr.rcvif = ifp; 1559 m->m_pkthdr.len = m->m_len = len; 1560 1561 /* Pass this up to any BPF listeners. */ 1562 bpf_mtap(ifp, m); 1563 1564 /* Pass it on. */ 1565 (*ifp->if_input)(ifp, m); 1566 ifp->if_ipackets++; 1567 } 1568 1569 /* Update the receive pointer. */ 1570 sc->sc_rxptr = i; 1571 return (0); 1572 } 1573 1574 /* 1575 * pcn_tick: 1576 * 1577 * One second timer, used to tick the MII. 1578 */ 1579 static void 1580 pcn_tick(void *arg) 1581 { 1582 struct pcn_softc *sc = arg; 1583 int s; 1584 1585 s = splnet(); 1586 mii_tick(&sc->sc_mii); 1587 splx(s); 1588 1589 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1590 } 1591 1592 /* 1593 * pcn_reset: 1594 * 1595 * Perform a soft reset on the PCnet-PCI. 1596 */ 1597 static void 1598 pcn_reset(struct pcn_softc *sc) 1599 { 1600 1601 /* 1602 * The PCnet-PCI chip is reset by reading from the 1603 * RESET register. Note that while the NE2100 LANCE 1604 * boards require a write after the read, the PCnet-PCI 1605 * chips do not require this. 1606 * 1607 * Since we don't know if we're in 16-bit or 32-bit 1608 * mode right now, issue both (it's safe) in the 1609 * hopes that one will succeed. 1610 */ 1611 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1612 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1613 1614 /* Wait 1ms for it to finish. */ 1615 delay(1000); 1616 1617 /* 1618 * Select 32-bit I/O mode by issuing a 32-bit write to the 1619 * RDP. Since the RAP is 0 after a reset, writing a 0 1620 * to RDP is safe (since it simply clears CSR0). 1621 */ 1622 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1623 } 1624 1625 /* 1626 * pcn_init: [ifnet interface function] 1627 * 1628 * Initialize the interface. Must be called at splnet(). 1629 */ 1630 static int 1631 pcn_init(struct ifnet *ifp) 1632 { 1633 struct pcn_softc *sc = ifp->if_softc; 1634 struct pcn_rxsoft *rxs; 1635 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1636 int i, error = 0; 1637 uint32_t reg; 1638 1639 /* Cancel any pending I/O. */ 1640 pcn_stop(ifp, 0); 1641 1642 /* Reset the chip to a known state. */ 1643 pcn_reset(sc); 1644 1645 /* 1646 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1647 * else. 1648 * 1649 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1650 * because the structure layout is compatible with ILACC, 1651 * but the burst mode is only available in SSTYLE 3, and 1652 * burst mode should provide some performance enhancement. 1653 */ 1654 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1655 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1656 else 1657 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1658 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1659 1660 /* Initialize the transmit descriptor ring. */ 1661 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1662 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1663 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1664 sc->sc_txfree = PCN_NTXDESC; 1665 sc->sc_txnext = 0; 1666 1667 /* Initialize the transmit job descriptors. */ 1668 for (i = 0; i < PCN_TXQUEUELEN; i++) 1669 sc->sc_txsoft[i].txs_mbuf = NULL; 1670 sc->sc_txsfree = PCN_TXQUEUELEN; 1671 sc->sc_txsnext = 0; 1672 sc->sc_txsdirty = 0; 1673 1674 /* 1675 * Initialize the receive descriptor and receive job 1676 * descriptor rings. 1677 */ 1678 for (i = 0; i < PCN_NRXDESC; i++) { 1679 rxs = &sc->sc_rxsoft[i]; 1680 if (rxs->rxs_mbuf == NULL) { 1681 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1682 printf("%s: unable to allocate or map rx " 1683 "buffer %d, error = %d\n", 1684 device_xname(sc->sc_dev), i, error); 1685 /* 1686 * XXX Should attempt to run with fewer receive 1687 * XXX buffers instead of just failing. 1688 */ 1689 pcn_rxdrain(sc); 1690 goto out; 1691 } 1692 } else 1693 PCN_INIT_RXDESC(sc, i); 1694 } 1695 sc->sc_rxptr = 0; 1696 1697 /* Initialize MODE for the initialization block. */ 1698 sc->sc_mode = 0; 1699 if (ifp->if_flags & IFF_PROMISC) 1700 sc->sc_mode |= LE_C15_PROM; 1701 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1702 sc->sc_mode |= LE_C15_DRCVBC; 1703 1704 /* 1705 * If we have MII, simply select MII in the MODE register, 1706 * and clear ASEL. Otherwise, let ASEL stand (for now), 1707 * and leave PORTSEL alone (it is ignored with ASEL is set). 1708 */ 1709 if (sc->sc_flags & PCN_F_HAS_MII) { 1710 pcn_bcr_write(sc, LE_BCR2, 1711 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1712 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1713 1714 /* 1715 * Disable MII auto-negotiation. We handle that in 1716 * our own MII layer. 1717 */ 1718 pcn_bcr_write(sc, LE_BCR32, 1719 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1720 } 1721 1722 /* 1723 * Set the Tx and Rx descriptor ring addresses in the init 1724 * block, the TLEN and RLEN other fields of the init block 1725 * MODE register. 1726 */ 1727 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1728 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1729 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1730 ((ffs(PCN_NTXDESC) - 1) << 28) | 1731 ((ffs(PCN_NRXDESC) - 1) << 20)); 1732 1733 /* Set the station address in the init block. */ 1734 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1735 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1736 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1737 (enaddr[5] << 8)); 1738 1739 /* Set the multicast filter in the init block. */ 1740 pcn_set_filter(sc); 1741 1742 /* Initialize CSR3. */ 1743 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1744 1745 /* Initialize CSR4. */ 1746 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1747 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1748 1749 /* Initialize CSR5. */ 1750 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1751 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1752 1753 /* 1754 * If we have an Am79c971 or greater, initialize CSR7. 1755 * 1756 * XXX Might be nice to use the MII auto-poll interrupt someday. 1757 */ 1758 switch (sc->sc_variant->pcv_chipid) { 1759 case PARTID_Am79c970: 1760 case PARTID_Am79c970A: 1761 /* Not available on these chips. */ 1762 break; 1763 1764 default: 1765 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1766 break; 1767 } 1768 1769 /* 1770 * On the Am79c970A and greater, initialize BCR18 to 1771 * enable burst mode. 1772 * 1773 * Also enable the "no underflow" option on the Am79c971 and 1774 * higher, which prevents the chip from generating transmit 1775 * underflows, yet sill provides decent performance. Note if 1776 * chip is not connected to external SRAM, then we still have 1777 * to handle underflow errors (the NOUFLO bit is ignored in 1778 * that case). 1779 */ 1780 reg = pcn_bcr_read(sc, LE_BCR18); 1781 switch (sc->sc_variant->pcv_chipid) { 1782 case PARTID_Am79c970: 1783 break; 1784 1785 case PARTID_Am79c970A: 1786 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1787 break; 1788 1789 default: 1790 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1791 break; 1792 } 1793 pcn_bcr_write(sc, LE_BCR18, reg); 1794 1795 /* 1796 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1797 */ 1798 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1799 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1800 1801 /* 1802 * Send the init block to the chip, and wait for it 1803 * to be processed. 1804 */ 1805 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1806 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1807 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1808 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1809 delay(100); 1810 for (i = 0; i < 10000; i++) { 1811 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1812 break; 1813 delay(10); 1814 } 1815 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1816 if (i == 10000) { 1817 printf("%s: timeout processing init block\n", 1818 device_xname(sc->sc_dev)); 1819 error = EIO; 1820 goto out; 1821 } 1822 1823 /* Set the media. */ 1824 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1825 goto out; 1826 1827 /* Enable interrupts and external activity (and ACK IDON). */ 1828 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1829 1830 if (sc->sc_flags & PCN_F_HAS_MII) { 1831 /* Start the one second MII clock. */ 1832 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1833 } 1834 1835 /* ...all done! */ 1836 ifp->if_flags |= IFF_RUNNING; 1837 ifp->if_flags &= ~IFF_OACTIVE; 1838 1839 out: 1840 if (error) 1841 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1842 return (error); 1843 } 1844 1845 /* 1846 * pcn_rxdrain: 1847 * 1848 * Drain the receive queue. 1849 */ 1850 static void 1851 pcn_rxdrain(struct pcn_softc *sc) 1852 { 1853 struct pcn_rxsoft *rxs; 1854 int i; 1855 1856 for (i = 0; i < PCN_NRXDESC; i++) { 1857 rxs = &sc->sc_rxsoft[i]; 1858 if (rxs->rxs_mbuf != NULL) { 1859 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1860 m_freem(rxs->rxs_mbuf); 1861 rxs->rxs_mbuf = NULL; 1862 } 1863 } 1864 } 1865 1866 /* 1867 * pcn_stop: [ifnet interface function] 1868 * 1869 * Stop transmission on the interface. 1870 */ 1871 static void 1872 pcn_stop(struct ifnet *ifp, int disable) 1873 { 1874 struct pcn_softc *sc = ifp->if_softc; 1875 struct pcn_txsoft *txs; 1876 int i; 1877 1878 if (sc->sc_flags & PCN_F_HAS_MII) { 1879 /* Stop the one second clock. */ 1880 callout_stop(&sc->sc_tick_ch); 1881 1882 /* Down the MII. */ 1883 mii_down(&sc->sc_mii); 1884 } 1885 1886 /* Stop the chip. */ 1887 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1888 1889 /* Release any queued transmit buffers. */ 1890 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1891 txs = &sc->sc_txsoft[i]; 1892 if (txs->txs_mbuf != NULL) { 1893 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1894 m_freem(txs->txs_mbuf); 1895 txs->txs_mbuf = NULL; 1896 } 1897 } 1898 1899 /* Mark the interface as down and cancel the watchdog timer. */ 1900 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1901 ifp->if_timer = 0; 1902 1903 if (disable) 1904 pcn_rxdrain(sc); 1905 } 1906 1907 /* 1908 * pcn_add_rxbuf: 1909 * 1910 * Add a receive buffer to the indicated descriptor. 1911 */ 1912 static int 1913 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1914 { 1915 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1916 struct mbuf *m; 1917 int error; 1918 1919 MGETHDR(m, M_DONTWAIT, MT_DATA); 1920 if (m == NULL) 1921 return (ENOBUFS); 1922 1923 MCLGET(m, M_DONTWAIT); 1924 if ((m->m_flags & M_EXT) == 0) { 1925 m_freem(m); 1926 return (ENOBUFS); 1927 } 1928 1929 if (rxs->rxs_mbuf != NULL) 1930 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1931 1932 rxs->rxs_mbuf = m; 1933 1934 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1935 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1936 BUS_DMA_READ|BUS_DMA_NOWAIT); 1937 if (error) { 1938 printf("%s: can't load rx DMA map %d, error = %d\n", 1939 device_xname(sc->sc_dev), idx, error); 1940 panic("pcn_add_rxbuf"); 1941 } 1942 1943 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1944 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1945 1946 PCN_INIT_RXDESC(sc, idx); 1947 1948 return (0); 1949 } 1950 1951 /* 1952 * pcn_set_filter: 1953 * 1954 * Set up the receive filter. 1955 */ 1956 static void 1957 pcn_set_filter(struct pcn_softc *sc) 1958 { 1959 struct ethercom *ec = &sc->sc_ethercom; 1960 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1961 struct ether_multi *enm; 1962 struct ether_multistep step; 1963 uint32_t crc; 1964 1965 /* 1966 * Set up the multicast address filter by passing all multicast 1967 * addresses through a CRC generator, and then using the high 1968 * order 6 bits as an index into the 64-bit logical address 1969 * filter. The high order bits select the word, while the rest 1970 * of the bits select the bit within the word. 1971 */ 1972 1973 if (ifp->if_flags & IFF_PROMISC) 1974 goto allmulti; 1975 1976 sc->sc_initblock.init_ladrf[0] = 1977 sc->sc_initblock.init_ladrf[1] = 1978 sc->sc_initblock.init_ladrf[2] = 1979 sc->sc_initblock.init_ladrf[3] = 0; 1980 1981 ETHER_FIRST_MULTI(step, ec, enm); 1982 while (enm != NULL) { 1983 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1984 /* 1985 * We must listen to a range of multicast addresses. 1986 * For now, just accept all multicasts, rather than 1987 * trying to set only those filter bits needed to match 1988 * the range. (At this time, the only use of address 1989 * ranges is for IP multicast routing, for which the 1990 * range is big enough to require all bits set.) 1991 */ 1992 goto allmulti; 1993 } 1994 1995 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1996 1997 /* Just want the 6 most significant bits. */ 1998 crc >>= 26; 1999 2000 /* Set the corresponding bit in the filter. */ 2001 sc->sc_initblock.init_ladrf[crc >> 4] |= 2002 htole16(1 << (crc & 0xf)); 2003 2004 ETHER_NEXT_MULTI(step, enm); 2005 } 2006 2007 ifp->if_flags &= ~IFF_ALLMULTI; 2008 return; 2009 2010 allmulti: 2011 ifp->if_flags |= IFF_ALLMULTI; 2012 sc->sc_initblock.init_ladrf[0] = 2013 sc->sc_initblock.init_ladrf[1] = 2014 sc->sc_initblock.init_ladrf[2] = 2015 sc->sc_initblock.init_ladrf[3] = 0xffff; 2016 } 2017 2018 /* 2019 * pcn_79c970_mediainit: 2020 * 2021 * Initialize media for the Am79c970. 2022 */ 2023 static void 2024 pcn_79c970_mediainit(struct pcn_softc *sc) 2025 { 2026 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2027 const char *sep = ""; 2028 2029 sc->sc_mii.mii_ifp = ifp; 2030 2031 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2032 pcn_79c970_mediastatus); 2033 2034 #define ADD(str, m, d) \ 2035 do { \ 2036 aprint_normal("%s%s", sep, str); \ 2037 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2038 sep = ", "; \ 2039 } while (/*CONSTCOND*/0) 2040 2041 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2042 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2043 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2044 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2045 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2046 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2047 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2048 ADD("auto", IFM_AUTO, 0); 2049 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2050 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2051 aprint_normal("\n"); 2052 2053 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2054 } 2055 2056 /* 2057 * pcn_79c970_mediastatus: [ifmedia interface function] 2058 * 2059 * Get the current interface media status (Am79c970 version). 2060 */ 2061 static void 2062 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2063 { 2064 struct pcn_softc *sc = ifp->if_softc; 2065 2066 /* 2067 * The currently selected media is always the active media. 2068 * Note: We have no way to determine what media the AUTO 2069 * process picked. 2070 */ 2071 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2072 } 2073 2074 /* 2075 * pcn_79c970_mediachange: [ifmedia interface function] 2076 * 2077 * Set hardware to newly-selected media (Am79c970 version). 2078 */ 2079 static int 2080 pcn_79c970_mediachange(struct ifnet *ifp) 2081 { 2082 struct pcn_softc *sc = ifp->if_softc; 2083 uint32_t reg; 2084 2085 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2086 /* 2087 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2088 */ 2089 reg = pcn_bcr_read(sc, LE_BCR2); 2090 reg |= LE_B2_ASEL; 2091 pcn_bcr_write(sc, LE_BCR2, reg); 2092 } else { 2093 /* 2094 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2095 */ 2096 reg = pcn_bcr_read(sc, LE_BCR2); 2097 reg &= ~LE_B2_ASEL; 2098 pcn_bcr_write(sc, LE_BCR2, reg); 2099 2100 reg = pcn_csr_read(sc, LE_CSR15); 2101 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2102 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2103 pcn_csr_write(sc, LE_CSR15, reg); 2104 } 2105 2106 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2107 reg = LE_B9_FDEN; 2108 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2109 reg |= LE_B9_AUIFD; 2110 pcn_bcr_write(sc, LE_BCR9, reg); 2111 } else 2112 pcn_bcr_write(sc, LE_BCR9, 0); 2113 2114 return (0); 2115 } 2116 2117 /* 2118 * pcn_79c971_mediainit: 2119 * 2120 * Initialize media for the Am79c971. 2121 */ 2122 static void 2123 pcn_79c971_mediainit(struct pcn_softc *sc) 2124 { 2125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2126 2127 /* We have MII. */ 2128 sc->sc_flags |= PCN_F_HAS_MII; 2129 2130 /* 2131 * The built-in 10BASE-T interface is mapped to the MII 2132 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2133 * word that tells us which PHY to use. 2134 * This driver used to ignore all but the first PHY to 2135 * answer, but this code was removed to support multiple 2136 * external PHYs. As the default instance will be the first 2137 * one to answer, no harm is done by letting the possibly 2138 * non-connected internal PHY show up. 2139 */ 2140 2141 /* Initialize our media structures and probe the MII. */ 2142 sc->sc_mii.mii_ifp = ifp; 2143 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2144 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2145 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2146 2147 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2148 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2149 ether_mediastatus); 2150 2151 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2152 MII_OFFSET_ANY, 0); 2153 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2154 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2155 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2156 } else 2157 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2158 } 2159 2160 /* 2161 * pcn_mii_readreg: [mii interface function] 2162 * 2163 * Read a PHY register on the MII. 2164 */ 2165 static int 2166 pcn_mii_readreg(device_t self, int phy, int reg) 2167 { 2168 struct pcn_softc *sc = device_private(self); 2169 uint32_t rv; 2170 2171 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2172 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2173 if (rv == 0xffff) 2174 return (0); 2175 2176 return (rv); 2177 } 2178 2179 /* 2180 * pcn_mii_writereg: [mii interface function] 2181 * 2182 * Write a PHY register on the MII. 2183 */ 2184 static void 2185 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2186 { 2187 struct pcn_softc *sc = device_private(self); 2188 2189 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2190 pcn_bcr_write(sc, LE_BCR34, val); 2191 } 2192 2193 /* 2194 * pcn_mii_statchg: [mii interface function] 2195 * 2196 * Callback from MII layer when media changes. 2197 */ 2198 static void 2199 pcn_mii_statchg(device_t self) 2200 { 2201 struct pcn_softc *sc = device_private(self); 2202 2203 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2204 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2205 else 2206 pcn_bcr_write(sc, LE_BCR9, 0); 2207 } 2208