1 /* $NetBSD: if_pcn.c,v 1.76 2020/03/16 01:54:23 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.76 2020/03/16 01:54:23 thorpej Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rndsource.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 271 struct evcnt sc_ev_txintr; /* Tx interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 274 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 275 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 276 277 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 278 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 279 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 280 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 281 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 282 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 283 struct evcnt sc_ev_txcopy; /* Tx copies required */ 284 #endif /* PCN_EVENT_COUNTERS */ 285 286 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 287 int sc_rcvfw; 288 289 const char * const *sc_xmtsp_desc; /* Tx start point info */ 290 int sc_xmtsp; 291 292 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 293 int sc_xmtfw; 294 295 int sc_flags; /* misc. flags; see below */ 296 int sc_swstyle; /* the software style in use */ 297 298 int sc_txfree; /* number of free Tx descriptors */ 299 int sc_txnext; /* next ready Tx descriptor */ 300 301 int sc_txsfree; /* number of free Tx jobs */ 302 int sc_txsnext; /* next free Tx job */ 303 int sc_txsdirty; /* dirty Tx jobs */ 304 305 int sc_rxptr; /* next ready Rx descriptor/job */ 306 307 uint32_t sc_csr5; /* prototype CSR5 register */ 308 uint32_t sc_mode; /* prototype MODE register */ 309 310 krndsource_t rnd_source; /* random source */ 311 }; 312 313 /* sc_flags */ 314 #define PCN_F_HAS_MII 0x0001 /* has MII */ 315 316 #ifdef PCN_EVENT_COUNTERS 317 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 318 #else 319 #define PCN_EVCNT_INCR(ev) /* nothing */ 320 #endif 321 322 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 323 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 324 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 325 326 #define PCN_CDTXSYNC(sc, x, n, ops) \ 327 do { \ 328 int __x, __n; \ 329 \ 330 __x = (x); \ 331 __n = (n); \ 332 \ 333 /* If it will wrap around, sync to the end of the ring. */ \ 334 if ((__x + __n) > PCN_NTXDESC) { \ 335 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 336 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 337 (PCN_NTXDESC - __x), (ops)); \ 338 __n -= (PCN_NTXDESC - __x); \ 339 __x = 0; \ 340 } \ 341 \ 342 /* Now sync whatever is left. */ \ 343 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 344 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 345 } while (/*CONSTCOND*/0) 346 347 #define PCN_CDRXSYNC(sc, x, ops) \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 350 351 #define PCN_CDINITSYNC(sc, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 354 355 #define PCN_INIT_RXDESC(sc, x) \ 356 do { \ 357 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 358 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 359 struct mbuf *__m = __rxs->rxs_mbuf; \ 360 \ 361 /* \ 362 * Note: We scoot the packet forward 2 bytes in the buffer \ 363 * so that the payload after the Ethernet header is aligned \ 364 * to a 4-byte boundary. \ 365 */ \ 366 __m->m_data = __m->m_ext.ext_buf + 2; \ 367 \ 368 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 369 __rmd->rmd2 = \ 370 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 371 __rmd->rmd0 = 0; \ 372 } else { \ 373 __rmd->rmd2 = 0; \ 374 __rmd->rmd0 = \ 375 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 376 } \ 377 __rmd->rmd1 = htole32(LE_R1_OWN | LE_R1_ONES | \ 378 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 379 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);\ 380 } while(/*CONSTCOND*/0) 381 382 static void pcn_start(struct ifnet *); 383 static void pcn_watchdog(struct ifnet *); 384 static int pcn_ioctl(struct ifnet *, u_long, void *); 385 static int pcn_init(struct ifnet *); 386 static void pcn_stop(struct ifnet *, int); 387 388 static bool pcn_shutdown(device_t, int); 389 390 static void pcn_reset(struct pcn_softc *); 391 static void pcn_rxdrain(struct pcn_softc *); 392 static int pcn_add_rxbuf(struct pcn_softc *, int); 393 static void pcn_tick(void *); 394 395 static void pcn_spnd(struct pcn_softc *); 396 397 static void pcn_set_filter(struct pcn_softc *); 398 399 static int pcn_intr(void *); 400 static void pcn_txintr(struct pcn_softc *); 401 static int pcn_rxintr(struct pcn_softc *); 402 403 static int pcn_mii_readreg(device_t, int, int, uint16_t *); 404 static int pcn_mii_writereg(device_t, int, int, uint16_t); 405 static void pcn_mii_statchg(struct ifnet *); 406 407 static void pcn_79c970_mediainit(struct pcn_softc *); 408 static int pcn_79c970_mediachange(struct ifnet *); 409 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 410 411 static void pcn_79c971_mediainit(struct pcn_softc *); 412 413 /* 414 * Description of a PCnet-PCI variant. Used to select media access 415 * method, mostly, and to print a nice description of the chip. 416 */ 417 static const struct pcn_variant { 418 const char *pcv_desc; 419 void (*pcv_mediainit)(struct pcn_softc *); 420 uint16_t pcv_chipid; 421 } pcn_variants[] = { 422 { "Am79c970 PCnet-PCI", 423 pcn_79c970_mediainit, 424 PARTID_Am79c970 }, 425 426 { "Am79c970A PCnet-PCI II", 427 pcn_79c970_mediainit, 428 PARTID_Am79c970A }, 429 430 { "Am79c971 PCnet-FAST", 431 pcn_79c971_mediainit, 432 PARTID_Am79c971 }, 433 434 { "Am79c972 PCnet-FAST+", 435 pcn_79c971_mediainit, 436 PARTID_Am79c972 }, 437 438 { "Am79c973 PCnet-FAST III", 439 pcn_79c971_mediainit, 440 PARTID_Am79c973 }, 441 442 { "Am79c975 PCnet-FAST III", 443 pcn_79c971_mediainit, 444 PARTID_Am79c975 }, 445 446 { "Unknown PCnet-PCI variant", 447 pcn_79c971_mediainit, 448 0 }, 449 }; 450 451 int pcn_copy_small = 0; 452 453 static int pcn_match(device_t, cfdata_t, void *); 454 static void pcn_attach(device_t, device_t, void *); 455 456 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 457 pcn_match, pcn_attach, NULL, NULL); 458 459 /* 460 * Routines to read and write the PCnet-PCI CSR/BCR space. 461 */ 462 463 static inline uint32_t 464 pcn_csr_read(struct pcn_softc *sc, int reg) 465 { 466 467 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 468 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP); 469 } 470 471 static inline void 472 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 473 { 474 475 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 477 } 478 479 static inline uint32_t 480 pcn_bcr_read(struct pcn_softc *sc, int reg) 481 { 482 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 484 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP); 485 } 486 487 static inline void 488 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 489 { 490 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 493 } 494 495 static bool 496 pcn_is_vmware(const char *enaddr) 497 { 498 499 /* 500 * VMware uses the OUI 00:0c:29 for auto-generated MAC 501 * addresses. 502 */ 503 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 504 return TRUE; 505 506 /* 507 * VMware uses the OUI 00:50:56 for manually-set MAC 508 * addresses (and some auto-generated ones). 509 */ 510 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 511 return TRUE; 512 513 return FALSE; 514 } 515 516 static const struct pcn_variant * 517 pcn_lookup_variant(uint16_t chipid) 518 { 519 const struct pcn_variant *pcv; 520 521 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 522 if (chipid == pcv->pcv_chipid) 523 return pcv; 524 } 525 526 /* 527 * This covers unknown chips, which we simply treat like 528 * a generic PCnet-FAST. 529 */ 530 return pcv; 531 } 532 533 static int 534 pcn_match(device_t parent, cfdata_t cf, void *aux) 535 { 536 struct pci_attach_args *pa = aux; 537 538 /* 539 * IBM Makes a PCI variant of this card which shows up as a 540 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 541 * this card is truly a pcn card, so we have a special case match for 542 * it 543 */ 544 545 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 546 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 547 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 548 return 1; 549 550 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 551 return 0; 552 553 switch (PCI_PRODUCT(pa->pa_id)) { 554 case PCI_PRODUCT_AMD_PCNET_PCI: 555 /* Beat if_le_pci.c */ 556 return 10; 557 } 558 559 return 0; 560 } 561 562 static void 563 pcn_attach(device_t parent, device_t self, void *aux) 564 { 565 struct pcn_softc *sc = device_private(self); 566 struct pci_attach_args *pa = aux; 567 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 568 pci_chipset_tag_t pc = pa->pa_pc; 569 pci_intr_handle_t ih; 570 const char *intrstr = NULL; 571 bus_space_tag_t iot, memt; 572 bus_space_handle_t ioh, memh; 573 bus_dma_segment_t seg; 574 int ioh_valid, memh_valid; 575 int ntxsegs, i, rseg, error; 576 uint32_t chipid, reg; 577 uint8_t enaddr[ETHER_ADDR_LEN]; 578 prop_object_t obj; 579 bool is_vmware; 580 char intrbuf[PCI_INTRSTR_LEN]; 581 582 sc->sc_dev = self; 583 callout_init(&sc->sc_tick_ch, 0); 584 callout_setfunc(&sc->sc_tick_ch, pcn_tick, sc); 585 586 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 587 588 /* 589 * Map the device. 590 */ 591 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 592 &iot, &ioh, NULL, NULL) == 0); 593 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 594 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 595 &memt, &memh, NULL, NULL) == 0); 596 597 if (memh_valid) { 598 sc->sc_st = memt; 599 sc->sc_sh = memh; 600 } else if (ioh_valid) { 601 sc->sc_st = iot; 602 sc->sc_sh = ioh; 603 } else { 604 aprint_error_dev(self, "unable to map device registers\n"); 605 return; 606 } 607 608 sc->sc_dmat = pa->pa_dmat; 609 610 /* Make sure bus mastering is enabled. */ 611 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 612 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 613 PCI_COMMAND_MASTER_ENABLE); 614 615 /* power up chip */ 616 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 617 NULL)) && error != EOPNOTSUPP) { 618 aprint_error_dev(self, "cannot activate %d\n", error); 619 return; 620 } 621 622 /* 623 * Reset the chip to a known state. This also puts the 624 * chip into 32-bit mode. 625 */ 626 pcn_reset(sc); 627 628 /* 629 * On some systems with the chip is an on-board device, the 630 * EEPROM is not used. Handle this by reading the MAC address 631 * from the CSRs (assuming that boot firmware has written 632 * it there). 633 */ 634 obj = prop_dictionary_get(device_properties(sc->sc_dev), 635 "am79c970-no-eeprom"); 636 if (prop_bool_true(obj)) { 637 for (i = 0; i < 3; i++) { 638 uint32_t val; 639 val = pcn_csr_read(sc, LE_CSR12 + i); 640 enaddr[2 * i] = val & 0xff; 641 enaddr[2 * i + 1] = (val >> 8) & 0xff; 642 } 643 } else { 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 646 PCN32_APROM + i); 647 } 648 } 649 650 /* Check to see if this is a VMware emulated network interface. */ 651 is_vmware = pcn_is_vmware(enaddr); 652 653 /* 654 * Now that the device is mapped, attempt to figure out what 655 * kind of chip we have. Note that IDL has all 32 bits of 656 * the chip ID when we're in 32-bit mode. 657 */ 658 chipid = pcn_csr_read(sc, LE_CSR88); 659 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 660 661 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 662 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 663 ether_sprintf(enaddr)); 664 665 /* 666 * VMware has a bug in its network interface emulation; we must 667 * limit the number of Tx segments. 668 */ 669 if (is_vmware) { 670 ntxsegs = PCN_NTXSEGS_VMWARE; 671 prop_dictionary_set_bool(device_properties(sc->sc_dev), 672 "am79c970-vmware-tx-bug", TRUE); 673 aprint_verbose_dev(self, 674 "VMware Tx segment count bug detected\n"); 675 } else { 676 ntxsegs = PCN_NTXSEGS; 677 } 678 679 /* 680 * Map and establish our interrupt. 681 */ 682 if (pci_intr_map(pa, &ih)) { 683 aprint_error_dev(self, "unable to map interrupt\n"); 684 return; 685 } 686 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 687 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, pcn_intr, sc, 688 device_xname(self)); 689 if (sc->sc_ih == NULL) { 690 aprint_error_dev(self, "unable to establish interrupt"); 691 if (intrstr != NULL) 692 aprint_error(" at %s", intrstr); 693 aprint_error("\n"); 694 return; 695 } 696 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 697 698 /* 699 * Allocate the control data structures, and create and load the 700 * DMA map for it. 701 */ 702 if ((error = bus_dmamem_alloc(sc->sc_dmat, 703 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 704 0)) != 0) { 705 aprint_error_dev(self, "unable to allocate control data, " 706 "error = %d\n", error); 707 goto fail_0; 708 } 709 710 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 711 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 712 BUS_DMA_COHERENT)) != 0) { 713 aprint_error_dev(self, "unable to map control data, " 714 "error = %d\n", error); 715 goto fail_1; 716 } 717 718 if ((error = bus_dmamap_create(sc->sc_dmat, 719 sizeof(struct pcn_control_data), 1, 720 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 721 aprint_error_dev(self, "unable to create control data DMA map, " 722 "error = %d\n", error); 723 goto fail_2; 724 } 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 727 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 728 0)) != 0) { 729 aprint_error_dev(self, 730 "unable to load control data DMA map, error = %d\n", error); 731 goto fail_3; 732 } 733 734 /* Create the transmit buffer DMA maps. */ 735 for (i = 0; i < PCN_TXQUEUELEN; i++) { 736 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 737 ntxsegs, MCLBYTES, 0, 0, 738 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 739 aprint_error_dev(self, 740 "unable to create tx DMA map %d, error = %d\n", 741 i, error); 742 goto fail_4; 743 } 744 } 745 746 /* Create the receive buffer DMA maps. */ 747 for (i = 0; i < PCN_NRXDESC; i++) { 748 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 749 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 750 aprint_error_dev(self, 751 "unable to create rx DMA map %d, error = %d\n", 752 i, error); 753 goto fail_5; 754 } 755 sc->sc_rxsoft[i].rxs_mbuf = NULL; 756 } 757 758 /* Initialize our media structures. */ 759 (*sc->sc_variant->pcv_mediainit)(sc); 760 761 /* 762 * Initialize FIFO watermark info. 763 */ 764 switch (sc->sc_variant->pcv_chipid) { 765 case PARTID_Am79c970: 766 case PARTID_Am79c970A: 767 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 768 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 769 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 770 break; 771 772 default: 773 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 774 /* 775 * Read BCR25 to determine how much SRAM is 776 * on the board. If > 0, then we the chip 777 * uses different Start Point thresholds. 778 * 779 * Note BCR25 and BCR26 are loaded from the 780 * EEPROM on RST, and unaffected by S_RESET, 781 * so we don't really have to worry about 782 * them except for this. 783 */ 784 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 785 if (reg != 0) 786 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 787 else 788 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 789 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 790 break; 791 } 792 793 /* 794 * Set up defaults -- see the tables above for what these 795 * values mean. 796 * 797 * XXX How should we tune RCVFW and XMTFW? 798 */ 799 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 800 sc->sc_xmtsp = 1; 801 sc->sc_xmtfw = 0; 802 803 ifp = &sc->sc_ethercom.ec_if; 804 strcpy(ifp->if_xname, device_xname(self)); 805 ifp->if_softc = sc; 806 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 807 ifp->if_ioctl = pcn_ioctl; 808 ifp->if_start = pcn_start; 809 ifp->if_watchdog = pcn_watchdog; 810 ifp->if_init = pcn_init; 811 ifp->if_stop = pcn_stop; 812 IFQ_SET_READY(&ifp->if_snd); 813 814 /* Attach the interface. */ 815 if_attach(ifp); 816 if_deferred_start_init(ifp, NULL); 817 ether_ifattach(ifp, enaddr); 818 rnd_attach_source(&sc->rnd_source, device_xname(self), 819 RND_TYPE_NET, RND_FLAG_DEFAULT); 820 821 #ifdef PCN_EVENT_COUNTERS 822 /* Attach event counters. */ 823 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 824 NULL, device_xname(self), "txdstall"); 825 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 826 NULL, device_xname(self), "txintr"); 827 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 828 NULL, device_xname(self), "rxintr"); 829 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 830 NULL, device_xname(self), "babl"); 831 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 832 NULL, device_xname(self), "miss"); 833 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 834 NULL, device_xname(self), "merr"); 835 836 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 837 NULL, device_xname(self), "txseg1"); 838 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 839 NULL, device_xname(self), "txseg2"); 840 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 841 NULL, device_xname(self), "txseg3"); 842 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 843 NULL, device_xname(self), "txseg4"); 844 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 845 NULL, device_xname(self), "txseg5"); 846 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 847 NULL, device_xname(self), "txsegmore"); 848 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 849 NULL, device_xname(self), "txcopy"); 850 #endif /* PCN_EVENT_COUNTERS */ 851 852 /* 853 * Establish power handler with shutdown hook, to make sure 854 * the interface is shutdown during reboot. 855 */ 856 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 857 pmf_class_network_register(self, ifp); 858 else 859 aprint_error_dev(self, "couldn't establish power handler\n"); 860 861 return; 862 863 /* 864 * Free any resources we've allocated during the failed attach 865 * attempt. Do this in reverse order and fall through. 866 */ 867 fail_5: 868 for (i = 0; i < PCN_NRXDESC; i++) { 869 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 870 bus_dmamap_destroy(sc->sc_dmat, 871 sc->sc_rxsoft[i].rxs_dmamap); 872 } 873 fail_4: 874 for (i = 0; i < PCN_TXQUEUELEN; i++) { 875 if (sc->sc_txsoft[i].txs_dmamap != NULL) 876 bus_dmamap_destroy(sc->sc_dmat, 877 sc->sc_txsoft[i].txs_dmamap); 878 } 879 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 880 fail_3: 881 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 882 fail_2: 883 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 884 sizeof(struct pcn_control_data)); 885 fail_1: 886 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 887 fail_0: 888 return; 889 } 890 891 /* 892 * pcn_shutdown: 893 * 894 * Make sure the interface is stopped at reboot time. 895 */ 896 static bool 897 pcn_shutdown(device_t self, int howto) 898 { 899 struct pcn_softc *sc = device_private(self); 900 901 pcn_stop(&sc->sc_ethercom.ec_if, 1); 902 /* explicitly reset the chip for some onboard one with lazy firmware */ 903 pcn_reset(sc); 904 905 return true; 906 } 907 908 /* 909 * pcn_start: [ifnet interface function] 910 * 911 * Start packet transmission on the interface. 912 */ 913 static void 914 pcn_start(struct ifnet *ifp) 915 { 916 struct pcn_softc *sc = ifp->if_softc; 917 struct mbuf *m0, *m; 918 struct pcn_txsoft *txs; 919 bus_dmamap_t dmamap; 920 int error, nexttx, lasttx = -1, ofree, seg; 921 922 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 923 return; 924 925 /* 926 * Remember the previous number of free descriptors and 927 * the first descriptor we'll use. 928 */ 929 ofree = sc->sc_txfree; 930 931 /* 932 * Loop through the send queue, setting up transmit descriptors 933 * until we drain the queue, or use up all available transmit 934 * descriptors. 935 */ 936 while (sc->sc_txsfree != 0) { 937 /* Grab a packet off the queue. */ 938 IFQ_POLL(&ifp->if_snd, m0); 939 if (m0 == NULL) 940 break; 941 m = NULL; 942 943 txs = &sc->sc_txsoft[sc->sc_txsnext]; 944 dmamap = txs->txs_dmamap; 945 946 /* 947 * Load the DMA map. If this fails, the packet either 948 * didn't fit in the alloted number of segments, or we 949 * were short on resources. In this case, we'll copy 950 * and try again. 951 */ 952 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 953 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 954 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 955 MGETHDR(m, M_DONTWAIT, MT_DATA); 956 if (m == NULL) { 957 printf("%s: unable to allocate Tx mbuf\n", 958 device_xname(sc->sc_dev)); 959 break; 960 } 961 if (m0->m_pkthdr.len > MHLEN) { 962 MCLGET(m, M_DONTWAIT); 963 if ((m->m_flags & M_EXT) == 0) { 964 printf("%s: unable to allocate Tx " 965 "cluster\n", 966 device_xname(sc->sc_dev)); 967 m_freem(m); 968 break; 969 } 970 } 971 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 972 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 973 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 974 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 975 if (error) { 976 printf("%s: unable to load Tx buffer, " 977 "error = %d\n", device_xname(sc->sc_dev), 978 error); 979 m_freem(m); 980 break; 981 } 982 } 983 984 /* 985 * Ensure we have enough descriptors free to describe 986 * the packet. Note, we always reserve one descriptor 987 * at the end of the ring as a termination point, to 988 * prevent wrap-around. 989 */ 990 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 991 /* 992 * Not enough free descriptors to transmit this 993 * packet. 994 */ 995 bus_dmamap_unload(sc->sc_dmat, dmamap); 996 if (m != NULL) 997 m_freem(m); 998 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 999 break; 1000 } 1001 1002 IFQ_DEQUEUE(&ifp->if_snd, m0); 1003 if (m != NULL) { 1004 m_freem(m0); 1005 m0 = m; 1006 } 1007 1008 /* 1009 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1010 */ 1011 1012 /* Sync the DMA map. */ 1013 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1014 BUS_DMASYNC_PREWRITE); 1015 1016 #ifdef PCN_EVENT_COUNTERS 1017 switch (dmamap->dm_nsegs) { 1018 case 1: 1019 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1020 break; 1021 case 2: 1022 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1023 break; 1024 case 3: 1025 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1026 break; 1027 case 4: 1028 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1029 break; 1030 case 5: 1031 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1032 break; 1033 default: 1034 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1035 break; 1036 } 1037 #endif /* PCN_EVENT_COUNTERS */ 1038 1039 /* 1040 * Initialize the transmit descriptors. 1041 */ 1042 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1043 for (nexttx = sc->sc_txnext, seg = 0; 1044 seg < dmamap->dm_nsegs; 1045 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1046 /* 1047 * If this is the first descriptor we're 1048 * enqueueing, don't set the OWN bit just 1049 * yet. That could cause a race condition. 1050 * We'll do it below. 1051 */ 1052 sc->sc_txdescs[nexttx].tmd0 = 0; 1053 sc->sc_txdescs[nexttx].tmd2 = 1054 htole32(dmamap->dm_segs[seg].ds_addr); 1055 sc->sc_txdescs[nexttx].tmd1 = 1056 htole32(LE_T1_ONES | 1057 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1058 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1059 LE_T1_BCNT_MASK)); 1060 lasttx = nexttx; 1061 } 1062 } else { 1063 for (nexttx = sc->sc_txnext, seg = 0; 1064 seg < dmamap->dm_nsegs; 1065 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1066 /* 1067 * If this is the first descriptor we're 1068 * enqueueing, don't set the OWN bit just 1069 * yet. That could cause a race condition. 1070 * We'll do it below. 1071 */ 1072 sc->sc_txdescs[nexttx].tmd0 = 1073 htole32(dmamap->dm_segs[seg].ds_addr); 1074 sc->sc_txdescs[nexttx].tmd2 = 0; 1075 sc->sc_txdescs[nexttx].tmd1 = 1076 htole32(LE_T1_ONES | 1077 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1078 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1079 LE_T1_BCNT_MASK)); 1080 lasttx = nexttx; 1081 } 1082 } 1083 1084 KASSERT(lasttx != -1); 1085 /* Interrupt on the packet, if appropriate. */ 1086 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1087 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1088 1089 /* Set `start of packet' and `end of packet' appropriately. */ 1090 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1091 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1092 htole32(LE_T1_OWN | LE_T1_STP); 1093 1094 /* Sync the descriptors we're using. */ 1095 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1097 1098 /* Kick the transmitter. */ 1099 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); 1100 1101 /* 1102 * Store a pointer to the packet so we can free it later, 1103 * and remember what txdirty will be once the packet is 1104 * done. 1105 */ 1106 txs->txs_mbuf = m0; 1107 txs->txs_firstdesc = sc->sc_txnext; 1108 txs->txs_lastdesc = lasttx; 1109 1110 /* Advance the tx pointer. */ 1111 sc->sc_txfree -= dmamap->dm_nsegs; 1112 sc->sc_txnext = nexttx; 1113 1114 sc->sc_txsfree--; 1115 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1116 1117 /* Pass the packet to any BPF listeners. */ 1118 bpf_mtap(ifp, m0, BPF_D_OUT); 1119 } 1120 1121 if (sc->sc_txfree != ofree) { 1122 /* Set a watchdog timer in case the chip flakes out. */ 1123 ifp->if_timer = 5; 1124 } 1125 } 1126 1127 /* 1128 * pcn_watchdog: [ifnet interface function] 1129 * 1130 * Watchdog timer handler. 1131 */ 1132 static void 1133 pcn_watchdog(struct ifnet *ifp) 1134 { 1135 struct pcn_softc *sc = ifp->if_softc; 1136 1137 /* 1138 * Since we're not interrupting every packet, sweep 1139 * up before we report an error. 1140 */ 1141 pcn_txintr(sc); 1142 1143 if (sc->sc_txfree != PCN_NTXDESC) { 1144 printf("%s: device timeout (txfree %d txsfree %d)\n", 1145 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1146 if_statinc(ifp, if_oerrors); 1147 1148 /* Reset the interface. */ 1149 (void) pcn_init(ifp); 1150 } 1151 1152 /* Try to get more packets going. */ 1153 pcn_start(ifp); 1154 } 1155 1156 /* 1157 * pcn_ioctl: [ifnet interface function] 1158 * 1159 * Handle control requests from the operator. 1160 */ 1161 static int 1162 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1163 { 1164 int s, error; 1165 1166 s = splnet(); 1167 1168 switch (cmd) { 1169 default: 1170 error = ether_ioctl(ifp, cmd, data); 1171 if (error == ENETRESET) { 1172 /* 1173 * Multicast list has changed; set the hardware filter 1174 * accordingly. 1175 */ 1176 if (ifp->if_flags & IFF_RUNNING) 1177 error = pcn_init(ifp); 1178 else 1179 error = 0; 1180 } 1181 break; 1182 } 1183 1184 /* Try to get more packets going. */ 1185 pcn_start(ifp); 1186 1187 splx(s); 1188 return error; 1189 } 1190 1191 /* 1192 * pcn_intr: 1193 * 1194 * Interrupt service routine. 1195 */ 1196 static int 1197 pcn_intr(void *arg) 1198 { 1199 struct pcn_softc *sc = arg; 1200 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1201 uint32_t csr0; 1202 int wantinit, handled = 0; 1203 1204 for (wantinit = 0; wantinit == 0;) { 1205 csr0 = pcn_csr_read(sc, LE_CSR0); 1206 if ((csr0 & LE_C0_INTR) == 0) 1207 break; 1208 1209 rnd_add_uint32(&sc->rnd_source, csr0); 1210 1211 /* ACK the bits and re-enable interrupts. */ 1212 pcn_csr_write(sc, LE_CSR0, csr0 & 1213 (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR | 1214 LE_C0_RINT | LE_C0_TINT | LE_C0_IDON)); 1215 1216 handled = 1; 1217 1218 if (csr0 & LE_C0_RINT) { 1219 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1220 wantinit = pcn_rxintr(sc); 1221 } 1222 1223 if (csr0 & LE_C0_TINT) { 1224 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1225 pcn_txintr(sc); 1226 } 1227 1228 if (csr0 & LE_C0_ERR) { 1229 if (csr0 & LE_C0_BABL) { 1230 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1231 if_statinc(ifp, if_oerrors); 1232 } 1233 if (csr0 & LE_C0_MISS) { 1234 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1235 if_statinc(ifp, if_ierrors); 1236 } 1237 if (csr0 & LE_C0_MERR) { 1238 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1239 printf("%s: memory error\n", 1240 device_xname(sc->sc_dev)); 1241 wantinit = 1; 1242 break; 1243 } 1244 } 1245 1246 if ((csr0 & LE_C0_RXON) == 0) { 1247 printf("%s: receiver disabled\n", 1248 device_xname(sc->sc_dev)); 1249 if_statinc(ifp, if_ierrors); 1250 wantinit = 1; 1251 } 1252 1253 if ((csr0 & LE_C0_TXON) == 0) { 1254 printf("%s: transmitter disabled\n", 1255 device_xname(sc->sc_dev)); 1256 if_statinc(ifp, if_oerrors); 1257 wantinit = 1; 1258 } 1259 } 1260 1261 if (handled) { 1262 if (wantinit) 1263 pcn_init(ifp); 1264 1265 /* Try to get more packets going. */ 1266 if_schedule_deferred_start(ifp); 1267 } 1268 1269 return handled; 1270 } 1271 1272 /* 1273 * pcn_spnd: 1274 * 1275 * Suspend the chip. 1276 */ 1277 static void 1278 pcn_spnd(struct pcn_softc *sc) 1279 { 1280 int i; 1281 1282 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1283 1284 for (i = 0; i < 10000; i++) { 1285 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1286 return; 1287 delay(5); 1288 } 1289 1290 printf("%s: WARNING: chip failed to enter suspended state\n", 1291 device_xname(sc->sc_dev)); 1292 } 1293 1294 /* 1295 * pcn_txintr: 1296 * 1297 * Helper; handle transmit interrupts. 1298 */ 1299 static void 1300 pcn_txintr(struct pcn_softc *sc) 1301 { 1302 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1303 struct pcn_txsoft *txs; 1304 uint32_t tmd1, tmd2, tmd; 1305 int i, j; 1306 1307 /* 1308 * Go through our Tx list and free mbufs for those 1309 * frames which have been transmitted. 1310 */ 1311 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1312 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1313 txs = &sc->sc_txsoft[i]; 1314 1315 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1317 1318 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1319 if (tmd1 & LE_T1_OWN) 1320 break; 1321 1322 /* 1323 * Slightly annoying -- we have to loop through the 1324 * descriptors we've used looking for ERR, since it 1325 * can appear on any descriptor in the chain. 1326 */ 1327 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1328 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1329 if (tmd & LE_T1_ERR) { 1330 if_statinc(ifp, if_oerrors); 1331 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1332 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1333 else 1334 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1335 if (tmd2 & LE_T2_UFLO) { 1336 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1337 sc->sc_xmtsp++; 1338 printf("%s: transmit " 1339 "underrun; new threshold: " 1340 "%s\n", 1341 device_xname(sc->sc_dev), 1342 sc->sc_xmtsp_desc[ 1343 sc->sc_xmtsp]); 1344 pcn_spnd(sc); 1345 pcn_csr_write(sc, LE_CSR80, 1346 LE_C80_RCVFW(sc->sc_rcvfw) | 1347 LE_C80_XMTSP(sc->sc_xmtsp) | 1348 LE_C80_XMTFW(sc->sc_xmtfw)); 1349 pcn_csr_write(sc, LE_CSR5, 1350 sc->sc_csr5); 1351 } else { 1352 printf("%s: transmit " 1353 "underrun\n", 1354 device_xname(sc->sc_dev)); 1355 } 1356 } else if (tmd2 & LE_T2_BUFF) { 1357 printf("%s: transmit buffer error\n", 1358 device_xname(sc->sc_dev)); 1359 } 1360 if (tmd2 & LE_T2_LCOL) 1361 if_statinc(ifp, if_collisions); 1362 if (tmd2 & LE_T2_RTRY) 1363 if_statadd(ifp, if_collisions, 16); 1364 goto next_packet; 1365 } 1366 if (j == txs->txs_lastdesc) 1367 break; 1368 } 1369 if (tmd1 & LE_T1_ONE) 1370 if_statinc(ifp, if_collisions); 1371 else if (tmd & LE_T1_MORE) { 1372 /* Real number is unknown. */ 1373 if_statadd(ifp, if_collisions, 2); 1374 } 1375 if_statinc(ifp, if_opackets); 1376 next_packet: 1377 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1378 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1379 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1380 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1381 m_freem(txs->txs_mbuf); 1382 txs->txs_mbuf = NULL; 1383 } 1384 1385 /* Update the dirty transmit buffer pointer. */ 1386 sc->sc_txsdirty = i; 1387 1388 /* 1389 * If there are no more pending transmissions, cancel the watchdog 1390 * timer. 1391 */ 1392 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1393 ifp->if_timer = 0; 1394 } 1395 1396 /* 1397 * pcn_rxintr: 1398 * 1399 * Helper; handle receive interrupts. 1400 */ 1401 static int 1402 pcn_rxintr(struct pcn_softc *sc) 1403 { 1404 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1405 struct pcn_rxsoft *rxs; 1406 struct mbuf *m; 1407 uint32_t rmd1; 1408 int i, len; 1409 1410 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1411 rxs = &sc->sc_rxsoft[i]; 1412 1413 PCN_CDRXSYNC(sc, i, 1414 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1415 1416 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1417 1418 if (rmd1 & LE_R1_OWN) 1419 break; 1420 1421 /* 1422 * Check for errors and make sure the packet fit into 1423 * a single buffer. We have structured this block of 1424 * code the way it is in order to compress it into 1425 * one test in the common case (no error). 1426 */ 1427 if (__predict_false((rmd1 & (LE_R1_STP | LE_R1_ENP |LE_R1_ERR)) 1428 != (LE_R1_STP | LE_R1_ENP))) { 1429 /* Make sure the packet is in a single buffer. */ 1430 if ((rmd1 & (LE_R1_STP | LE_R1_ENP)) != 1431 (LE_R1_STP | LE_R1_ENP)) { 1432 printf("%s: packet spilled into next buffer\n", 1433 device_xname(sc->sc_dev)); 1434 return 1; /* pcn_intr() will re-init */ 1435 } 1436 1437 /* 1438 * If the packet had an error, simple recycle the 1439 * buffer. 1440 */ 1441 if (rmd1 & LE_R1_ERR) { 1442 if_statinc(ifp, if_ierrors); 1443 /* 1444 * If we got an overflow error, chances 1445 * are there will be a CRC error. In 1446 * this case, just print the overflow 1447 * error, and skip the others. 1448 */ 1449 if (rmd1 & LE_R1_OFLO) 1450 printf("%s: overflow error\n", 1451 device_xname(sc->sc_dev)); 1452 else { 1453 #define PRINTIT(x, str) \ 1454 if (rmd1 & (x)) \ 1455 printf("%s: %s\n", \ 1456 device_xname(sc->sc_dev), \ 1457 str); 1458 PRINTIT(LE_R1_FRAM, "framing error"); 1459 PRINTIT(LE_R1_CRC, "CRC error"); 1460 PRINTIT(LE_R1_BUFF, "buffer error"); 1461 } 1462 #undef PRINTIT 1463 PCN_INIT_RXDESC(sc, i); 1464 continue; 1465 } 1466 } 1467 1468 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1469 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1470 1471 /* 1472 * No errors; receive the packet. 1473 */ 1474 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1475 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1476 else 1477 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1478 1479 /* 1480 * The LANCE family includes the CRC with every packet; 1481 * trim it off here. 1482 */ 1483 len -= ETHER_CRC_LEN; 1484 1485 /* 1486 * If the packet is small enough to fit in a 1487 * single header mbuf, allocate one and copy 1488 * the data into it. This greatly reduces 1489 * memory consumption when we receive lots 1490 * of small packets. 1491 * 1492 * Otherwise, we add a new buffer to the receive 1493 * chain. If this fails, we drop the packet and 1494 * recycle the old buffer. 1495 */ 1496 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1497 MGETHDR(m, M_DONTWAIT, MT_DATA); 1498 if (m == NULL) 1499 goto dropit; 1500 m->m_data += 2; 1501 memcpy(mtod(m, void *), 1502 mtod(rxs->rxs_mbuf, void *), len); 1503 PCN_INIT_RXDESC(sc, i); 1504 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1505 rxs->rxs_dmamap->dm_mapsize, 1506 BUS_DMASYNC_PREREAD); 1507 } else { 1508 m = rxs->rxs_mbuf; 1509 if (pcn_add_rxbuf(sc, i) != 0) { 1510 dropit: 1511 if_statinc(ifp, if_ierrors); 1512 PCN_INIT_RXDESC(sc, i); 1513 bus_dmamap_sync(sc->sc_dmat, 1514 rxs->rxs_dmamap, 0, 1515 rxs->rxs_dmamap->dm_mapsize, 1516 BUS_DMASYNC_PREREAD); 1517 continue; 1518 } 1519 } 1520 1521 m_set_rcvif(m, ifp); 1522 m->m_pkthdr.len = m->m_len = len; 1523 1524 /* Pass it on. */ 1525 if_percpuq_enqueue(ifp->if_percpuq, m); 1526 } 1527 1528 /* Update the receive pointer. */ 1529 sc->sc_rxptr = i; 1530 return 0; 1531 } 1532 1533 /* 1534 * pcn_tick: 1535 * 1536 * One second timer, used to tick the MII. 1537 */ 1538 static void 1539 pcn_tick(void *arg) 1540 { 1541 struct pcn_softc *sc = arg; 1542 int s; 1543 1544 s = splnet(); 1545 mii_tick(&sc->sc_mii); 1546 splx(s); 1547 1548 callout_schedule(&sc->sc_tick_ch, hz); 1549 } 1550 1551 /* 1552 * pcn_reset: 1553 * 1554 * Perform a soft reset on the PCnet-PCI. 1555 */ 1556 static void 1557 pcn_reset(struct pcn_softc *sc) 1558 { 1559 1560 /* 1561 * The PCnet-PCI chip is reset by reading from the 1562 * RESET register. Note that while the NE2100 LANCE 1563 * boards require a write after the read, the PCnet-PCI 1564 * chips do not require this. 1565 * 1566 * Since we don't know if we're in 16-bit or 32-bit 1567 * mode right now, issue both (it's safe) in the 1568 * hopes that one will succeed. 1569 */ 1570 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1571 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1572 1573 /* Wait 1ms for it to finish. */ 1574 delay(1000); 1575 1576 /* 1577 * Select 32-bit I/O mode by issuing a 32-bit write to the 1578 * RDP. Since the RAP is 0 after a reset, writing a 0 1579 * to RDP is safe (since it simply clears CSR0). 1580 */ 1581 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1582 } 1583 1584 /* 1585 * pcn_init: [ifnet interface function] 1586 * 1587 * Initialize the interface. Must be called at splnet(). 1588 */ 1589 static int 1590 pcn_init(struct ifnet *ifp) 1591 { 1592 struct pcn_softc *sc = ifp->if_softc; 1593 struct pcn_rxsoft *rxs; 1594 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1595 int i, error = 0; 1596 uint32_t reg; 1597 1598 /* Cancel any pending I/O. */ 1599 pcn_stop(ifp, 0); 1600 1601 /* Reset the chip to a known state. */ 1602 pcn_reset(sc); 1603 1604 /* 1605 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1606 * else. 1607 * 1608 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1609 * because the structure layout is compatible with ILACC, 1610 * but the burst mode is only available in SSTYLE 3, and 1611 * burst mode should provide some performance enhancement. 1612 */ 1613 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1614 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1615 else 1616 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1617 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1618 1619 /* Initialize the transmit descriptor ring. */ 1620 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1621 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1623 sc->sc_txfree = PCN_NTXDESC; 1624 sc->sc_txnext = 0; 1625 1626 /* Initialize the transmit job descriptors. */ 1627 for (i = 0; i < PCN_TXQUEUELEN; i++) 1628 sc->sc_txsoft[i].txs_mbuf = NULL; 1629 sc->sc_txsfree = PCN_TXQUEUELEN; 1630 sc->sc_txsnext = 0; 1631 sc->sc_txsdirty = 0; 1632 1633 /* 1634 * Initialize the receive descriptor and receive job 1635 * descriptor rings. 1636 */ 1637 for (i = 0; i < PCN_NRXDESC; i++) { 1638 rxs = &sc->sc_rxsoft[i]; 1639 if (rxs->rxs_mbuf == NULL) { 1640 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1641 printf("%s: unable to allocate or map rx " 1642 "buffer %d, error = %d\n", 1643 device_xname(sc->sc_dev), i, error); 1644 /* 1645 * XXX Should attempt to run with fewer receive 1646 * XXX buffers instead of just failing. 1647 */ 1648 pcn_rxdrain(sc); 1649 goto out; 1650 } 1651 } else 1652 PCN_INIT_RXDESC(sc, i); 1653 } 1654 sc->sc_rxptr = 0; 1655 1656 /* Initialize MODE for the initialization block. */ 1657 sc->sc_mode = 0; 1658 if (ifp->if_flags & IFF_PROMISC) 1659 sc->sc_mode |= LE_C15_PROM; 1660 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1661 sc->sc_mode |= LE_C15_DRCVBC; 1662 1663 /* 1664 * If we have MII, simply select MII in the MODE register, 1665 * and clear ASEL. Otherwise, let ASEL stand (for now), 1666 * and leave PORTSEL alone (it is ignored with ASEL is set). 1667 */ 1668 if (sc->sc_flags & PCN_F_HAS_MII) { 1669 pcn_bcr_write(sc, LE_BCR2, 1670 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1671 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1672 1673 /* 1674 * Disable MII auto-negotiation. We handle that in 1675 * our own MII layer. 1676 */ 1677 pcn_bcr_write(sc, LE_BCR32, 1678 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1679 } 1680 1681 /* 1682 * Set the Tx and Rx descriptor ring addresses in the init 1683 * block, the TLEN and RLEN other fields of the init block 1684 * MODE register. 1685 */ 1686 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1687 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1688 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1689 (((uint32_t)ffs(PCN_NTXDESC) - 1) << 28) | 1690 ((ffs(PCN_NRXDESC) - 1) << 20)); 1691 1692 /* Set the station address in the init block. */ 1693 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1694 (enaddr[1] << 8) | (enaddr[2] << 16) | 1695 ((uint32_t)enaddr[3] << 24)); 1696 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1697 (enaddr[5] << 8)); 1698 1699 /* Set the multicast filter in the init block. */ 1700 pcn_set_filter(sc); 1701 1702 /* Initialize CSR3. */ 1703 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM | LE_C3_IDONM | LE_C3_DXSUFLO); 1704 1705 /* Initialize CSR4. */ 1706 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS | LE_C4_APAD_XMT | 1707 LE_C4_MFCOM | LE_C4_RCVCCOM | LE_C4_TXSTRTM); 1708 1709 /* Initialize CSR5. */ 1710 sc->sc_csr5 = LE_C5_LTINTEN | LE_C5_SINTE; 1711 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1712 1713 /* 1714 * If we have an Am79c971 or greater, initialize CSR7. 1715 * 1716 * XXX Might be nice to use the MII auto-poll interrupt someday. 1717 */ 1718 switch (sc->sc_variant->pcv_chipid) { 1719 case PARTID_Am79c970: 1720 case PARTID_Am79c970A: 1721 /* Not available on these chips. */ 1722 break; 1723 1724 default: 1725 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1726 break; 1727 } 1728 1729 /* 1730 * On the Am79c970A and greater, initialize BCR18 to 1731 * enable burst mode. 1732 * 1733 * Also enable the "no underflow" option on the Am79c971 and 1734 * higher, which prevents the chip from generating transmit 1735 * underflows, yet sill provides decent performance. Note if 1736 * chip is not connected to external SRAM, then we still have 1737 * to handle underflow errors (the NOUFLO bit is ignored in 1738 * that case). 1739 */ 1740 reg = pcn_bcr_read(sc, LE_BCR18); 1741 switch (sc->sc_variant->pcv_chipid) { 1742 case PARTID_Am79c970: 1743 break; 1744 1745 case PARTID_Am79c970A: 1746 reg |= LE_B18_BREADE | LE_B18_BWRITE; 1747 break; 1748 1749 default: 1750 reg |= LE_B18_BREADE | LE_B18_BWRITE | LE_B18_NOUFLO; 1751 break; 1752 } 1753 pcn_bcr_write(sc, LE_BCR18, reg); 1754 1755 /* 1756 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1757 */ 1758 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1759 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1760 1761 /* 1762 * Send the init block to the chip, and wait for it 1763 * to be processed. 1764 */ 1765 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1766 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1767 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1768 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1769 delay(100); 1770 for (i = 0; i < 10000; i++) { 1771 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1772 break; 1773 delay(10); 1774 } 1775 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1776 if (i == 10000) { 1777 printf("%s: timeout processing init block\n", 1778 device_xname(sc->sc_dev)); 1779 error = EIO; 1780 goto out; 1781 } 1782 1783 /* Set the media. */ 1784 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1785 goto out; 1786 1787 /* Enable interrupts and external activity (and ACK IDON). */ 1788 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT | LE_C0_IDON); 1789 1790 if (sc->sc_flags & PCN_F_HAS_MII) { 1791 /* Start the one second MII clock. */ 1792 callout_schedule(&sc->sc_tick_ch, hz); 1793 } 1794 1795 /* ...all done! */ 1796 ifp->if_flags |= IFF_RUNNING; 1797 1798 out: 1799 if (error) 1800 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1801 return error; 1802 } 1803 1804 /* 1805 * pcn_rxdrain: 1806 * 1807 * Drain the receive queue. 1808 */ 1809 static void 1810 pcn_rxdrain(struct pcn_softc *sc) 1811 { 1812 struct pcn_rxsoft *rxs; 1813 int i; 1814 1815 for (i = 0; i < PCN_NRXDESC; i++) { 1816 rxs = &sc->sc_rxsoft[i]; 1817 if (rxs->rxs_mbuf != NULL) { 1818 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1819 m_freem(rxs->rxs_mbuf); 1820 rxs->rxs_mbuf = NULL; 1821 } 1822 } 1823 } 1824 1825 /* 1826 * pcn_stop: [ifnet interface function] 1827 * 1828 * Stop transmission on the interface. 1829 */ 1830 static void 1831 pcn_stop(struct ifnet *ifp, int disable) 1832 { 1833 struct pcn_softc *sc = ifp->if_softc; 1834 struct pcn_txsoft *txs; 1835 int i; 1836 1837 if (sc->sc_flags & PCN_F_HAS_MII) { 1838 /* Stop the one second clock. */ 1839 callout_stop(&sc->sc_tick_ch); 1840 1841 /* Down the MII. */ 1842 mii_down(&sc->sc_mii); 1843 } 1844 1845 /* Stop the chip. */ 1846 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1847 1848 /* Release any queued transmit buffers. */ 1849 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1850 txs = &sc->sc_txsoft[i]; 1851 if (txs->txs_mbuf != NULL) { 1852 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1853 m_freem(txs->txs_mbuf); 1854 txs->txs_mbuf = NULL; 1855 } 1856 } 1857 1858 /* Mark the interface as down and cancel the watchdog timer. */ 1859 ifp->if_flags &= ~IFF_RUNNING; 1860 ifp->if_timer = 0; 1861 1862 if (disable) 1863 pcn_rxdrain(sc); 1864 } 1865 1866 /* 1867 * pcn_add_rxbuf: 1868 * 1869 * Add a receive buffer to the indicated descriptor. 1870 */ 1871 static int 1872 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1873 { 1874 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1875 struct mbuf *m; 1876 int error; 1877 1878 MGETHDR(m, M_DONTWAIT, MT_DATA); 1879 if (m == NULL) 1880 return ENOBUFS; 1881 1882 MCLGET(m, M_DONTWAIT); 1883 if ((m->m_flags & M_EXT) == 0) { 1884 m_freem(m); 1885 return ENOBUFS; 1886 } 1887 1888 if (rxs->rxs_mbuf != NULL) 1889 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1890 1891 rxs->rxs_mbuf = m; 1892 1893 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1894 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1895 BUS_DMA_READ | BUS_DMA_NOWAIT); 1896 if (error) { 1897 printf("%s: can't load rx DMA map %d, error = %d\n", 1898 device_xname(sc->sc_dev), idx, error); 1899 panic("pcn_add_rxbuf"); 1900 } 1901 1902 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1903 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1904 1905 PCN_INIT_RXDESC(sc, idx); 1906 1907 return 0; 1908 } 1909 1910 /* 1911 * pcn_set_filter: 1912 * 1913 * Set up the receive filter. 1914 */ 1915 static void 1916 pcn_set_filter(struct pcn_softc *sc) 1917 { 1918 struct ethercom *ec = &sc->sc_ethercom; 1919 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1920 struct ether_multi *enm; 1921 struct ether_multistep step; 1922 uint32_t crc; 1923 1924 /* 1925 * Set up the multicast address filter by passing all multicast 1926 * addresses through a CRC generator, and then using the high 1927 * order 6 bits as an index into the 64-bit logical address 1928 * filter. The high order bits select the word, while the rest 1929 * of the bits select the bit within the word. 1930 */ 1931 1932 if (ifp->if_flags & IFF_PROMISC) 1933 goto allmulti; 1934 1935 sc->sc_initblock.init_ladrf[0] = 1936 sc->sc_initblock.init_ladrf[1] = 1937 sc->sc_initblock.init_ladrf[2] = 1938 sc->sc_initblock.init_ladrf[3] = 0; 1939 1940 ETHER_LOCK(ec); 1941 ETHER_FIRST_MULTI(step, ec, enm); 1942 while (enm != NULL) { 1943 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1944 /* 1945 * We must listen to a range of multicast addresses. 1946 * For now, just accept all multicasts, rather than 1947 * trying to set only those filter bits needed to match 1948 * the range. (At this time, the only use of address 1949 * ranges is for IP multicast routing, for which the 1950 * range is big enough to require all bits set.) 1951 */ 1952 ETHER_UNLOCK(ec); 1953 goto allmulti; 1954 } 1955 1956 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1957 1958 /* Just want the 6 most significant bits. */ 1959 crc >>= 26; 1960 1961 /* Set the corresponding bit in the filter. */ 1962 sc->sc_initblock.init_ladrf[crc >> 4] |= 1963 htole16(1 << (crc & 0xf)); 1964 1965 ETHER_NEXT_MULTI(step, enm); 1966 } 1967 ETHER_UNLOCK(ec); 1968 1969 ifp->if_flags &= ~IFF_ALLMULTI; 1970 return; 1971 1972 allmulti: 1973 ifp->if_flags |= IFF_ALLMULTI; 1974 sc->sc_initblock.init_ladrf[0] = 1975 sc->sc_initblock.init_ladrf[1] = 1976 sc->sc_initblock.init_ladrf[2] = 1977 sc->sc_initblock.init_ladrf[3] = 0xffff; 1978 } 1979 1980 /* 1981 * pcn_79c970_mediainit: 1982 * 1983 * Initialize media for the Am79c970. 1984 */ 1985 static void 1986 pcn_79c970_mediainit(struct pcn_softc *sc) 1987 { 1988 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1989 struct mii_data * const mii = &sc->sc_mii; 1990 const char *sep = ""; 1991 1992 mii->mii_ifp = ifp; 1993 1994 ifmedia_init(&mii->mii_media, IFM_IMASK, pcn_79c970_mediachange, 1995 pcn_79c970_mediastatus); 1996 1997 #define ADD(str, m, d) \ 1998 do { \ 1999 aprint_normal("%s%s", sep, str); \ 2000 ifmedia_add(&mii->mii_media, IFM_ETHER | (m), (d), NULL); \ 2001 sep = ", "; \ 2002 } while (/*CONSTCOND*/0) 2003 2004 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2005 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2006 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2007 ADD("10base5-FDX", IFM_10_5 | IFM_FDX, PORTSEL_AUI); 2008 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2009 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2010 ADD("10baseT-FDX", IFM_10_T | IFM_FDX, PORTSEL_10T); 2011 ADD("auto", IFM_AUTO, 0); 2012 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2013 ADD("auto-FDX", IFM_AUTO | IFM_FDX, 0); 2014 aprint_normal("\n"); 2015 2016 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2017 } 2018 2019 /* 2020 * pcn_79c970_mediastatus: [ifmedia interface function] 2021 * 2022 * Get the current interface media status (Am79c970 version). 2023 */ 2024 static void 2025 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2026 { 2027 struct pcn_softc *sc = ifp->if_softc; 2028 2029 /* 2030 * The currently selected media is always the active media. 2031 * Note: We have no way to determine what media the AUTO 2032 * process picked. 2033 */ 2034 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2035 } 2036 2037 /* 2038 * pcn_79c970_mediachange: [ifmedia interface function] 2039 * 2040 * Set hardware to newly-selected media (Am79c970 version). 2041 */ 2042 static int 2043 pcn_79c970_mediachange(struct ifnet *ifp) 2044 { 2045 struct pcn_softc *sc = ifp->if_softc; 2046 uint32_t reg; 2047 2048 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2049 /* 2050 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2051 */ 2052 reg = pcn_bcr_read(sc, LE_BCR2); 2053 reg |= LE_B2_ASEL; 2054 pcn_bcr_write(sc, LE_BCR2, reg); 2055 } else { 2056 /* 2057 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2058 */ 2059 reg = pcn_bcr_read(sc, LE_BCR2); 2060 reg &= ~LE_B2_ASEL; 2061 pcn_bcr_write(sc, LE_BCR2, reg); 2062 2063 reg = pcn_csr_read(sc, LE_CSR15); 2064 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2065 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2066 pcn_csr_write(sc, LE_CSR15, reg); 2067 } 2068 2069 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2070 reg = LE_B9_FDEN; 2071 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2072 reg |= LE_B9_AUIFD; 2073 pcn_bcr_write(sc, LE_BCR9, reg); 2074 } else 2075 pcn_bcr_write(sc, LE_BCR9, 0); 2076 2077 return 0; 2078 } 2079 2080 /* 2081 * pcn_79c971_mediainit: 2082 * 2083 * Initialize media for the Am79c971. 2084 */ 2085 static void 2086 pcn_79c971_mediainit(struct pcn_softc *sc) 2087 { 2088 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2089 struct mii_data * const mii = &sc->sc_mii; 2090 2091 /* We have MII. */ 2092 sc->sc_flags |= PCN_F_HAS_MII; 2093 2094 /* 2095 * The built-in 10BASE-T interface is mapped to the MII 2096 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2097 * word that tells us which PHY to use. 2098 * This driver used to ignore all but the first PHY to 2099 * answer, but this code was removed to support multiple 2100 * external PHYs. As the default instance will be the first 2101 * one to answer, no harm is done by letting the possibly 2102 * non-connected internal PHY show up. 2103 */ 2104 2105 /* Initialize our media structures and probe the MII. */ 2106 mii->mii_ifp = ifp; 2107 mii->mii_readreg = pcn_mii_readreg; 2108 mii->mii_writereg = pcn_mii_writereg; 2109 mii->mii_statchg = pcn_mii_statchg; 2110 2111 sc->sc_ethercom.ec_mii = mii; 2112 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 2113 2114 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 2115 MII_OFFSET_ANY, 0); 2116 if (LIST_FIRST(&mii->mii_phys) == NULL) { 2117 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 2118 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 2119 } else 2120 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2121 } 2122 2123 /* 2124 * pcn_mii_readreg: [mii interface function] 2125 * 2126 * Read a PHY register on the MII. 2127 */ 2128 static int 2129 pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2130 { 2131 struct pcn_softc *sc = device_private(self); 2132 2133 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2134 *val = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2135 if (*val == 0xffff) 2136 return -1; 2137 2138 return 0; 2139 } 2140 2141 /* 2142 * pcn_mii_writereg: [mii interface function] 2143 * 2144 * Write a PHY register on the MII. 2145 */ 2146 static int 2147 pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2148 { 2149 struct pcn_softc *sc = device_private(self); 2150 2151 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2152 pcn_bcr_write(sc, LE_BCR34, val); 2153 2154 return 0; 2155 } 2156 2157 /* 2158 * pcn_mii_statchg: [mii interface function] 2159 * 2160 * Callback from MII layer when media changes. 2161 */ 2162 static void 2163 pcn_mii_statchg(struct ifnet *ifp) 2164 { 2165 struct pcn_softc *sc = ifp->if_softc; 2166 2167 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2168 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2169 else 2170 pcn_bcr_write(sc, LE_BCR9, 0); 2171 } 2172