1 /* $NetBSD: if_pcn.c,v 1.43 2008/01/20 11:28:12 jmmv Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.43 2008/01/20 11:28:12 jmmv Exp $"); 69 70 #include "bpfilter.h" 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/callout.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/ioctl.h> 81 #include <sys/errno.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #include <sys/bus.h> 101 #include <sys/intr.h> 102 #include <machine/endian.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/ic/am79900reg.h> 108 #include <dev/ic/lancereg.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/pci/if_pcnreg.h> 115 116 /* 117 * Transmit descriptor list size. This is arbitrary, but allocate 118 * enough descriptors for 128 pending transmissions, and 4 segments 119 * per packet. This MUST work out to a power of 2. 120 * 121 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 122 * 123 * So we play a little trick here. We give each packet up to 16 124 * DMA segments, but only allocate the max of 512 descriptors. The 125 * transmit logic can deal with this, we just are hoping to sneak by. 126 */ 127 #define PCN_NTXSEGS 16 128 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 129 130 #define PCN_TXQUEUELEN 128 131 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 132 #define PCN_NTXDESC 512 133 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 134 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 135 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 136 137 /* Tx interrupt every N + 1 packets. */ 138 #define PCN_TXINTR_MASK 7 139 140 /* 141 * Receive descriptor list size. We have one Rx buffer per incoming 142 * packet, so this logic is a little simpler. 143 */ 144 #define PCN_NRXDESC 128 145 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 146 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 147 148 /* 149 * Control structures are DMA'd to the PCnet chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct pcn_control_data { 154 /* The transmit descriptors. */ 155 struct letmd pcd_txdescs[PCN_NTXDESC]; 156 157 /* The receive descriptors. */ 158 struct lermd pcd_rxdescs[PCN_NRXDESC]; 159 160 /* The init block. */ 161 struct leinit pcd_initblock; 162 }; 163 164 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 165 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 166 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 167 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct pcn_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 }; 178 179 /* 180 * Software state for receive jobs. 181 */ 182 struct pcn_rxsoft { 183 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t rxs_dmamap; /* our DMA map */ 185 }; 186 187 /* 188 * Description of Rx FIFO watermarks for various revisions. 189 */ 190 static const char * const pcn_79c970_rcvfw[] = { 191 "16 bytes", 192 "64 bytes", 193 "128 bytes", 194 NULL, 195 }; 196 197 static const char * const pcn_79c971_rcvfw[] = { 198 "16 bytes", 199 "64 bytes", 200 "112 bytes", 201 NULL, 202 }; 203 204 /* 205 * Description of Tx start points for various revisions. 206 */ 207 static const char * const pcn_79c970_xmtsp[] = { 208 "8 bytes", 209 "64 bytes", 210 "128 bytes", 211 "248 bytes", 212 }; 213 214 static const char * const pcn_79c971_xmtsp[] = { 215 "20 bytes", 216 "64 bytes", 217 "128 bytes", 218 "248 bytes", 219 }; 220 221 static const char * const pcn_79c971_xmtsp_sram[] = { 222 "44 bytes", 223 "64 bytes", 224 "128 bytes", 225 "store-and-forward", 226 }; 227 228 /* 229 * Description of Tx FIFO watermarks for various revisions. 230 */ 231 static const char * const pcn_79c970_xmtfw[] = { 232 "16 bytes", 233 "64 bytes", 234 "128 bytes", 235 NULL, 236 }; 237 238 static const char * const pcn_79c971_xmtfw[] = { 239 "16 bytes", 240 "64 bytes", 241 "108 bytes", 242 NULL, 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct pcn_softc { 249 struct device sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* Ethernet common data */ 254 void *sc_sdhook; /* shutdown hook */ 255 256 /* Points to our media routines, etc. */ 257 const struct pcn_variant *sc_variant; 258 259 void *sc_ih; /* interrupt cookie */ 260 261 struct mii_data sc_mii; /* MII/media information */ 262 263 callout_t sc_tick_ch; /* tick callout */ 264 265 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 266 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 267 268 /* Software state for transmit and receive descriptors. */ 269 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 270 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 271 272 /* Control data structures */ 273 struct pcn_control_data *sc_control_data; 274 #define sc_txdescs sc_control_data->pcd_txdescs 275 #define sc_rxdescs sc_control_data->pcd_rxdescs 276 #define sc_initblock sc_control_data->pcd_initblock 277 278 #ifdef PCN_EVENT_COUNTERS 279 /* Event counters. */ 280 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 281 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 282 struct evcnt sc_ev_txintr; /* Tx interrupts */ 283 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 284 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 285 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 286 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 287 288 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 289 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 290 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 291 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 292 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 293 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 294 struct evcnt sc_ev_txcopy; /* Tx copies required */ 295 #endif /* PCN_EVENT_COUNTERS */ 296 297 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 298 int sc_rcvfw; 299 300 const char * const *sc_xmtsp_desc; /* Tx start point info */ 301 int sc_xmtsp; 302 303 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 304 int sc_xmtfw; 305 306 int sc_flags; /* misc. flags; see below */ 307 int sc_swstyle; /* the software style in use */ 308 309 int sc_txfree; /* number of free Tx descriptors */ 310 int sc_txnext; /* next ready Tx descriptor */ 311 312 int sc_txsfree; /* number of free Tx jobs */ 313 int sc_txsnext; /* next free Tx job */ 314 int sc_txsdirty; /* dirty Tx jobs */ 315 316 int sc_rxptr; /* next ready Rx descriptor/job */ 317 318 uint32_t sc_csr5; /* prototype CSR5 register */ 319 uint32_t sc_mode; /* prototype MODE register */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 /* sc_flags */ 327 #define PCN_F_HAS_MII 0x0001 /* has MII */ 328 329 #ifdef PCN_EVENT_COUNTERS 330 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 331 #else 332 #define PCN_EVCNT_INCR(ev) /* nothing */ 333 #endif 334 335 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 336 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 337 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 338 339 #define PCN_CDTXSYNC(sc, x, n, ops) \ 340 do { \ 341 int __x, __n; \ 342 \ 343 __x = (x); \ 344 __n = (n); \ 345 \ 346 /* If it will wrap around, sync to the end of the ring. */ \ 347 if ((__x + __n) > PCN_NTXDESC) { \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 350 (PCN_NTXDESC - __x), (ops)); \ 351 __n -= (PCN_NTXDESC - __x); \ 352 __x = 0; \ 353 } \ 354 \ 355 /* Now sync whatever is left. */ \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 358 } while (/*CONSTCOND*/0) 359 360 #define PCN_CDRXSYNC(sc, x, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 363 364 #define PCN_CDINITSYNC(sc, ops) \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 367 368 #define PCN_INIT_RXDESC(sc, x) \ 369 do { \ 370 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 371 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 372 struct mbuf *__m = __rxs->rxs_mbuf; \ 373 \ 374 /* \ 375 * Note: We scoot the packet forward 2 bytes in the buffer \ 376 * so that the payload after the Ethernet header is aligned \ 377 * to a 4-byte boundary. \ 378 */ \ 379 __m->m_data = __m->m_ext.ext_buf + 2; \ 380 \ 381 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 382 __rmd->rmd2 = \ 383 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 384 __rmd->rmd0 = 0; \ 385 } else { \ 386 __rmd->rmd2 = 0; \ 387 __rmd->rmd0 = \ 388 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 389 } \ 390 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 391 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 392 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 393 } while(/*CONSTCOND*/0) 394 395 static void pcn_start(struct ifnet *); 396 static void pcn_watchdog(struct ifnet *); 397 static int pcn_ioctl(struct ifnet *, u_long, void *); 398 static int pcn_init(struct ifnet *); 399 static void pcn_stop(struct ifnet *, int); 400 401 static void pcn_shutdown(void *); 402 403 static void pcn_reset(struct pcn_softc *); 404 static void pcn_rxdrain(struct pcn_softc *); 405 static int pcn_add_rxbuf(struct pcn_softc *, int); 406 static void pcn_tick(void *); 407 408 static void pcn_spnd(struct pcn_softc *); 409 410 static void pcn_set_filter(struct pcn_softc *); 411 412 static int pcn_intr(void *); 413 static void pcn_txintr(struct pcn_softc *); 414 static int pcn_rxintr(struct pcn_softc *); 415 416 static int pcn_mii_readreg(struct device *, int, int); 417 static void pcn_mii_writereg(struct device *, int, int, int); 418 static void pcn_mii_statchg(struct device *); 419 420 static void pcn_79c970_mediainit(struct pcn_softc *); 421 static int pcn_79c970_mediachange(struct ifnet *); 422 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 423 424 static void pcn_79c971_mediainit(struct pcn_softc *); 425 426 /* 427 * Description of a PCnet-PCI variant. Used to select media access 428 * method, mostly, and to print a nice description of the chip. 429 */ 430 static const struct pcn_variant { 431 const char *pcv_desc; 432 void (*pcv_mediainit)(struct pcn_softc *); 433 uint16_t pcv_chipid; 434 } pcn_variants[] = { 435 { "Am79c970 PCnet-PCI", 436 pcn_79c970_mediainit, 437 PARTID_Am79c970 }, 438 439 { "Am79c970A PCnet-PCI II", 440 pcn_79c970_mediainit, 441 PARTID_Am79c970A }, 442 443 { "Am79c971 PCnet-FAST", 444 pcn_79c971_mediainit, 445 PARTID_Am79c971 }, 446 447 { "Am79c972 PCnet-FAST+", 448 pcn_79c971_mediainit, 449 PARTID_Am79c972 }, 450 451 { "Am79c973 PCnet-FAST III", 452 pcn_79c971_mediainit, 453 PARTID_Am79c973 }, 454 455 { "Am79c975 PCnet-FAST III", 456 pcn_79c971_mediainit, 457 PARTID_Am79c975 }, 458 459 { "Unknown PCnet-PCI variant", 460 pcn_79c971_mediainit, 461 0 }, 462 }; 463 464 int pcn_copy_small = 0; 465 466 static int pcn_match(struct device *, struct cfdata *, void *); 467 static void pcn_attach(struct device *, struct device *, void *); 468 469 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 470 pcn_match, pcn_attach, NULL, NULL); 471 472 /* 473 * Routines to read and write the PCnet-PCI CSR/BCR space. 474 */ 475 476 static inline uint32_t 477 pcn_csr_read(struct pcn_softc *sc, int reg) 478 { 479 480 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 481 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 482 } 483 484 static inline void 485 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 486 { 487 488 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 489 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 490 } 491 492 static inline uint32_t 493 pcn_bcr_read(struct pcn_softc *sc, int reg) 494 { 495 496 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 497 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 498 } 499 500 static inline void 501 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 502 { 503 504 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 505 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 506 } 507 508 static bool 509 pcn_is_vmware(const char *enaddr) 510 { 511 512 /* 513 * VMware uses the OUI 00:0c:29 for auto-generated MAC 514 * addresses. 515 */ 516 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 517 return (TRUE); 518 519 /* 520 * VMware uses the OUI 00:50:56 for manually-set MAC 521 * addresses (and some auto-generated ones). 522 */ 523 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 524 return (TRUE); 525 526 return (FALSE); 527 } 528 529 static const struct pcn_variant * 530 pcn_lookup_variant(uint16_t chipid) 531 { 532 const struct pcn_variant *pcv; 533 534 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 535 if (chipid == pcv->pcv_chipid) 536 return (pcv); 537 } 538 539 /* 540 * This covers unknown chips, which we simply treat like 541 * a generic PCnet-FAST. 542 */ 543 return (pcv); 544 } 545 546 static int 547 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 548 { 549 struct pci_attach_args *pa = aux; 550 551 /* 552 * IBM Makes a PCI variant of this card which shows up as a 553 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 554 * this card is truly a pcn card, so we have a special case match for 555 * it 556 */ 557 558 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 559 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 560 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 561 return(1); 562 563 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 564 return (0); 565 566 switch (PCI_PRODUCT(pa->pa_id)) { 567 case PCI_PRODUCT_AMD_PCNET_PCI: 568 /* Beat if_le_pci.c */ 569 return (10); 570 } 571 572 return (0); 573 } 574 575 static void 576 pcn_attach(struct device *parent, struct device *self, void *aux) 577 { 578 struct pcn_softc *sc = (struct pcn_softc *) self; 579 struct pci_attach_args *pa = aux; 580 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 581 pci_chipset_tag_t pc = pa->pa_pc; 582 pci_intr_handle_t ih; 583 const char *intrstr = NULL; 584 bus_space_tag_t iot, memt; 585 bus_space_handle_t ioh, memh; 586 bus_dma_segment_t seg; 587 int ioh_valid, memh_valid; 588 int ntxsegs, i, rseg, error; 589 uint32_t chipid, reg; 590 uint8_t enaddr[ETHER_ADDR_LEN]; 591 prop_object_t obj; 592 bool is_vmware; 593 594 callout_init(&sc->sc_tick_ch, 0); 595 596 printf(": AMD PCnet-PCI Ethernet\n"); 597 598 /* 599 * Map the device. 600 */ 601 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 602 &iot, &ioh, NULL, NULL) == 0); 603 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 604 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 605 &memt, &memh, NULL, NULL) == 0); 606 607 if (memh_valid) { 608 sc->sc_st = memt; 609 sc->sc_sh = memh; 610 } else if (ioh_valid) { 611 sc->sc_st = iot; 612 sc->sc_sh = ioh; 613 } else { 614 printf("%s: unable to map device registers\n", 615 sc->sc_dev.dv_xname); 616 return; 617 } 618 619 sc->sc_dmat = pa->pa_dmat; 620 621 /* Make sure bus mastering is enabled. */ 622 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 623 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 624 PCI_COMMAND_MASTER_ENABLE); 625 626 /* power up chip */ 627 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 628 NULL)) && error != EOPNOTSUPP) { 629 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 630 error); 631 return; 632 } 633 634 /* 635 * Reset the chip to a known state. This also puts the 636 * chip into 32-bit mode. 637 */ 638 pcn_reset(sc); 639 640 /* 641 * On some systems with the chip is an on-board device, the 642 * EEPROM is not used. Handle this by reading the MAC address 643 * from the CSRs (assuming that boot firmware has written 644 * it there). 645 */ 646 obj = prop_dictionary_get(device_properties(&sc->sc_dev), 647 "am79c970-no-eeprom"); 648 if (prop_bool_true(obj)) { 649 for (i = 0; i < 3; i++) { 650 uint32_t val; 651 val = pcn_csr_read(sc, LE_CSR12 + i); 652 enaddr[2*i] = val & 0x0ff; 653 enaddr[2*i+1] = (val >> 8) & 0x0ff; 654 } 655 } else { 656 for (i = 0; i < ETHER_ADDR_LEN; i++) { 657 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 658 PCN32_APROM + i); 659 } 660 } 661 662 /* Check to see if this is a VMware emulated network interface. */ 663 is_vmware = pcn_is_vmware(enaddr); 664 665 /* 666 * Now that the device is mapped, attempt to figure out what 667 * kind of chip we have. Note that IDL has all 32 bits of 668 * the chip ID when we're in 32-bit mode. 669 */ 670 chipid = pcn_csr_read(sc, LE_CSR88); 671 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 672 673 printf("%s: %s rev %d, Ethernet address %s\n", 674 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 675 ether_sprintf(enaddr)); 676 677 /* 678 * VMware has a bug in its network interface emulation; we must 679 * limit the number of Tx segments. 680 */ 681 if (is_vmware) { 682 ntxsegs = PCN_NTXSEGS_VMWARE; 683 prop_dictionary_set_bool(device_properties(&sc->sc_dev), 684 "am79c970-vmware-tx-bug", TRUE); 685 aprint_verbose("%s: VMware Tx segment count bug detected\n", 686 sc->sc_dev.dv_xname); 687 } else { 688 ntxsegs = PCN_NTXSEGS; 689 } 690 691 /* 692 * Map and establish our interrupt. 693 */ 694 if (pci_intr_map(pa, &ih)) { 695 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 696 return; 697 } 698 intrstr = pci_intr_string(pc, ih); 699 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 700 if (sc->sc_ih == NULL) { 701 printf("%s: unable to establish interrupt", 702 sc->sc_dev.dv_xname); 703 if (intrstr != NULL) 704 printf(" at %s", intrstr); 705 printf("\n"); 706 return; 707 } 708 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 709 710 /* 711 * Allocate the control data structures, and create and load the 712 * DMA map for it. 713 */ 714 if ((error = bus_dmamem_alloc(sc->sc_dmat, 715 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 716 0)) != 0) { 717 printf("%s: unable to allocate control data, error = %d\n", 718 sc->sc_dev.dv_xname, error); 719 goto fail_0; 720 } 721 722 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 723 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 724 BUS_DMA_COHERENT)) != 0) { 725 printf("%s: unable to map control data, error = %d\n", 726 sc->sc_dev.dv_xname, error); 727 goto fail_1; 728 } 729 730 if ((error = bus_dmamap_create(sc->sc_dmat, 731 sizeof(struct pcn_control_data), 1, 732 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 733 printf("%s: unable to create control data DMA map, " 734 "error = %d\n", sc->sc_dev.dv_xname, error); 735 goto fail_2; 736 } 737 738 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 739 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 740 0)) != 0) { 741 printf("%s: unable to load control data DMA map, error = %d\n", 742 sc->sc_dev.dv_xname, error); 743 goto fail_3; 744 } 745 746 /* Create the transmit buffer DMA maps. */ 747 for (i = 0; i < PCN_TXQUEUELEN; i++) { 748 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 749 ntxsegs, MCLBYTES, 0, 0, 750 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 751 printf("%s: unable to create tx DMA map %d, " 752 "error = %d\n", sc->sc_dev.dv_xname, i, error); 753 goto fail_4; 754 } 755 } 756 757 /* Create the receive buffer DMA maps. */ 758 for (i = 0; i < PCN_NRXDESC; i++) { 759 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 760 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 761 printf("%s: unable to create rx DMA map %d, " 762 "error = %d\n", sc->sc_dev.dv_xname, i, error); 763 goto fail_5; 764 } 765 sc->sc_rxsoft[i].rxs_mbuf = NULL; 766 } 767 768 /* Initialize our media structures. */ 769 (*sc->sc_variant->pcv_mediainit)(sc); 770 771 /* 772 * Initialize FIFO watermark info. 773 */ 774 switch (sc->sc_variant->pcv_chipid) { 775 case PARTID_Am79c970: 776 case PARTID_Am79c970A: 777 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 778 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 779 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 780 break; 781 782 default: 783 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 784 /* 785 * Read BCR25 to determine how much SRAM is 786 * on the board. If > 0, then we the chip 787 * uses different Start Point thresholds. 788 * 789 * Note BCR25 and BCR26 are loaded from the 790 * EEPROM on RST, and unaffected by S_RESET, 791 * so we don't really have to worry about 792 * them except for this. 793 */ 794 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 795 if (reg != 0) 796 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 797 else 798 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 799 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 800 break; 801 } 802 803 /* 804 * Set up defaults -- see the tables above for what these 805 * values mean. 806 * 807 * XXX How should we tune RCVFW and XMTFW? 808 */ 809 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 810 sc->sc_xmtsp = 1; 811 sc->sc_xmtfw = 0; 812 813 ifp = &sc->sc_ethercom.ec_if; 814 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 815 ifp->if_softc = sc; 816 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 817 ifp->if_ioctl = pcn_ioctl; 818 ifp->if_start = pcn_start; 819 ifp->if_watchdog = pcn_watchdog; 820 ifp->if_init = pcn_init; 821 ifp->if_stop = pcn_stop; 822 IFQ_SET_READY(&ifp->if_snd); 823 824 /* Attach the interface. */ 825 if_attach(ifp); 826 ether_ifattach(ifp, enaddr); 827 #if NRND > 0 828 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 829 RND_TYPE_NET, 0); 830 #endif 831 832 #ifdef PCN_EVENT_COUNTERS 833 /* Attach event counters. */ 834 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 835 NULL, sc->sc_dev.dv_xname, "txsstall"); 836 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 837 NULL, sc->sc_dev.dv_xname, "txdstall"); 838 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 839 NULL, sc->sc_dev.dv_xname, "txintr"); 840 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 841 NULL, sc->sc_dev.dv_xname, "rxintr"); 842 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 843 NULL, sc->sc_dev.dv_xname, "babl"); 844 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 845 NULL, sc->sc_dev.dv_xname, "miss"); 846 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 847 NULL, sc->sc_dev.dv_xname, "merr"); 848 849 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 850 NULL, sc->sc_dev.dv_xname, "txseg1"); 851 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 852 NULL, sc->sc_dev.dv_xname, "txseg2"); 853 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 854 NULL, sc->sc_dev.dv_xname, "txseg3"); 855 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 856 NULL, sc->sc_dev.dv_xname, "txseg4"); 857 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 858 NULL, sc->sc_dev.dv_xname, "txseg5"); 859 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 860 NULL, sc->sc_dev.dv_xname, "txsegmore"); 861 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 862 NULL, sc->sc_dev.dv_xname, "txcopy"); 863 #endif /* PCN_EVENT_COUNTERS */ 864 865 /* Make sure the interface is shutdown during reboot. */ 866 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 867 if (sc->sc_sdhook == NULL) 868 printf("%s: WARNING: unable to establish shutdown hook\n", 869 sc->sc_dev.dv_xname); 870 return; 871 872 /* 873 * Free any resources we've allocated during the failed attach 874 * attempt. Do this in reverse order and fall through. 875 */ 876 fail_5: 877 for (i = 0; i < PCN_NRXDESC; i++) { 878 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 879 bus_dmamap_destroy(sc->sc_dmat, 880 sc->sc_rxsoft[i].rxs_dmamap); 881 } 882 fail_4: 883 for (i = 0; i < PCN_TXQUEUELEN; i++) { 884 if (sc->sc_txsoft[i].txs_dmamap != NULL) 885 bus_dmamap_destroy(sc->sc_dmat, 886 sc->sc_txsoft[i].txs_dmamap); 887 } 888 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 889 fail_3: 890 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 891 fail_2: 892 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 893 sizeof(struct pcn_control_data)); 894 fail_1: 895 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 896 fail_0: 897 return; 898 } 899 900 /* 901 * pcn_shutdown: 902 * 903 * Make sure the interface is stopped at reboot time. 904 */ 905 static void 906 pcn_shutdown(void *arg) 907 { 908 struct pcn_softc *sc = arg; 909 910 pcn_stop(&sc->sc_ethercom.ec_if, 1); 911 /* explicitly reset the chip for some onboard one with lazy firmware */ 912 pcn_reset(sc); 913 } 914 915 /* 916 * pcn_start: [ifnet interface function] 917 * 918 * Start packet transmission on the interface. 919 */ 920 static void 921 pcn_start(struct ifnet *ifp) 922 { 923 struct pcn_softc *sc = ifp->if_softc; 924 struct mbuf *m0, *m; 925 struct pcn_txsoft *txs; 926 bus_dmamap_t dmamap; 927 int error, nexttx, lasttx = -1, ofree, seg; 928 929 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 930 return; 931 932 /* 933 * Remember the previous number of free descriptors and 934 * the first descriptor we'll use. 935 */ 936 ofree = sc->sc_txfree; 937 938 /* 939 * Loop through the send queue, setting up transmit descriptors 940 * until we drain the queue, or use up all available transmit 941 * descriptors. 942 */ 943 for (;;) { 944 /* Grab a packet off the queue. */ 945 IFQ_POLL(&ifp->if_snd, m0); 946 if (m0 == NULL) 947 break; 948 m = NULL; 949 950 /* Get a work queue entry. */ 951 if (sc->sc_txsfree == 0) { 952 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 953 break; 954 } 955 956 txs = &sc->sc_txsoft[sc->sc_txsnext]; 957 dmamap = txs->txs_dmamap; 958 959 /* 960 * Load the DMA map. If this fails, the packet either 961 * didn't fit in the alloted number of segments, or we 962 * were short on resources. In this case, we'll copy 963 * and try again. 964 */ 965 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 966 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 967 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 968 MGETHDR(m, M_DONTWAIT, MT_DATA); 969 if (m == NULL) { 970 printf("%s: unable to allocate Tx mbuf\n", 971 sc->sc_dev.dv_xname); 972 break; 973 } 974 if (m0->m_pkthdr.len > MHLEN) { 975 MCLGET(m, M_DONTWAIT); 976 if ((m->m_flags & M_EXT) == 0) { 977 printf("%s: unable to allocate Tx " 978 "cluster\n", sc->sc_dev.dv_xname); 979 m_freem(m); 980 break; 981 } 982 } 983 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 984 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 985 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 986 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 987 if (error) { 988 printf("%s: unable to load Tx buffer, " 989 "error = %d\n", sc->sc_dev.dv_xname, error); 990 break; 991 } 992 } 993 994 /* 995 * Ensure we have enough descriptors free to describe 996 * the packet. Note, we always reserve one descriptor 997 * at the end of the ring as a termination point, to 998 * prevent wrap-around. 999 */ 1000 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1001 /* 1002 * Not enough free descriptors to transmit this 1003 * packet. We haven't committed anything yet, 1004 * so just unload the DMA map, put the packet 1005 * back on the queue, and punt. Notify the upper 1006 * layer that there are not more slots left. 1007 * 1008 * XXX We could allocate an mbuf and copy, but 1009 * XXX is it worth it? 1010 */ 1011 ifp->if_flags |= IFF_OACTIVE; 1012 bus_dmamap_unload(sc->sc_dmat, dmamap); 1013 if (m != NULL) 1014 m_freem(m); 1015 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1016 break; 1017 } 1018 1019 IFQ_DEQUEUE(&ifp->if_snd, m0); 1020 if (m != NULL) { 1021 m_freem(m0); 1022 m0 = m; 1023 } 1024 1025 /* 1026 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1027 */ 1028 1029 /* Sync the DMA map. */ 1030 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1031 BUS_DMASYNC_PREWRITE); 1032 1033 #ifdef PCN_EVENT_COUNTERS 1034 switch (dmamap->dm_nsegs) { 1035 case 1: 1036 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1037 break; 1038 case 2: 1039 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1040 break; 1041 case 3: 1042 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1043 break; 1044 case 4: 1045 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1046 break; 1047 case 5: 1048 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1049 break; 1050 default: 1051 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1052 break; 1053 } 1054 #endif /* PCN_EVENT_COUNTERS */ 1055 1056 /* 1057 * Initialize the transmit descriptors. 1058 */ 1059 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1060 for (nexttx = sc->sc_txnext, seg = 0; 1061 seg < dmamap->dm_nsegs; 1062 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1063 /* 1064 * If this is the first descriptor we're 1065 * enqueueing, don't set the OWN bit just 1066 * yet. That could cause a race condition. 1067 * We'll do it below. 1068 */ 1069 sc->sc_txdescs[nexttx].tmd0 = 0; 1070 sc->sc_txdescs[nexttx].tmd2 = 1071 htole32(dmamap->dm_segs[seg].ds_addr); 1072 sc->sc_txdescs[nexttx].tmd1 = 1073 htole32(LE_T1_ONES | 1074 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1075 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1076 LE_T1_BCNT_MASK)); 1077 lasttx = nexttx; 1078 } 1079 } else { 1080 for (nexttx = sc->sc_txnext, seg = 0; 1081 seg < dmamap->dm_nsegs; 1082 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1083 /* 1084 * If this is the first descriptor we're 1085 * enqueueing, don't set the OWN bit just 1086 * yet. That could cause a race condition. 1087 * We'll do it below. 1088 */ 1089 sc->sc_txdescs[nexttx].tmd0 = 1090 htole32(dmamap->dm_segs[seg].ds_addr); 1091 sc->sc_txdescs[nexttx].tmd2 = 0; 1092 sc->sc_txdescs[nexttx].tmd1 = 1093 htole32(LE_T1_ONES | 1094 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1095 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1096 LE_T1_BCNT_MASK)); 1097 lasttx = nexttx; 1098 } 1099 } 1100 1101 KASSERT(lasttx != -1); 1102 /* Interrupt on the packet, if appropriate. */ 1103 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1104 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1105 1106 /* Set `start of packet' and `end of packet' appropriately. */ 1107 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1108 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1109 htole32(LE_T1_OWN|LE_T1_STP); 1110 1111 /* Sync the descriptors we're using. */ 1112 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 1115 /* Kick the transmitter. */ 1116 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1117 1118 /* 1119 * Store a pointer to the packet so we can free it later, 1120 * and remember what txdirty will be once the packet is 1121 * done. 1122 */ 1123 txs->txs_mbuf = m0; 1124 txs->txs_firstdesc = sc->sc_txnext; 1125 txs->txs_lastdesc = lasttx; 1126 1127 /* Advance the tx pointer. */ 1128 sc->sc_txfree -= dmamap->dm_nsegs; 1129 sc->sc_txnext = nexttx; 1130 1131 sc->sc_txsfree--; 1132 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1133 1134 #if NBPFILTER > 0 1135 /* Pass the packet to any BPF listeners. */ 1136 if (ifp->if_bpf) 1137 bpf_mtap(ifp->if_bpf, m0); 1138 #endif /* NBPFILTER > 0 */ 1139 } 1140 1141 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1142 /* No more slots left; notify upper layer. */ 1143 ifp->if_flags |= IFF_OACTIVE; 1144 } 1145 1146 if (sc->sc_txfree != ofree) { 1147 /* Set a watchdog timer in case the chip flakes out. */ 1148 ifp->if_timer = 5; 1149 } 1150 } 1151 1152 /* 1153 * pcn_watchdog: [ifnet interface function] 1154 * 1155 * Watchdog timer handler. 1156 */ 1157 static void 1158 pcn_watchdog(struct ifnet *ifp) 1159 { 1160 struct pcn_softc *sc = ifp->if_softc; 1161 1162 /* 1163 * Since we're not interrupting every packet, sweep 1164 * up before we report an error. 1165 */ 1166 pcn_txintr(sc); 1167 1168 if (sc->sc_txfree != PCN_NTXDESC) { 1169 printf("%s: device timeout (txfree %d txsfree %d)\n", 1170 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1171 ifp->if_oerrors++; 1172 1173 /* Reset the interface. */ 1174 (void) pcn_init(ifp); 1175 } 1176 1177 /* Try to get more packets going. */ 1178 pcn_start(ifp); 1179 } 1180 1181 /* 1182 * pcn_ioctl: [ifnet interface function] 1183 * 1184 * Handle control requests from the operator. 1185 */ 1186 static int 1187 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1188 { 1189 struct pcn_softc *sc = ifp->if_softc; 1190 struct ifreq *ifr = (struct ifreq *) data; 1191 int s, error; 1192 1193 s = splnet(); 1194 1195 switch (cmd) { 1196 case SIOCSIFMEDIA: 1197 case SIOCGIFMEDIA: 1198 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1199 break; 1200 1201 default: 1202 error = ether_ioctl(ifp, cmd, data); 1203 if (error == ENETRESET) { 1204 /* 1205 * Multicast list has changed; set the hardware filter 1206 * accordingly. 1207 */ 1208 if (ifp->if_flags & IFF_RUNNING) 1209 error = pcn_init(ifp); 1210 else 1211 error = 0; 1212 } 1213 break; 1214 } 1215 1216 /* Try to get more packets going. */ 1217 pcn_start(ifp); 1218 1219 splx(s); 1220 return (error); 1221 } 1222 1223 /* 1224 * pcn_intr: 1225 * 1226 * Interrupt service routine. 1227 */ 1228 static int 1229 pcn_intr(void *arg) 1230 { 1231 struct pcn_softc *sc = arg; 1232 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1233 uint32_t csr0; 1234 int wantinit, handled = 0; 1235 1236 for (wantinit = 0; wantinit == 0;) { 1237 csr0 = pcn_csr_read(sc, LE_CSR0); 1238 if ((csr0 & LE_C0_INTR) == 0) 1239 break; 1240 1241 #if NRND > 0 1242 if (RND_ENABLED(&sc->rnd_source)) 1243 rnd_add_uint32(&sc->rnd_source, csr0); 1244 #endif 1245 1246 /* ACK the bits and re-enable interrupts. */ 1247 pcn_csr_write(sc, LE_CSR0, csr0 & 1248 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1249 LE_C0_TINT|LE_C0_IDON)); 1250 1251 handled = 1; 1252 1253 if (csr0 & LE_C0_RINT) { 1254 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1255 wantinit = pcn_rxintr(sc); 1256 } 1257 1258 if (csr0 & LE_C0_TINT) { 1259 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1260 pcn_txintr(sc); 1261 } 1262 1263 if (csr0 & LE_C0_ERR) { 1264 if (csr0 & LE_C0_BABL) { 1265 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1266 ifp->if_oerrors++; 1267 } 1268 if (csr0 & LE_C0_MISS) { 1269 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1270 ifp->if_ierrors++; 1271 } 1272 if (csr0 & LE_C0_MERR) { 1273 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1274 printf("%s: memory error\n", 1275 sc->sc_dev.dv_xname); 1276 wantinit = 1; 1277 break; 1278 } 1279 } 1280 1281 if ((csr0 & LE_C0_RXON) == 0) { 1282 printf("%s: receiver disabled\n", 1283 sc->sc_dev.dv_xname); 1284 ifp->if_ierrors++; 1285 wantinit = 1; 1286 } 1287 1288 if ((csr0 & LE_C0_TXON) == 0) { 1289 printf("%s: transmitter disabled\n", 1290 sc->sc_dev.dv_xname); 1291 ifp->if_oerrors++; 1292 wantinit = 1; 1293 } 1294 } 1295 1296 if (handled) { 1297 if (wantinit) 1298 pcn_init(ifp); 1299 1300 /* Try to get more packets going. */ 1301 pcn_start(ifp); 1302 } 1303 1304 return (handled); 1305 } 1306 1307 /* 1308 * pcn_spnd: 1309 * 1310 * Suspend the chip. 1311 */ 1312 static void 1313 pcn_spnd(struct pcn_softc *sc) 1314 { 1315 int i; 1316 1317 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1318 1319 for (i = 0; i < 10000; i++) { 1320 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1321 return; 1322 delay(5); 1323 } 1324 1325 printf("%s: WARNING: chip failed to enter suspended state\n", 1326 sc->sc_dev.dv_xname); 1327 } 1328 1329 /* 1330 * pcn_txintr: 1331 * 1332 * Helper; handle transmit interrupts. 1333 */ 1334 static void 1335 pcn_txintr(struct pcn_softc *sc) 1336 { 1337 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1338 struct pcn_txsoft *txs; 1339 uint32_t tmd1, tmd2, tmd; 1340 int i, j; 1341 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 1344 /* 1345 * Go through our Tx list and free mbufs for those 1346 * frames which have been transmitted. 1347 */ 1348 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1349 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1350 txs = &sc->sc_txsoft[i]; 1351 1352 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1353 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1354 1355 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1356 if (tmd1 & LE_T1_OWN) 1357 break; 1358 1359 /* 1360 * Slightly annoying -- we have to loop through the 1361 * descriptors we've used looking for ERR, since it 1362 * can appear on any descriptor in the chain. 1363 */ 1364 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1365 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1366 if (tmd & LE_T1_ERR) { 1367 ifp->if_oerrors++; 1368 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1369 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1370 else 1371 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1372 if (tmd2 & LE_T2_UFLO) { 1373 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1374 sc->sc_xmtsp++; 1375 printf("%s: transmit " 1376 "underrun; new threshold: " 1377 "%s\n", 1378 sc->sc_dev.dv_xname, 1379 sc->sc_xmtsp_desc[ 1380 sc->sc_xmtsp]); 1381 pcn_spnd(sc); 1382 pcn_csr_write(sc, LE_CSR80, 1383 LE_C80_RCVFW(sc->sc_rcvfw) | 1384 LE_C80_XMTSP(sc->sc_xmtsp) | 1385 LE_C80_XMTFW(sc->sc_xmtfw)); 1386 pcn_csr_write(sc, LE_CSR5, 1387 sc->sc_csr5); 1388 } else { 1389 printf("%s: transmit " 1390 "underrun\n", 1391 sc->sc_dev.dv_xname); 1392 } 1393 } else if (tmd2 & LE_T2_BUFF) { 1394 printf("%s: transmit buffer error\n", 1395 sc->sc_dev.dv_xname); 1396 } 1397 if (tmd2 & LE_T2_LCOL) 1398 ifp->if_collisions++; 1399 if (tmd2 & LE_T2_RTRY) 1400 ifp->if_collisions += 16; 1401 goto next_packet; 1402 } 1403 if (j == txs->txs_lastdesc) 1404 break; 1405 } 1406 if (tmd1 & LE_T1_ONE) 1407 ifp->if_collisions++; 1408 else if (tmd & LE_T1_MORE) { 1409 /* Real number is unknown. */ 1410 ifp->if_collisions += 2; 1411 } 1412 ifp->if_opackets++; 1413 next_packet: 1414 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1415 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1416 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1417 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1418 m_freem(txs->txs_mbuf); 1419 txs->txs_mbuf = NULL; 1420 } 1421 1422 /* Update the dirty transmit buffer pointer. */ 1423 sc->sc_txsdirty = i; 1424 1425 /* 1426 * If there are no more pending transmissions, cancel the watchdog 1427 * timer. 1428 */ 1429 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1430 ifp->if_timer = 0; 1431 } 1432 1433 /* 1434 * pcn_rxintr: 1435 * 1436 * Helper; handle receive interrupts. 1437 */ 1438 static int 1439 pcn_rxintr(struct pcn_softc *sc) 1440 { 1441 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1442 struct pcn_rxsoft *rxs; 1443 struct mbuf *m; 1444 uint32_t rmd1; 1445 int i, len; 1446 1447 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1448 rxs = &sc->sc_rxsoft[i]; 1449 1450 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1451 1452 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1453 1454 if (rmd1 & LE_R1_OWN) 1455 break; 1456 1457 /* 1458 * Check for errors and make sure the packet fit into 1459 * a single buffer. We have structured this block of 1460 * code the way it is in order to compress it into 1461 * one test in the common case (no error). 1462 */ 1463 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1464 (LE_R1_STP|LE_R1_ENP))) { 1465 /* Make sure the packet is in a single buffer. */ 1466 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1467 (LE_R1_STP|LE_R1_ENP)) { 1468 printf("%s: packet spilled into next buffer\n", 1469 sc->sc_dev.dv_xname); 1470 return (1); /* pcn_intr() will re-init */ 1471 } 1472 1473 /* 1474 * If the packet had an error, simple recycle the 1475 * buffer. 1476 */ 1477 if (rmd1 & LE_R1_ERR) { 1478 ifp->if_ierrors++; 1479 /* 1480 * If we got an overflow error, chances 1481 * are there will be a CRC error. In 1482 * this case, just print the overflow 1483 * error, and skip the others. 1484 */ 1485 if (rmd1 & LE_R1_OFLO) 1486 printf("%s: overflow error\n", 1487 sc->sc_dev.dv_xname); 1488 else { 1489 #define PRINTIT(x, str) \ 1490 if (rmd1 & (x)) \ 1491 printf("%s: %s\n", \ 1492 sc->sc_dev.dv_xname, str); 1493 PRINTIT(LE_R1_FRAM, "framing error"); 1494 PRINTIT(LE_R1_CRC, "CRC error"); 1495 PRINTIT(LE_R1_BUFF, "buffer error"); 1496 } 1497 #undef PRINTIT 1498 PCN_INIT_RXDESC(sc, i); 1499 continue; 1500 } 1501 } 1502 1503 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1504 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1505 1506 /* 1507 * No errors; receive the packet. 1508 */ 1509 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1510 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1511 else 1512 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1513 1514 /* 1515 * The LANCE family includes the CRC with every packet; 1516 * trim it off here. 1517 */ 1518 len -= ETHER_CRC_LEN; 1519 1520 /* 1521 * If the packet is small enough to fit in a 1522 * single header mbuf, allocate one and copy 1523 * the data into it. This greatly reduces 1524 * memory consumption when we receive lots 1525 * of small packets. 1526 * 1527 * Otherwise, we add a new buffer to the receive 1528 * chain. If this fails, we drop the packet and 1529 * recycle the old buffer. 1530 */ 1531 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1532 MGETHDR(m, M_DONTWAIT, MT_DATA); 1533 if (m == NULL) 1534 goto dropit; 1535 m->m_data += 2; 1536 memcpy(mtod(m, void *), 1537 mtod(rxs->rxs_mbuf, void *), len); 1538 PCN_INIT_RXDESC(sc, i); 1539 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1540 rxs->rxs_dmamap->dm_mapsize, 1541 BUS_DMASYNC_PREREAD); 1542 } else { 1543 m = rxs->rxs_mbuf; 1544 if (pcn_add_rxbuf(sc, i) != 0) { 1545 dropit: 1546 ifp->if_ierrors++; 1547 PCN_INIT_RXDESC(sc, i); 1548 bus_dmamap_sync(sc->sc_dmat, 1549 rxs->rxs_dmamap, 0, 1550 rxs->rxs_dmamap->dm_mapsize, 1551 BUS_DMASYNC_PREREAD); 1552 continue; 1553 } 1554 } 1555 1556 m->m_pkthdr.rcvif = ifp; 1557 m->m_pkthdr.len = m->m_len = len; 1558 1559 #if NBPFILTER > 0 1560 /* Pass this up to any BPF listeners. */ 1561 if (ifp->if_bpf) 1562 bpf_mtap(ifp->if_bpf, m); 1563 #endif /* NBPFILTER > 0 */ 1564 1565 /* Pass it on. */ 1566 (*ifp->if_input)(ifp, m); 1567 ifp->if_ipackets++; 1568 } 1569 1570 /* Update the receive pointer. */ 1571 sc->sc_rxptr = i; 1572 return (0); 1573 } 1574 1575 /* 1576 * pcn_tick: 1577 * 1578 * One second timer, used to tick the MII. 1579 */ 1580 static void 1581 pcn_tick(void *arg) 1582 { 1583 struct pcn_softc *sc = arg; 1584 int s; 1585 1586 s = splnet(); 1587 mii_tick(&sc->sc_mii); 1588 splx(s); 1589 1590 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1591 } 1592 1593 /* 1594 * pcn_reset: 1595 * 1596 * Perform a soft reset on the PCnet-PCI. 1597 */ 1598 static void 1599 pcn_reset(struct pcn_softc *sc) 1600 { 1601 1602 /* 1603 * The PCnet-PCI chip is reset by reading from the 1604 * RESET register. Note that while the NE2100 LANCE 1605 * boards require a write after the read, the PCnet-PCI 1606 * chips do not require this. 1607 * 1608 * Since we don't know if we're in 16-bit or 32-bit 1609 * mode right now, issue both (it's safe) in the 1610 * hopes that one will succeed. 1611 */ 1612 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1613 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1614 1615 /* Wait 1ms for it to finish. */ 1616 delay(1000); 1617 1618 /* 1619 * Select 32-bit I/O mode by issuing a 32-bit write to the 1620 * RDP. Since the RAP is 0 after a reset, writing a 0 1621 * to RDP is safe (since it simply clears CSR0). 1622 */ 1623 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1624 } 1625 1626 /* 1627 * pcn_init: [ifnet interface function] 1628 * 1629 * Initialize the interface. Must be called at splnet(). 1630 */ 1631 static int 1632 pcn_init(struct ifnet *ifp) 1633 { 1634 struct pcn_softc *sc = ifp->if_softc; 1635 struct pcn_rxsoft *rxs; 1636 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1637 int i, error = 0; 1638 uint32_t reg; 1639 1640 /* Cancel any pending I/O. */ 1641 pcn_stop(ifp, 0); 1642 1643 /* Reset the chip to a known state. */ 1644 pcn_reset(sc); 1645 1646 /* 1647 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1648 * else. 1649 * 1650 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1651 * because the structure layout is compatible with ILACC, 1652 * but the burst mode is only available in SSTYLE 3, and 1653 * burst mode should provide some performance enhancement. 1654 */ 1655 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1656 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1657 else 1658 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1659 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1660 1661 /* Initialize the transmit descriptor ring. */ 1662 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1663 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1664 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1665 sc->sc_txfree = PCN_NTXDESC; 1666 sc->sc_txnext = 0; 1667 1668 /* Initialize the transmit job descriptors. */ 1669 for (i = 0; i < PCN_TXQUEUELEN; i++) 1670 sc->sc_txsoft[i].txs_mbuf = NULL; 1671 sc->sc_txsfree = PCN_TXQUEUELEN; 1672 sc->sc_txsnext = 0; 1673 sc->sc_txsdirty = 0; 1674 1675 /* 1676 * Initialize the receive descriptor and receive job 1677 * descriptor rings. 1678 */ 1679 for (i = 0; i < PCN_NRXDESC; i++) { 1680 rxs = &sc->sc_rxsoft[i]; 1681 if (rxs->rxs_mbuf == NULL) { 1682 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1683 printf("%s: unable to allocate or map rx " 1684 "buffer %d, error = %d\n", 1685 sc->sc_dev.dv_xname, i, error); 1686 /* 1687 * XXX Should attempt to run with fewer receive 1688 * XXX buffers instead of just failing. 1689 */ 1690 pcn_rxdrain(sc); 1691 goto out; 1692 } 1693 } else 1694 PCN_INIT_RXDESC(sc, i); 1695 } 1696 sc->sc_rxptr = 0; 1697 1698 /* Initialize MODE for the initialization block. */ 1699 sc->sc_mode = 0; 1700 if (ifp->if_flags & IFF_PROMISC) 1701 sc->sc_mode |= LE_C15_PROM; 1702 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1703 sc->sc_mode |= LE_C15_DRCVBC; 1704 1705 /* 1706 * If we have MII, simply select MII in the MODE register, 1707 * and clear ASEL. Otherwise, let ASEL stand (for now), 1708 * and leave PORTSEL alone (it is ignored with ASEL is set). 1709 */ 1710 if (sc->sc_flags & PCN_F_HAS_MII) { 1711 pcn_bcr_write(sc, LE_BCR2, 1712 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1713 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1714 1715 /* 1716 * Disable MII auto-negotiation. We handle that in 1717 * our own MII layer. 1718 */ 1719 pcn_bcr_write(sc, LE_BCR32, 1720 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1721 } 1722 1723 /* 1724 * Set the Tx and Rx descriptor ring addresses in the init 1725 * block, the TLEN and RLEN other fields of the init block 1726 * MODE register. 1727 */ 1728 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1729 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1730 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1731 ((ffs(PCN_NTXDESC) - 1) << 28) | 1732 ((ffs(PCN_NRXDESC) - 1) << 20)); 1733 1734 /* Set the station address in the init block. */ 1735 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1736 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1737 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1738 (enaddr[5] << 8)); 1739 1740 /* Set the multicast filter in the init block. */ 1741 pcn_set_filter(sc); 1742 1743 /* Initialize CSR3. */ 1744 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1745 1746 /* Initialize CSR4. */ 1747 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1748 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1749 1750 /* Initialize CSR5. */ 1751 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1752 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1753 1754 /* 1755 * If we have an Am79c971 or greater, initialize CSR7. 1756 * 1757 * XXX Might be nice to use the MII auto-poll interrupt someday. 1758 */ 1759 switch (sc->sc_variant->pcv_chipid) { 1760 case PARTID_Am79c970: 1761 case PARTID_Am79c970A: 1762 /* Not available on these chips. */ 1763 break; 1764 1765 default: 1766 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1767 break; 1768 } 1769 1770 /* 1771 * On the Am79c970A and greater, initialize BCR18 to 1772 * enable burst mode. 1773 * 1774 * Also enable the "no underflow" option on the Am79c971 and 1775 * higher, which prevents the chip from generating transmit 1776 * underflows, yet sill provides decent performance. Note if 1777 * chip is not connected to external SRAM, then we still have 1778 * to handle underflow errors (the NOUFLO bit is ignored in 1779 * that case). 1780 */ 1781 reg = pcn_bcr_read(sc, LE_BCR18); 1782 switch (sc->sc_variant->pcv_chipid) { 1783 case PARTID_Am79c970: 1784 break; 1785 1786 case PARTID_Am79c970A: 1787 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1788 break; 1789 1790 default: 1791 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1792 break; 1793 } 1794 pcn_bcr_write(sc, LE_BCR18, reg); 1795 1796 /* 1797 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1798 */ 1799 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1800 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1801 1802 /* 1803 * Send the init block to the chip, and wait for it 1804 * to be processed. 1805 */ 1806 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1807 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1808 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1809 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1810 delay(100); 1811 for (i = 0; i < 10000; i++) { 1812 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1813 break; 1814 delay(10); 1815 } 1816 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1817 if (i == 10000) { 1818 printf("%s: timeout processing init block\n", 1819 sc->sc_dev.dv_xname); 1820 error = EIO; 1821 goto out; 1822 } 1823 1824 /* Set the media. */ 1825 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1826 goto out; 1827 1828 /* Enable interrupts and external activity (and ACK IDON). */ 1829 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1830 1831 if (sc->sc_flags & PCN_F_HAS_MII) { 1832 /* Start the one second MII clock. */ 1833 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1834 } 1835 1836 /* ...all done! */ 1837 ifp->if_flags |= IFF_RUNNING; 1838 ifp->if_flags &= ~IFF_OACTIVE; 1839 1840 out: 1841 if (error) 1842 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1843 return (error); 1844 } 1845 1846 /* 1847 * pcn_rxdrain: 1848 * 1849 * Drain the receive queue. 1850 */ 1851 static void 1852 pcn_rxdrain(struct pcn_softc *sc) 1853 { 1854 struct pcn_rxsoft *rxs; 1855 int i; 1856 1857 for (i = 0; i < PCN_NRXDESC; i++) { 1858 rxs = &sc->sc_rxsoft[i]; 1859 if (rxs->rxs_mbuf != NULL) { 1860 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1861 m_freem(rxs->rxs_mbuf); 1862 rxs->rxs_mbuf = NULL; 1863 } 1864 } 1865 } 1866 1867 /* 1868 * pcn_stop: [ifnet interface function] 1869 * 1870 * Stop transmission on the interface. 1871 */ 1872 static void 1873 pcn_stop(struct ifnet *ifp, int disable) 1874 { 1875 struct pcn_softc *sc = ifp->if_softc; 1876 struct pcn_txsoft *txs; 1877 int i; 1878 1879 if (sc->sc_flags & PCN_F_HAS_MII) { 1880 /* Stop the one second clock. */ 1881 callout_stop(&sc->sc_tick_ch); 1882 1883 /* Down the MII. */ 1884 mii_down(&sc->sc_mii); 1885 } 1886 1887 /* Stop the chip. */ 1888 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1889 1890 /* Release any queued transmit buffers. */ 1891 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1892 txs = &sc->sc_txsoft[i]; 1893 if (txs->txs_mbuf != NULL) { 1894 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1895 m_freem(txs->txs_mbuf); 1896 txs->txs_mbuf = NULL; 1897 } 1898 } 1899 1900 if (disable) 1901 pcn_rxdrain(sc); 1902 1903 /* Mark the interface as down and cancel the watchdog timer. */ 1904 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1905 ifp->if_timer = 0; 1906 } 1907 1908 /* 1909 * pcn_add_rxbuf: 1910 * 1911 * Add a receive buffer to the indicated descriptor. 1912 */ 1913 static int 1914 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1915 { 1916 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1917 struct mbuf *m; 1918 int error; 1919 1920 MGETHDR(m, M_DONTWAIT, MT_DATA); 1921 if (m == NULL) 1922 return (ENOBUFS); 1923 1924 MCLGET(m, M_DONTWAIT); 1925 if ((m->m_flags & M_EXT) == 0) { 1926 m_freem(m); 1927 return (ENOBUFS); 1928 } 1929 1930 if (rxs->rxs_mbuf != NULL) 1931 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1932 1933 rxs->rxs_mbuf = m; 1934 1935 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1936 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1937 BUS_DMA_READ|BUS_DMA_NOWAIT); 1938 if (error) { 1939 printf("%s: can't load rx DMA map %d, error = %d\n", 1940 sc->sc_dev.dv_xname, idx, error); 1941 panic("pcn_add_rxbuf"); 1942 } 1943 1944 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1945 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1946 1947 PCN_INIT_RXDESC(sc, idx); 1948 1949 return (0); 1950 } 1951 1952 /* 1953 * pcn_set_filter: 1954 * 1955 * Set up the receive filter. 1956 */ 1957 static void 1958 pcn_set_filter(struct pcn_softc *sc) 1959 { 1960 struct ethercom *ec = &sc->sc_ethercom; 1961 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1962 struct ether_multi *enm; 1963 struct ether_multistep step; 1964 uint32_t crc; 1965 1966 /* 1967 * Set up the multicast address filter by passing all multicast 1968 * addresses through a CRC generator, and then using the high 1969 * order 6 bits as an index into the 64-bit logical address 1970 * filter. The high order bits select the word, while the rest 1971 * of the bits select the bit within the word. 1972 */ 1973 1974 if (ifp->if_flags & IFF_PROMISC) 1975 goto allmulti; 1976 1977 sc->sc_initblock.init_ladrf[0] = 1978 sc->sc_initblock.init_ladrf[1] = 1979 sc->sc_initblock.init_ladrf[2] = 1980 sc->sc_initblock.init_ladrf[3] = 0; 1981 1982 ETHER_FIRST_MULTI(step, ec, enm); 1983 while (enm != NULL) { 1984 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1985 /* 1986 * We must listen to a range of multicast addresses. 1987 * For now, just accept all multicasts, rather than 1988 * trying to set only those filter bits needed to match 1989 * the range. (At this time, the only use of address 1990 * ranges is for IP multicast routing, for which the 1991 * range is big enough to require all bits set.) 1992 */ 1993 goto allmulti; 1994 } 1995 1996 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1997 1998 /* Just want the 6 most significant bits. */ 1999 crc >>= 26; 2000 2001 /* Set the corresponding bit in the filter. */ 2002 sc->sc_initblock.init_ladrf[crc >> 4] |= 2003 htole16(1 << (crc & 0xf)); 2004 2005 ETHER_NEXT_MULTI(step, enm); 2006 } 2007 2008 ifp->if_flags &= ~IFF_ALLMULTI; 2009 return; 2010 2011 allmulti: 2012 ifp->if_flags |= IFF_ALLMULTI; 2013 sc->sc_initblock.init_ladrf[0] = 2014 sc->sc_initblock.init_ladrf[1] = 2015 sc->sc_initblock.init_ladrf[2] = 2016 sc->sc_initblock.init_ladrf[3] = 0xffff; 2017 } 2018 2019 /* 2020 * pcn_79c970_mediainit: 2021 * 2022 * Initialize media for the Am79c970. 2023 */ 2024 static void 2025 pcn_79c970_mediainit(struct pcn_softc *sc) 2026 { 2027 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2028 const char *sep = ""; 2029 2030 sc->sc_mii.mii_ifp = ifp; 2031 2032 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2033 pcn_79c970_mediastatus); 2034 2035 #define ADD(str, m, d) \ 2036 do { \ 2037 printf("%s%s", sep, str); \ 2038 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2039 sep = ", "; \ 2040 } while (/*CONSTCOND*/0) 2041 2042 printf("%s: ", sc->sc_dev.dv_xname); 2043 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2044 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2045 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2046 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2047 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2048 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2049 ADD("auto", IFM_AUTO, 0); 2050 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2051 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2052 printf("\n"); 2053 2054 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2055 } 2056 2057 /* 2058 * pcn_79c970_mediastatus: [ifmedia interface function] 2059 * 2060 * Get the current interface media status (Am79c970 version). 2061 */ 2062 static void 2063 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2064 { 2065 struct pcn_softc *sc = ifp->if_softc; 2066 2067 /* 2068 * The currently selected media is always the active media. 2069 * Note: We have no way to determine what media the AUTO 2070 * process picked. 2071 */ 2072 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2073 } 2074 2075 /* 2076 * pcn_79c970_mediachange: [ifmedia interface function] 2077 * 2078 * Set hardware to newly-selected media (Am79c970 version). 2079 */ 2080 static int 2081 pcn_79c970_mediachange(struct ifnet *ifp) 2082 { 2083 struct pcn_softc *sc = ifp->if_softc; 2084 uint32_t reg; 2085 2086 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2087 /* 2088 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2089 */ 2090 reg = pcn_bcr_read(sc, LE_BCR2); 2091 reg |= LE_B2_ASEL; 2092 pcn_bcr_write(sc, LE_BCR2, reg); 2093 } else { 2094 /* 2095 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2096 */ 2097 reg = pcn_bcr_read(sc, LE_BCR2); 2098 reg &= ~LE_B2_ASEL; 2099 pcn_bcr_write(sc, LE_BCR2, reg); 2100 2101 reg = pcn_csr_read(sc, LE_CSR15); 2102 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2103 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2104 pcn_csr_write(sc, LE_CSR15, reg); 2105 } 2106 2107 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2108 reg = LE_B9_FDEN; 2109 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2110 reg |= LE_B9_AUIFD; 2111 pcn_bcr_write(sc, LE_BCR9, reg); 2112 } else 2113 pcn_bcr_write(sc, LE_BCR9, 0); 2114 2115 return (0); 2116 } 2117 2118 /* 2119 * pcn_79c971_mediainit: 2120 * 2121 * Initialize media for the Am79c971. 2122 */ 2123 static void 2124 pcn_79c971_mediainit(struct pcn_softc *sc) 2125 { 2126 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2127 2128 /* We have MII. */ 2129 sc->sc_flags |= PCN_F_HAS_MII; 2130 2131 /* 2132 * The built-in 10BASE-T interface is mapped to the MII 2133 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2134 * word that tells us which PHY to use. 2135 * This driver used to ignore all but the first PHY to 2136 * answer, but this code was removed to support multiple 2137 * external PHYs. As the default instance will be the first 2138 * one to answer, no harm is done by letting the possibly 2139 * non-connected internal PHY show up. 2140 */ 2141 2142 /* Initialize our media structures and probe the MII. */ 2143 sc->sc_mii.mii_ifp = ifp; 2144 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2145 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2146 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2147 2148 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2149 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2150 ether_mediastatus); 2151 2152 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2153 MII_OFFSET_ANY, 0); 2154 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2155 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2156 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2157 } else 2158 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2159 } 2160 2161 /* 2162 * pcn_mii_readreg: [mii interface function] 2163 * 2164 * Read a PHY register on the MII. 2165 */ 2166 static int 2167 pcn_mii_readreg(struct device *self, int phy, int reg) 2168 { 2169 struct pcn_softc *sc = (void *) self; 2170 uint32_t rv; 2171 2172 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2173 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2174 if (rv == 0xffff) 2175 return (0); 2176 2177 return (rv); 2178 } 2179 2180 /* 2181 * pcn_mii_writereg: [mii interface function] 2182 * 2183 * Write a PHY register on the MII. 2184 */ 2185 static void 2186 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2187 { 2188 struct pcn_softc *sc = (void *) self; 2189 2190 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2191 pcn_bcr_write(sc, LE_BCR34, val); 2192 } 2193 2194 /* 2195 * pcn_mii_statchg: [mii interface function] 2196 * 2197 * Callback from MII layer when media changes. 2198 */ 2199 static void 2200 pcn_mii_statchg(struct device *self) 2201 { 2202 struct pcn_softc *sc = (void *) self; 2203 2204 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2205 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2206 else 2207 pcn_bcr_write(sc, LE_BCR9, 0); 2208 } 2209