1 /* $NetBSD: if_pcn.c,v 1.11 2002/09/04 01:36:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.11 2002/09/04 01:36:07 thorpej Exp $"); 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_ether.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 16 119 * DMA segments, but only allocate the max of 512 descriptors. The 120 * transmit logic can deal with this, we just are hoping to sneak by. 121 */ 122 #define PCN_NTXSEGS 16 123 124 #define PCN_TXQUEUELEN 128 125 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 126 #define PCN_NTXDESC 512 127 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 128 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 129 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 130 131 /* Tx interrupt every N + 1 packets. */ 132 #define PCN_TXINTR_MASK 7 133 134 /* 135 * Receive descriptor list size. We have one Rx buffer per incoming 136 * packet, so this logic is a little simpler. 137 */ 138 #define PCN_NRXDESC 128 139 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 140 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 141 142 /* 143 * Control structures are DMA'd to the PCnet chip. We allocate them in 144 * a single clump that maps to a single DMA segment to make several things 145 * easier. 146 */ 147 struct pcn_control_data { 148 /* The transmit descriptors. */ 149 struct letmd pcd_txdescs[PCN_NTXDESC]; 150 151 /* The receive descriptors. */ 152 struct lermd pcd_rxdescs[PCN_NRXDESC]; 153 154 /* The init block. */ 155 struct leinit pcd_initblock; 156 }; 157 158 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 159 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 160 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 161 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 162 163 /* 164 * Software state for transmit jobs. 165 */ 166 struct pcn_txsoft { 167 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 168 bus_dmamap_t txs_dmamap; /* our DMA map */ 169 int txs_firstdesc; /* first descriptor in packet */ 170 int txs_lastdesc; /* last descriptor in packet */ 171 }; 172 173 /* 174 * Software state for receive jobs. 175 */ 176 struct pcn_rxsoft { 177 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 178 bus_dmamap_t rxs_dmamap; /* our DMA map */ 179 }; 180 181 /* 182 * Description of Rx FIFO watermarks for various revisions. 183 */ 184 const char *pcn_79c970_rcvfw[] = { 185 "16 bytes", 186 "64 bytes", 187 "128 bytes", 188 NULL, 189 }; 190 191 const char *pcn_79c971_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "112 bytes", 195 NULL, 196 }; 197 198 /* 199 * Description of Tx start points for various revisions. 200 */ 201 const char *pcn_79c970_xmtsp[] = { 202 "8 bytes", 203 "64 bytes", 204 "128 bytes", 205 "248 bytes", 206 }; 207 208 const char *pcn_79c971_xmtsp[] = { 209 "20 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 const char *pcn_79c971_xmtsp_sram[] = { 216 "44 bytes", 217 "64 bytes", 218 "128 bytes", 219 "store-and-forward", 220 }; 221 222 /* 223 * Description of Tx FIFO watermarks for various revisions. 224 */ 225 const char *pcn_79c970_xmtfw[] = { 226 "16 bytes", 227 "64 bytes", 228 "128 bytes", 229 NULL, 230 }; 231 232 const char *pcn_79c971_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "108 bytes", 236 NULL, 237 }; 238 239 /* 240 * Software state per device. 241 */ 242 struct pcn_softc { 243 struct device sc_dev; /* generic device information */ 244 bus_space_tag_t sc_st; /* bus space tag */ 245 bus_space_handle_t sc_sh; /* bus space handle */ 246 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 247 struct ethercom sc_ethercom; /* Ethernet common data */ 248 void *sc_sdhook; /* shutdown hook */ 249 250 /* Points to our media routines, etc. */ 251 const struct pcn_variant *sc_variant; 252 253 void *sc_ih; /* interrupt cookie */ 254 255 struct mii_data sc_mii; /* MII/media information */ 256 257 struct callout sc_tick_ch; /* tick callout */ 258 259 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 260 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 261 262 /* Software state for transmit and receive descriptors. */ 263 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 264 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 265 266 /* Control data structures */ 267 struct pcn_control_data *sc_control_data; 268 #define sc_txdescs sc_control_data->pcd_txdescs 269 #define sc_rxdescs sc_control_data->pcd_rxdescs 270 #define sc_initblock sc_control_data->pcd_initblock 271 272 #ifdef PCN_EVENT_COUNTERS 273 /* Event counters. */ 274 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 275 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 276 struct evcnt sc_ev_txintr; /* Tx interrupts */ 277 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 278 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 279 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 280 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 281 282 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 283 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 284 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 285 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 286 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 287 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 288 struct evcnt sc_ev_txcopy; /* Tx copies required */ 289 #endif /* PCN_EVENT_COUNTERS */ 290 291 const char **sc_rcvfw_desc; /* Rx FIFO watermark info */ 292 int sc_rcvfw; 293 294 const char **sc_xmtsp_desc; /* Tx start point info */ 295 int sc_xmtsp; 296 297 const char **sc_xmtfw_desc; /* Tx FIFO watermark info */ 298 int sc_xmtfw; 299 300 int sc_flags; /* misc. flags; see below */ 301 int sc_swstyle; /* the software style in use */ 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 306 int sc_txsfree; /* number of free Tx jobs */ 307 int sc_txsnext; /* next free Tx job */ 308 int sc_txsdirty; /* dirty Tx jobs */ 309 310 int sc_rxptr; /* next ready Rx descriptor/job */ 311 312 uint32_t sc_csr5; /* prototype CSR5 register */ 313 uint32_t sc_mode; /* prototype MODE register */ 314 int sc_phyaddr; /* PHY address */ 315 }; 316 317 /* sc_flags */ 318 #define PCN_F_HAS_MII 0x0001 /* has MII */ 319 320 #ifdef PCN_EVENT_COUNTERS 321 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 322 #else 323 #define PCN_EVCNT_INCR(ev) /* nothing */ 324 #endif 325 326 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 327 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 328 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 329 330 #define PCN_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > PCN_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 341 (PCN_NTXDESC - __x), (ops)); \ 342 __n -= (PCN_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 349 } while (/*CONSTCOND*/0) 350 351 #define PCN_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 354 355 #define PCN_CDINITSYNC(sc, ops) \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 358 359 #define PCN_INIT_RXDESC(sc, x) \ 360 do { \ 361 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 362 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 363 struct mbuf *__m = __rxs->rxs_mbuf; \ 364 \ 365 /* \ 366 * Note: We scoot the packet forward 2 bytes in the buffer \ 367 * so that the payload after the Ethernet header is aligned \ 368 * to a 4-byte boundary. \ 369 */ \ 370 __m->m_data = __m->m_ext.ext_buf + 2; \ 371 \ 372 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 373 __rmd->rmd2 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 __rmd->rmd0 = 0; \ 376 } else { \ 377 __rmd->rmd2 = 0; \ 378 __rmd->rmd0 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 } \ 381 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 382 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 383 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 384 } while(/*CONSTCOND*/0) 385 386 void pcn_start(struct ifnet *); 387 void pcn_watchdog(struct ifnet *); 388 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 389 int pcn_init(struct ifnet *); 390 void pcn_stop(struct ifnet *, int); 391 392 void pcn_shutdown(void *); 393 394 void pcn_reset(struct pcn_softc *); 395 void pcn_rxdrain(struct pcn_softc *); 396 int pcn_add_rxbuf(struct pcn_softc *, int); 397 void pcn_tick(void *); 398 399 void pcn_spnd(struct pcn_softc *); 400 401 void pcn_set_filter(struct pcn_softc *); 402 403 int pcn_intr(void *); 404 void pcn_txintr(struct pcn_softc *); 405 int pcn_rxintr(struct pcn_softc *); 406 407 int pcn_mii_readreg(struct device *, int, int); 408 void pcn_mii_writereg(struct device *, int, int, int); 409 void pcn_mii_statchg(struct device *); 410 411 void pcn_79c970_mediainit(struct pcn_softc *); 412 int pcn_79c970_mediachange(struct ifnet *); 413 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 414 415 void pcn_79c971_mediainit(struct pcn_softc *); 416 int pcn_79c971_mediachange(struct ifnet *); 417 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 418 419 /* 420 * Description of a PCnet-PCI variant. Used to select media access 421 * method, mostly, and to print a nice description of the chip. 422 */ 423 const struct pcn_variant { 424 const char *pcv_desc; 425 void (*pcv_mediainit)(struct pcn_softc *); 426 uint16_t pcv_chipid; 427 } pcn_variants[] = { 428 { "Am79c970 PCnet-PCI", 429 pcn_79c970_mediainit, 430 PARTID_Am79c970 }, 431 432 { "Am79c970A PCnet-PCI II", 433 pcn_79c970_mediainit, 434 PARTID_Am79c970A }, 435 436 { "Am79c971 PCnet-FAST", 437 pcn_79c971_mediainit, 438 PARTID_Am79c971 }, 439 440 { "Am79c972 PCnet-FAST+", 441 pcn_79c971_mediainit, 442 PARTID_Am79c972 }, 443 444 { "Am79c973 PCnet-FAST III", 445 pcn_79c971_mediainit, 446 PARTID_Am79c973 }, 447 448 { "Am79c975 PCnet-FAST III", 449 pcn_79c971_mediainit, 450 PARTID_Am79c975 }, 451 452 { "Unknown PCnet-PCI variant", 453 pcn_79c971_mediainit, 454 0 }, 455 }; 456 457 int pcn_copy_small = 0; 458 459 int pcn_match(struct device *, struct cfdata *, void *); 460 void pcn_attach(struct device *, struct device *, void *); 461 462 struct cfattach pcn_ca = { 463 sizeof(struct pcn_softc), pcn_match, pcn_attach, 464 }; 465 466 /* 467 * Routines to read and write the PCnet-PCI CSR/BCR space. 468 */ 469 470 static __inline uint32_t 471 pcn_csr_read(struct pcn_softc *sc, int reg) 472 { 473 474 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 475 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 476 } 477 478 static __inline void 479 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 484 } 485 486 static __inline uint32_t 487 pcn_bcr_read(struct pcn_softc *sc, int reg) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 492 } 493 494 static __inline void 495 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 496 { 497 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 500 } 501 502 static const struct pcn_variant * 503 pcn_lookup_variant(uint16_t chipid) 504 { 505 const struct pcn_variant *pcv; 506 507 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 508 if (chipid == pcv->pcv_chipid) 509 return (pcv); 510 } 511 512 /* 513 * This covers unknown chips, which we simply treat like 514 * a generic PCnet-FAST. 515 */ 516 return (pcv); 517 } 518 519 int 520 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 521 { 522 struct pci_attach_args *pa = aux; 523 524 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 525 return (0); 526 527 switch (PCI_PRODUCT(pa->pa_id)) { 528 case PCI_PRODUCT_AMD_PCNET_PCI: 529 /* Beat if_le_pci.c */ 530 return (10); 531 } 532 533 return (0); 534 } 535 536 void 537 pcn_attach(struct device *parent, struct device *self, void *aux) 538 { 539 struct pcn_softc *sc = (struct pcn_softc *) self; 540 struct pci_attach_args *pa = aux; 541 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 542 pci_chipset_tag_t pc = pa->pa_pc; 543 pci_intr_handle_t ih; 544 const char *intrstr = NULL; 545 bus_space_tag_t iot, memt; 546 bus_space_handle_t ioh, memh; 547 bus_dma_segment_t seg; 548 int ioh_valid, memh_valid; 549 int i, rseg, error; 550 pcireg_t pmode; 551 uint32_t chipid, reg; 552 uint8_t enaddr[ETHER_ADDR_LEN]; 553 int pmreg; 554 555 callout_init(&sc->sc_tick_ch); 556 557 printf(": AMD PCnet-PCI Ethernet\n"); 558 559 /* 560 * Map the device. 561 */ 562 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 563 &iot, &ioh, NULL, NULL) == 0); 564 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 565 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 566 &memt, &memh, NULL, NULL) == 0); 567 568 if (memh_valid) { 569 sc->sc_st = memt; 570 sc->sc_sh = memh; 571 } else if (ioh_valid) { 572 sc->sc_st = iot; 573 sc->sc_sh = ioh; 574 } else { 575 printf("%s: unable to map device registers\n", 576 sc->sc_dev.dv_xname); 577 return; 578 } 579 580 sc->sc_dmat = pa->pa_dmat; 581 582 /* Make sure bus mastering is enabled. */ 583 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 584 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 585 PCI_COMMAND_MASTER_ENABLE); 586 587 /* Get it out of power save mode, if needed. */ 588 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 589 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 590 if (pmode == 3) { 591 /* 592 * The card has lost all configuration data in 593 * this state, so punt. 594 */ 595 printf("%s: unable to wake from power state D3\n", 596 sc->sc_dev.dv_xname); 597 return; 598 } 599 if (pmode != 0) { 600 printf("%s: waking up from power date D%d\n", 601 sc->sc_dev.dv_xname, pmode); 602 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 603 } 604 } 605 606 /* 607 * Reset the chip to a known state. This also puts the 608 * chip into 32-bit mode. 609 */ 610 pcn_reset(sc); 611 612 /* 613 * Read the Ethernet address from the EEPROM. 614 */ 615 for (i = 0; i < ETHER_ADDR_LEN; i++) 616 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 617 PCN32_APROM + i); 618 619 /* 620 * Now that the device is mapped, attempt to figure out what 621 * kind of chip we have. Note that IDL has all 32 bits of 622 * the chip ID when we're in 32-bit mode. 623 */ 624 chipid = pcn_csr_read(sc, LE_CSR88); 625 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 626 627 printf("%s: %s rev %d, Ethernet address %s\n", 628 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 629 ether_sprintf(enaddr)); 630 631 /* 632 * Map and establish our interrupt. 633 */ 634 if (pci_intr_map(pa, &ih)) { 635 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 intrstr = pci_intr_string(pc, ih); 639 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 640 if (sc->sc_ih == NULL) { 641 printf("%s: unable to establish interrupt", 642 sc->sc_dev.dv_xname); 643 if (intrstr != NULL) 644 printf(" at %s", intrstr); 645 printf("\n"); 646 return; 647 } 648 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 649 650 /* 651 * Allocate the control data structures, and create and load the 652 * DMA map for it. 653 */ 654 if ((error = bus_dmamem_alloc(sc->sc_dmat, 655 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 656 0)) != 0) { 657 printf("%s: unable to allocate control data, error = %d\n", 658 sc->sc_dev.dv_xname, error); 659 goto fail_0; 660 } 661 662 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 663 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 664 BUS_DMA_COHERENT)) != 0) { 665 printf("%s: unable to map control data, error = %d\n", 666 sc->sc_dev.dv_xname, error); 667 goto fail_1; 668 } 669 670 if ((error = bus_dmamap_create(sc->sc_dmat, 671 sizeof(struct pcn_control_data), 1, 672 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 673 printf("%s: unable to create control data DMA map, " 674 "error = %d\n", sc->sc_dev.dv_xname, error); 675 goto fail_2; 676 } 677 678 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 679 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 680 0)) != 0) { 681 printf("%s: unable to load control data DMA map, error = %d\n", 682 sc->sc_dev.dv_xname, error); 683 goto fail_3; 684 } 685 686 /* Create the transmit buffer DMA maps. */ 687 for (i = 0; i < PCN_TXQUEUELEN; i++) { 688 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 689 PCN_NTXSEGS, MCLBYTES, 0, 0, 690 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 691 printf("%s: unable to create tx DMA map %d, " 692 "error = %d\n", sc->sc_dev.dv_xname, i, error); 693 goto fail_4; 694 } 695 } 696 697 /* Create the receive buffer DMA maps. */ 698 for (i = 0; i < PCN_NRXDESC; i++) { 699 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 700 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 701 printf("%s: unable to create rx DMA map %d, " 702 "error = %d\n", sc->sc_dev.dv_xname, i, error); 703 goto fail_5; 704 } 705 sc->sc_rxsoft[i].rxs_mbuf = NULL; 706 } 707 708 /* Initialize our media structures. */ 709 (*sc->sc_variant->pcv_mediainit)(sc); 710 711 /* 712 * Initialize FIFO watermark info. 713 */ 714 switch (sc->sc_variant->pcv_chipid) { 715 case PARTID_Am79c970: 716 case PARTID_Am79c970A: 717 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 718 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 719 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 720 break; 721 722 default: 723 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 724 /* 725 * Read BCR25 to determine how much SRAM is 726 * on the board. If > 0, then we the chip 727 * uses different Start Point thresholds. 728 * 729 * Note BCR25 and BCR26 are loaded from the 730 * EEPROM on RST, and unaffected by S_RESET, 731 * so we don't really have to worry about 732 * them except for this. 733 */ 734 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 735 if (reg != 0) 736 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 737 else 738 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 739 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 740 break; 741 } 742 743 /* 744 * Set up defaults -- see the tables above for what these 745 * values mean. 746 * 747 * XXX How should we tune RCVFW and XMTFW? 748 */ 749 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 750 sc->sc_xmtsp = 1; 751 sc->sc_xmtfw = 0; 752 753 ifp = &sc->sc_ethercom.ec_if; 754 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 755 ifp->if_softc = sc; 756 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 757 ifp->if_ioctl = pcn_ioctl; 758 ifp->if_start = pcn_start; 759 ifp->if_watchdog = pcn_watchdog; 760 ifp->if_init = pcn_init; 761 ifp->if_stop = pcn_stop; 762 IFQ_SET_READY(&ifp->if_snd); 763 764 /* Attach the interface. */ 765 if_attach(ifp); 766 ether_ifattach(ifp, enaddr); 767 768 #ifdef PCN_EVENT_COUNTERS 769 /* Attach event counters. */ 770 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 771 NULL, sc->sc_dev.dv_xname, "txsstall"); 772 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 773 NULL, sc->sc_dev.dv_xname, "txdstall"); 774 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 775 NULL, sc->sc_dev.dv_xname, "txintr"); 776 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 777 NULL, sc->sc_dev.dv_xname, "rxintr"); 778 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 779 NULL, sc->sc_dev.dv_xname, "babl"); 780 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 781 NULL, sc->sc_dev.dv_xname, "miss"); 782 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 783 NULL, sc->sc_dev.dv_xname, "merr"); 784 785 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 786 NULL, sc->sc_dev.dv_xname, "txseg1"); 787 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 788 NULL, sc->sc_dev.dv_xname, "txseg2"); 789 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 790 NULL, sc->sc_dev.dv_xname, "txseg3"); 791 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 792 NULL, sc->sc_dev.dv_xname, "txseg4"); 793 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 794 NULL, sc->sc_dev.dv_xname, "txseg5"); 795 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 796 NULL, sc->sc_dev.dv_xname, "txsegmore"); 797 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 798 NULL, sc->sc_dev.dv_xname, "txcopy"); 799 #endif /* PCN_EVENT_COUNTERS */ 800 801 /* Make sure the interface is shutdown during reboot. */ 802 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 803 if (sc->sc_sdhook == NULL) 804 printf("%s: WARNING: unable to establish shutdown hook\n", 805 sc->sc_dev.dv_xname); 806 return; 807 808 /* 809 * Free any resources we've allocated during the failed attach 810 * attempt. Do this in reverse order and fall through. 811 */ 812 fail_5: 813 for (i = 0; i < PCN_NRXDESC; i++) { 814 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 815 bus_dmamap_destroy(sc->sc_dmat, 816 sc->sc_rxsoft[i].rxs_dmamap); 817 } 818 fail_4: 819 for (i = 0; i < PCN_TXQUEUELEN; i++) { 820 if (sc->sc_txsoft[i].txs_dmamap != NULL) 821 bus_dmamap_destroy(sc->sc_dmat, 822 sc->sc_txsoft[i].txs_dmamap); 823 } 824 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 825 fail_3: 826 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 827 fail_2: 828 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 829 sizeof(struct pcn_control_data)); 830 fail_1: 831 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 832 fail_0: 833 return; 834 } 835 836 /* 837 * pcn_shutdown: 838 * 839 * Make sure the interface is stopped at reboot time. 840 */ 841 void 842 pcn_shutdown(void *arg) 843 { 844 struct pcn_softc *sc = arg; 845 846 pcn_stop(&sc->sc_ethercom.ec_if, 1); 847 } 848 849 /* 850 * pcn_start: [ifnet interface function] 851 * 852 * Start packet transmission on the interface. 853 */ 854 void 855 pcn_start(struct ifnet *ifp) 856 { 857 struct pcn_softc *sc = ifp->if_softc; 858 struct mbuf *m0, *m; 859 struct pcn_txsoft *txs; 860 bus_dmamap_t dmamap; 861 int error, nexttx, lasttx, ofree, seg; 862 863 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 864 return; 865 866 /* 867 * Remember the previous number of free descriptors and 868 * the first descriptor we'll use. 869 */ 870 ofree = sc->sc_txfree; 871 872 /* 873 * Loop through the send queue, setting up transmit descriptors 874 * until we drain the queue, or use up all available transmit 875 * descriptors. 876 */ 877 for (;;) { 878 /* Grab a packet off the queue. */ 879 IFQ_POLL(&ifp->if_snd, m0); 880 if (m0 == NULL) 881 break; 882 m = NULL; 883 884 /* Get a work queue entry. */ 885 if (sc->sc_txsfree == 0) { 886 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 887 break; 888 } 889 890 txs = &sc->sc_txsoft[sc->sc_txsnext]; 891 dmamap = txs->txs_dmamap; 892 893 /* 894 * Load the DMA map. If this fails, the packet either 895 * didn't fit in the alloted number of segments, or we 896 * were short on resources. In this case, we'll copy 897 * and try again. 898 */ 899 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 900 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 901 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 902 MGETHDR(m, M_DONTWAIT, MT_DATA); 903 if (m == NULL) { 904 printf("%s: unable to allocate Tx mbuf\n", 905 sc->sc_dev.dv_xname); 906 break; 907 } 908 if (m0->m_pkthdr.len > MHLEN) { 909 MCLGET(m, M_DONTWAIT); 910 if ((m->m_flags & M_EXT) == 0) { 911 printf("%s: unable to allocate Tx " 912 "cluster\n", sc->sc_dev.dv_xname); 913 m_freem(m); 914 break; 915 } 916 } 917 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 918 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 919 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 920 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 921 if (error) { 922 printf("%s: unable to load Tx buffer, " 923 "error = %d\n", sc->sc_dev.dv_xname, error); 924 break; 925 } 926 } 927 928 /* 929 * Ensure we have enough descriptors free to describe 930 * the packet. Note, we always reserve one descriptor 931 * at the end of the ring as a termination point, to 932 * prevent wrap-around. 933 */ 934 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 935 /* 936 * Not enough free descriptors to transmit this 937 * packet. We haven't committed anything yet, 938 * so just unload the DMA map, put the packet 939 * back on the queue, and punt. Notify the upper 940 * layer that there are not more slots left. 941 * 942 * XXX We could allocate an mbuf and copy, but 943 * XXX is it worth it? 944 */ 945 ifp->if_flags |= IFF_OACTIVE; 946 bus_dmamap_unload(sc->sc_dmat, dmamap); 947 if (m != NULL) 948 m_freem(m); 949 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 950 break; 951 } 952 953 IFQ_DEQUEUE(&ifp->if_snd, m0); 954 if (m != NULL) { 955 m_freem(m0); 956 m0 = m; 957 } 958 959 /* 960 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 961 */ 962 963 /* Sync the DMA map. */ 964 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 965 BUS_DMASYNC_PREWRITE); 966 967 #ifdef PCN_EVENT_COUNTERS 968 switch (dmamap->dm_nsegs) { 969 case 1: 970 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 971 break; 972 case 2: 973 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 974 break; 975 case 3: 976 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 977 break; 978 case 4: 979 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 980 break; 981 case 5: 982 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 983 break; 984 default: 985 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 986 break; 987 } 988 #endif /* PCN_EVENT_COUNTERS */ 989 990 /* 991 * Initialize the transmit descriptors. 992 */ 993 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 994 for (nexttx = sc->sc_txnext, seg = 0; 995 seg < dmamap->dm_nsegs; 996 seg++, nexttx = PCN_NEXTTX(nexttx)) { 997 /* 998 * If this is the first descriptor we're 999 * enqueueing, don't set the OWN bit just 1000 * yet. That could cause a race condition. 1001 * We'll do it below. 1002 */ 1003 sc->sc_txdescs[nexttx].tmd0 = 0; 1004 sc->sc_txdescs[nexttx].tmd2 = 1005 htole32(dmamap->dm_segs[seg].ds_addr); 1006 sc->sc_txdescs[nexttx].tmd1 = 1007 htole32(LE_T1_ONES | 1008 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1009 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1010 LE_T1_BCNT_MASK)); 1011 lasttx = nexttx; 1012 } 1013 } else { 1014 for (nexttx = sc->sc_txnext, seg = 0; 1015 seg < dmamap->dm_nsegs; 1016 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1017 /* 1018 * If this is the first descriptor we're 1019 * enqueueing, don't set the OWN bit just 1020 * yet. That could cause a race condition. 1021 * We'll do it below. 1022 */ 1023 sc->sc_txdescs[nexttx].tmd0 = 1024 htole32(dmamap->dm_segs[seg].ds_addr); 1025 sc->sc_txdescs[nexttx].tmd2 = 0; 1026 sc->sc_txdescs[nexttx].tmd1 = 1027 htole32(LE_T1_ONES | 1028 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1029 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1030 LE_T1_BCNT_MASK)); 1031 lasttx = nexttx; 1032 } 1033 } 1034 1035 /* Interrupt on the packet, if appropriate. */ 1036 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1037 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1038 1039 /* Set `start of packet' and `end of packet' appropriately. */ 1040 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1041 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1042 htole32(LE_T1_OWN|LE_T1_STP); 1043 1044 /* Sync the descriptors we're using. */ 1045 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1046 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1047 1048 /* Kick the transmitter. */ 1049 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1050 1051 /* 1052 * Store a pointer to the packet so we can free it later, 1053 * and remember what txdirty will be once the packet is 1054 * done. 1055 */ 1056 txs->txs_mbuf = m0; 1057 txs->txs_firstdesc = sc->sc_txnext; 1058 txs->txs_lastdesc = lasttx; 1059 1060 /* Advance the tx pointer. */ 1061 sc->sc_txfree -= dmamap->dm_nsegs; 1062 sc->sc_txnext = nexttx; 1063 1064 sc->sc_txsfree--; 1065 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1066 1067 #if NBPFILTER > 0 1068 /* Pass the packet to any BPF listeners. */ 1069 if (ifp->if_bpf) 1070 bpf_mtap(ifp->if_bpf, m0); 1071 #endif /* NBPFILTER > 0 */ 1072 } 1073 1074 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1075 /* No more slots left; notify upper layer. */ 1076 ifp->if_flags |= IFF_OACTIVE; 1077 } 1078 1079 if (sc->sc_txfree != ofree) { 1080 /* Set a watchdog timer in case the chip flakes out. */ 1081 ifp->if_timer = 5; 1082 } 1083 } 1084 1085 /* 1086 * pcn_watchdog: [ifnet interface function] 1087 * 1088 * Watchdog timer handler. 1089 */ 1090 void 1091 pcn_watchdog(struct ifnet *ifp) 1092 { 1093 struct pcn_softc *sc = ifp->if_softc; 1094 1095 /* 1096 * Since we're not interrupting every packet, sweep 1097 * up before we report an error. 1098 */ 1099 pcn_txintr(sc); 1100 1101 if (sc->sc_txfree != PCN_NTXDESC) { 1102 printf("%s: device timeout (txfree %d txsfree %d)\n", 1103 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1104 ifp->if_oerrors++; 1105 1106 /* Reset the interface. */ 1107 (void) pcn_init(ifp); 1108 } 1109 1110 /* Try to get more packets going. */ 1111 pcn_start(ifp); 1112 } 1113 1114 /* 1115 * pcn_ioctl: [ifnet interface function] 1116 * 1117 * Handle control requests from the operator. 1118 */ 1119 int 1120 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1121 { 1122 struct pcn_softc *sc = ifp->if_softc; 1123 struct ifreq *ifr = (struct ifreq *) data; 1124 int s, error; 1125 1126 s = splnet(); 1127 1128 switch (cmd) { 1129 case SIOCSIFMEDIA: 1130 case SIOCGIFMEDIA: 1131 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1132 break; 1133 1134 default: 1135 error = ether_ioctl(ifp, cmd, data); 1136 if (error == ENETRESET) { 1137 /* 1138 * Multicast list has changed; set the hardware filter 1139 * accordingly. 1140 */ 1141 error = pcn_init(ifp); 1142 } 1143 break; 1144 } 1145 1146 /* Try to get more packets going. */ 1147 pcn_start(ifp); 1148 1149 splx(s); 1150 return (error); 1151 } 1152 1153 /* 1154 * pcn_intr: 1155 * 1156 * Interrupt service routine. 1157 */ 1158 int 1159 pcn_intr(void *arg) 1160 { 1161 struct pcn_softc *sc = arg; 1162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1163 uint32_t csr0; 1164 int wantinit, handled = 0; 1165 1166 for (wantinit = 0; wantinit == 0;) { 1167 csr0 = pcn_csr_read(sc, LE_CSR0); 1168 if ((csr0 & LE_C0_INTR) == 0) 1169 break; 1170 1171 /* ACK the bits and re-enable interrupts. */ 1172 pcn_csr_write(sc, LE_CSR0, csr0 & 1173 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1174 LE_C0_TINT|LE_C0_IDON)); 1175 1176 handled = 1; 1177 1178 if (csr0 & LE_C0_RINT) { 1179 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1180 wantinit = pcn_rxintr(sc); 1181 } 1182 1183 if (csr0 & LE_C0_TINT) { 1184 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1185 pcn_txintr(sc); 1186 } 1187 1188 if (csr0 & LE_C0_ERR) { 1189 if (csr0 & LE_C0_BABL) { 1190 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1191 ifp->if_oerrors++; 1192 } 1193 if (csr0 & LE_C0_MISS) { 1194 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1195 ifp->if_ierrors++; 1196 } 1197 if (csr0 & LE_C0_MERR) { 1198 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1199 printf("%s: memory error\n", 1200 sc->sc_dev.dv_xname); 1201 wantinit = 1; 1202 break; 1203 } 1204 } 1205 1206 if ((csr0 & LE_C0_RXON) == 0) { 1207 printf("%s: receiver disabled\n", 1208 sc->sc_dev.dv_xname); 1209 ifp->if_ierrors++; 1210 wantinit = 1; 1211 } 1212 1213 if ((csr0 & LE_C0_TXON) == 0) { 1214 printf("%s: transmitter disabled\n", 1215 sc->sc_dev.dv_xname); 1216 ifp->if_oerrors++; 1217 wantinit = 1; 1218 } 1219 } 1220 1221 if (handled) { 1222 if (wantinit) 1223 pcn_init(ifp); 1224 1225 /* Try to get more packets going. */ 1226 pcn_start(ifp); 1227 } 1228 1229 return (handled); 1230 } 1231 1232 /* 1233 * pcn_spnd: 1234 * 1235 * Suspend the chip. 1236 */ 1237 void 1238 pcn_spnd(struct pcn_softc *sc) 1239 { 1240 int i; 1241 1242 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1243 1244 for (i = 0; i < 10000; i++) { 1245 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1246 return; 1247 delay(5); 1248 } 1249 1250 printf("%s: WARNING: chip failed to enter suspended state\n", 1251 sc->sc_dev.dv_xname); 1252 } 1253 1254 /* 1255 * pcn_txintr: 1256 * 1257 * Helper; handle transmit interrupts. 1258 */ 1259 void 1260 pcn_txintr(struct pcn_softc *sc) 1261 { 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 struct pcn_txsoft *txs; 1264 uint32_t tmd1, tmd2, tmd; 1265 int i, j; 1266 1267 ifp->if_flags &= ~IFF_OACTIVE; 1268 1269 /* 1270 * Go through our Tx list and free mbufs for those 1271 * frames which have been transmitted. 1272 */ 1273 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1274 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1275 txs = &sc->sc_txsoft[i]; 1276 1277 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1278 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1279 1280 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1281 if (tmd1 & LE_T1_OWN) 1282 break; 1283 1284 /* 1285 * Slightly annoying -- we have to loop through the 1286 * descriptors we've used looking for ERR, since it 1287 * can appear on any descriptor in the chain. 1288 */ 1289 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1290 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1291 if (tmd & LE_T1_ERR) { 1292 ifp->if_oerrors++; 1293 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1294 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1295 else 1296 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1297 if (tmd2 & LE_T2_UFLO) { 1298 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1299 sc->sc_xmtsp++; 1300 printf("%s: transmit " 1301 "underrun; new threshold: " 1302 "%s\n", 1303 sc->sc_dev.dv_xname, 1304 sc->sc_xmtsp_desc[ 1305 sc->sc_xmtsp]); 1306 pcn_spnd(sc); 1307 pcn_csr_write(sc, LE_CSR80, 1308 LE_C80_RCVFW(sc->sc_rcvfw) | 1309 LE_C80_XMTSP(sc->sc_xmtsp) | 1310 LE_C80_XMTFW(sc->sc_xmtfw)); 1311 pcn_csr_write(sc, LE_CSR5, 1312 sc->sc_csr5); 1313 } else { 1314 printf("%s: transmit " 1315 "underrun\n", 1316 sc->sc_dev.dv_xname); 1317 } 1318 } else if (tmd2 & LE_T2_BUFF) { 1319 printf("%s: transmit buffer error\n", 1320 sc->sc_dev.dv_xname); 1321 } 1322 if (tmd2 & LE_T2_LCOL) 1323 ifp->if_collisions++; 1324 if (tmd2 & LE_T2_RTRY) 1325 ifp->if_collisions += 16; 1326 goto next_packet; 1327 } 1328 if (j == txs->txs_lastdesc) 1329 break; 1330 } 1331 if (tmd1 & LE_T1_ONE) 1332 ifp->if_collisions++; 1333 else if (tmd & LE_T1_MORE) { 1334 /* Real number is unknown. */ 1335 ifp->if_collisions += 2; 1336 } 1337 ifp->if_opackets++; 1338 next_packet: 1339 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1340 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1341 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1342 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1343 m_freem(txs->txs_mbuf); 1344 txs->txs_mbuf = NULL; 1345 } 1346 1347 /* Update the dirty transmit buffer pointer. */ 1348 sc->sc_txsdirty = i; 1349 1350 /* 1351 * If there are no more pending transmissions, cancel the watchdog 1352 * timer. 1353 */ 1354 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1355 ifp->if_timer = 0; 1356 } 1357 1358 /* 1359 * pcn_rxintr: 1360 * 1361 * Helper; handle receive interrupts. 1362 */ 1363 int 1364 pcn_rxintr(struct pcn_softc *sc) 1365 { 1366 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1367 struct pcn_rxsoft *rxs; 1368 struct mbuf *m; 1369 uint32_t rmd1; 1370 int i, len; 1371 1372 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1373 rxs = &sc->sc_rxsoft[i]; 1374 1375 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1376 1377 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1378 1379 if (rmd1 & LE_R1_OWN) 1380 break; 1381 1382 /* 1383 * Check for errors and make sure the packet fit into 1384 * a single buffer. We have structured this block of 1385 * code the way it is in order to compress it into 1386 * one test in the common case (no error). 1387 */ 1388 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1389 (LE_R1_STP|LE_R1_ENP))) { 1390 /* Make sure the packet is in a single buffer. */ 1391 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1392 (LE_R1_STP|LE_R1_ENP)) { 1393 printf("%s: packet spilled into next buffer\n", 1394 sc->sc_dev.dv_xname); 1395 return (1); /* pcn_intr() will re-init */ 1396 } 1397 1398 /* 1399 * If the packet had an error, simple recycle the 1400 * buffer. 1401 */ 1402 if (rmd1 & LE_R1_ERR) { 1403 ifp->if_ierrors++; 1404 /* 1405 * If we got an overflow error, chances 1406 * are there will be a CRC error. In 1407 * this case, just print the overflow 1408 * error, and skip the others. 1409 */ 1410 if (rmd1 & LE_R1_OFLO) 1411 printf("%s: overflow error\n", 1412 sc->sc_dev.dv_xname); 1413 else { 1414 #define PRINTIT(x, s) \ 1415 if (rmd1 & (x)) \ 1416 printf("%s: %s\n", \ 1417 sc->sc_dev.dv_xname, s); 1418 PRINTIT(LE_R1_FRAM, "framing error"); 1419 PRINTIT(LE_R1_CRC, "CRC error"); 1420 PRINTIT(LE_R1_BUFF, "buffer error"); 1421 } 1422 #undef PRINTIT 1423 PCN_INIT_RXDESC(sc, i); 1424 continue; 1425 } 1426 } 1427 1428 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1429 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1430 1431 /* 1432 * No errors; receive the packet. 1433 */ 1434 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1435 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1436 else 1437 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1438 1439 /* 1440 * The LANCE family includes the CRC with every packet; 1441 * trim it off here. 1442 */ 1443 len -= ETHER_CRC_LEN; 1444 1445 /* 1446 * If the packet is small enough to fit in a 1447 * single header mbuf, allocate one and copy 1448 * the data into it. This greatly reduces 1449 * memory consumption when we receive lots 1450 * of small packets. 1451 * 1452 * Otherwise, we add a new buffer to the receive 1453 * chain. If this fails, we drop the packet and 1454 * recycle the old buffer. 1455 */ 1456 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1457 MGETHDR(m, M_DONTWAIT, MT_DATA); 1458 if (m == NULL) 1459 goto dropit; 1460 m->m_data += 2; 1461 memcpy(mtod(m, caddr_t), 1462 mtod(rxs->rxs_mbuf, caddr_t), len); 1463 PCN_INIT_RXDESC(sc, i); 1464 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1465 rxs->rxs_dmamap->dm_mapsize, 1466 BUS_DMASYNC_PREREAD); 1467 } else { 1468 m = rxs->rxs_mbuf; 1469 if (pcn_add_rxbuf(sc, i) != 0) { 1470 dropit: 1471 ifp->if_ierrors++; 1472 PCN_INIT_RXDESC(sc, i); 1473 bus_dmamap_sync(sc->sc_dmat, 1474 rxs->rxs_dmamap, 0, 1475 rxs->rxs_dmamap->dm_mapsize, 1476 BUS_DMASYNC_PREREAD); 1477 continue; 1478 } 1479 } 1480 1481 m->m_pkthdr.rcvif = ifp; 1482 m->m_pkthdr.len = m->m_len = len; 1483 1484 #if NBPFILTER > 0 1485 /* Pass this up to any BPF listeners. */ 1486 if (ifp->if_bpf) 1487 bpf_mtap(ifp->if_bpf, m); 1488 #endif /* NBPFILTER > 0 */ 1489 1490 /* Pass it on. */ 1491 (*ifp->if_input)(ifp, m); 1492 ifp->if_ipackets++; 1493 } 1494 1495 /* Update the receive pointer. */ 1496 sc->sc_rxptr = i; 1497 return (0); 1498 } 1499 1500 /* 1501 * pcn_tick: 1502 * 1503 * One second timer, used to tick the MII. 1504 */ 1505 void 1506 pcn_tick(void *arg) 1507 { 1508 struct pcn_softc *sc = arg; 1509 int s; 1510 1511 s = splnet(); 1512 mii_tick(&sc->sc_mii); 1513 splx(s); 1514 1515 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1516 } 1517 1518 /* 1519 * pcn_reset: 1520 * 1521 * Perform a soft reset on the PCnet-PCI. 1522 */ 1523 void 1524 pcn_reset(struct pcn_softc *sc) 1525 { 1526 1527 /* 1528 * The PCnet-PCI chip is reset by reading from the 1529 * RESET register. Note that while the NE2100 LANCE 1530 * boards require a write after the read, the PCnet-PCI 1531 * chips do not require this. 1532 * 1533 * Since we don't know if we're in 16-bit or 32-bit 1534 * mode right now, issue both (it's safe) in the 1535 * hopes that one will succeed. 1536 */ 1537 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1538 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1539 1540 /* Wait 1ms for it to finish. */ 1541 delay(1000); 1542 1543 /* 1544 * Select 32-bit I/O mode by issuing a 32-bit write to the 1545 * RDP. Since the RAP is 0 after a reset, writing a 0 1546 * to RDP is safe (since it simply clears CSR0). 1547 */ 1548 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1549 } 1550 1551 /* 1552 * pcn_init: [ifnet interface function] 1553 * 1554 * Initialize the interface. Must be called at splnet(). 1555 */ 1556 int 1557 pcn_init(struct ifnet *ifp) 1558 { 1559 struct pcn_softc *sc = ifp->if_softc; 1560 struct pcn_rxsoft *rxs; 1561 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1562 int i, error = 0; 1563 uint32_t reg; 1564 1565 /* Cancel any pending I/O. */ 1566 pcn_stop(ifp, 0); 1567 1568 /* Reset the chip to a known state. */ 1569 pcn_reset(sc); 1570 1571 /* 1572 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1573 * else. 1574 * 1575 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1576 * because the structure layout is compatible with ILACC, 1577 * but the burst mode is only available in SSTYLE 3, and 1578 * burst mode should provide some performance enhancement. 1579 */ 1580 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1581 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1582 else 1583 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1584 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1585 1586 /* Initialize the transmit descriptor ring. */ 1587 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1588 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1589 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1590 sc->sc_txfree = PCN_NTXDESC; 1591 sc->sc_txnext = 0; 1592 1593 /* Initialize the transmit job descriptors. */ 1594 for (i = 0; i < PCN_TXQUEUELEN; i++) 1595 sc->sc_txsoft[i].txs_mbuf = NULL; 1596 sc->sc_txsfree = PCN_TXQUEUELEN; 1597 sc->sc_txsnext = 0; 1598 sc->sc_txsdirty = 0; 1599 1600 /* 1601 * Initialize the receive descriptor and receive job 1602 * descriptor rings. 1603 */ 1604 for (i = 0; i < PCN_NRXDESC; i++) { 1605 rxs = &sc->sc_rxsoft[i]; 1606 if (rxs->rxs_mbuf == NULL) { 1607 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1608 printf("%s: unable to allocate or map rx " 1609 "buffer %d, error = %d\n", 1610 sc->sc_dev.dv_xname, i, error); 1611 /* 1612 * XXX Should attempt to run with fewer receive 1613 * XXX buffers instead of just failing. 1614 */ 1615 pcn_rxdrain(sc); 1616 goto out; 1617 } 1618 } else 1619 PCN_INIT_RXDESC(sc, i); 1620 } 1621 sc->sc_rxptr = 0; 1622 1623 /* Initialize MODE for the initialization block. */ 1624 sc->sc_mode = 0; 1625 if (ifp->if_flags & IFF_PROMISC) 1626 sc->sc_mode |= LE_C15_PROM; 1627 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1628 sc->sc_mode |= LE_C15_DRCVBC; 1629 1630 /* 1631 * If we have MII, simply select MII in the MODE register, 1632 * and clear ASEL. Otherwise, let ASEL stand (for now), 1633 * and leave PORTSEL alone (it is ignored with ASEL is set). 1634 */ 1635 if (sc->sc_flags & PCN_F_HAS_MII) { 1636 pcn_bcr_write(sc, LE_BCR2, 1637 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1638 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1639 1640 /* 1641 * Disable MII auto-negotiation. We handle that in 1642 * our own MII layer. 1643 */ 1644 pcn_bcr_write(sc, LE_BCR32, 1645 pcn_csr_read(sc, LE_BCR32) | LE_B32_DANAS); 1646 } 1647 1648 /* 1649 * Set the Tx and Rx descriptor ring addresses in the init 1650 * block, the TLEN and RLEN other fields of the init block 1651 * MODE register. 1652 */ 1653 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1654 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1655 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1656 ((ffs(PCN_NTXDESC) - 1) << 28) | 1657 ((ffs(PCN_NRXDESC) - 1) << 20)); 1658 1659 /* Set the station address in the init block. */ 1660 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1661 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1662 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1663 (enaddr[5] << 8)); 1664 1665 /* Set the multicast filter in the init block. */ 1666 pcn_set_filter(sc); 1667 1668 /* Initialize CSR3. */ 1669 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1670 1671 /* Initialize CSR4. */ 1672 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1673 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1674 1675 /* Initialize CSR5. */ 1676 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1677 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1678 1679 /* 1680 * If we have an Am79c971 or greater, initialize CSR7. 1681 * 1682 * XXX Might be nice to use the MII auto-poll interrupt someday. 1683 */ 1684 switch (sc->sc_variant->pcv_chipid) { 1685 case PARTID_Am79c970: 1686 case PARTID_Am79c970A: 1687 /* Not available on these chips. */ 1688 break; 1689 1690 default: 1691 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1692 break; 1693 } 1694 1695 /* 1696 * On the Am79c970A and greater, initialize BCR18 to 1697 * enable burst mode. 1698 * 1699 * Also enable the "no underflow" option on the Am79c971 and 1700 * higher, which prevents the chip from generating transmit 1701 * underflows, yet sill provides decent performance. Note if 1702 * chip is not connected to external SRAM, then we still have 1703 * to handle underflow errors (the NOUFLO bit is ignored in 1704 * that case). 1705 */ 1706 reg = pcn_bcr_read(sc, LE_BCR18); 1707 switch (sc->sc_variant->pcv_chipid) { 1708 case PARTID_Am79c970: 1709 break; 1710 1711 case PARTID_Am79c970A: 1712 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1713 break; 1714 1715 default: 1716 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1717 break; 1718 } 1719 pcn_bcr_write(sc, LE_BCR18, reg); 1720 1721 /* 1722 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1723 */ 1724 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1725 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1726 1727 /* 1728 * Send the init block to the chip, and wait for it 1729 * to be processed. 1730 */ 1731 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1732 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1733 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1734 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1735 delay(100); 1736 for (i = 0; i < 10000; i++) { 1737 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1738 break; 1739 delay(10); 1740 } 1741 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1742 if (i == 10000) { 1743 printf("%s: timeout processing init block\n", 1744 sc->sc_dev.dv_xname); 1745 error = EIO; 1746 goto out; 1747 } 1748 1749 /* Set the media. */ 1750 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1751 1752 /* Enable interrupts and external activity (and ACK IDON). */ 1753 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1754 1755 if (sc->sc_flags & PCN_F_HAS_MII) { 1756 /* Start the one second MII clock. */ 1757 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1758 } 1759 1760 /* ...all done! */ 1761 ifp->if_flags |= IFF_RUNNING; 1762 ifp->if_flags &= ~IFF_OACTIVE; 1763 1764 out: 1765 if (error) 1766 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1767 return (error); 1768 } 1769 1770 /* 1771 * pcn_rxdrain: 1772 * 1773 * Drain the receive queue. 1774 */ 1775 void 1776 pcn_rxdrain(struct pcn_softc *sc) 1777 { 1778 struct pcn_rxsoft *rxs; 1779 int i; 1780 1781 for (i = 0; i < PCN_NRXDESC; i++) { 1782 rxs = &sc->sc_rxsoft[i]; 1783 if (rxs->rxs_mbuf != NULL) { 1784 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1785 m_freem(rxs->rxs_mbuf); 1786 rxs->rxs_mbuf = NULL; 1787 } 1788 } 1789 } 1790 1791 /* 1792 * pcn_stop: [ifnet interface function] 1793 * 1794 * Stop transmission on the interface. 1795 */ 1796 void 1797 pcn_stop(struct ifnet *ifp, int disable) 1798 { 1799 struct pcn_softc *sc = ifp->if_softc; 1800 struct pcn_txsoft *txs; 1801 int i; 1802 1803 if (sc->sc_flags & PCN_F_HAS_MII) { 1804 /* Stop the one second clock. */ 1805 callout_stop(&sc->sc_tick_ch); 1806 1807 /* Down the MII. */ 1808 mii_down(&sc->sc_mii); 1809 } 1810 1811 /* Stop the chip. */ 1812 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1813 1814 /* Release any queued transmit buffers. */ 1815 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1816 txs = &sc->sc_txsoft[i]; 1817 if (txs->txs_mbuf != NULL) { 1818 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1819 m_freem(txs->txs_mbuf); 1820 txs->txs_mbuf = NULL; 1821 } 1822 } 1823 1824 if (disable) 1825 pcn_rxdrain(sc); 1826 1827 /* Mark the interface as down and cancel the watchdog timer. */ 1828 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1829 ifp->if_timer = 0; 1830 } 1831 1832 /* 1833 * pcn_add_rxbuf: 1834 * 1835 * Add a receive buffer to the indicated descriptor. 1836 */ 1837 int 1838 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1839 { 1840 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1841 struct mbuf *m; 1842 int error; 1843 1844 MGETHDR(m, M_DONTWAIT, MT_DATA); 1845 if (m == NULL) 1846 return (ENOBUFS); 1847 1848 MCLGET(m, M_DONTWAIT); 1849 if ((m->m_flags & M_EXT) == 0) { 1850 m_freem(m); 1851 return (ENOBUFS); 1852 } 1853 1854 if (rxs->rxs_mbuf != NULL) 1855 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1856 1857 rxs->rxs_mbuf = m; 1858 1859 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1860 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1861 BUS_DMA_READ|BUS_DMA_NOWAIT); 1862 if (error) { 1863 printf("%s: can't load rx DMA map %d, error = %d\n", 1864 sc->sc_dev.dv_xname, idx, error); 1865 panic("pcn_add_rxbuf"); 1866 } 1867 1868 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1869 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1870 1871 PCN_INIT_RXDESC(sc, idx); 1872 1873 return (0); 1874 } 1875 1876 /* 1877 * pcn_set_filter: 1878 * 1879 * Set up the receive filter. 1880 */ 1881 void 1882 pcn_set_filter(struct pcn_softc *sc) 1883 { 1884 struct ethercom *ec = &sc->sc_ethercom; 1885 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1886 struct ether_multi *enm; 1887 struct ether_multistep step; 1888 uint32_t crc; 1889 1890 /* 1891 * Set up the multicast address filter by passing all multicast 1892 * addresses through a CRC generator, and then using the high 1893 * order 6 bits as an index into the 64-bit logical address 1894 * filter. The high order bits select the word, while the rest 1895 * of the bits select the bit within the word. 1896 */ 1897 1898 if (ifp->if_flags & IFF_PROMISC) 1899 goto allmulti; 1900 1901 sc->sc_initblock.init_ladrf[0] = 1902 sc->sc_initblock.init_ladrf[1] = 1903 sc->sc_initblock.init_ladrf[2] = 1904 sc->sc_initblock.init_ladrf[3] = 0; 1905 1906 ETHER_FIRST_MULTI(step, ec, enm); 1907 while (enm != NULL) { 1908 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1909 /* 1910 * We must listen to a range of multicast addresses. 1911 * For now, just accept all multicasts, rather than 1912 * trying to set only those filter bits needed to match 1913 * the range. (At this time, the only use of address 1914 * ranges is for IP multicast routing, for which the 1915 * range is big enough to require all bits set.) 1916 */ 1917 goto allmulti; 1918 } 1919 1920 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1921 1922 /* Just want the 6 most significant bits. */ 1923 crc >>= 26; 1924 1925 /* Set the corresponding bit in the filter. */ 1926 sc->sc_initblock.init_ladrf[crc >> 4] |= 1927 htole16(1 << (crc & 0xf)); 1928 1929 ETHER_NEXT_MULTI(step, enm); 1930 } 1931 1932 ifp->if_flags &= ~IFF_ALLMULTI; 1933 return; 1934 1935 allmulti: 1936 ifp->if_flags |= IFF_ALLMULTI; 1937 sc->sc_initblock.init_ladrf[0] = 1938 sc->sc_initblock.init_ladrf[1] = 1939 sc->sc_initblock.init_ladrf[2] = 1940 sc->sc_initblock.init_ladrf[3] = 0xffff; 1941 } 1942 1943 /* 1944 * pcn_79c970_mediainit: 1945 * 1946 * Initialize media for the Am79c970. 1947 */ 1948 void 1949 pcn_79c970_mediainit(struct pcn_softc *sc) 1950 { 1951 const char *sep = ""; 1952 1953 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c970_mediachange, 1954 pcn_79c970_mediastatus); 1955 1956 #define ADD(s, m, d) \ 1957 do { \ 1958 printf("%s%s", sep, s); \ 1959 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 1960 sep = ", "; \ 1961 } while (/*CONSTCOND*/0) 1962 1963 printf("%s: ", sc->sc_dev.dv_xname); 1964 ADD("10base5", IFM_10_5, PORTSEL_AUI); 1965 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1966 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 1967 ADD("10baseT", IFM_10_T, PORTSEL_10T); 1968 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1969 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 1970 ADD("auto", IFM_AUTO, 0); 1971 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1972 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 1973 printf("\n"); 1974 1975 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1976 } 1977 1978 /* 1979 * pcn_79c970_mediastatus: [ifmedia interface function] 1980 * 1981 * Get the current interface media status (Am79c970 version). 1982 */ 1983 void 1984 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1985 { 1986 struct pcn_softc *sc = ifp->if_softc; 1987 1988 /* 1989 * The currently selected media is always the active media. 1990 * Note: We have no way to determine what media the AUTO 1991 * process picked. 1992 */ 1993 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1994 } 1995 1996 /* 1997 * pcn_79c970_mediachange: [ifmedia interface function] 1998 * 1999 * Set hardware to newly-selected media (Am79c970 version). 2000 */ 2001 int 2002 pcn_79c970_mediachange(struct ifnet *ifp) 2003 { 2004 struct pcn_softc *sc = ifp->if_softc; 2005 uint32_t reg; 2006 2007 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2008 /* 2009 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2010 */ 2011 reg = pcn_bcr_read(sc, LE_BCR2); 2012 reg |= LE_B2_ASEL; 2013 pcn_bcr_write(sc, LE_BCR2, reg); 2014 } else { 2015 /* 2016 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2017 */ 2018 reg = pcn_bcr_read(sc, LE_BCR2); 2019 reg &= ~LE_B2_ASEL; 2020 pcn_bcr_write(sc, LE_BCR2, reg); 2021 2022 reg = pcn_csr_read(sc, LE_CSR15); 2023 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2024 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2025 pcn_csr_write(sc, LE_CSR15, reg); 2026 } 2027 2028 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2029 reg = LE_B9_FDEN; 2030 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2031 reg |= LE_B9_AUIFD; 2032 pcn_bcr_write(sc, LE_BCR9, reg); 2033 } else 2034 pcn_bcr_write(sc, LE_BCR0, 0); 2035 2036 return (0); 2037 } 2038 2039 /* 2040 * pcn_79c971_mediainit: 2041 * 2042 * Initialize media for the Am79c971. 2043 */ 2044 void 2045 pcn_79c971_mediainit(struct pcn_softc *sc) 2046 { 2047 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2048 2049 /* We have MII. */ 2050 sc->sc_flags |= PCN_F_HAS_MII; 2051 2052 /* 2053 * The built-in 10BASE-T interface is mapped to the MII 2054 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2055 * word that tells us which PHY to use. Since the 10BASE-T 2056 * interface is always at PHY 31, we make a note of the 2057 * first PHY that responds, and disallow any PHYs after 2058 * it. This is all handled in the MII read routine. 2059 */ 2060 sc->sc_phyaddr = -1; 2061 2062 /* Initialize our media structures and probe the MII. */ 2063 sc->sc_mii.mii_ifp = ifp; 2064 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2065 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2066 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2067 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2068 pcn_79c971_mediastatus); 2069 2070 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2071 MII_OFFSET_ANY, 0); 2072 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2073 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2074 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2075 } else 2076 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2077 } 2078 2079 /* 2080 * pcn_79c971_mediastatus: [ifmedia interface function] 2081 * 2082 * Get the current interface media status (Am79c971 version). 2083 */ 2084 void 2085 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2086 { 2087 struct pcn_softc *sc = ifp->if_softc; 2088 2089 mii_pollstat(&sc->sc_mii); 2090 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2091 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2092 } 2093 2094 /* 2095 * pcn_79c971_mediachange: [ifmedia interface function] 2096 * 2097 * Set hardware to newly-selected media (Am79c971 version). 2098 */ 2099 int 2100 pcn_79c971_mediachange(struct ifnet *ifp) 2101 { 2102 struct pcn_softc *sc = ifp->if_softc; 2103 2104 if (ifp->if_flags & IFF_UP) 2105 mii_mediachg(&sc->sc_mii); 2106 return (0); 2107 } 2108 2109 /* 2110 * pcn_mii_readreg: [mii interface function] 2111 * 2112 * Read a PHY register on the MII. 2113 */ 2114 int 2115 pcn_mii_readreg(struct device *self, int phy, int reg) 2116 { 2117 struct pcn_softc *sc = (void *) self; 2118 uint32_t rv; 2119 2120 if (sc->sc_phyaddr != -1 && phy != sc->sc_phyaddr) 2121 return (0); 2122 2123 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2124 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2125 if (rv == 0xffff) 2126 return (0); 2127 2128 if (sc->sc_phyaddr == -1) 2129 sc->sc_phyaddr = phy; 2130 2131 return (rv); 2132 } 2133 2134 /* 2135 * pcn_mii_writereg: [mii interface function] 2136 * 2137 * Write a PHY register on the MII. 2138 */ 2139 void 2140 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2141 { 2142 struct pcn_softc *sc = (void *) self; 2143 2144 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2145 pcn_bcr_write(sc, LE_BCR34, val); 2146 } 2147 2148 /* 2149 * pcn_mii_statchg: [mii interface function] 2150 * 2151 * Callback from MII layer when media changes. 2152 */ 2153 void 2154 pcn_mii_statchg(struct device *self) 2155 { 2156 struct pcn_softc *sc = (void *) self; 2157 2158 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2159 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2160 else 2161 pcn_bcr_write(sc, LE_BCR9, 0); 2162 } 2163