1 /* $NetBSD: if_pcn.c,v 1.5 2001/11/13 07:48:44 lukem Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.5 2001/11/13 07:48:44 lukem Exp $"); 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_ether.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 8 119 * DMA segments, but only allocate 4 DMA segments per packet. 120 * The transmit logic can deal with this, we just are hoping to 121 * sneak by. 122 */ 123 #define PCN_NTXSEGS 8 124 #define PCN_NTXSEGS_ALLOC 4 125 126 #define PCN_TXQUEUELEN 128 127 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 128 #define PCN_NTXDESC (PCN_TXQUEUELEN * PCN_NTXSEGS_ALLOC) 129 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 130 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 131 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 132 133 /* Tx interrupt every N + 1 packets. */ 134 #define PCN_TXINTR_MASK 7 135 136 /* 137 * Receive descriptor list size. We have one Rx buffer per incoming 138 * packet, so this logic is a little simpler. 139 */ 140 #define PCN_NRXDESC 128 141 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 142 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 143 144 /* 145 * Control structures are DMA'd to the PCnet chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct pcn_control_data { 150 /* The transmit descriptors. */ 151 struct letmd pcd_txdescs[PCN_NTXDESC]; 152 153 /* The receive descriptors. */ 154 struct lermd pcd_rxdescs[PCN_NRXDESC]; 155 156 /* The init block. */ 157 struct leinit pcd_initblock; 158 }; 159 160 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 161 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 162 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 163 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct pcn_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 }; 174 175 /* 176 * Software state for receive jobs. 177 */ 178 struct pcn_rxsoft { 179 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 180 bus_dmamap_t rxs_dmamap; /* our DMA map */ 181 }; 182 183 /* 184 * Description of Rx FIFO watermarks for various revisions. 185 */ 186 const char *pcn_79c970_rcvfw[] = { 187 "16 bytes", 188 "64 bytes", 189 "128 bytes", 190 NULL, 191 }; 192 193 const char *pcn_79c971_rcvfw[] = { 194 "16 bytes", 195 "64 bytes", 196 "112 bytes", 197 NULL, 198 }; 199 200 /* 201 * Description of Tx start points for various revisions. 202 */ 203 const char *pcn_79c970_xmtsp[] = { 204 "8 bytes", 205 "64 bytes", 206 "128 bytes", 207 "248 bytes", 208 }; 209 210 const char *pcn_79c971_xmtsp[] = { 211 "20 bytes", 212 "64 bytes", 213 "128 bytes", 214 "248 bytes", 215 }; 216 217 const char *pcn_79c971_xmtsp_sram[] = { 218 "44 bytes", 219 "64 bytes", 220 "128 bytes", 221 "store-and-forward", 222 }; 223 224 /* 225 * Description of Tx FIFO watermarks for various revisions. 226 */ 227 const char *pcn_79c970_xmtfw[] = { 228 "16 bytes", 229 "64 bytes", 230 "128 bytes", 231 NULL, 232 }; 233 234 const char *pcn_79c971_xmtfw[] = { 235 "16 bytes", 236 "64 bytes", 237 "108 bytes", 238 NULL, 239 }; 240 241 /* 242 * Software state per device. 243 */ 244 struct pcn_softc { 245 struct device sc_dev; /* generic device information */ 246 bus_space_tag_t sc_st; /* bus space tag */ 247 bus_space_handle_t sc_sh; /* bus space handle */ 248 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 249 struct ethercom sc_ethercom; /* Ethernet common data */ 250 void *sc_sdhook; /* shutdown hook */ 251 252 /* Points to our media routines, etc. */ 253 const struct pcn_variant *sc_variant; 254 255 void *sc_ih; /* interrupt cookie */ 256 257 struct mii_data sc_mii; /* MII/media information */ 258 259 struct callout sc_tick_ch; /* tick callout */ 260 261 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 262 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 263 264 /* Software state for transmit and receive descriptors. */ 265 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 266 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 267 268 /* Control data structures */ 269 struct pcn_control_data *sc_control_data; 270 #define sc_txdescs sc_control_data->pcd_txdescs 271 #define sc_rxdescs sc_control_data->pcd_rxdescs 272 #define sc_initblock sc_control_data->pcd_initblock 273 274 #ifdef PCN_EVENT_COUNTERS 275 /* Event counters. */ 276 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 277 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 278 struct evcnt sc_ev_txintr; /* Tx interrupts */ 279 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 280 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 281 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 282 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 283 284 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 285 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 286 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 287 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 288 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 289 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 290 struct evcnt sc_ev_txcopy; /* Tx copies required */ 291 #endif /* PCN_EVENT_COUNTERS */ 292 293 const char **sc_rcvfw_desc; /* Rx FIFO watermark info */ 294 int sc_rcvfw; 295 296 const char **sc_xmtsp_desc; /* Tx start point info */ 297 int sc_xmtsp; 298 299 const char **sc_xmtfw_desc; /* Tx FIFO watermark info */ 300 int sc_xmtfw; 301 302 int sc_flags; /* misc. flags; see below */ 303 int sc_swstyle; /* the software style in use */ 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 308 int sc_txsfree; /* number of free Tx jobs */ 309 int sc_txsnext; /* next free Tx job */ 310 int sc_txsdirty; /* dirty Tx jobs */ 311 312 int sc_rxptr; /* next ready Rx descriptor/job */ 313 314 uint32_t sc_csr5; /* prototype CSR5 register */ 315 uint32_t sc_mode; /* prototype MODE register */ 316 int sc_phyaddr; /* PHY address */ 317 }; 318 319 /* sc_flags */ 320 #define PCN_F_HAS_MII 0x0001 /* has MII */ 321 322 #ifdef PCN_EVENT_COUNTERS 323 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 324 #else 325 #define PCN_EVCNT_INCR(ev) /* nothing */ 326 #endif 327 328 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 329 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 330 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 331 332 #define PCN_CDTXSYNC(sc, x, n, ops) \ 333 do { \ 334 int __x, __n; \ 335 \ 336 __x = (x); \ 337 __n = (n); \ 338 \ 339 /* If it will wrap around, sync to the end of the ring. */ \ 340 if ((__x + __n) > PCN_NTXDESC) { \ 341 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 342 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 343 (PCN_NTXDESC - __x), (ops)); \ 344 __n -= (PCN_NTXDESC - __x); \ 345 __x = 0; \ 346 } \ 347 \ 348 /* Now sync whatever is left. */ \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 351 } while (/*CONSTCOND*/0) 352 353 #define PCN_CDRXSYNC(sc, x, ops) \ 354 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 355 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 356 357 #define PCN_CDINITSYNC(sc, ops) \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 360 361 #define PCN_INIT_RXDESC(sc, x) \ 362 do { \ 363 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 364 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 365 struct mbuf *__m = __rxs->rxs_mbuf; \ 366 \ 367 /* \ 368 * Note: We scoot the packet forward 2 bytes in the buffer \ 369 * so that the payload after the Ethernet header is aligned \ 370 * to a 4-byte boundary. \ 371 */ \ 372 __m->m_data = __m->m_ext.ext_buf + 2; \ 373 \ 374 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 375 __rmd->rmd2 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 __rmd->rmd0 = 0; \ 378 } else { \ 379 __rmd->rmd2 = 0; \ 380 __rmd->rmd0 = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 382 } \ 383 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 384 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 385 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 386 } while(/*CONSTCOND*/0) 387 388 void pcn_start(struct ifnet *); 389 void pcn_watchdog(struct ifnet *); 390 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 391 int pcn_init(struct ifnet *); 392 void pcn_stop(struct ifnet *, int); 393 394 void pcn_shutdown(void *); 395 396 void pcn_reset(struct pcn_softc *); 397 void pcn_rxdrain(struct pcn_softc *); 398 int pcn_add_rxbuf(struct pcn_softc *, int); 399 void pcn_tick(void *); 400 401 void pcn_spnd(struct pcn_softc *); 402 403 void pcn_set_filter(struct pcn_softc *); 404 405 int pcn_intr(void *); 406 void pcn_txintr(struct pcn_softc *); 407 int pcn_rxintr(struct pcn_softc *); 408 409 int pcn_mii_readreg(struct device *, int, int); 410 void pcn_mii_writereg(struct device *, int, int, int); 411 void pcn_mii_statchg(struct device *); 412 413 void pcn_79c970_mediainit(struct pcn_softc *); 414 int pcn_79c970_mediachange(struct ifnet *); 415 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 416 417 void pcn_79c971_mediainit(struct pcn_softc *); 418 int pcn_79c971_mediachange(struct ifnet *); 419 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 420 421 /* 422 * Description of a PCnet-PCI variant. Used to select media access 423 * method, mostly, and to print a nice description of the chip. 424 */ 425 const struct pcn_variant { 426 const char *pcv_desc; 427 void (*pcv_mediainit)(struct pcn_softc *); 428 uint16_t pcv_chipid; 429 } pcn_variants[] = { 430 { "Am79c970 PCnet-PCI", 431 pcn_79c970_mediainit, 432 PARTID_Am79c970 }, 433 434 { "Am79c970A PCnet-PCI II", 435 pcn_79c970_mediainit, 436 PARTID_Am79c970A }, 437 438 { "Am79c971 PCnet-FAST", 439 pcn_79c971_mediainit, 440 PARTID_Am79c971 }, 441 442 { "Am79c972 PCnet-FAST+", 443 pcn_79c971_mediainit, 444 PARTID_Am79c972 }, 445 446 { "Am79c973 PCnet-FAST III", 447 pcn_79c971_mediainit, 448 PARTID_Am79c973 }, 449 450 { "Am79c975 PCnet-FAST III", 451 pcn_79c971_mediainit, 452 PARTID_Am79c975 }, 453 454 { "Unknown PCnet-PCI variant", 455 pcn_79c971_mediainit, 456 0 }, 457 }; 458 459 int pcn_copy_small = 0; 460 461 int pcn_match(struct device *, struct cfdata *, void *); 462 void pcn_attach(struct device *, struct device *, void *); 463 464 struct cfattach pcn_ca = { 465 sizeof(struct pcn_softc), pcn_match, pcn_attach, 466 }; 467 468 /* 469 * Routines to read and write the PCnet-PCI CSR/BCR space. 470 */ 471 472 static __inline uint32_t 473 pcn_csr_read(struct pcn_softc *sc, int reg) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 478 } 479 480 static __inline void 481 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 486 } 487 488 static __inline uint32_t 489 pcn_bcr_read(struct pcn_softc *sc, int reg) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 494 } 495 496 static __inline void 497 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 498 { 499 500 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 501 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 502 } 503 504 static const struct pcn_variant * 505 pcn_lookup_variant(uint16_t chipid) 506 { 507 const struct pcn_variant *pcv; 508 509 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 510 if (chipid == pcv->pcv_chipid) 511 return (pcv); 512 } 513 514 /* 515 * This covers unknown chips, which we simply treat like 516 * a generic PCnet-FAST. 517 */ 518 return (pcv); 519 } 520 521 int 522 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 523 { 524 struct pci_attach_args *pa = aux; 525 526 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 527 return (0); 528 529 switch (PCI_PRODUCT(pa->pa_id)) { 530 case PCI_PRODUCT_AMD_PCNET_PCI: 531 /* Beat if_le_pci.c */ 532 return (10); 533 } 534 535 return (0); 536 } 537 538 void 539 pcn_attach(struct device *parent, struct device *self, void *aux) 540 { 541 struct pcn_softc *sc = (struct pcn_softc *) self; 542 struct pci_attach_args *pa = aux; 543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 544 pci_chipset_tag_t pc = pa->pa_pc; 545 pci_intr_handle_t ih; 546 const char *intrstr = NULL; 547 bus_space_tag_t iot; 548 bus_space_handle_t ioh; 549 bus_dma_segment_t seg; 550 int ioh_valid; 551 int i, rseg, error; 552 pcireg_t pmode; 553 uint32_t chipid, reg; 554 uint8_t enaddr[ETHER_ADDR_LEN]; 555 int pmreg; 556 557 callout_init(&sc->sc_tick_ch); 558 559 printf(": AMD PCnet-PCI Ethernet\n"); 560 561 /* 562 * Map the device. 563 */ 564 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 565 &iot, &ioh, NULL, NULL) == 0); 566 567 if (ioh_valid) { 568 sc->sc_st = iot; 569 sc->sc_sh = ioh; 570 } else { 571 printf("%s: unable to map device registers\n", 572 sc->sc_dev.dv_xname); 573 return; 574 } 575 576 sc->sc_dmat = pa->pa_dmat; 577 578 /* Make sure bus mastering is enabled. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 580 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 581 PCI_COMMAND_MASTER_ENABLE); 582 583 /* Get it out of power save mode, if needed. */ 584 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 585 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 586 if (pmode == 3) { 587 /* 588 * The card has lost all configuration data in 589 * this state, so punt. 590 */ 591 printf("%s: unable to wake from power state D3\n", 592 sc->sc_dev.dv_xname); 593 return; 594 } 595 if (pmode != 0) { 596 printf("%s: waking up from power date D%d\n", 597 sc->sc_dev.dv_xname, pmode); 598 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 599 } 600 } 601 602 /* 603 * Reset the chip to a known state. This also puts the 604 * chip into 32-bit mode. 605 */ 606 pcn_reset(sc); 607 608 /* 609 * Read the Ethernet address from the EEPROM. 610 */ 611 for (i = 0; i < ETHER_ADDR_LEN; i++) 612 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 613 PCN32_APROM + i); 614 615 /* 616 * Now that the device is mapped, attempt to figure out what 617 * kind of chip we have. Note that IDL has all 32 bits of 618 * the chip ID when we're in 32-bit mode. 619 */ 620 chipid = pcn_csr_read(sc, LE_CSR88); 621 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 622 623 printf("%s: %s rev %d, Ethernet address %s\n", 624 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 625 ether_sprintf(enaddr)); 626 627 /* 628 * Map and establish our interrupt. 629 */ 630 if (pci_intr_map(pa, &ih)) { 631 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 632 return; 633 } 634 intrstr = pci_intr_string(pc, ih); 635 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 636 if (sc->sc_ih == NULL) { 637 printf("%s: unable to establish interrupt", 638 sc->sc_dev.dv_xname); 639 if (intrstr != NULL) 640 printf(" at %s", intrstr); 641 printf("\n"); 642 return; 643 } 644 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 645 646 /* 647 * Allocate the control data structures, and create and load the 648 * DMA map for it. 649 */ 650 if ((error = bus_dmamem_alloc(sc->sc_dmat, 651 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 652 0)) != 0) { 653 printf("%s: unable to allocate control data, error = %d\n", 654 sc->sc_dev.dv_xname, error); 655 goto fail_0; 656 } 657 658 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 659 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 660 BUS_DMA_COHERENT)) != 0) { 661 printf("%s: unable to map control data, error = %d\n", 662 sc->sc_dev.dv_xname, error); 663 goto fail_1; 664 } 665 666 if ((error = bus_dmamap_create(sc->sc_dmat, 667 sizeof(struct pcn_control_data), 1, 668 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 669 printf("%s: unable to create control data DMA map, " 670 "error = %d\n", sc->sc_dev.dv_xname, error); 671 goto fail_2; 672 } 673 674 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 675 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 676 0)) != 0) { 677 printf("%s: unable to load control data DMA map, error = %d\n", 678 sc->sc_dev.dv_xname, error); 679 goto fail_3; 680 } 681 682 /* Create the transmit buffer DMA maps. */ 683 for (i = 0; i < PCN_TXQUEUELEN; i++) { 684 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 685 PCN_NTXSEGS, MCLBYTES, 0, 0, 686 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 687 printf("%s: unable to create tx DMA map %d, " 688 "error = %d\n", sc->sc_dev.dv_xname, i, error); 689 goto fail_4; 690 } 691 } 692 693 /* Create the receive buffer DMA maps. */ 694 for (i = 0; i < PCN_NRXDESC; i++) { 695 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 696 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 697 printf("%s: unable to create rx DMA map %d, " 698 "error = %d\n", sc->sc_dev.dv_xname, i, error); 699 goto fail_5; 700 } 701 sc->sc_rxsoft[i].rxs_mbuf = NULL; 702 } 703 704 /* Initialize our media structures. */ 705 (*sc->sc_variant->pcv_mediainit)(sc); 706 707 /* 708 * Initialize FIFO watermark info. 709 */ 710 switch (sc->sc_variant->pcv_chipid) { 711 case PARTID_Am79c970: 712 case PARTID_Am79c970A: 713 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 714 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 715 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 716 break; 717 718 default: 719 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 720 /* 721 * Read BCR25 to determine how much SRAM is 722 * on the board. If > 0, then we the chip 723 * uses different Start Point thresholds. 724 * 725 * Note BCR25 and BCR26 are loaded from the 726 * EEPROM on RST, and unaffected by S_RESET, 727 * so we don't really have to worry about 728 * them except for this. 729 */ 730 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 731 if (reg != 0) 732 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 733 else 734 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 735 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 736 break; 737 } 738 739 /* 740 * Set up defaults -- see the tables above for what these 741 * values mean. 742 * 743 * XXX How should we tune RCVFW and XMTFW? 744 */ 745 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 746 sc->sc_xmtsp = 1; 747 sc->sc_xmtfw = 0; 748 749 ifp = &sc->sc_ethercom.ec_if; 750 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 751 ifp->if_softc = sc; 752 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 753 ifp->if_ioctl = pcn_ioctl; 754 ifp->if_start = pcn_start; 755 ifp->if_watchdog = pcn_watchdog; 756 ifp->if_init = pcn_init; 757 ifp->if_stop = pcn_stop; 758 IFQ_SET_READY(&ifp->if_snd); 759 760 /* Attach the interface. */ 761 if_attach(ifp); 762 ether_ifattach(ifp, enaddr); 763 764 #ifdef PCN_EVENT_COUNTERS 765 /* Attach event counters. */ 766 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 767 NULL, sc->sc_dev.dv_xname, "txsstall"); 768 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 769 NULL, sc->sc_dev.dv_xname, "txdstall"); 770 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 771 NULL, sc->sc_dev.dv_xname, "txintr"); 772 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 773 NULL, sc->sc_dev.dv_xname, "rxintr"); 774 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 775 NULL, sc->sc_dev.dv_xname, "babl"); 776 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 777 NULL, sc->sc_dev.dv_xname, "miss"); 778 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 779 NULL, sc->sc_dev.dv_xname, "merr"); 780 781 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 782 NULL, sc->sc_dev.dv_xname, "txseg1"); 783 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 784 NULL, sc->sc_dev.dv_xname, "txseg2"); 785 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 786 NULL, sc->sc_dev.dv_xname, "txseg3"); 787 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 788 NULL, sc->sc_dev.dv_xname, "txseg4"); 789 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 790 NULL, sc->sc_dev.dv_xname, "txseg5"); 791 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 792 NULL, sc->sc_dev.dv_xname, "txsegmore"); 793 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 794 NULL, sc->sc_dev.dv_xname, "txcopy"); 795 #endif /* PCN_EVENT_COUNTERS */ 796 797 /* Make sure the interface is shutdown during reboot. */ 798 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 799 if (sc->sc_sdhook == NULL) 800 printf("%s: WARNING: unable to establish shutdown hook\n", 801 sc->sc_dev.dv_xname); 802 return; 803 804 /* 805 * Free any resources we've allocated during the failed attach 806 * attempt. Do this in reverse order and fall through. 807 */ 808 fail_5: 809 for (i = 0; i < PCN_NRXDESC; i++) { 810 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 811 bus_dmamap_destroy(sc->sc_dmat, 812 sc->sc_rxsoft[i].rxs_dmamap); 813 } 814 fail_4: 815 for (i = 0; i < PCN_TXQUEUELEN; i++) { 816 if (sc->sc_txsoft[i].txs_dmamap != NULL) 817 bus_dmamap_destroy(sc->sc_dmat, 818 sc->sc_txsoft[i].txs_dmamap); 819 } 820 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 821 fail_3: 822 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 823 fail_2: 824 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 825 sizeof(struct pcn_control_data)); 826 fail_1: 827 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 828 fail_0: 829 return; 830 } 831 832 /* 833 * pcn_shutdown: 834 * 835 * Make sure the interface is stopped at reboot time. 836 */ 837 void 838 pcn_shutdown(void *arg) 839 { 840 struct pcn_softc *sc = arg; 841 842 pcn_stop(&sc->sc_ethercom.ec_if, 1); 843 } 844 845 /* 846 * pcn_start: [ifnet interface function] 847 * 848 * Start packet transmission on the interface. 849 */ 850 void 851 pcn_start(struct ifnet *ifp) 852 { 853 struct pcn_softc *sc = ifp->if_softc; 854 struct mbuf *m0, *m; 855 struct pcn_txsoft *txs; 856 bus_dmamap_t dmamap; 857 int error, nexttx, lasttx, ofree, seg; 858 859 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 860 return; 861 862 /* 863 * Remember the previous number of free descriptors and 864 * the first descriptor we'll use. 865 */ 866 ofree = sc->sc_txfree; 867 868 /* 869 * Loop through the send queue, setting up transmit descriptors 870 * until we drain the queue, or use up all available transmit 871 * descriptors. 872 */ 873 for (;;) { 874 /* Grab a packet off the queue. */ 875 IFQ_POLL(&ifp->if_snd, m0); 876 if (m0 == NULL) 877 break; 878 m = NULL; 879 880 /* Get a work queue entry. */ 881 if (sc->sc_txsfree == 0) { 882 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 883 break; 884 } 885 886 txs = &sc->sc_txsoft[sc->sc_txsnext]; 887 dmamap = txs->txs_dmamap; 888 889 /* 890 * Load the DMA map. If this fails, the packet either 891 * didn't fit in the alloted number of segments, or we 892 * were short on resources. In this case, we'll copy 893 * and try again. 894 */ 895 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 896 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 897 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 898 MGETHDR(m, M_DONTWAIT, MT_DATA); 899 if (m == NULL) { 900 printf("%s: unable to allocate Tx mbuf\n", 901 sc->sc_dev.dv_xname); 902 break; 903 } 904 if (m0->m_pkthdr.len > MHLEN) { 905 MCLGET(m, M_DONTWAIT); 906 if ((m->m_flags & M_EXT) == 0) { 907 printf("%s: unable to allocate Tx " 908 "cluster\n", sc->sc_dev.dv_xname); 909 m_freem(m); 910 break; 911 } 912 } 913 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 914 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 915 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 916 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 917 if (error) { 918 printf("%s: unable to load Tx buffer, " 919 "error = %d\n", sc->sc_dev.dv_xname, error); 920 break; 921 } 922 } 923 924 /* 925 * Ensure we have enough descriptors free to describe 926 * the packet. Note, we always reserve one descriptor 927 * at the end of the ring as a termination point, to 928 * prevent wrap-around. 929 */ 930 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 931 /* 932 * Not enough free descriptors to transmit this 933 * packet. We haven't committed anything yet, 934 * so just unload the DMA map, put the packet 935 * back on the queue, and punt. Notify the upper 936 * layer that there are not more slots left. 937 * 938 * XXX We could allocate an mbuf and copy, but 939 * XXX is it worth it? 940 */ 941 ifp->if_flags |= IFF_OACTIVE; 942 bus_dmamap_unload(sc->sc_dmat, dmamap); 943 if (m != NULL) 944 m_freem(m); 945 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 946 break; 947 } 948 949 IFQ_DEQUEUE(&ifp->if_snd, m0); 950 if (m != NULL) { 951 m_freem(m0); 952 m0 = m; 953 } 954 955 /* 956 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 957 */ 958 959 /* Sync the DMA map. */ 960 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 961 BUS_DMASYNC_PREWRITE); 962 963 #ifdef PCN_EVENT_COUNTERS 964 switch (dmamap->dm_nsegs) { 965 case 1: 966 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 967 break; 968 case 2: 969 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 970 break; 971 case 3: 972 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 973 break; 974 case 4: 975 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 976 break; 977 case 5: 978 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 979 break; 980 default: 981 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 982 break; 983 } 984 #endif /* PCN_EVENT_COUNTERS */ 985 986 /* 987 * Initialize the transmit descriptors. 988 */ 989 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 990 for (nexttx = sc->sc_txnext, seg = 0; 991 seg < dmamap->dm_nsegs; 992 seg++, nexttx = PCN_NEXTTX(nexttx)) { 993 /* 994 * If this is the first descriptor we're 995 * enqueueing, don't set the OWN bit just 996 * yet. That could cause a race condition. 997 * We'll do it below. 998 */ 999 sc->sc_txdescs[nexttx].tmd0 = 0; 1000 sc->sc_txdescs[nexttx].tmd2 = 1001 htole32(dmamap->dm_segs[seg].ds_addr); 1002 sc->sc_txdescs[nexttx].tmd1 = 1003 ((nexttx == sc->sc_txnext) ? 0 : 1004 htole32(LE_T1_OWN)) | 1005 htole32((LE_BCNT(dmamap->dm_segs[ 1006 seg].ds_len) & 1007 LE_T1_BCNT_MASK)); 1008 lasttx = nexttx; 1009 } 1010 } else { 1011 for (nexttx = sc->sc_txnext, seg = 0; 1012 seg < dmamap->dm_nsegs; 1013 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1014 /* 1015 * If this is the first descriptor we're 1016 * enqueueing, don't set the OWN bit just 1017 * yet. That could cause a race condition. 1018 * We'll do it below. 1019 */ 1020 sc->sc_txdescs[nexttx].tmd0 = 1021 htole32(dmamap->dm_segs[seg].ds_addr); 1022 sc->sc_txdescs[nexttx].tmd2 = 0; 1023 sc->sc_txdescs[nexttx].tmd1 = 1024 ((nexttx == sc->sc_txnext) ? 0 : 1025 htole32(LE_T1_OWN)) | 1026 htole32((LE_BCNT(dmamap->dm_segs[ 1027 seg].ds_len) & 1028 LE_T1_BCNT_MASK)); 1029 lasttx = nexttx; 1030 } 1031 } 1032 1033 /* Interrupt on the packet, if appropriate. */ 1034 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1035 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1036 1037 /* Set `start of packet' and `end of packet' appropriately. */ 1038 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1039 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1040 htole32(LE_T1_OWN|LE_T1_STP); 1041 1042 /* Sync the descriptors we're using. */ 1043 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1044 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1045 1046 /* Kick the transmitter. */ 1047 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1048 1049 /* 1050 * Store a pointer to the packet so we can free it later, 1051 * and remember what txdirty will be once the packet is 1052 * done. 1053 */ 1054 txs->txs_mbuf = m0; 1055 txs->txs_firstdesc = sc->sc_txnext; 1056 txs->txs_lastdesc = lasttx; 1057 1058 /* Advance the tx pointer. */ 1059 sc->sc_txfree -= dmamap->dm_nsegs; 1060 sc->sc_txnext = nexttx; 1061 1062 sc->sc_txsfree--; 1063 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1064 1065 #if NBPFILTER > 0 1066 /* Pass the packet to any BPF listeners. */ 1067 if (ifp->if_bpf) 1068 bpf_mtap(ifp->if_bpf, m0); 1069 #endif /* NBPFILTER > 0 */ 1070 } 1071 1072 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1073 /* No more slots left; notify upper layer. */ 1074 ifp->if_flags |= IFF_OACTIVE; 1075 } 1076 1077 if (sc->sc_txfree != ofree) { 1078 /* Set a watchdog timer in case the chip flakes out. */ 1079 ifp->if_timer = 5; 1080 } 1081 } 1082 1083 /* 1084 * pcn_watchdog: [ifnet interface function] 1085 * 1086 * Watchdog timer handler. 1087 */ 1088 void 1089 pcn_watchdog(struct ifnet *ifp) 1090 { 1091 struct pcn_softc *sc = ifp->if_softc; 1092 1093 /* 1094 * Since we're not interrupting every packet, sweep 1095 * up before we report an error. 1096 */ 1097 pcn_txintr(sc); 1098 1099 if (sc->sc_txfree != PCN_NTXDESC) { 1100 printf("%s: device timeout (txfree %d txsfree %d)\n", 1101 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1102 ifp->if_oerrors++; 1103 1104 /* Reset the interface. */ 1105 (void) pcn_init(ifp); 1106 } 1107 1108 /* Try to get more packets going. */ 1109 pcn_start(ifp); 1110 } 1111 1112 /* 1113 * pcn_ioctl: [ifnet interface function] 1114 * 1115 * Handle control requests from the operator. 1116 */ 1117 int 1118 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1119 { 1120 struct pcn_softc *sc = ifp->if_softc; 1121 struct ifreq *ifr = (struct ifreq *) data; 1122 int s, error; 1123 1124 s = splnet(); 1125 1126 switch (cmd) { 1127 case SIOCSIFMEDIA: 1128 case SIOCGIFMEDIA: 1129 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1130 break; 1131 1132 default: 1133 error = ether_ioctl(ifp, cmd, data); 1134 if (error == ENETRESET) { 1135 /* 1136 * Multicast list has changed; set the hardware filter 1137 * accordingly. 1138 */ 1139 error = pcn_init(ifp); 1140 } 1141 break; 1142 } 1143 1144 /* Try to get more packets going. */ 1145 pcn_start(ifp); 1146 1147 splx(s); 1148 return (error); 1149 } 1150 1151 /* 1152 * pcn_intr: 1153 * 1154 * Interrupt service routine. 1155 */ 1156 int 1157 pcn_intr(void *arg) 1158 { 1159 struct pcn_softc *sc = arg; 1160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1161 uint32_t csr0; 1162 int wantinit, handled = 0; 1163 1164 for (wantinit = 0; wantinit == 0;) { 1165 csr0 = pcn_csr_read(sc, LE_CSR0); 1166 if ((csr0 & LE_C0_INTR) == 0) 1167 break; 1168 1169 /* ACK the bits and re-enable interrupts. */ 1170 pcn_csr_write(sc, LE_CSR0, csr0 & 1171 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1172 LE_C0_TINT|LE_C0_IDON)); 1173 1174 handled = 1; 1175 1176 if (csr0 & LE_C0_RINT) { 1177 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1178 wantinit = pcn_rxintr(sc); 1179 } 1180 1181 if (csr0 & LE_C0_TINT) { 1182 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1183 pcn_txintr(sc); 1184 } 1185 1186 if (csr0 & LE_C0_ERR) { 1187 if (csr0 & LE_C0_BABL) { 1188 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1189 ifp->if_oerrors++; 1190 } 1191 if (csr0 & LE_C0_MISS) { 1192 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1193 ifp->if_ierrors++; 1194 } 1195 if (csr0 & LE_C0_MERR) { 1196 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1197 printf("%s: memory error\n", 1198 sc->sc_dev.dv_xname); 1199 wantinit = 1; 1200 break; 1201 } 1202 } 1203 1204 if ((csr0 & LE_C0_RXON) == 0) { 1205 printf("%s: receiver disabled\n", 1206 sc->sc_dev.dv_xname); 1207 ifp->if_ierrors++; 1208 wantinit = 1; 1209 } 1210 1211 if ((csr0 & LE_C0_TXON) == 0) { 1212 printf("%s: transmitter disabled\n", 1213 sc->sc_dev.dv_xname); 1214 ifp->if_oerrors++; 1215 wantinit = 1; 1216 } 1217 } 1218 1219 if (handled) { 1220 if (wantinit) 1221 pcn_init(ifp); 1222 1223 /* Try to get more packets going. */ 1224 pcn_start(ifp); 1225 } 1226 1227 return (handled); 1228 } 1229 1230 /* 1231 * pcn_spnd: 1232 * 1233 * Suspend the chip. 1234 */ 1235 void 1236 pcn_spnd(struct pcn_softc *sc) 1237 { 1238 int i; 1239 1240 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1241 1242 for (i = 0; i < 10000; i++) { 1243 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1244 return; 1245 delay(5); 1246 } 1247 1248 printf("%s: WARNING: chip failed to enter suspended state\n", 1249 sc->sc_dev.dv_xname); 1250 } 1251 1252 /* 1253 * pcn_txintr: 1254 * 1255 * Helper; handle transmit interrupts. 1256 */ 1257 void 1258 pcn_txintr(struct pcn_softc *sc) 1259 { 1260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1261 struct pcn_txsoft *txs; 1262 uint32_t tmd1, tmd2, tmd; 1263 int i, j; 1264 1265 ifp->if_flags &= ~IFF_OACTIVE; 1266 1267 /* 1268 * Go through our Tx list and free mbufs for those 1269 * frames which have been transmitted. 1270 */ 1271 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1272 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1273 txs = &sc->sc_txsoft[i]; 1274 1275 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1276 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1277 1278 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1279 if (tmd1 & LE_T1_OWN) 1280 break; 1281 1282 /* 1283 * Slightly annoying -- we have to loop through the 1284 * descriptors we've used looking for ERR, since it 1285 * can appear on any descriptor in the chain. 1286 */ 1287 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1288 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1289 if (tmd & LE_T1_ERR) { 1290 ifp->if_oerrors++; 1291 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1292 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1293 else 1294 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1295 if (tmd2 & LE_T2_UFLO) { 1296 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1297 sc->sc_xmtsp++; 1298 printf("%s: transmit " 1299 "underrun; new threshold: " 1300 "%s\n", 1301 sc->sc_dev.dv_xname, 1302 sc->sc_xmtsp_desc[ 1303 sc->sc_xmtsp]); 1304 pcn_spnd(sc); 1305 pcn_csr_write(sc, LE_CSR80, 1306 LE_C80_RCVFW(sc->sc_rcvfw) | 1307 LE_C80_XMTSP(sc->sc_xmtsp) | 1308 LE_C80_XMTFW(sc->sc_xmtfw)); 1309 pcn_csr_write(sc, LE_CSR5, 1310 sc->sc_csr5); 1311 } else { 1312 printf("%s: transmit " 1313 "underrun\n", 1314 sc->sc_dev.dv_xname); 1315 } 1316 } else if (tmd2 & LE_T2_BUFF) { 1317 printf("%s: transmit buffer error\n", 1318 sc->sc_dev.dv_xname); 1319 } 1320 if (tmd2 & LE_T2_LCOL) 1321 ifp->if_collisions++; 1322 if (tmd2 & LE_T2_RTRY) 1323 ifp->if_collisions += 16; 1324 goto next_packet; 1325 } 1326 if (j == txs->txs_lastdesc) 1327 break; 1328 } 1329 if (tmd1 & LE_T1_ONE) 1330 ifp->if_collisions++; 1331 else if (tmd & LE_T1_MORE) { 1332 /* Real number is unknown. */ 1333 ifp->if_collisions += 2; 1334 } 1335 ifp->if_opackets++; 1336 next_packet: 1337 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1338 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1339 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1340 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1341 m_freem(txs->txs_mbuf); 1342 txs->txs_mbuf = NULL; 1343 } 1344 1345 /* Update the dirty transmit buffer pointer. */ 1346 sc->sc_txsdirty = i; 1347 1348 /* 1349 * If there are no more pending transmissions, cancel the watchdog 1350 * timer. 1351 */ 1352 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1353 ifp->if_timer = 0; 1354 } 1355 1356 /* 1357 * pcn_rxintr: 1358 * 1359 * Helper; handle receive interrupts. 1360 */ 1361 int 1362 pcn_rxintr(struct pcn_softc *sc) 1363 { 1364 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1365 struct pcn_rxsoft *rxs; 1366 struct mbuf *m; 1367 uint32_t rmd1; 1368 int i, len; 1369 1370 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1371 rxs = &sc->sc_rxsoft[i]; 1372 1373 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1374 1375 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1376 1377 if (rmd1 & LE_R1_OWN) 1378 break; 1379 1380 /* 1381 * Check for errors and make sure the packet fit into 1382 * a single buffer. We have structured this block of 1383 * code the way it is in order to compress it into 1384 * one test in the common case (no error). 1385 */ 1386 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1387 (LE_R1_STP|LE_R1_ENP))) { 1388 /* Make sure the packet is in a single buffer. */ 1389 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1390 (LE_R1_STP|LE_R1_ENP)) { 1391 printf("%s: packet spilled into next buffer\n", 1392 sc->sc_dev.dv_xname); 1393 return (1); /* pcn_intr() will re-init */ 1394 } 1395 1396 /* 1397 * If the packet had an error, simple recycle the 1398 * buffer. 1399 */ 1400 if (rmd1 & LE_R1_ERR) { 1401 ifp->if_ierrors++; 1402 /* 1403 * If we got an overflow error, chances 1404 * are there will be a CRC error. In 1405 * this case, just print the overflow 1406 * error, and skip the others. 1407 */ 1408 if (rmd1 & LE_R1_OFLO) 1409 printf("%s: overflow error\n", 1410 sc->sc_dev.dv_xname); 1411 else { 1412 #define PRINTIT(x, s) \ 1413 if (rmd1 & (x)) \ 1414 printf("%s: %s\n", \ 1415 sc->sc_dev.dv_xname, s); 1416 PRINTIT(LE_R1_FRAM, "framing error"); 1417 PRINTIT(LE_R1_CRC, "CRC error"); 1418 PRINTIT(LE_R1_BUFF, "buffer error"); 1419 } 1420 #undef PRINTIT 1421 PCN_INIT_RXDESC(sc, i); 1422 continue; 1423 } 1424 } 1425 1426 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1427 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1428 1429 /* 1430 * No errors; receive the packet. 1431 */ 1432 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1433 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1434 else 1435 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1436 1437 /* 1438 * The LANCE family includes the CRC with every packet; 1439 * trim it off here. 1440 */ 1441 len -= ETHER_CRC_LEN; 1442 1443 /* 1444 * If the packet is small enough to fit in a 1445 * single header mbuf, allocate one and copy 1446 * the data into it. This greatly reduces 1447 * memory consumption when we receive lots 1448 * of small packets. 1449 * 1450 * Otherwise, we add a new buffer to the receive 1451 * chain. If this fails, we drop the packet and 1452 * recycle the old buffer. 1453 */ 1454 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1455 MGETHDR(m, M_DONTWAIT, MT_DATA); 1456 if (m == NULL) 1457 goto dropit; 1458 m->m_data += 2; 1459 memcpy(mtod(m, caddr_t), 1460 mtod(rxs->rxs_mbuf, caddr_t), len); 1461 PCN_INIT_RXDESC(sc, i); 1462 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1463 rxs->rxs_dmamap->dm_mapsize, 1464 BUS_DMASYNC_PREREAD); 1465 } else { 1466 m = rxs->rxs_mbuf; 1467 if (pcn_add_rxbuf(sc, i) != 0) { 1468 dropit: 1469 ifp->if_ierrors++; 1470 PCN_INIT_RXDESC(sc, i); 1471 bus_dmamap_sync(sc->sc_dmat, 1472 rxs->rxs_dmamap, 0, 1473 rxs->rxs_dmamap->dm_mapsize, 1474 BUS_DMASYNC_PREREAD); 1475 continue; 1476 } 1477 } 1478 1479 m->m_pkthdr.rcvif = ifp; 1480 m->m_pkthdr.len = m->m_len = len; 1481 1482 #if NBPFILTER > 0 1483 /* Pass this up to any BPF listeners. */ 1484 if (ifp->if_bpf) 1485 bpf_mtap(ifp->if_bpf, m); 1486 #endif /* NBPFILTER > 0 */ 1487 1488 /* Pass it on. */ 1489 (*ifp->if_input)(ifp, m); 1490 ifp->if_ipackets++; 1491 } 1492 1493 /* Update the receive pointer. */ 1494 sc->sc_rxptr = i; 1495 return (0); 1496 } 1497 1498 /* 1499 * pcn_tick: 1500 * 1501 * One second timer, used to tick the MII. 1502 */ 1503 void 1504 pcn_tick(void *arg) 1505 { 1506 struct pcn_softc *sc = arg; 1507 int s; 1508 1509 s = splnet(); 1510 mii_tick(&sc->sc_mii); 1511 splx(s); 1512 1513 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1514 } 1515 1516 /* 1517 * pcn_reset: 1518 * 1519 * Perform a soft reset on the PCnet-PCI. 1520 */ 1521 void 1522 pcn_reset(struct pcn_softc *sc) 1523 { 1524 1525 /* 1526 * The PCnet-PCI chip is reset by reading from the 1527 * RESET register. Note that while the NE2100 LANCE 1528 * boards require a write after the read, the PCnet-PCI 1529 * chips do not require this. 1530 * 1531 * Since we don't know if we're in 16-bit or 32-bit 1532 * mode right now, issue both (it's safe) in the 1533 * hopes that one will succeed. 1534 */ 1535 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1536 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1537 1538 /* Wait 1ms for it to finish. */ 1539 delay(1000); 1540 1541 /* 1542 * Select 32-bit I/O mode by issuing a 32-bit write to the 1543 * RDP. Since the RAP is 0 after a reset, writing a 0 1544 * to RDP is safe (since it simply clears CSR0). 1545 */ 1546 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1547 } 1548 1549 /* 1550 * pcn_init: [ifnet interface function] 1551 * 1552 * Initialize the interface. Must be called at splnet(). 1553 */ 1554 int 1555 pcn_init(struct ifnet *ifp) 1556 { 1557 struct pcn_softc *sc = ifp->if_softc; 1558 struct pcn_rxsoft *rxs; 1559 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1560 int i, error = 0; 1561 uint32_t reg; 1562 1563 /* Cancel any pending I/O. */ 1564 pcn_stop(ifp, 0); 1565 1566 /* Reset the chip to a known state. */ 1567 pcn_reset(sc); 1568 1569 /* 1570 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1571 * else. 1572 * 1573 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1574 * because the structure layout is compatible with ILACC, 1575 * but the burst mode is only available in SSTYLE 3, and 1576 * burst mode should provide some performance enhancement. 1577 */ 1578 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1579 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1580 else 1581 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1582 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1583 1584 /* Initialize the transmit descriptor ring. */ 1585 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1586 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1587 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1588 sc->sc_txfree = PCN_NTXDESC; 1589 sc->sc_txnext = 0; 1590 1591 /* Initialize the transmit job descriptors. */ 1592 for (i = 0; i < PCN_TXQUEUELEN; i++) 1593 sc->sc_txsoft[i].txs_mbuf = NULL; 1594 sc->sc_txsfree = PCN_TXQUEUELEN; 1595 sc->sc_txsnext = 0; 1596 sc->sc_txsdirty = 0; 1597 1598 /* 1599 * Initialize the receive descriptor and receive job 1600 * descriptor rings. 1601 */ 1602 for (i = 0; i < PCN_NRXDESC; i++) { 1603 rxs = &sc->sc_rxsoft[i]; 1604 if (rxs->rxs_mbuf == NULL) { 1605 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1606 printf("%s: unable to allocate or map rx " 1607 "buffer %d, error = %d\n", 1608 sc->sc_dev.dv_xname, i, error); 1609 /* 1610 * XXX Should attempt to run with fewer receive 1611 * XXX buffers instead of just failing. 1612 */ 1613 pcn_rxdrain(sc); 1614 goto out; 1615 } 1616 } else 1617 PCN_INIT_RXDESC(sc, i); 1618 } 1619 sc->sc_rxptr = 0; 1620 1621 /* Initialize MODE for the initialization block. */ 1622 sc->sc_mode = 0; 1623 if (ifp->if_flags & IFF_PROMISC) 1624 sc->sc_mode |= LE_C15_PROM; 1625 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1626 sc->sc_mode |= LE_C15_DRCVBC; 1627 1628 /* 1629 * If we have MII, simply select MII in the MODE register, 1630 * and clear ASEL. Otherwise, let ASEL stand (for now), 1631 * and leave PORTSEL alone (it is ignored with ASEL is set). 1632 */ 1633 if (sc->sc_flags & PCN_F_HAS_MII) { 1634 pcn_bcr_write(sc, LE_BCR2, 1635 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1636 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1637 1638 /* 1639 * Disable MII auto-negotiation. We handle that in 1640 * our own MII layer. 1641 */ 1642 pcn_bcr_write(sc, LE_BCR32, 1643 pcn_csr_read(sc, LE_BCR32) & ~LE_B32_DANAS); 1644 } 1645 1646 /* 1647 * Set the Tx and Rx descriptor ring addresses in the init 1648 * block, the TLEN and RLEN other fields of the init block 1649 * MODE register. 1650 */ 1651 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1652 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1653 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1654 ((ffs(PCN_NTXDESC) - 1) << 28) | 1655 ((ffs(PCN_NRXDESC) - 1) << 20)); 1656 1657 /* Set the station address in the init block. */ 1658 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1659 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1660 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1661 (enaddr[5] << 8)); 1662 1663 /* Set the multicast filter in the init block. */ 1664 pcn_set_filter(sc); 1665 1666 /* Initialize CSR3. */ 1667 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1668 1669 /* Initialize CSR4. */ 1670 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1671 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1672 1673 /* Initialize CSR5. */ 1674 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1675 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1676 1677 /* 1678 * If we have an Am79c971 or greater, initialize CSR7. 1679 * 1680 * XXX Might be nice to use the MII auto-poll interrupt someday. 1681 */ 1682 switch (sc->sc_variant->pcv_chipid) { 1683 case PARTID_Am79c970: 1684 case PARTID_Am79c970A: 1685 /* Not available on these chips. */ 1686 break; 1687 1688 default: 1689 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1690 break; 1691 } 1692 1693 /* 1694 * On the Am79c970A and greater, initialize BCR18 to 1695 * enable burst mode. 1696 * 1697 * Also enable the "no underflow" option on the Am79c971 and 1698 * higher, which prevents the chip from generating transmit 1699 * underflows, yet sill provides decent performance. Note if 1700 * chip is not connected to external SRAM, then we still have 1701 * to handle underflow errors (the NOUFLO bit is ignored in 1702 * that case). 1703 */ 1704 reg = pcn_bcr_read(sc, LE_BCR18); 1705 switch (sc->sc_variant->pcv_chipid) { 1706 case PARTID_Am79c970: 1707 break; 1708 1709 case PARTID_Am79c970A: 1710 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1711 break; 1712 1713 default: 1714 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1715 break; 1716 } 1717 pcn_bcr_write(sc, LE_BCR18, reg); 1718 1719 /* 1720 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1721 */ 1722 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1723 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1724 1725 /* 1726 * Send the init block to the chip, and wait for it 1727 * to be processed. 1728 */ 1729 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1730 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1731 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1732 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1733 delay(100); 1734 for (i = 0; i < 10000; i++) { 1735 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1736 break; 1737 delay(10); 1738 } 1739 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1740 if (i == 10000) { 1741 printf("%s: timeout processing init block\n", 1742 sc->sc_dev.dv_xname); 1743 error = EIO; 1744 goto out; 1745 } 1746 1747 /* Set the media. */ 1748 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1749 1750 /* Enable interrupts and external activity (and ACK IDON). */ 1751 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1752 1753 if (sc->sc_flags & PCN_F_HAS_MII) { 1754 /* Start the one second MII clock. */ 1755 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1756 } 1757 1758 /* ...all done! */ 1759 ifp->if_flags |= IFF_RUNNING; 1760 ifp->if_flags &= ~IFF_OACTIVE; 1761 1762 out: 1763 if (error) 1764 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1765 return (error); 1766 } 1767 1768 /* 1769 * pcn_rxdrain: 1770 * 1771 * Drain the receive queue. 1772 */ 1773 void 1774 pcn_rxdrain(struct pcn_softc *sc) 1775 { 1776 struct pcn_rxsoft *rxs; 1777 int i; 1778 1779 for (i = 0; i < PCN_NRXDESC; i++) { 1780 rxs = &sc->sc_rxsoft[i]; 1781 if (rxs->rxs_mbuf != NULL) { 1782 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1783 m_freem(rxs->rxs_mbuf); 1784 rxs->rxs_mbuf = NULL; 1785 } 1786 } 1787 } 1788 1789 /* 1790 * pcn_stop: [ifnet interface function] 1791 * 1792 * Stop transmission on the interface. 1793 */ 1794 void 1795 pcn_stop(struct ifnet *ifp, int disable) 1796 { 1797 struct pcn_softc *sc = ifp->if_softc; 1798 struct pcn_txsoft *txs; 1799 int i; 1800 1801 if (sc->sc_flags & PCN_F_HAS_MII) { 1802 /* Stop the one second clock. */ 1803 callout_stop(&sc->sc_tick_ch); 1804 1805 /* Down the MII. */ 1806 mii_down(&sc->sc_mii); 1807 } 1808 1809 /* Stop the chip. */ 1810 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1811 1812 /* Release any queued transmit buffers. */ 1813 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1814 txs = &sc->sc_txsoft[i]; 1815 if (txs->txs_mbuf != NULL) { 1816 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1817 m_freem(txs->txs_mbuf); 1818 txs->txs_mbuf = NULL; 1819 } 1820 } 1821 1822 if (disable) 1823 pcn_rxdrain(sc); 1824 1825 /* Mark the interface as down and cancel the watchdog timer. */ 1826 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1827 ifp->if_timer = 0; 1828 } 1829 1830 /* 1831 * pcn_add_rxbuf: 1832 * 1833 * Add a receive buffer to the indicated descriptor. 1834 */ 1835 int 1836 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1837 { 1838 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1839 struct mbuf *m; 1840 int error; 1841 1842 MGETHDR(m, M_DONTWAIT, MT_DATA); 1843 if (m == NULL) 1844 return (ENOBUFS); 1845 1846 MCLGET(m, M_DONTWAIT); 1847 if ((m->m_flags & M_EXT) == 0) { 1848 m_freem(m); 1849 return (ENOBUFS); 1850 } 1851 1852 if (rxs->rxs_mbuf != NULL) 1853 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1854 1855 rxs->rxs_mbuf = m; 1856 1857 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1858 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1859 BUS_DMA_READ|BUS_DMA_NOWAIT); 1860 if (error) { 1861 printf("%s: can't load rx DMA map %d, error = %d\n", 1862 sc->sc_dev.dv_xname, idx, error); 1863 panic("pcn_add_rxbuf"); 1864 } 1865 1866 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1867 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1868 1869 PCN_INIT_RXDESC(sc, idx); 1870 1871 return (0); 1872 } 1873 1874 /* 1875 * pcn_set_filter: 1876 * 1877 * Set up the receive filter. 1878 */ 1879 void 1880 pcn_set_filter(struct pcn_softc *sc) 1881 { 1882 struct ethercom *ec = &sc->sc_ethercom; 1883 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1884 struct ether_multi *enm; 1885 struct ether_multistep step; 1886 uint32_t crc; 1887 1888 /* 1889 * Set up the multicast address filter by passing all multicast 1890 * addresses through a CRC generator, and then using the high 1891 * order 6 bits as an index into the 64-bit logical address 1892 * filter. The high order bits select the word, while the rest 1893 * of the bits select the bit within the word. 1894 */ 1895 1896 if (ifp->if_flags & IFF_PROMISC) 1897 goto allmulti; 1898 1899 sc->sc_initblock.init_ladrf[0] = 1900 sc->sc_initblock.init_ladrf[1] = 1901 sc->sc_initblock.init_ladrf[2] = 1902 sc->sc_initblock.init_ladrf[3] = 0; 1903 1904 ETHER_FIRST_MULTI(step, ec, enm); 1905 while (enm != NULL) { 1906 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1907 /* 1908 * We must listen to a range of multicast addresses. 1909 * For now, just accept all multicasts, rather than 1910 * trying to set only those filter bits needed to match 1911 * the range. (At this time, the only use of address 1912 * ranges is for IP multicast routing, for which the 1913 * range is big enough to require all bits set.) 1914 */ 1915 goto allmulti; 1916 } 1917 1918 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1919 1920 /* Just want the 6 most significant bits. */ 1921 crc >>= 26; 1922 1923 /* Set the corresponding bit in the filter. */ 1924 sc->sc_initblock.init_ladrf[crc >> 4] |= 1925 htole16(1 << (crc & 0xf)); 1926 1927 ETHER_NEXT_MULTI(step, enm); 1928 } 1929 1930 ifp->if_flags &= ~IFF_ALLMULTI; 1931 return; 1932 1933 allmulti: 1934 ifp->if_flags |= IFF_ALLMULTI; 1935 sc->sc_initblock.init_ladrf[0] = 1936 sc->sc_initblock.init_ladrf[1] = 1937 sc->sc_initblock.init_ladrf[2] = 1938 sc->sc_initblock.init_ladrf[3] = 0xffff; 1939 } 1940 1941 /* 1942 * pcn_79c970_mediainit: 1943 * 1944 * Initialize media for the Am79c970. 1945 */ 1946 void 1947 pcn_79c970_mediainit(struct pcn_softc *sc) 1948 { 1949 const char *sep = ""; 1950 1951 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c970_mediachange, 1952 pcn_79c970_mediastatus); 1953 1954 #define ADD(s, m, d) \ 1955 do { \ 1956 printf("%s%s", sep, s); \ 1957 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 1958 sep = ", "; \ 1959 } while (/*CONSTCOND*/0) 1960 1961 printf("%s: ", sc->sc_dev.dv_xname); 1962 ADD("10base5", IFM_10_5, PORTSEL_AUI); 1963 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1964 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 1965 ADD("10baseT", IFM_10_T, PORTSEL_10T); 1966 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1967 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 1968 ADD("auto", IFM_AUTO, 0); 1969 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1970 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 1971 printf("\n"); 1972 1973 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1974 } 1975 1976 /* 1977 * pcn_79c970_mediastatus: [ifmedia interface function] 1978 * 1979 * Get the current interface media status (Am79c970 version). 1980 */ 1981 void 1982 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1983 { 1984 struct pcn_softc *sc = ifp->if_softc; 1985 1986 /* 1987 * The currently selected media is always the active media. 1988 * Note: We have no way to determine what media the AUTO 1989 * process picked. 1990 */ 1991 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1992 } 1993 1994 /* 1995 * pcn_79c970_mediachange: [ifmedia interface function] 1996 * 1997 * Set hardware to newly-selected media (Am79c970 version). 1998 */ 1999 int 2000 pcn_79c970_mediachange(struct ifnet *ifp) 2001 { 2002 struct pcn_softc *sc = ifp->if_softc; 2003 uint32_t reg; 2004 2005 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2006 /* 2007 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2008 */ 2009 reg = pcn_bcr_read(sc, LE_BCR2); 2010 reg |= LE_B2_ASEL; 2011 pcn_bcr_write(sc, LE_BCR2, reg); 2012 } else { 2013 /* 2014 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2015 */ 2016 reg = pcn_bcr_read(sc, LE_BCR2); 2017 reg &= ~LE_B2_ASEL; 2018 pcn_bcr_write(sc, LE_BCR2, reg); 2019 2020 reg = pcn_csr_read(sc, LE_CSR15); 2021 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2022 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2023 pcn_csr_write(sc, LE_CSR15, reg); 2024 } 2025 2026 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2027 reg = LE_B9_FDEN; 2028 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2029 reg |= LE_B9_AUIFD; 2030 pcn_bcr_write(sc, LE_BCR9, reg); 2031 } else 2032 pcn_bcr_write(sc, LE_BCR0, 0); 2033 2034 return (0); 2035 } 2036 2037 /* 2038 * pcn_79c971_mediainit: 2039 * 2040 * Initialize media for the Am79c971. 2041 */ 2042 void 2043 pcn_79c971_mediainit(struct pcn_softc *sc) 2044 { 2045 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2046 2047 /* We have MII. */ 2048 sc->sc_flags |= PCN_F_HAS_MII; 2049 2050 /* 2051 * The built-in 10BASE-T interface is mapped to the MII 2052 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2053 * word that tells us which PHY to use. Since the 10BASE-T 2054 * interface is always at PHY 31, we make a note of the 2055 * first PHY that responds, and disallow any PHYs after 2056 * it. This is all handled in the MII read routine. 2057 */ 2058 sc->sc_phyaddr = -1; 2059 2060 /* Initialize our media structures and probe the MII. */ 2061 sc->sc_mii.mii_ifp = ifp; 2062 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2063 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2064 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2065 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2066 pcn_79c971_mediastatus); 2067 2068 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2069 MII_OFFSET_ANY, 0); 2070 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2071 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2072 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2073 } else 2074 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2075 } 2076 2077 /* 2078 * pcn_79c971_mediastatus: [ifmedia interface function] 2079 * 2080 * Get the current interface media status (Am79c971 version). 2081 */ 2082 void 2083 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2084 { 2085 struct pcn_softc *sc = ifp->if_softc; 2086 2087 mii_pollstat(&sc->sc_mii); 2088 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2089 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2090 } 2091 2092 /* 2093 * pcn_79c971_mediachange: [ifmedia interface function] 2094 * 2095 * Set hardware to newly-selected media (Am79c971 version). 2096 */ 2097 int 2098 pcn_79c971_mediachange(struct ifnet *ifp) 2099 { 2100 struct pcn_softc *sc = ifp->if_softc; 2101 2102 if (ifp->if_flags & IFF_UP) 2103 mii_mediachg(&sc->sc_mii); 2104 return (0); 2105 } 2106 2107 /* 2108 * pcn_mii_readreg: [mii interface function] 2109 * 2110 * Read a PHY register on the MII. 2111 */ 2112 int 2113 pcn_mii_readreg(struct device *self, int phy, int reg) 2114 { 2115 struct pcn_softc *sc = (void *) self; 2116 uint32_t rv; 2117 2118 if (sc->sc_phyaddr != -1 && phy != sc->sc_phyaddr) 2119 return (0); 2120 2121 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2122 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2123 if (rv == 0xffff) 2124 return (0); 2125 2126 if (sc->sc_phyaddr == -1) 2127 sc->sc_phyaddr = phy; 2128 2129 return (rv); 2130 } 2131 2132 /* 2133 * pcn_mii_writereg: [mii interface function] 2134 * 2135 * Write a PHY register on the MII. 2136 */ 2137 void 2138 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2139 { 2140 struct pcn_softc *sc = (void *) self; 2141 2142 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2143 pcn_bcr_write(sc, LE_BCR34, val); 2144 } 2145 2146 /* 2147 * pcn_mii_statchg: [mii interface function] 2148 * 2149 * Callback from MII layer when media changes. 2150 */ 2151 void 2152 pcn_mii_statchg(struct device *self) 2153 { 2154 struct pcn_softc *sc = (void *) self; 2155 2156 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2157 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2158 else 2159 pcn_bcr_write(sc, LE_BCR0, 0); 2160 } 2161