1 /* $NetBSD: if_pcn.c,v 1.19 2003/03/30 19:20:37 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.19 2003/03/30 19:20:37 jdolecek Exp $"); 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_ether.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 16 119 * DMA segments, but only allocate the max of 512 descriptors. The 120 * transmit logic can deal with this, we just are hoping to sneak by. 121 */ 122 #define PCN_NTXSEGS 16 123 124 #define PCN_TXQUEUELEN 128 125 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 126 #define PCN_NTXDESC 512 127 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 128 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 129 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 130 131 /* Tx interrupt every N + 1 packets. */ 132 #define PCN_TXINTR_MASK 7 133 134 /* 135 * Receive descriptor list size. We have one Rx buffer per incoming 136 * packet, so this logic is a little simpler. 137 */ 138 #define PCN_NRXDESC 128 139 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 140 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 141 142 /* 143 * Control structures are DMA'd to the PCnet chip. We allocate them in 144 * a single clump that maps to a single DMA segment to make several things 145 * easier. 146 */ 147 struct pcn_control_data { 148 /* The transmit descriptors. */ 149 struct letmd pcd_txdescs[PCN_NTXDESC]; 150 151 /* The receive descriptors. */ 152 struct lermd pcd_rxdescs[PCN_NRXDESC]; 153 154 /* The init block. */ 155 struct leinit pcd_initblock; 156 }; 157 158 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 159 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 160 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 161 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 162 163 /* 164 * Software state for transmit jobs. 165 */ 166 struct pcn_txsoft { 167 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 168 bus_dmamap_t txs_dmamap; /* our DMA map */ 169 int txs_firstdesc; /* first descriptor in packet */ 170 int txs_lastdesc; /* last descriptor in packet */ 171 }; 172 173 /* 174 * Software state for receive jobs. 175 */ 176 struct pcn_rxsoft { 177 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 178 bus_dmamap_t rxs_dmamap; /* our DMA map */ 179 }; 180 181 /* 182 * Description of Rx FIFO watermarks for various revisions. 183 */ 184 const char * const pcn_79c970_rcvfw[] = { 185 "16 bytes", 186 "64 bytes", 187 "128 bytes", 188 NULL, 189 }; 190 191 const char * const pcn_79c971_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "112 bytes", 195 NULL, 196 }; 197 198 /* 199 * Description of Tx start points for various revisions. 200 */ 201 const char * const pcn_79c970_xmtsp[] = { 202 "8 bytes", 203 "64 bytes", 204 "128 bytes", 205 "248 bytes", 206 }; 207 208 const char * const pcn_79c971_xmtsp[] = { 209 "20 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 const char * const pcn_79c971_xmtsp_sram[] = { 216 "44 bytes", 217 "64 bytes", 218 "128 bytes", 219 "store-and-forward", 220 }; 221 222 /* 223 * Description of Tx FIFO watermarks for various revisions. 224 */ 225 const char * const pcn_79c970_xmtfw[] = { 226 "16 bytes", 227 "64 bytes", 228 "128 bytes", 229 NULL, 230 }; 231 232 const char * const pcn_79c971_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "108 bytes", 236 NULL, 237 }; 238 239 /* 240 * Software state per device. 241 */ 242 struct pcn_softc { 243 struct device sc_dev; /* generic device information */ 244 bus_space_tag_t sc_st; /* bus space tag */ 245 bus_space_handle_t sc_sh; /* bus space handle */ 246 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 247 struct ethercom sc_ethercom; /* Ethernet common data */ 248 void *sc_sdhook; /* shutdown hook */ 249 250 /* Points to our media routines, etc. */ 251 const struct pcn_variant *sc_variant; 252 253 void *sc_ih; /* interrupt cookie */ 254 255 struct mii_data sc_mii; /* MII/media information */ 256 257 struct callout sc_tick_ch; /* tick callout */ 258 259 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 260 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 261 262 /* Software state for transmit and receive descriptors. */ 263 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 264 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 265 266 /* Control data structures */ 267 struct pcn_control_data *sc_control_data; 268 #define sc_txdescs sc_control_data->pcd_txdescs 269 #define sc_rxdescs sc_control_data->pcd_rxdescs 270 #define sc_initblock sc_control_data->pcd_initblock 271 272 #ifdef PCN_EVENT_COUNTERS 273 /* Event counters. */ 274 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 275 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 276 struct evcnt sc_ev_txintr; /* Tx interrupts */ 277 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 278 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 279 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 280 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 281 282 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 283 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 284 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 285 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 286 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 287 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 288 struct evcnt sc_ev_txcopy; /* Tx copies required */ 289 #endif /* PCN_EVENT_COUNTERS */ 290 291 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 292 int sc_rcvfw; 293 294 const char * const *sc_xmtsp_desc; /* Tx start point info */ 295 int sc_xmtsp; 296 297 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 298 int sc_xmtfw; 299 300 int sc_flags; /* misc. flags; see below */ 301 int sc_swstyle; /* the software style in use */ 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 306 int sc_txsfree; /* number of free Tx jobs */ 307 int sc_txsnext; /* next free Tx job */ 308 int sc_txsdirty; /* dirty Tx jobs */ 309 310 int sc_rxptr; /* next ready Rx descriptor/job */ 311 312 uint32_t sc_csr5; /* prototype CSR5 register */ 313 uint32_t sc_mode; /* prototype MODE register */ 314 int sc_phyaddr; /* PHY address */ 315 }; 316 317 /* sc_flags */ 318 #define PCN_F_HAS_MII 0x0001 /* has MII */ 319 320 #ifdef PCN_EVENT_COUNTERS 321 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 322 #else 323 #define PCN_EVCNT_INCR(ev) /* nothing */ 324 #endif 325 326 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 327 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 328 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 329 330 #define PCN_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > PCN_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 341 (PCN_NTXDESC - __x), (ops)); \ 342 __n -= (PCN_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 349 } while (/*CONSTCOND*/0) 350 351 #define PCN_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 354 355 #define PCN_CDINITSYNC(sc, ops) \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 358 359 #define PCN_INIT_RXDESC(sc, x) \ 360 do { \ 361 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 362 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 363 struct mbuf *__m = __rxs->rxs_mbuf; \ 364 \ 365 /* \ 366 * Note: We scoot the packet forward 2 bytes in the buffer \ 367 * so that the payload after the Ethernet header is aligned \ 368 * to a 4-byte boundary. \ 369 */ \ 370 __m->m_data = __m->m_ext.ext_buf + 2; \ 371 \ 372 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 373 __rmd->rmd2 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 __rmd->rmd0 = 0; \ 376 } else { \ 377 __rmd->rmd2 = 0; \ 378 __rmd->rmd0 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 } \ 381 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 382 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 383 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 384 } while(/*CONSTCOND*/0) 385 386 void pcn_start(struct ifnet *); 387 void pcn_watchdog(struct ifnet *); 388 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 389 int pcn_init(struct ifnet *); 390 void pcn_stop(struct ifnet *, int); 391 392 void pcn_shutdown(void *); 393 394 void pcn_reset(struct pcn_softc *); 395 void pcn_rxdrain(struct pcn_softc *); 396 int pcn_add_rxbuf(struct pcn_softc *, int); 397 void pcn_tick(void *); 398 399 void pcn_spnd(struct pcn_softc *); 400 401 void pcn_set_filter(struct pcn_softc *); 402 403 int pcn_intr(void *); 404 void pcn_txintr(struct pcn_softc *); 405 int pcn_rxintr(struct pcn_softc *); 406 407 int pcn_mii_readreg(struct device *, int, int); 408 void pcn_mii_writereg(struct device *, int, int, int); 409 void pcn_mii_statchg(struct device *); 410 411 void pcn_79c970_mediainit(struct pcn_softc *); 412 int pcn_79c970_mediachange(struct ifnet *); 413 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 414 415 void pcn_79c971_mediainit(struct pcn_softc *); 416 int pcn_79c971_mediachange(struct ifnet *); 417 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 418 419 /* 420 * Description of a PCnet-PCI variant. Used to select media access 421 * method, mostly, and to print a nice description of the chip. 422 */ 423 const struct pcn_variant { 424 const char *pcv_desc; 425 void (*pcv_mediainit)(struct pcn_softc *); 426 uint16_t pcv_chipid; 427 } pcn_variants[] = { 428 { "Am79c970 PCnet-PCI", 429 pcn_79c970_mediainit, 430 PARTID_Am79c970 }, 431 432 { "Am79c970A PCnet-PCI II", 433 pcn_79c970_mediainit, 434 PARTID_Am79c970A }, 435 436 { "Am79c971 PCnet-FAST", 437 pcn_79c971_mediainit, 438 PARTID_Am79c971 }, 439 440 { "Am79c972 PCnet-FAST+", 441 pcn_79c971_mediainit, 442 PARTID_Am79c972 }, 443 444 { "Am79c973 PCnet-FAST III", 445 pcn_79c971_mediainit, 446 PARTID_Am79c973 }, 447 448 { "Am79c975 PCnet-FAST III", 449 pcn_79c971_mediainit, 450 PARTID_Am79c975 }, 451 452 { "Unknown PCnet-PCI variant", 453 pcn_79c971_mediainit, 454 0 }, 455 }; 456 457 int pcn_copy_small = 0; 458 459 int pcn_match(struct device *, struct cfdata *, void *); 460 void pcn_attach(struct device *, struct device *, void *); 461 462 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 463 pcn_match, pcn_attach, NULL, NULL); 464 465 /* 466 * Routines to read and write the PCnet-PCI CSR/BCR space. 467 */ 468 469 static __inline uint32_t 470 pcn_csr_read(struct pcn_softc *sc, int reg) 471 { 472 473 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 474 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 475 } 476 477 static __inline void 478 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 479 { 480 481 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 483 } 484 485 static __inline uint32_t 486 pcn_bcr_read(struct pcn_softc *sc, int reg) 487 { 488 489 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 490 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 491 } 492 493 static __inline void 494 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 495 { 496 497 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 499 } 500 501 static const struct pcn_variant * 502 pcn_lookup_variant(uint16_t chipid) 503 { 504 const struct pcn_variant *pcv; 505 506 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 507 if (chipid == pcv->pcv_chipid) 508 return (pcv); 509 } 510 511 /* 512 * This covers unknown chips, which we simply treat like 513 * a generic PCnet-FAST. 514 */ 515 return (pcv); 516 } 517 518 int 519 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 520 { 521 struct pci_attach_args *pa = aux; 522 523 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 524 return (0); 525 526 switch (PCI_PRODUCT(pa->pa_id)) { 527 case PCI_PRODUCT_AMD_PCNET_PCI: 528 /* Beat if_le_pci.c */ 529 return (10); 530 } 531 532 return (0); 533 } 534 535 void 536 pcn_attach(struct device *parent, struct device *self, void *aux) 537 { 538 struct pcn_softc *sc = (struct pcn_softc *) self; 539 struct pci_attach_args *pa = aux; 540 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 541 pci_chipset_tag_t pc = pa->pa_pc; 542 pci_intr_handle_t ih; 543 const char *intrstr = NULL; 544 bus_space_tag_t iot, memt; 545 bus_space_handle_t ioh, memh; 546 bus_dma_segment_t seg; 547 int ioh_valid, memh_valid; 548 int i, rseg, error; 549 pcireg_t pmode; 550 uint32_t chipid, reg; 551 uint8_t enaddr[ETHER_ADDR_LEN]; 552 int pmreg; 553 554 callout_init(&sc->sc_tick_ch); 555 556 printf(": AMD PCnet-PCI Ethernet\n"); 557 558 /* 559 * Map the device. 560 */ 561 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 562 &iot, &ioh, NULL, NULL) == 0); 563 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 564 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 565 &memt, &memh, NULL, NULL) == 0); 566 567 if (memh_valid) { 568 sc->sc_st = memt; 569 sc->sc_sh = memh; 570 } else if (ioh_valid) { 571 sc->sc_st = iot; 572 sc->sc_sh = ioh; 573 } else { 574 printf("%s: unable to map device registers\n", 575 sc->sc_dev.dv_xname); 576 return; 577 } 578 579 sc->sc_dmat = pa->pa_dmat; 580 581 /* Make sure bus mastering is enabled. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 583 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 584 PCI_COMMAND_MASTER_ENABLE); 585 586 /* Get it out of power save mode, if needed. */ 587 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 588 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 589 PCI_PMCSR_STATE_MASK; 590 if (pmode == PCI_PMCSR_STATE_D3) { 591 /* 592 * The card has lost all configuration data in 593 * this state, so punt. 594 */ 595 printf("%s: unable to wake from power state D3\n", 596 sc->sc_dev.dv_xname); 597 return; 598 } 599 if (pmode != PCI_PMCSR_STATE_D0) { 600 printf("%s: waking up from power date D%d\n", 601 sc->sc_dev.dv_xname, pmode); 602 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 603 PCI_PMCSR_STATE_D0); 604 } 605 } 606 607 /* 608 * Reset the chip to a known state. This also puts the 609 * chip into 32-bit mode. 610 */ 611 pcn_reset(sc); 612 613 /* 614 * Read the Ethernet address from the EEPROM. 615 */ 616 for (i = 0; i < ETHER_ADDR_LEN; i++) 617 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 618 PCN32_APROM + i); 619 620 /* 621 * Now that the device is mapped, attempt to figure out what 622 * kind of chip we have. Note that IDL has all 32 bits of 623 * the chip ID when we're in 32-bit mode. 624 */ 625 chipid = pcn_csr_read(sc, LE_CSR88); 626 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 627 628 printf("%s: %s rev %d, Ethernet address %s\n", 629 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 630 ether_sprintf(enaddr)); 631 632 /* 633 * Map and establish our interrupt. 634 */ 635 if (pci_intr_map(pa, &ih)) { 636 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 637 return; 638 } 639 intrstr = pci_intr_string(pc, ih); 640 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 641 if (sc->sc_ih == NULL) { 642 printf("%s: unable to establish interrupt", 643 sc->sc_dev.dv_xname); 644 if (intrstr != NULL) 645 printf(" at %s", intrstr); 646 printf("\n"); 647 return; 648 } 649 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 650 651 /* 652 * Allocate the control data structures, and create and load the 653 * DMA map for it. 654 */ 655 if ((error = bus_dmamem_alloc(sc->sc_dmat, 656 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 657 0)) != 0) { 658 printf("%s: unable to allocate control data, error = %d\n", 659 sc->sc_dev.dv_xname, error); 660 goto fail_0; 661 } 662 663 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 664 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 665 BUS_DMA_COHERENT)) != 0) { 666 printf("%s: unable to map control data, error = %d\n", 667 sc->sc_dev.dv_xname, error); 668 goto fail_1; 669 } 670 671 if ((error = bus_dmamap_create(sc->sc_dmat, 672 sizeof(struct pcn_control_data), 1, 673 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 674 printf("%s: unable to create control data DMA map, " 675 "error = %d\n", sc->sc_dev.dv_xname, error); 676 goto fail_2; 677 } 678 679 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 680 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 681 0)) != 0) { 682 printf("%s: unable to load control data DMA map, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail_3; 685 } 686 687 /* Create the transmit buffer DMA maps. */ 688 for (i = 0; i < PCN_TXQUEUELEN; i++) { 689 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 690 PCN_NTXSEGS, MCLBYTES, 0, 0, 691 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 692 printf("%s: unable to create tx DMA map %d, " 693 "error = %d\n", sc->sc_dev.dv_xname, i, error); 694 goto fail_4; 695 } 696 } 697 698 /* Create the receive buffer DMA maps. */ 699 for (i = 0; i < PCN_NRXDESC; i++) { 700 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 701 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 702 printf("%s: unable to create rx DMA map %d, " 703 "error = %d\n", sc->sc_dev.dv_xname, i, error); 704 goto fail_5; 705 } 706 sc->sc_rxsoft[i].rxs_mbuf = NULL; 707 } 708 709 /* Initialize our media structures. */ 710 (*sc->sc_variant->pcv_mediainit)(sc); 711 712 /* 713 * Initialize FIFO watermark info. 714 */ 715 switch (sc->sc_variant->pcv_chipid) { 716 case PARTID_Am79c970: 717 case PARTID_Am79c970A: 718 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 719 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 720 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 721 break; 722 723 default: 724 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 725 /* 726 * Read BCR25 to determine how much SRAM is 727 * on the board. If > 0, then we the chip 728 * uses different Start Point thresholds. 729 * 730 * Note BCR25 and BCR26 are loaded from the 731 * EEPROM on RST, and unaffected by S_RESET, 732 * so we don't really have to worry about 733 * them except for this. 734 */ 735 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 736 if (reg != 0) 737 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 738 else 739 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 740 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 741 break; 742 } 743 744 /* 745 * Set up defaults -- see the tables above for what these 746 * values mean. 747 * 748 * XXX How should we tune RCVFW and XMTFW? 749 */ 750 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 751 sc->sc_xmtsp = 1; 752 sc->sc_xmtfw = 0; 753 754 ifp = &sc->sc_ethercom.ec_if; 755 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 756 ifp->if_softc = sc; 757 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 758 ifp->if_ioctl = pcn_ioctl; 759 ifp->if_start = pcn_start; 760 ifp->if_watchdog = pcn_watchdog; 761 ifp->if_init = pcn_init; 762 ifp->if_stop = pcn_stop; 763 IFQ_SET_READY(&ifp->if_snd); 764 765 /* Attach the interface. */ 766 if_attach(ifp); 767 ether_ifattach(ifp, enaddr); 768 769 #ifdef PCN_EVENT_COUNTERS 770 /* Attach event counters. */ 771 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 772 NULL, sc->sc_dev.dv_xname, "txsstall"); 773 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 774 NULL, sc->sc_dev.dv_xname, "txdstall"); 775 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 776 NULL, sc->sc_dev.dv_xname, "txintr"); 777 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 778 NULL, sc->sc_dev.dv_xname, "rxintr"); 779 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 780 NULL, sc->sc_dev.dv_xname, "babl"); 781 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 782 NULL, sc->sc_dev.dv_xname, "miss"); 783 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 784 NULL, sc->sc_dev.dv_xname, "merr"); 785 786 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 787 NULL, sc->sc_dev.dv_xname, "txseg1"); 788 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 789 NULL, sc->sc_dev.dv_xname, "txseg2"); 790 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 791 NULL, sc->sc_dev.dv_xname, "txseg3"); 792 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 793 NULL, sc->sc_dev.dv_xname, "txseg4"); 794 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 795 NULL, sc->sc_dev.dv_xname, "txseg5"); 796 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 797 NULL, sc->sc_dev.dv_xname, "txsegmore"); 798 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 799 NULL, sc->sc_dev.dv_xname, "txcopy"); 800 #endif /* PCN_EVENT_COUNTERS */ 801 802 /* Make sure the interface is shutdown during reboot. */ 803 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 804 if (sc->sc_sdhook == NULL) 805 printf("%s: WARNING: unable to establish shutdown hook\n", 806 sc->sc_dev.dv_xname); 807 return; 808 809 /* 810 * Free any resources we've allocated during the failed attach 811 * attempt. Do this in reverse order and fall through. 812 */ 813 fail_5: 814 for (i = 0; i < PCN_NRXDESC; i++) { 815 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 816 bus_dmamap_destroy(sc->sc_dmat, 817 sc->sc_rxsoft[i].rxs_dmamap); 818 } 819 fail_4: 820 for (i = 0; i < PCN_TXQUEUELEN; i++) { 821 if (sc->sc_txsoft[i].txs_dmamap != NULL) 822 bus_dmamap_destroy(sc->sc_dmat, 823 sc->sc_txsoft[i].txs_dmamap); 824 } 825 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 826 fail_3: 827 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 828 fail_2: 829 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 830 sizeof(struct pcn_control_data)); 831 fail_1: 832 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 833 fail_0: 834 return; 835 } 836 837 /* 838 * pcn_shutdown: 839 * 840 * Make sure the interface is stopped at reboot time. 841 */ 842 void 843 pcn_shutdown(void *arg) 844 { 845 struct pcn_softc *sc = arg; 846 847 pcn_stop(&sc->sc_ethercom.ec_if, 1); 848 } 849 850 /* 851 * pcn_start: [ifnet interface function] 852 * 853 * Start packet transmission on the interface. 854 */ 855 void 856 pcn_start(struct ifnet *ifp) 857 { 858 struct pcn_softc *sc = ifp->if_softc; 859 struct mbuf *m0, *m; 860 struct pcn_txsoft *txs; 861 bus_dmamap_t dmamap; 862 int error, nexttx, lasttx, ofree, seg; 863 864 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 865 return; 866 867 /* 868 * Remember the previous number of free descriptors and 869 * the first descriptor we'll use. 870 */ 871 ofree = sc->sc_txfree; 872 873 /* 874 * Loop through the send queue, setting up transmit descriptors 875 * until we drain the queue, or use up all available transmit 876 * descriptors. 877 */ 878 for (;;) { 879 /* Grab a packet off the queue. */ 880 IFQ_POLL(&ifp->if_snd, m0); 881 if (m0 == NULL) 882 break; 883 m = NULL; 884 885 /* Get a work queue entry. */ 886 if (sc->sc_txsfree == 0) { 887 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 888 break; 889 } 890 891 txs = &sc->sc_txsoft[sc->sc_txsnext]; 892 dmamap = txs->txs_dmamap; 893 894 /* 895 * Load the DMA map. If this fails, the packet either 896 * didn't fit in the alloted number of segments, or we 897 * were short on resources. In this case, we'll copy 898 * and try again. 899 */ 900 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 901 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 902 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 903 MGETHDR(m, M_DONTWAIT, MT_DATA); 904 if (m == NULL) { 905 printf("%s: unable to allocate Tx mbuf\n", 906 sc->sc_dev.dv_xname); 907 break; 908 } 909 if (m0->m_pkthdr.len > MHLEN) { 910 MCLGET(m, M_DONTWAIT); 911 if ((m->m_flags & M_EXT) == 0) { 912 printf("%s: unable to allocate Tx " 913 "cluster\n", sc->sc_dev.dv_xname); 914 m_freem(m); 915 break; 916 } 917 } 918 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 919 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 920 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 921 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 922 if (error) { 923 printf("%s: unable to load Tx buffer, " 924 "error = %d\n", sc->sc_dev.dv_xname, error); 925 break; 926 } 927 } 928 929 /* 930 * Ensure we have enough descriptors free to describe 931 * the packet. Note, we always reserve one descriptor 932 * at the end of the ring as a termination point, to 933 * prevent wrap-around. 934 */ 935 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 936 /* 937 * Not enough free descriptors to transmit this 938 * packet. We haven't committed anything yet, 939 * so just unload the DMA map, put the packet 940 * back on the queue, and punt. Notify the upper 941 * layer that there are not more slots left. 942 * 943 * XXX We could allocate an mbuf and copy, but 944 * XXX is it worth it? 945 */ 946 ifp->if_flags |= IFF_OACTIVE; 947 bus_dmamap_unload(sc->sc_dmat, dmamap); 948 if (m != NULL) 949 m_freem(m); 950 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 951 break; 952 } 953 954 IFQ_DEQUEUE(&ifp->if_snd, m0); 955 if (m != NULL) { 956 m_freem(m0); 957 m0 = m; 958 } 959 960 /* 961 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 962 */ 963 964 /* Sync the DMA map. */ 965 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 966 BUS_DMASYNC_PREWRITE); 967 968 #ifdef PCN_EVENT_COUNTERS 969 switch (dmamap->dm_nsegs) { 970 case 1: 971 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 972 break; 973 case 2: 974 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 975 break; 976 case 3: 977 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 978 break; 979 case 4: 980 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 981 break; 982 case 5: 983 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 984 break; 985 default: 986 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 987 break; 988 } 989 #endif /* PCN_EVENT_COUNTERS */ 990 991 /* 992 * Initialize the transmit descriptors. 993 */ 994 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 995 for (nexttx = sc->sc_txnext, seg = 0; 996 seg < dmamap->dm_nsegs; 997 seg++, nexttx = PCN_NEXTTX(nexttx)) { 998 /* 999 * If this is the first descriptor we're 1000 * enqueueing, don't set the OWN bit just 1001 * yet. That could cause a race condition. 1002 * We'll do it below. 1003 */ 1004 sc->sc_txdescs[nexttx].tmd0 = 0; 1005 sc->sc_txdescs[nexttx].tmd2 = 1006 htole32(dmamap->dm_segs[seg].ds_addr); 1007 sc->sc_txdescs[nexttx].tmd1 = 1008 htole32(LE_T1_ONES | 1009 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1010 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1011 LE_T1_BCNT_MASK)); 1012 lasttx = nexttx; 1013 } 1014 } else { 1015 for (nexttx = sc->sc_txnext, seg = 0; 1016 seg < dmamap->dm_nsegs; 1017 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1018 /* 1019 * If this is the first descriptor we're 1020 * enqueueing, don't set the OWN bit just 1021 * yet. That could cause a race condition. 1022 * We'll do it below. 1023 */ 1024 sc->sc_txdescs[nexttx].tmd0 = 1025 htole32(dmamap->dm_segs[seg].ds_addr); 1026 sc->sc_txdescs[nexttx].tmd2 = 0; 1027 sc->sc_txdescs[nexttx].tmd1 = 1028 htole32(LE_T1_ONES | 1029 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1030 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1031 LE_T1_BCNT_MASK)); 1032 lasttx = nexttx; 1033 } 1034 } 1035 1036 /* Interrupt on the packet, if appropriate. */ 1037 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1038 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1039 1040 /* Set `start of packet' and `end of packet' appropriately. */ 1041 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1042 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1043 htole32(LE_T1_OWN|LE_T1_STP); 1044 1045 /* Sync the descriptors we're using. */ 1046 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1047 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1048 1049 /* Kick the transmitter. */ 1050 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1051 1052 /* 1053 * Store a pointer to the packet so we can free it later, 1054 * and remember what txdirty will be once the packet is 1055 * done. 1056 */ 1057 txs->txs_mbuf = m0; 1058 txs->txs_firstdesc = sc->sc_txnext; 1059 txs->txs_lastdesc = lasttx; 1060 1061 /* Advance the tx pointer. */ 1062 sc->sc_txfree -= dmamap->dm_nsegs; 1063 sc->sc_txnext = nexttx; 1064 1065 sc->sc_txsfree--; 1066 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1067 1068 #if NBPFILTER > 0 1069 /* Pass the packet to any BPF listeners. */ 1070 if (ifp->if_bpf) 1071 bpf_mtap(ifp->if_bpf, m0); 1072 #endif /* NBPFILTER > 0 */ 1073 } 1074 1075 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1076 /* No more slots left; notify upper layer. */ 1077 ifp->if_flags |= IFF_OACTIVE; 1078 } 1079 1080 if (sc->sc_txfree != ofree) { 1081 /* Set a watchdog timer in case the chip flakes out. */ 1082 ifp->if_timer = 5; 1083 } 1084 } 1085 1086 /* 1087 * pcn_watchdog: [ifnet interface function] 1088 * 1089 * Watchdog timer handler. 1090 */ 1091 void 1092 pcn_watchdog(struct ifnet *ifp) 1093 { 1094 struct pcn_softc *sc = ifp->if_softc; 1095 1096 /* 1097 * Since we're not interrupting every packet, sweep 1098 * up before we report an error. 1099 */ 1100 pcn_txintr(sc); 1101 1102 if (sc->sc_txfree != PCN_NTXDESC) { 1103 printf("%s: device timeout (txfree %d txsfree %d)\n", 1104 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1105 ifp->if_oerrors++; 1106 1107 /* Reset the interface. */ 1108 (void) pcn_init(ifp); 1109 } 1110 1111 /* Try to get more packets going. */ 1112 pcn_start(ifp); 1113 } 1114 1115 /* 1116 * pcn_ioctl: [ifnet interface function] 1117 * 1118 * Handle control requests from the operator. 1119 */ 1120 int 1121 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1122 { 1123 struct pcn_softc *sc = ifp->if_softc; 1124 struct ifreq *ifr = (struct ifreq *) data; 1125 int s, error; 1126 1127 s = splnet(); 1128 1129 switch (cmd) { 1130 case SIOCSIFMEDIA: 1131 case SIOCGIFMEDIA: 1132 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1133 break; 1134 1135 default: 1136 error = ether_ioctl(ifp, cmd, data); 1137 if (error == ENETRESET) { 1138 /* 1139 * Multicast list has changed; set the hardware filter 1140 * accordingly. 1141 */ 1142 error = pcn_init(ifp); 1143 } 1144 break; 1145 } 1146 1147 /* Try to get more packets going. */ 1148 pcn_start(ifp); 1149 1150 splx(s); 1151 return (error); 1152 } 1153 1154 /* 1155 * pcn_intr: 1156 * 1157 * Interrupt service routine. 1158 */ 1159 int 1160 pcn_intr(void *arg) 1161 { 1162 struct pcn_softc *sc = arg; 1163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1164 uint32_t csr0; 1165 int wantinit, handled = 0; 1166 1167 for (wantinit = 0; wantinit == 0;) { 1168 csr0 = pcn_csr_read(sc, LE_CSR0); 1169 if ((csr0 & LE_C0_INTR) == 0) 1170 break; 1171 1172 /* ACK the bits and re-enable interrupts. */ 1173 pcn_csr_write(sc, LE_CSR0, csr0 & 1174 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1175 LE_C0_TINT|LE_C0_IDON)); 1176 1177 handled = 1; 1178 1179 if (csr0 & LE_C0_RINT) { 1180 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1181 wantinit = pcn_rxintr(sc); 1182 } 1183 1184 if (csr0 & LE_C0_TINT) { 1185 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1186 pcn_txintr(sc); 1187 } 1188 1189 if (csr0 & LE_C0_ERR) { 1190 if (csr0 & LE_C0_BABL) { 1191 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1192 ifp->if_oerrors++; 1193 } 1194 if (csr0 & LE_C0_MISS) { 1195 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1196 ifp->if_ierrors++; 1197 } 1198 if (csr0 & LE_C0_MERR) { 1199 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1200 printf("%s: memory error\n", 1201 sc->sc_dev.dv_xname); 1202 wantinit = 1; 1203 break; 1204 } 1205 } 1206 1207 if ((csr0 & LE_C0_RXON) == 0) { 1208 printf("%s: receiver disabled\n", 1209 sc->sc_dev.dv_xname); 1210 ifp->if_ierrors++; 1211 wantinit = 1; 1212 } 1213 1214 if ((csr0 & LE_C0_TXON) == 0) { 1215 printf("%s: transmitter disabled\n", 1216 sc->sc_dev.dv_xname); 1217 ifp->if_oerrors++; 1218 wantinit = 1; 1219 } 1220 } 1221 1222 if (handled) { 1223 if (wantinit) 1224 pcn_init(ifp); 1225 1226 /* Try to get more packets going. */ 1227 pcn_start(ifp); 1228 } 1229 1230 return (handled); 1231 } 1232 1233 /* 1234 * pcn_spnd: 1235 * 1236 * Suspend the chip. 1237 */ 1238 void 1239 pcn_spnd(struct pcn_softc *sc) 1240 { 1241 int i; 1242 1243 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1244 1245 for (i = 0; i < 10000; i++) { 1246 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1247 return; 1248 delay(5); 1249 } 1250 1251 printf("%s: WARNING: chip failed to enter suspended state\n", 1252 sc->sc_dev.dv_xname); 1253 } 1254 1255 /* 1256 * pcn_txintr: 1257 * 1258 * Helper; handle transmit interrupts. 1259 */ 1260 void 1261 pcn_txintr(struct pcn_softc *sc) 1262 { 1263 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1264 struct pcn_txsoft *txs; 1265 uint32_t tmd1, tmd2, tmd; 1266 int i, j; 1267 1268 ifp->if_flags &= ~IFF_OACTIVE; 1269 1270 /* 1271 * Go through our Tx list and free mbufs for those 1272 * frames which have been transmitted. 1273 */ 1274 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1275 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1276 txs = &sc->sc_txsoft[i]; 1277 1278 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1279 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1280 1281 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1282 if (tmd1 & LE_T1_OWN) 1283 break; 1284 1285 /* 1286 * Slightly annoying -- we have to loop through the 1287 * descriptors we've used looking for ERR, since it 1288 * can appear on any descriptor in the chain. 1289 */ 1290 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1291 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1292 if (tmd & LE_T1_ERR) { 1293 ifp->if_oerrors++; 1294 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1295 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1296 else 1297 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1298 if (tmd2 & LE_T2_UFLO) { 1299 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1300 sc->sc_xmtsp++; 1301 printf("%s: transmit " 1302 "underrun; new threshold: " 1303 "%s\n", 1304 sc->sc_dev.dv_xname, 1305 sc->sc_xmtsp_desc[ 1306 sc->sc_xmtsp]); 1307 pcn_spnd(sc); 1308 pcn_csr_write(sc, LE_CSR80, 1309 LE_C80_RCVFW(sc->sc_rcvfw) | 1310 LE_C80_XMTSP(sc->sc_xmtsp) | 1311 LE_C80_XMTFW(sc->sc_xmtfw)); 1312 pcn_csr_write(sc, LE_CSR5, 1313 sc->sc_csr5); 1314 } else { 1315 printf("%s: transmit " 1316 "underrun\n", 1317 sc->sc_dev.dv_xname); 1318 } 1319 } else if (tmd2 & LE_T2_BUFF) { 1320 printf("%s: transmit buffer error\n", 1321 sc->sc_dev.dv_xname); 1322 } 1323 if (tmd2 & LE_T2_LCOL) 1324 ifp->if_collisions++; 1325 if (tmd2 & LE_T2_RTRY) 1326 ifp->if_collisions += 16; 1327 goto next_packet; 1328 } 1329 if (j == txs->txs_lastdesc) 1330 break; 1331 } 1332 if (tmd1 & LE_T1_ONE) 1333 ifp->if_collisions++; 1334 else if (tmd & LE_T1_MORE) { 1335 /* Real number is unknown. */ 1336 ifp->if_collisions += 2; 1337 } 1338 ifp->if_opackets++; 1339 next_packet: 1340 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1341 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1342 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1343 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1344 m_freem(txs->txs_mbuf); 1345 txs->txs_mbuf = NULL; 1346 } 1347 1348 /* Update the dirty transmit buffer pointer. */ 1349 sc->sc_txsdirty = i; 1350 1351 /* 1352 * If there are no more pending transmissions, cancel the watchdog 1353 * timer. 1354 */ 1355 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1356 ifp->if_timer = 0; 1357 } 1358 1359 /* 1360 * pcn_rxintr: 1361 * 1362 * Helper; handle receive interrupts. 1363 */ 1364 int 1365 pcn_rxintr(struct pcn_softc *sc) 1366 { 1367 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1368 struct pcn_rxsoft *rxs; 1369 struct mbuf *m; 1370 uint32_t rmd1; 1371 int i, len; 1372 1373 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1374 rxs = &sc->sc_rxsoft[i]; 1375 1376 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1377 1378 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1379 1380 if (rmd1 & LE_R1_OWN) 1381 break; 1382 1383 /* 1384 * Check for errors and make sure the packet fit into 1385 * a single buffer. We have structured this block of 1386 * code the way it is in order to compress it into 1387 * one test in the common case (no error). 1388 */ 1389 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1390 (LE_R1_STP|LE_R1_ENP))) { 1391 /* Make sure the packet is in a single buffer. */ 1392 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1393 (LE_R1_STP|LE_R1_ENP)) { 1394 printf("%s: packet spilled into next buffer\n", 1395 sc->sc_dev.dv_xname); 1396 return (1); /* pcn_intr() will re-init */ 1397 } 1398 1399 /* 1400 * If the packet had an error, simple recycle the 1401 * buffer. 1402 */ 1403 if (rmd1 & LE_R1_ERR) { 1404 ifp->if_ierrors++; 1405 /* 1406 * If we got an overflow error, chances 1407 * are there will be a CRC error. In 1408 * this case, just print the overflow 1409 * error, and skip the others. 1410 */ 1411 if (rmd1 & LE_R1_OFLO) 1412 printf("%s: overflow error\n", 1413 sc->sc_dev.dv_xname); 1414 else { 1415 #define PRINTIT(x, str) \ 1416 if (rmd1 & (x)) \ 1417 printf("%s: %s\n", \ 1418 sc->sc_dev.dv_xname, str); 1419 PRINTIT(LE_R1_FRAM, "framing error"); 1420 PRINTIT(LE_R1_CRC, "CRC error"); 1421 PRINTIT(LE_R1_BUFF, "buffer error"); 1422 } 1423 #undef PRINTIT 1424 PCN_INIT_RXDESC(sc, i); 1425 continue; 1426 } 1427 } 1428 1429 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1430 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1431 1432 /* 1433 * No errors; receive the packet. 1434 */ 1435 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1436 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1437 else 1438 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1439 1440 /* 1441 * The LANCE family includes the CRC with every packet; 1442 * trim it off here. 1443 */ 1444 len -= ETHER_CRC_LEN; 1445 1446 /* 1447 * If the packet is small enough to fit in a 1448 * single header mbuf, allocate one and copy 1449 * the data into it. This greatly reduces 1450 * memory consumption when we receive lots 1451 * of small packets. 1452 * 1453 * Otherwise, we add a new buffer to the receive 1454 * chain. If this fails, we drop the packet and 1455 * recycle the old buffer. 1456 */ 1457 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1458 MGETHDR(m, M_DONTWAIT, MT_DATA); 1459 if (m == NULL) 1460 goto dropit; 1461 m->m_data += 2; 1462 memcpy(mtod(m, caddr_t), 1463 mtod(rxs->rxs_mbuf, caddr_t), len); 1464 PCN_INIT_RXDESC(sc, i); 1465 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1466 rxs->rxs_dmamap->dm_mapsize, 1467 BUS_DMASYNC_PREREAD); 1468 } else { 1469 m = rxs->rxs_mbuf; 1470 if (pcn_add_rxbuf(sc, i) != 0) { 1471 dropit: 1472 ifp->if_ierrors++; 1473 PCN_INIT_RXDESC(sc, i); 1474 bus_dmamap_sync(sc->sc_dmat, 1475 rxs->rxs_dmamap, 0, 1476 rxs->rxs_dmamap->dm_mapsize, 1477 BUS_DMASYNC_PREREAD); 1478 continue; 1479 } 1480 } 1481 1482 m->m_pkthdr.rcvif = ifp; 1483 m->m_pkthdr.len = m->m_len = len; 1484 1485 #if NBPFILTER > 0 1486 /* Pass this up to any BPF listeners. */ 1487 if (ifp->if_bpf) 1488 bpf_mtap(ifp->if_bpf, m); 1489 #endif /* NBPFILTER > 0 */ 1490 1491 /* Pass it on. */ 1492 (*ifp->if_input)(ifp, m); 1493 ifp->if_ipackets++; 1494 } 1495 1496 /* Update the receive pointer. */ 1497 sc->sc_rxptr = i; 1498 return (0); 1499 } 1500 1501 /* 1502 * pcn_tick: 1503 * 1504 * One second timer, used to tick the MII. 1505 */ 1506 void 1507 pcn_tick(void *arg) 1508 { 1509 struct pcn_softc *sc = arg; 1510 int s; 1511 1512 s = splnet(); 1513 mii_tick(&sc->sc_mii); 1514 splx(s); 1515 1516 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1517 } 1518 1519 /* 1520 * pcn_reset: 1521 * 1522 * Perform a soft reset on the PCnet-PCI. 1523 */ 1524 void 1525 pcn_reset(struct pcn_softc *sc) 1526 { 1527 1528 /* 1529 * The PCnet-PCI chip is reset by reading from the 1530 * RESET register. Note that while the NE2100 LANCE 1531 * boards require a write after the read, the PCnet-PCI 1532 * chips do not require this. 1533 * 1534 * Since we don't know if we're in 16-bit or 32-bit 1535 * mode right now, issue both (it's safe) in the 1536 * hopes that one will succeed. 1537 */ 1538 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1539 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1540 1541 /* Wait 1ms for it to finish. */ 1542 delay(1000); 1543 1544 /* 1545 * Select 32-bit I/O mode by issuing a 32-bit write to the 1546 * RDP. Since the RAP is 0 after a reset, writing a 0 1547 * to RDP is safe (since it simply clears CSR0). 1548 */ 1549 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1550 } 1551 1552 /* 1553 * pcn_init: [ifnet interface function] 1554 * 1555 * Initialize the interface. Must be called at splnet(). 1556 */ 1557 int 1558 pcn_init(struct ifnet *ifp) 1559 { 1560 struct pcn_softc *sc = ifp->if_softc; 1561 struct pcn_rxsoft *rxs; 1562 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1563 int i, error = 0; 1564 uint32_t reg; 1565 1566 /* Cancel any pending I/O. */ 1567 pcn_stop(ifp, 0); 1568 1569 /* Reset the chip to a known state. */ 1570 pcn_reset(sc); 1571 1572 /* 1573 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1574 * else. 1575 * 1576 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1577 * because the structure layout is compatible with ILACC, 1578 * but the burst mode is only available in SSTYLE 3, and 1579 * burst mode should provide some performance enhancement. 1580 */ 1581 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1582 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1583 else 1584 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1585 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1586 1587 /* Initialize the transmit descriptor ring. */ 1588 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1589 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1590 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1591 sc->sc_txfree = PCN_NTXDESC; 1592 sc->sc_txnext = 0; 1593 1594 /* Initialize the transmit job descriptors. */ 1595 for (i = 0; i < PCN_TXQUEUELEN; i++) 1596 sc->sc_txsoft[i].txs_mbuf = NULL; 1597 sc->sc_txsfree = PCN_TXQUEUELEN; 1598 sc->sc_txsnext = 0; 1599 sc->sc_txsdirty = 0; 1600 1601 /* 1602 * Initialize the receive descriptor and receive job 1603 * descriptor rings. 1604 */ 1605 for (i = 0; i < PCN_NRXDESC; i++) { 1606 rxs = &sc->sc_rxsoft[i]; 1607 if (rxs->rxs_mbuf == NULL) { 1608 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1609 printf("%s: unable to allocate or map rx " 1610 "buffer %d, error = %d\n", 1611 sc->sc_dev.dv_xname, i, error); 1612 /* 1613 * XXX Should attempt to run with fewer receive 1614 * XXX buffers instead of just failing. 1615 */ 1616 pcn_rxdrain(sc); 1617 goto out; 1618 } 1619 } else 1620 PCN_INIT_RXDESC(sc, i); 1621 } 1622 sc->sc_rxptr = 0; 1623 1624 /* Initialize MODE for the initialization block. */ 1625 sc->sc_mode = 0; 1626 if (ifp->if_flags & IFF_PROMISC) 1627 sc->sc_mode |= LE_C15_PROM; 1628 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1629 sc->sc_mode |= LE_C15_DRCVBC; 1630 1631 /* 1632 * If we have MII, simply select MII in the MODE register, 1633 * and clear ASEL. Otherwise, let ASEL stand (for now), 1634 * and leave PORTSEL alone (it is ignored with ASEL is set). 1635 */ 1636 if (sc->sc_flags & PCN_F_HAS_MII) { 1637 pcn_bcr_write(sc, LE_BCR2, 1638 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1639 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1640 1641 /* 1642 * Disable MII auto-negotiation. We handle that in 1643 * our own MII layer. 1644 */ 1645 pcn_bcr_write(sc, LE_BCR32, 1646 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1647 } 1648 1649 /* 1650 * Set the Tx and Rx descriptor ring addresses in the init 1651 * block, the TLEN and RLEN other fields of the init block 1652 * MODE register. 1653 */ 1654 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1655 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1656 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1657 ((ffs(PCN_NTXDESC) - 1) << 28) | 1658 ((ffs(PCN_NRXDESC) - 1) << 20)); 1659 1660 /* Set the station address in the init block. */ 1661 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1662 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1663 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1664 (enaddr[5] << 8)); 1665 1666 /* Set the multicast filter in the init block. */ 1667 pcn_set_filter(sc); 1668 1669 /* Initialize CSR3. */ 1670 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1671 1672 /* Initialize CSR4. */ 1673 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1674 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1675 1676 /* Initialize CSR5. */ 1677 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1678 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1679 1680 /* 1681 * If we have an Am79c971 or greater, initialize CSR7. 1682 * 1683 * XXX Might be nice to use the MII auto-poll interrupt someday. 1684 */ 1685 switch (sc->sc_variant->pcv_chipid) { 1686 case PARTID_Am79c970: 1687 case PARTID_Am79c970A: 1688 /* Not available on these chips. */ 1689 break; 1690 1691 default: 1692 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1693 break; 1694 } 1695 1696 /* 1697 * On the Am79c970A and greater, initialize BCR18 to 1698 * enable burst mode. 1699 * 1700 * Also enable the "no underflow" option on the Am79c971 and 1701 * higher, which prevents the chip from generating transmit 1702 * underflows, yet sill provides decent performance. Note if 1703 * chip is not connected to external SRAM, then we still have 1704 * to handle underflow errors (the NOUFLO bit is ignored in 1705 * that case). 1706 */ 1707 reg = pcn_bcr_read(sc, LE_BCR18); 1708 switch (sc->sc_variant->pcv_chipid) { 1709 case PARTID_Am79c970: 1710 break; 1711 1712 case PARTID_Am79c970A: 1713 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1714 break; 1715 1716 default: 1717 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1718 break; 1719 } 1720 pcn_bcr_write(sc, LE_BCR18, reg); 1721 1722 /* 1723 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1724 */ 1725 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1726 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1727 1728 /* 1729 * Send the init block to the chip, and wait for it 1730 * to be processed. 1731 */ 1732 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1733 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1734 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1735 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1736 delay(100); 1737 for (i = 0; i < 10000; i++) { 1738 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1739 break; 1740 delay(10); 1741 } 1742 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1743 if (i == 10000) { 1744 printf("%s: timeout processing init block\n", 1745 sc->sc_dev.dv_xname); 1746 error = EIO; 1747 goto out; 1748 } 1749 1750 /* Set the media. */ 1751 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1752 1753 /* Enable interrupts and external activity (and ACK IDON). */ 1754 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1755 1756 if (sc->sc_flags & PCN_F_HAS_MII) { 1757 /* Start the one second MII clock. */ 1758 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1759 } 1760 1761 /* ...all done! */ 1762 ifp->if_flags |= IFF_RUNNING; 1763 ifp->if_flags &= ~IFF_OACTIVE; 1764 1765 out: 1766 if (error) 1767 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1768 return (error); 1769 } 1770 1771 /* 1772 * pcn_rxdrain: 1773 * 1774 * Drain the receive queue. 1775 */ 1776 void 1777 pcn_rxdrain(struct pcn_softc *sc) 1778 { 1779 struct pcn_rxsoft *rxs; 1780 int i; 1781 1782 for (i = 0; i < PCN_NRXDESC; i++) { 1783 rxs = &sc->sc_rxsoft[i]; 1784 if (rxs->rxs_mbuf != NULL) { 1785 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1786 m_freem(rxs->rxs_mbuf); 1787 rxs->rxs_mbuf = NULL; 1788 } 1789 } 1790 } 1791 1792 /* 1793 * pcn_stop: [ifnet interface function] 1794 * 1795 * Stop transmission on the interface. 1796 */ 1797 void 1798 pcn_stop(struct ifnet *ifp, int disable) 1799 { 1800 struct pcn_softc *sc = ifp->if_softc; 1801 struct pcn_txsoft *txs; 1802 int i; 1803 1804 if (sc->sc_flags & PCN_F_HAS_MII) { 1805 /* Stop the one second clock. */ 1806 callout_stop(&sc->sc_tick_ch); 1807 1808 /* Down the MII. */ 1809 mii_down(&sc->sc_mii); 1810 } 1811 1812 /* Stop the chip. */ 1813 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1814 1815 /* Release any queued transmit buffers. */ 1816 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1817 txs = &sc->sc_txsoft[i]; 1818 if (txs->txs_mbuf != NULL) { 1819 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1820 m_freem(txs->txs_mbuf); 1821 txs->txs_mbuf = NULL; 1822 } 1823 } 1824 1825 if (disable) 1826 pcn_rxdrain(sc); 1827 1828 /* Mark the interface as down and cancel the watchdog timer. */ 1829 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1830 ifp->if_timer = 0; 1831 } 1832 1833 /* 1834 * pcn_add_rxbuf: 1835 * 1836 * Add a receive buffer to the indicated descriptor. 1837 */ 1838 int 1839 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1840 { 1841 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1842 struct mbuf *m; 1843 int error; 1844 1845 MGETHDR(m, M_DONTWAIT, MT_DATA); 1846 if (m == NULL) 1847 return (ENOBUFS); 1848 1849 MCLGET(m, M_DONTWAIT); 1850 if ((m->m_flags & M_EXT) == 0) { 1851 m_freem(m); 1852 return (ENOBUFS); 1853 } 1854 1855 if (rxs->rxs_mbuf != NULL) 1856 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1857 1858 rxs->rxs_mbuf = m; 1859 1860 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1861 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1862 BUS_DMA_READ|BUS_DMA_NOWAIT); 1863 if (error) { 1864 printf("%s: can't load rx DMA map %d, error = %d\n", 1865 sc->sc_dev.dv_xname, idx, error); 1866 panic("pcn_add_rxbuf"); 1867 } 1868 1869 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1870 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1871 1872 PCN_INIT_RXDESC(sc, idx); 1873 1874 return (0); 1875 } 1876 1877 /* 1878 * pcn_set_filter: 1879 * 1880 * Set up the receive filter. 1881 */ 1882 void 1883 pcn_set_filter(struct pcn_softc *sc) 1884 { 1885 struct ethercom *ec = &sc->sc_ethercom; 1886 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1887 struct ether_multi *enm; 1888 struct ether_multistep step; 1889 uint32_t crc; 1890 1891 /* 1892 * Set up the multicast address filter by passing all multicast 1893 * addresses through a CRC generator, and then using the high 1894 * order 6 bits as an index into the 64-bit logical address 1895 * filter. The high order bits select the word, while the rest 1896 * of the bits select the bit within the word. 1897 */ 1898 1899 if (ifp->if_flags & IFF_PROMISC) 1900 goto allmulti; 1901 1902 sc->sc_initblock.init_ladrf[0] = 1903 sc->sc_initblock.init_ladrf[1] = 1904 sc->sc_initblock.init_ladrf[2] = 1905 sc->sc_initblock.init_ladrf[3] = 0; 1906 1907 ETHER_FIRST_MULTI(step, ec, enm); 1908 while (enm != NULL) { 1909 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1910 /* 1911 * We must listen to a range of multicast addresses. 1912 * For now, just accept all multicasts, rather than 1913 * trying to set only those filter bits needed to match 1914 * the range. (At this time, the only use of address 1915 * ranges is for IP multicast routing, for which the 1916 * range is big enough to require all bits set.) 1917 */ 1918 goto allmulti; 1919 } 1920 1921 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1922 1923 /* Just want the 6 most significant bits. */ 1924 crc >>= 26; 1925 1926 /* Set the corresponding bit in the filter. */ 1927 sc->sc_initblock.init_ladrf[crc >> 4] |= 1928 htole16(1 << (crc & 0xf)); 1929 1930 ETHER_NEXT_MULTI(step, enm); 1931 } 1932 1933 ifp->if_flags &= ~IFF_ALLMULTI; 1934 return; 1935 1936 allmulti: 1937 ifp->if_flags |= IFF_ALLMULTI; 1938 sc->sc_initblock.init_ladrf[0] = 1939 sc->sc_initblock.init_ladrf[1] = 1940 sc->sc_initblock.init_ladrf[2] = 1941 sc->sc_initblock.init_ladrf[3] = 0xffff; 1942 } 1943 1944 /* 1945 * pcn_79c970_mediainit: 1946 * 1947 * Initialize media for the Am79c970. 1948 */ 1949 void 1950 pcn_79c970_mediainit(struct pcn_softc *sc) 1951 { 1952 const char *sep = ""; 1953 1954 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 1955 pcn_79c970_mediastatus); 1956 1957 #define ADD(str, m, d) \ 1958 do { \ 1959 printf("%s%s", sep, str); \ 1960 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 1961 sep = ", "; \ 1962 } while (/*CONSTCOND*/0) 1963 1964 printf("%s: ", sc->sc_dev.dv_xname); 1965 ADD("10base5", IFM_10_5, PORTSEL_AUI); 1966 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1967 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 1968 ADD("10baseT", IFM_10_T, PORTSEL_10T); 1969 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1970 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 1971 ADD("auto", IFM_AUTO, 0); 1972 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1973 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 1974 printf("\n"); 1975 1976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1977 } 1978 1979 /* 1980 * pcn_79c970_mediastatus: [ifmedia interface function] 1981 * 1982 * Get the current interface media status (Am79c970 version). 1983 */ 1984 void 1985 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1986 { 1987 struct pcn_softc *sc = ifp->if_softc; 1988 1989 /* 1990 * The currently selected media is always the active media. 1991 * Note: We have no way to determine what media the AUTO 1992 * process picked. 1993 */ 1994 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1995 } 1996 1997 /* 1998 * pcn_79c970_mediachange: [ifmedia interface function] 1999 * 2000 * Set hardware to newly-selected media (Am79c970 version). 2001 */ 2002 int 2003 pcn_79c970_mediachange(struct ifnet *ifp) 2004 { 2005 struct pcn_softc *sc = ifp->if_softc; 2006 uint32_t reg; 2007 2008 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2009 /* 2010 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2011 */ 2012 reg = pcn_bcr_read(sc, LE_BCR2); 2013 reg |= LE_B2_ASEL; 2014 pcn_bcr_write(sc, LE_BCR2, reg); 2015 } else { 2016 /* 2017 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2018 */ 2019 reg = pcn_bcr_read(sc, LE_BCR2); 2020 reg &= ~LE_B2_ASEL; 2021 pcn_bcr_write(sc, LE_BCR2, reg); 2022 2023 reg = pcn_csr_read(sc, LE_CSR15); 2024 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2025 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2026 pcn_csr_write(sc, LE_CSR15, reg); 2027 } 2028 2029 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2030 reg = LE_B9_FDEN; 2031 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2032 reg |= LE_B9_AUIFD; 2033 pcn_bcr_write(sc, LE_BCR9, reg); 2034 } else 2035 pcn_bcr_write(sc, LE_BCR9, 0); 2036 2037 return (0); 2038 } 2039 2040 /* 2041 * pcn_79c971_mediainit: 2042 * 2043 * Initialize media for the Am79c971. 2044 */ 2045 void 2046 pcn_79c971_mediainit(struct pcn_softc *sc) 2047 { 2048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2049 2050 /* We have MII. */ 2051 sc->sc_flags |= PCN_F_HAS_MII; 2052 2053 /* 2054 * The built-in 10BASE-T interface is mapped to the MII 2055 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2056 * word that tells us which PHY to use. Since the 10BASE-T 2057 * interface is always at PHY 31, we make a note of the 2058 * first PHY that responds, and disallow any PHYs after 2059 * it. This is all handled in the MII read routine. 2060 */ 2061 sc->sc_phyaddr = -1; 2062 2063 /* Initialize our media structures and probe the MII. */ 2064 sc->sc_mii.mii_ifp = ifp; 2065 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2066 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2067 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2068 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2069 pcn_79c971_mediastatus); 2070 2071 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2072 MII_OFFSET_ANY, 0); 2073 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2074 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2075 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2076 } else 2077 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2078 } 2079 2080 /* 2081 * pcn_79c971_mediastatus: [ifmedia interface function] 2082 * 2083 * Get the current interface media status (Am79c971 version). 2084 */ 2085 void 2086 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2087 { 2088 struct pcn_softc *sc = ifp->if_softc; 2089 2090 mii_pollstat(&sc->sc_mii); 2091 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2092 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2093 } 2094 2095 /* 2096 * pcn_79c971_mediachange: [ifmedia interface function] 2097 * 2098 * Set hardware to newly-selected media (Am79c971 version). 2099 */ 2100 int 2101 pcn_79c971_mediachange(struct ifnet *ifp) 2102 { 2103 struct pcn_softc *sc = ifp->if_softc; 2104 2105 if (ifp->if_flags & IFF_UP) 2106 mii_mediachg(&sc->sc_mii); 2107 return (0); 2108 } 2109 2110 /* 2111 * pcn_mii_readreg: [mii interface function] 2112 * 2113 * Read a PHY register on the MII. 2114 */ 2115 int 2116 pcn_mii_readreg(struct device *self, int phy, int reg) 2117 { 2118 struct pcn_softc *sc = (void *) self; 2119 uint32_t rv; 2120 2121 if (sc->sc_phyaddr != -1 && phy != sc->sc_phyaddr) 2122 return (0); 2123 2124 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2125 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2126 if (rv == 0xffff) 2127 return (0); 2128 2129 if (sc->sc_phyaddr == -1) 2130 sc->sc_phyaddr = phy; 2131 2132 return (rv); 2133 } 2134 2135 /* 2136 * pcn_mii_writereg: [mii interface function] 2137 * 2138 * Write a PHY register on the MII. 2139 */ 2140 void 2141 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2142 { 2143 struct pcn_softc *sc = (void *) self; 2144 2145 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2146 pcn_bcr_write(sc, LE_BCR34, val); 2147 } 2148 2149 /* 2150 * pcn_mii_statchg: [mii interface function] 2151 * 2152 * Callback from MII layer when media changes. 2153 */ 2154 void 2155 pcn_mii_statchg(struct device *self) 2156 { 2157 struct pcn_softc *sc = (void *) self; 2158 2159 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2160 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2161 else 2162 pcn_bcr_write(sc, LE_BCR9, 0); 2163 } 2164