1 /* $NetBSD: if_msk.c,v 1.18 2008/04/10 19:13:37 cegger Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.18 2008/04/10 19:13:37 cegger Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/device.h> 68 #include <sys/queue.h> 69 #include <sys/callout.h> 70 #include <sys/sysctl.h> 71 #include <sys/endian.h> 72 #ifdef __NetBSD__ 73 #define letoh16 htole16 74 #define letoh32 htole32 75 #endif 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 81 #include <net/if_media.h> 82 83 #if NBPFILTER > 0 84 #include <net/bpf.h> 85 #endif 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 #include <dev/mii/brgphyreg.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/pci/if_skreg.h> 99 #include <dev/pci/if_mskvar.h> 100 101 int mskc_probe(struct device *, struct cfdata *, void *); 102 void mskc_attach(struct device *, struct device *self, void *aux); 103 void mskc_shutdown(void *); 104 int msk_probe(struct device *, struct cfdata *, void *); 105 void msk_attach(struct device *, struct device *self, void *aux); 106 int mskcprint(void *, const char *); 107 int msk_intr(void *); 108 void msk_intr_yukon(struct sk_if_softc *); 109 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 110 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 111 void msk_txeof(struct sk_if_softc *, int); 112 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 113 void msk_start(struct ifnet *); 114 int msk_ioctl(struct ifnet *, u_long, void *); 115 int msk_init(struct ifnet *); 116 void msk_init_yukon(struct sk_if_softc *); 117 void msk_stop(struct ifnet *, int); 118 void msk_watchdog(struct ifnet *); 119 void msk_reset(struct sk_softc *); 120 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 121 int msk_alloc_jumbo_mem(struct sk_if_softc *); 122 void *msk_jalloc(struct sk_if_softc *); 123 void msk_jfree(struct mbuf *, void *, size_t, void *); 124 int msk_init_rx_ring(struct sk_if_softc *); 125 int msk_init_tx_ring(struct sk_if_softc *); 126 127 void msk_update_int_mod(struct sk_softc *); 128 129 int msk_miibus_readreg(struct device *, int, int); 130 void msk_miibus_writereg(struct device *, int, int, int); 131 void msk_miibus_statchg(struct device *); 132 133 void msk_setfilt(struct sk_if_softc *, void *, int); 134 void msk_setmulti(struct sk_if_softc *); 135 void msk_setpromisc(struct sk_if_softc *); 136 void msk_tick(void *); 137 138 /* #define MSK_DEBUG 1 */ 139 #ifdef MSK_DEBUG 140 #define DPRINTF(x) if (mskdebug) printf x 141 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 142 int mskdebug = MSK_DEBUG; 143 144 void msk_dump_txdesc(struct msk_tx_desc *, int); 145 void msk_dump_mbuf(struct mbuf *); 146 void msk_dump_bytes(const char *, int); 147 #else 148 #define DPRINTF(x) 149 #define DPRINTFN(n,x) 150 #endif 151 152 static int msk_sysctl_handler(SYSCTLFN_PROTO); 153 static int msk_root_num; 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 188 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 189 }; 190 191 static inline u_int32_t 192 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_4(sc, reg); 195 } 196 197 static inline u_int16_t 198 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 199 { 200 return CSR_READ_2(sc, reg); 201 } 202 203 static inline u_int8_t 204 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 205 { 206 return CSR_READ_1(sc, reg); 207 } 208 209 static inline void 210 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 211 { 212 CSR_WRITE_4(sc, reg, x); 213 } 214 215 static inline void 216 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 217 { 218 CSR_WRITE_2(sc, reg, x); 219 } 220 221 static inline void 222 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 223 { 224 CSR_WRITE_1(sc, reg, x); 225 } 226 227 int 228 msk_miibus_readreg(struct device *dev, int phy, int reg) 229 { 230 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 231 u_int16_t val; 232 int i; 233 234 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 235 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 236 237 for (i = 0; i < SK_TIMEOUT; i++) { 238 DELAY(1); 239 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 240 if (val & YU_SMICR_READ_VALID) 241 break; 242 } 243 244 if (i == SK_TIMEOUT) { 245 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 246 return (0); 247 } 248 249 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 250 SK_TIMEOUT)); 251 252 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 253 254 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 255 phy, reg, val)); 256 257 return (val); 258 } 259 260 void 261 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 262 { 263 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 264 int i; 265 266 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 267 phy, reg, val)); 268 269 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 270 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 271 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 272 273 for (i = 0; i < SK_TIMEOUT; i++) { 274 DELAY(1); 275 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 276 break; 277 } 278 279 if (i == SK_TIMEOUT) 280 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 281 } 282 283 void 284 msk_miibus_statchg(struct device *dev) 285 { 286 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 287 struct mii_data *mii = &sc_if->sk_mii; 288 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 289 int gpcr; 290 291 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 292 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 293 294 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 295 /* Set speed. */ 296 gpcr |= YU_GPCR_SPEED_DIS; 297 switch (IFM_SUBTYPE(mii->mii_media_active)) { 298 case IFM_1000_SX: 299 case IFM_1000_LX: 300 case IFM_1000_CX: 301 case IFM_1000_T: 302 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 303 break; 304 case IFM_100_TX: 305 gpcr |= YU_GPCR_SPEED; 306 break; 307 } 308 309 /* Set duplex. */ 310 gpcr |= YU_GPCR_DPLX_DIS; 311 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 312 gpcr |= YU_GPCR_DUPLEX; 313 314 /* Disable flow control. */ 315 gpcr |= YU_GPCR_FCTL_DIS; 316 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 317 } 318 319 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 320 321 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 322 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 323 } 324 325 #define HASH_BITS 6 326 327 void 328 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 329 { 330 char *addr = addrv; 331 int base = XM_RXFILT_ENTRY(slot); 332 333 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 334 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 335 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 336 } 337 338 void 339 msk_setmulti(struct sk_if_softc *sc_if) 340 { 341 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 342 u_int32_t hashes[2] = { 0, 0 }; 343 int h; 344 struct ethercom *ec = &sc_if->sk_ethercom; 345 struct ether_multi *enm; 346 struct ether_multistep step; 347 u_int16_t reg; 348 349 /* First, zot all the existing filters. */ 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 354 355 356 /* Now program new ones. */ 357 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 358 reg |= YU_RCR_UFLEN; 359 allmulti: 360 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 361 if ((ifp->if_flags & IFF_PROMISC) != 0) 362 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 363 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 364 hashes[0] = 0xFFFFFFFF; 365 hashes[1] = 0xFFFFFFFF; 366 } 367 } else { 368 /* First find the tail of the list. */ 369 ETHER_FIRST_MULTI(step, ec, enm); 370 while (enm != NULL) { 371 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 372 ETHER_ADDR_LEN)) { 373 ifp->if_flags |= IFF_ALLMULTI; 374 goto allmulti; 375 } 376 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 377 ((1 << HASH_BITS) - 1); 378 if (h < 32) 379 hashes[0] |= (1 << h); 380 else 381 hashes[1] |= (1 << (h - 32)); 382 383 ETHER_NEXT_MULTI(step, enm); 384 } 385 reg |= YU_RCR_MUFLEN; 386 } 387 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 393 } 394 395 void 396 msk_setpromisc(struct sk_if_softc *sc_if) 397 { 398 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 399 400 if (ifp->if_flags & IFF_PROMISC) 401 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 402 YU_RCR_UFLEN | YU_RCR_MUFLEN); 403 else 404 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 405 YU_RCR_UFLEN | YU_RCR_MUFLEN); 406 } 407 408 int 409 msk_init_rx_ring(struct sk_if_softc *sc_if) 410 { 411 struct msk_chain_data *cd = &sc_if->sk_cdata; 412 struct msk_ring_data *rd = sc_if->sk_rdata; 413 int i, nexti; 414 415 bzero((char *)rd->sk_rx_ring, 416 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 417 418 for (i = 0; i < MSK_RX_RING_CNT; i++) { 419 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 420 if (i == (MSK_RX_RING_CNT - 1)) 421 nexti = 0; 422 else 423 nexti = i + 1; 424 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 425 } 426 427 for (i = 0; i < MSK_RX_RING_CNT; i++) { 428 if (msk_newbuf(sc_if, i, NULL, 429 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 430 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 431 return (ENOBUFS); 432 } 433 } 434 435 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 436 sc_if->sk_cdata.sk_rx_cons = 0; 437 438 return (0); 439 } 440 441 int 442 msk_init_tx_ring(struct sk_if_softc *sc_if) 443 { 444 struct sk_softc *sc = sc_if->sk_softc; 445 struct msk_chain_data *cd = &sc_if->sk_cdata; 446 struct msk_ring_data *rd = sc_if->sk_rdata; 447 bus_dmamap_t dmamap; 448 struct sk_txmap_entry *entry; 449 int i, nexti; 450 451 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 452 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 453 454 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 455 for (i = 0; i < MSK_TX_RING_CNT; i++) { 456 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 457 if (i == (MSK_TX_RING_CNT - 1)) 458 nexti = 0; 459 else 460 nexti = i + 1; 461 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 462 463 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 464 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 465 return (ENOBUFS); 466 467 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 468 if (!entry) { 469 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 470 return (ENOBUFS); 471 } 472 entry->dmamap = dmamap; 473 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 474 } 475 476 sc_if->sk_cdata.sk_tx_prod = 0; 477 sc_if->sk_cdata.sk_tx_cons = 0; 478 sc_if->sk_cdata.sk_tx_cnt = 0; 479 480 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 481 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 482 483 return (0); 484 } 485 486 int 487 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 488 bus_dmamap_t dmamap) 489 { 490 struct mbuf *m_new = NULL; 491 struct sk_chain *c; 492 struct msk_rx_desc *r; 493 494 if (m == NULL) { 495 void *buf = NULL; 496 497 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 498 if (m_new == NULL) 499 return (ENOBUFS); 500 501 /* Allocate the jumbo buffer */ 502 buf = msk_jalloc(sc_if); 503 if (buf == NULL) { 504 m_freem(m_new); 505 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 506 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 507 return (ENOBUFS); 508 } 509 510 /* Attach the buffer to the mbuf */ 511 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 512 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 513 } else { 514 /* 515 * We're re-using a previously allocated mbuf; 516 * be sure to re-init pointers and lengths to 517 * default values. 518 */ 519 m_new = m; 520 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 521 m_new->m_data = m_new->m_ext.ext_buf; 522 } 523 m_adj(m_new, ETHER_ALIGN); 524 525 c = &sc_if->sk_cdata.sk_rx_chain[i]; 526 r = c->sk_le; 527 c->sk_mbuf = m_new; 528 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 529 (((vaddr_t)m_new->m_data 530 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 531 r->sk_len = htole16(SK_JLEN); 532 r->sk_ctl = 0; 533 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 534 535 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 536 537 return (0); 538 } 539 540 /* 541 * Memory management for jumbo frames. 542 */ 543 544 int 545 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 546 { 547 struct sk_softc *sc = sc_if->sk_softc; 548 char *ptr, *kva; 549 bus_dma_segment_t seg; 550 int i, rseg, state, error; 551 struct sk_jpool_entry *entry; 552 553 state = error = 0; 554 555 /* Grab a big chunk o' storage. */ 556 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 557 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 558 aprint_error(": can't alloc rx buffers"); 559 return (ENOBUFS); 560 } 561 562 state = 1; 563 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 564 BUS_DMA_NOWAIT)) { 565 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 566 error = ENOBUFS; 567 goto out; 568 } 569 570 state = 2; 571 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 572 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 573 aprint_error(": can't create dma map"); 574 error = ENOBUFS; 575 goto out; 576 } 577 578 state = 3; 579 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 580 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 581 aprint_error(": can't load dma map"); 582 error = ENOBUFS; 583 goto out; 584 } 585 586 state = 4; 587 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 588 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 589 590 LIST_INIT(&sc_if->sk_jfree_listhead); 591 LIST_INIT(&sc_if->sk_jinuse_listhead); 592 593 /* 594 * Now divide it up into 9K pieces and save the addresses 595 * in an array. 596 */ 597 ptr = sc_if->sk_cdata.sk_jumbo_buf; 598 for (i = 0; i < MSK_JSLOTS; i++) { 599 sc_if->sk_cdata.sk_jslots[i] = ptr; 600 ptr += SK_JLEN; 601 entry = malloc(sizeof(struct sk_jpool_entry), 602 M_DEVBUF, M_NOWAIT); 603 if (entry == NULL) { 604 sc_if->sk_cdata.sk_jumbo_buf = NULL; 605 aprint_error(": no memory for jumbo buffer queue!"); 606 error = ENOBUFS; 607 goto out; 608 } 609 entry->slot = i; 610 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 611 entry, jpool_entries); 612 } 613 out: 614 if (error != 0) { 615 switch (state) { 616 case 4: 617 bus_dmamap_unload(sc->sc_dmatag, 618 sc_if->sk_cdata.sk_rx_jumbo_map); 619 case 3: 620 bus_dmamap_destroy(sc->sc_dmatag, 621 sc_if->sk_cdata.sk_rx_jumbo_map); 622 case 2: 623 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 624 case 1: 625 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 626 break; 627 default: 628 break; 629 } 630 } 631 632 return (error); 633 } 634 635 /* 636 * Allocate a jumbo buffer. 637 */ 638 void * 639 msk_jalloc(struct sk_if_softc *sc_if) 640 { 641 struct sk_jpool_entry *entry; 642 643 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 644 645 if (entry == NULL) 646 return (NULL); 647 648 LIST_REMOVE(entry, jpool_entries); 649 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 650 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 651 } 652 653 /* 654 * Release a jumbo buffer. 655 */ 656 void 657 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 658 { 659 struct sk_jpool_entry *entry; 660 struct sk_if_softc *sc; 661 int i, s; 662 663 /* Extract the softc struct pointer. */ 664 sc = (struct sk_if_softc *)arg; 665 666 if (sc == NULL) 667 panic("msk_jfree: can't find softc pointer!"); 668 669 /* calculate the slot this buffer belongs to */ 670 i = ((vaddr_t)buf 671 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 672 673 if ((i < 0) || (i >= MSK_JSLOTS)) 674 panic("msk_jfree: asked to free buffer that we don't manage!"); 675 676 s = splvm(); 677 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 678 if (entry == NULL) 679 panic("msk_jfree: buffer not in use!"); 680 entry->slot = i; 681 LIST_REMOVE(entry, jpool_entries); 682 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 683 684 if (__predict_true(m != NULL)) 685 pool_cache_put(mb_cache, m); 686 splx(s); 687 } 688 689 int 690 msk_ioctl(struct ifnet *ifp, u_long command, void *data) 691 { 692 struct sk_if_softc *sc_if = ifp->if_softc; 693 struct ifreq *ifr = (struct ifreq *) data; 694 int s, error = 0; 695 696 s = splnet(); 697 698 switch(command) { 699 case SIOCSIFMTU: 700 if (ifr->ifr_mtu < ETHERMIN) 701 return EINVAL; 702 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) { 703 if (ifr->ifr_mtu > SK_JUMBO_MTU) 704 error = EINVAL; 705 } else if (ifr->ifr_mtu > ETHERMTU) 706 error = EINVAL; 707 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET) 708 error = 0; 709 break; 710 default: 711 DPRINTFN(2, ("msk_ioctl ETHER\n")); 712 error = ether_ioctl(ifp, command, data); 713 714 if (error == ENETRESET) { 715 /* 716 * Multicast list has changed; set the hardware 717 * filter accordingly. 718 */ 719 if (ifp->if_flags & IFF_RUNNING) 720 msk_setmulti(sc_if); 721 error = 0; 722 } 723 break; 724 } 725 726 splx(s); 727 return (error); 728 } 729 730 void 731 msk_update_int_mod(struct sk_softc *sc) 732 { 733 u_int32_t imtimer_ticks; 734 735 /* 736 * Configure interrupt moderation. The moderation timer 737 * defers interrupts specified in the interrupt moderation 738 * timer mask based on the timeout specified in the interrupt 739 * moderation timer init register. Each bit in the timer 740 * register represents one tick, so to specify a timeout in 741 * microseconds, we have to multiply by the correct number of 742 * ticks-per-microsecond. 743 */ 744 switch (sc->sk_type) { 745 case SK_YUKON_EC: 746 case SK_YUKON_EC_U: 747 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 748 break; 749 case SK_YUKON_FE: 750 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 751 break; 752 case SK_YUKON_XL: 753 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 754 break; 755 default: 756 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 757 } 758 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 759 sc->sk_int_mod); 760 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 761 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 762 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 763 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 764 sc->sk_int_mod_pending = 0; 765 } 766 767 static int 768 msk_lookup(const struct pci_attach_args *pa) 769 { 770 const struct msk_product *pmsk; 771 772 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 773 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 774 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 775 return 1; 776 } 777 return 0; 778 } 779 780 /* 781 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 782 * IDs against our list and return a device name if we find a match. 783 */ 784 int 785 mskc_probe(struct device *parent, struct cfdata *match, 786 void *aux) 787 { 788 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 789 790 return msk_lookup(pa); 791 } 792 793 /* 794 * Force the GEnesis into reset, then bring it out of reset. 795 */ 796 void msk_reset(struct sk_softc *sc) 797 { 798 u_int32_t imtimer_ticks, reg1; 799 int reg; 800 801 DPRINTFN(2, ("msk_reset\n")); 802 803 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 804 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 805 806 DELAY(1000); 807 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 808 DELAY(2); 809 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 810 sk_win_write_1(sc, SK_TESTCTL1, 2); 811 812 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 813 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 814 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 815 else 816 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 817 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 818 819 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 820 sk_win_write_1(sc, SK_Y2_CLKGATE, 821 SK_Y2_CLKGATE_LINK1_GATE_DIS | 822 SK_Y2_CLKGATE_LINK2_GATE_DIS | 823 SK_Y2_CLKGATE_LINK1_CORE_DIS | 824 SK_Y2_CLKGATE_LINK2_CORE_DIS | 825 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 826 else 827 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 828 829 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 830 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 831 DELAY(1000); 832 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 833 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 834 835 sk_win_write_1(sc, SK_TESTCTL1, 1); 836 837 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 838 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 839 CSR_READ_2(sc, SK_LINK_CTRL))); 840 841 /* Disable ASF */ 842 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 843 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 844 845 /* Clear I2C IRQ noise */ 846 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 847 848 /* Disable hardware timer */ 849 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 850 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 851 852 /* Disable descriptor polling */ 853 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 854 855 /* Disable time stamps */ 856 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 857 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 858 859 /* Enable RAM interface */ 860 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 861 for (reg = SK_TO0;reg <= SK_TO11; reg++) 862 sk_win_write_1(sc, reg, 36); 863 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 864 for (reg = SK_TO0;reg <= SK_TO11; reg++) 865 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 866 867 /* 868 * Configure interrupt moderation. The moderation timer 869 * defers interrupts specified in the interrupt moderation 870 * timer mask based on the timeout specified in the interrupt 871 * moderation timer init register. Each bit in the timer 872 * register represents one tick, so to specify a timeout in 873 * microseconds, we have to multiply by the correct number of 874 * ticks-per-microsecond. 875 */ 876 switch (sc->sk_type) { 877 case SK_YUKON_EC: 878 case SK_YUKON_EC_U: 879 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 880 break; 881 case SK_YUKON_FE: 882 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 883 break; 884 case SK_YUKON_XL: 885 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 886 break; 887 default: 888 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 889 } 890 891 /* Reset status ring. */ 892 bzero((char *)sc->sk_status_ring, 893 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 894 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 895 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 896 sc->sk_status_idx = 0; 897 sc->sk_status_own_idx = 0; 898 899 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 900 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 901 902 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 903 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 904 sc->sk_status_map->dm_segs[0].ds_addr); 905 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 906 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 907 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 908 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 909 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 910 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 911 } else { 912 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 913 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 914 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 915 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 916 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 917 } 918 919 #if 0 920 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 921 #endif 922 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 923 924 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 925 926 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 927 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 928 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 929 930 msk_update_int_mod(sc); 931 } 932 933 int 934 msk_probe(struct device *parent, struct cfdata *match, 935 void *aux) 936 { 937 struct skc_attach_args *sa = aux; 938 939 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 940 return (0); 941 942 switch (sa->skc_type) { 943 case SK_YUKON_XL: 944 case SK_YUKON_EC_U: 945 case SK_YUKON_EC: 946 case SK_YUKON_FE: 947 return (1); 948 } 949 950 return (0); 951 } 952 953 /* 954 * Each XMAC chip is attached as a separate logical IP interface. 955 * Single port cards will have only one logical interface of course. 956 */ 957 void 958 msk_attach(struct device *parent, struct device *self, void *aux) 959 { 960 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 961 struct sk_softc *sc = (struct sk_softc *)parent; 962 struct skc_attach_args *sa = aux; 963 struct ifnet *ifp; 964 void *kva; 965 bus_dma_segment_t seg; 966 int i, rseg; 967 u_int32_t chunk, val; 968 969 sc_if->sk_port = sa->skc_port; 970 sc_if->sk_softc = sc; 971 sc->sk_if[sa->skc_port] = sc_if; 972 973 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 974 975 /* 976 * Get station address for this interface. Note that 977 * dual port cards actually come with three station 978 * addresses: one for each port, plus an extra. The 979 * extra one is used by the SysKonnect driver software 980 * as a 'virtual' station address for when both ports 981 * are operating in failover mode. Currently we don't 982 * use this extra address. 983 */ 984 for (i = 0; i < ETHER_ADDR_LEN; i++) 985 sc_if->sk_enaddr[i] = 986 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 987 988 aprint_normal(": Ethernet address %s\n", 989 ether_sprintf(sc_if->sk_enaddr)); 990 991 /* 992 * Set up RAM buffer addresses. The NIC will have a certain 993 * amount of SRAM on it, somewhere between 512K and 2MB. We 994 * need to divide this up a) between the transmitter and 995 * receiver and b) between the two XMACs, if this is a 996 * dual port NIC. Our algorithm is to divide up the memory 997 * evenly so that everyone gets a fair share. 998 * 999 * Just to be contrary, Yukon2 appears to have separate memory 1000 * for each MAC. 1001 */ 1002 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1003 val = sc->sk_rboff / sizeof(u_int64_t); 1004 sc_if->sk_rx_ramstart = val; 1005 val += (chunk / sizeof(u_int64_t)); 1006 sc_if->sk_rx_ramend = val - 1; 1007 chunk = sc->sk_ramsize - chunk; 1008 sc_if->sk_tx_ramstart = val; 1009 val += (chunk / sizeof(u_int64_t)); 1010 sc_if->sk_tx_ramend = val - 1; 1011 1012 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1013 " tx_ramstart=%#x tx_ramend=%#x\n", 1014 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1015 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1016 1017 /* Allocate the descriptor queues. */ 1018 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1019 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1020 aprint_error(": can't alloc rx buffers\n"); 1021 goto fail; 1022 } 1023 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1024 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1025 aprint_error(": can't map dma buffers (%zu bytes)\n", 1026 sizeof(struct msk_ring_data)); 1027 goto fail_1; 1028 } 1029 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1030 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1031 &sc_if->sk_ring_map)) { 1032 aprint_error(": can't create dma map\n"); 1033 goto fail_2; 1034 } 1035 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1036 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1037 aprint_error(": can't load dma map\n"); 1038 goto fail_3; 1039 } 1040 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1041 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1042 1043 ifp = &sc_if->sk_ethercom.ec_if; 1044 /* Try to allocate memory for jumbo buffers. */ 1045 if (msk_alloc_jumbo_mem(sc_if)) { 1046 aprint_error(": jumbo buffer allocation failed\n"); 1047 goto fail_3; 1048 } 1049 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1050 | ETHERCAP_JUMBO_MTU; 1051 1052 ifp->if_softc = sc_if; 1053 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1054 ifp->if_ioctl = msk_ioctl; 1055 ifp->if_start = msk_start; 1056 ifp->if_stop = msk_stop; 1057 ifp->if_init = msk_init; 1058 ifp->if_watchdog = msk_watchdog; 1059 ifp->if_baudrate = 1000000000; 1060 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1061 IFQ_SET_READY(&ifp->if_snd); 1062 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1063 1064 /* 1065 * Do miibus setup. 1066 */ 1067 msk_init_yukon(sc_if); 1068 1069 DPRINTFN(2, ("msk_attach: 1\n")); 1070 1071 sc_if->sk_mii.mii_ifp = ifp; 1072 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1073 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1074 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1075 1076 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1077 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1078 ether_mediachange, ether_mediastatus); 1079 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1080 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1081 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1082 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1083 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1084 0, NULL); 1085 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1086 } else 1087 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1088 1089 callout_init(&sc_if->sk_tick_ch, 0); 1090 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1091 callout_schedule(&sc_if->sk_tick_ch, hz); 1092 1093 /* 1094 * Call MI attach routines. 1095 */ 1096 if_attach(ifp); 1097 ether_ifattach(ifp, sc_if->sk_enaddr); 1098 1099 shutdownhook_establish(mskc_shutdown, sc); 1100 1101 #if NRND > 0 1102 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1103 RND_TYPE_NET, 0); 1104 #endif 1105 1106 DPRINTFN(2, ("msk_attach: end\n")); 1107 return; 1108 1109 fail_3: 1110 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1111 fail_2: 1112 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1113 fail_1: 1114 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1115 fail: 1116 sc->sk_if[sa->skc_port] = NULL; 1117 } 1118 1119 int 1120 mskcprint(void *aux, const char *pnp) 1121 { 1122 struct skc_attach_args *sa = aux; 1123 1124 if (pnp) 1125 aprint_normal("sk port %c at %s", 1126 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1127 else 1128 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1129 return (UNCONF); 1130 } 1131 1132 /* 1133 * Attach the interface. Allocate softc structures, do ifmedia 1134 * setup and ethernet/BPF attach. 1135 */ 1136 void 1137 mskc_attach(struct device *parent, struct device *self, void *aux) 1138 { 1139 struct sk_softc *sc = (struct sk_softc *)self; 1140 struct pci_attach_args *pa = aux; 1141 struct skc_attach_args skca; 1142 pci_chipset_tag_t pc = pa->pa_pc; 1143 pcireg_t command, memtype; 1144 pci_intr_handle_t ih; 1145 const char *intrstr = NULL; 1146 bus_size_t size; 1147 int rc, sk_nodenum; 1148 u_int8_t hw, skrs; 1149 const char *revstr = NULL; 1150 const struct sysctlnode *node; 1151 void *kva; 1152 bus_dma_segment_t seg; 1153 int rseg; 1154 1155 DPRINTFN(2, ("begin mskc_attach\n")); 1156 1157 /* 1158 * Handle power management nonsense. 1159 */ 1160 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1161 1162 if (command == 0x01) { 1163 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1164 if (command & SK_PSTATE_MASK) { 1165 u_int32_t iobase, membase, irq; 1166 1167 /* Save important PCI config data. */ 1168 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1169 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1170 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1171 1172 /* Reset the power state. */ 1173 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1174 "-- setting to D0\n", 1175 command & SK_PSTATE_MASK); 1176 command &= 0xFFFFFFFC; 1177 pci_conf_write(pc, pa->pa_tag, 1178 SK_PCI_PWRMGMTCTRL, command); 1179 1180 /* Restore PCI config data. */ 1181 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1182 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1183 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1184 } 1185 } 1186 1187 /* 1188 * Map control/status registers. 1189 */ 1190 1191 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1192 switch (memtype) { 1193 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1194 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1195 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1196 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1197 NULL, &size) == 0) 1198 break; 1199 default: 1200 aprint_error(": can't map mem space\n"); 1201 return; 1202 } 1203 1204 sc->sc_dmatag = pa->pa_dmat; 1205 1206 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1207 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1208 1209 /* bail out here if chip is not recognized */ 1210 if (!(SK_IS_YUKON2(sc))) { 1211 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1212 goto fail_1; 1213 } 1214 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1215 1216 /* Allocate interrupt */ 1217 if (pci_intr_map(pa, &ih)) { 1218 aprint_error(": couldn't map interrupt\n"); 1219 goto fail_1; 1220 } 1221 1222 intrstr = pci_intr_string(pc, ih); 1223 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1224 if (sc->sk_intrhand == NULL) { 1225 aprint_error(": couldn't establish interrupt"); 1226 if (intrstr != NULL) 1227 aprint_error(" at %s", intrstr); 1228 aprint_error("\n"); 1229 goto fail_1; 1230 } 1231 1232 if (bus_dmamem_alloc(sc->sc_dmatag, 1233 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1234 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1235 aprint_error(": can't alloc status buffers\n"); 1236 goto fail_2; 1237 } 1238 1239 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1240 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1241 &kva, BUS_DMA_NOWAIT)) { 1242 aprint_error(": can't map dma buffers (%zu bytes)\n", 1243 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1244 goto fail_3; 1245 } 1246 if (bus_dmamap_create(sc->sc_dmatag, 1247 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1248 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1249 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1250 aprint_error(": can't create dma map\n"); 1251 goto fail_4; 1252 } 1253 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1254 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1255 NULL, BUS_DMA_NOWAIT)) { 1256 aprint_error(": can't load dma map\n"); 1257 goto fail_5; 1258 } 1259 sc->sk_status_ring = (struct msk_status_desc *)kva; 1260 1261 /* Reset the adapter. */ 1262 msk_reset(sc); 1263 1264 skrs = sk_win_read_1(sc, SK_EPROM0); 1265 if (skrs == 0x00) 1266 sc->sk_ramsize = 0x20000; 1267 else 1268 sc->sk_ramsize = skrs * (1<<12); 1269 sc->sk_rboff = SK_RBOFF_0; 1270 1271 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1272 sc->sk_ramsize, sc->sk_ramsize / 1024, 1273 sc->sk_rboff)); 1274 1275 switch (sc->sk_type) { 1276 case SK_YUKON_XL: 1277 sc->sk_name = "Yukon-2 XL"; 1278 break; 1279 case SK_YUKON_EC_U: 1280 sc->sk_name = "Yukon-2 EC Ultra"; 1281 break; 1282 case SK_YUKON_EC: 1283 sc->sk_name = "Yukon-2 EC"; 1284 break; 1285 case SK_YUKON_FE: 1286 sc->sk_name = "Yukon-2 FE"; 1287 break; 1288 default: 1289 sc->sk_name = "Yukon (Unknown)"; 1290 } 1291 1292 if (sc->sk_type == SK_YUKON_XL) { 1293 switch (sc->sk_rev) { 1294 case SK_YUKON_XL_REV_A0: 1295 sc->sk_workaround = 0; 1296 revstr = "A0"; 1297 break; 1298 case SK_YUKON_XL_REV_A1: 1299 sc->sk_workaround = SK_WA_4109; 1300 revstr = "A1"; 1301 break; 1302 case SK_YUKON_XL_REV_A2: 1303 sc->sk_workaround = SK_WA_4109; 1304 revstr = "A2"; 1305 break; 1306 case SK_YUKON_XL_REV_A3: 1307 sc->sk_workaround = SK_WA_4109; 1308 revstr = "A3"; 1309 break; 1310 default: 1311 sc->sk_workaround = 0; 1312 break; 1313 } 1314 } 1315 1316 if (sc->sk_type == SK_YUKON_EC) { 1317 switch (sc->sk_rev) { 1318 case SK_YUKON_EC_REV_A1: 1319 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1320 revstr = "A1"; 1321 break; 1322 case SK_YUKON_EC_REV_A2: 1323 sc->sk_workaround = SK_WA_4109; 1324 revstr = "A2"; 1325 break; 1326 case SK_YUKON_EC_REV_A3: 1327 sc->sk_workaround = SK_WA_4109; 1328 revstr = "A3"; 1329 break; 1330 default: 1331 sc->sk_workaround = 0; 1332 break; 1333 } 1334 } 1335 1336 if (sc->sk_type == SK_YUKON_FE) { 1337 sc->sk_workaround = SK_WA_4109; 1338 switch (sc->sk_rev) { 1339 case SK_YUKON_FE_REV_A1: 1340 revstr = "A1"; 1341 break; 1342 case SK_YUKON_FE_REV_A2: 1343 revstr = "A2"; 1344 break; 1345 default: 1346 sc->sk_workaround = 0; 1347 break; 1348 } 1349 } 1350 1351 if (sc->sk_type == SK_YUKON_EC_U) { 1352 sc->sk_workaround = SK_WA_4109; 1353 switch (sc->sk_rev) { 1354 case SK_YUKON_EC_U_REV_A0: 1355 revstr = "A0"; 1356 break; 1357 case SK_YUKON_EC_U_REV_A1: 1358 revstr = "A1"; 1359 break; 1360 case SK_YUKON_EC_U_REV_B0: 1361 revstr = "B0"; 1362 break; 1363 default: 1364 sc->sk_workaround = 0; 1365 break; 1366 } 1367 } 1368 1369 /* Announce the product name. */ 1370 aprint_normal(", %s", sc->sk_name); 1371 if (revstr != NULL) 1372 aprint_normal(" rev. %s", revstr); 1373 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1374 1375 sc->sk_macs = 1; 1376 1377 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1378 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1379 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1380 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1381 sc->sk_macs++; 1382 } 1383 1384 skca.skc_port = SK_PORT_A; 1385 skca.skc_type = sc->sk_type; 1386 skca.skc_rev = sc->sk_rev; 1387 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1388 1389 if (sc->sk_macs > 1) { 1390 skca.skc_port = SK_PORT_B; 1391 skca.skc_type = sc->sk_type; 1392 skca.skc_rev = sc->sk_rev; 1393 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1394 } 1395 1396 /* Turn on the 'driver is loaded' LED. */ 1397 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1398 1399 /* skc sysctl setup */ 1400 1401 sc->sk_int_mod = SK_IM_DEFAULT; 1402 sc->sk_int_mod_pending = 0; 1403 1404 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1405 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1406 SYSCTL_DESCR("mskc per-controller controls"), 1407 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1408 CTL_EOL)) != 0) { 1409 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1410 goto fail_6; 1411 } 1412 1413 sk_nodenum = node->sysctl_num; 1414 1415 /* interrupt moderation time in usecs */ 1416 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1417 CTLFLAG_READWRITE, 1418 CTLTYPE_INT, "int_mod", 1419 SYSCTL_DESCR("msk interrupt moderation timer"), 1420 msk_sysctl_handler, 0, sc, 1421 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1422 CTL_EOL)) != 0) { 1423 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1424 goto fail_6; 1425 } 1426 1427 return; 1428 1429 fail_6: 1430 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1431 fail_5: 1432 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1433 fail_4: 1434 bus_dmamem_unmap(sc->sc_dmatag, kva, 1435 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1436 fail_3: 1437 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1438 fail_2: 1439 pci_intr_disestablish(pc, sc->sk_intrhand); 1440 fail_1: 1441 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1442 } 1443 1444 int 1445 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1446 { 1447 struct sk_softc *sc = sc_if->sk_softc; 1448 struct msk_tx_desc *f = NULL; 1449 u_int32_t frag, cur; 1450 int i; 1451 struct sk_txmap_entry *entry; 1452 bus_dmamap_t txmap; 1453 1454 DPRINTFN(2, ("msk_encap\n")); 1455 1456 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1457 if (entry == NULL) { 1458 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1459 return (ENOBUFS); 1460 } 1461 txmap = entry->dmamap; 1462 1463 cur = frag = *txidx; 1464 1465 #ifdef MSK_DEBUG 1466 if (mskdebug >= 2) 1467 msk_dump_mbuf(m_head); 1468 #endif 1469 1470 /* 1471 * Start packing the mbufs in this chain into 1472 * the fragment pointers. Stop when we run out 1473 * of fragments or hit the end of the mbuf chain. 1474 */ 1475 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1476 BUS_DMA_NOWAIT)) { 1477 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1478 return (ENOBUFS); 1479 } 1480 1481 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1482 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1483 bus_dmamap_unload(sc->sc_dmatag, txmap); 1484 return (ENOBUFS); 1485 } 1486 1487 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1488 1489 /* Sync the DMA map. */ 1490 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1491 BUS_DMASYNC_PREWRITE); 1492 1493 for (i = 0; i < txmap->dm_nsegs; i++) { 1494 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1495 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1496 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1497 f->sk_ctl = 0; 1498 if (i == 0) 1499 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1500 else 1501 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1502 cur = frag; 1503 SK_INC(frag, MSK_TX_RING_CNT); 1504 } 1505 1506 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1507 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1508 1509 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1510 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1511 1512 /* Sync descriptors before handing to chip */ 1513 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1514 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1515 1516 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1517 1518 /* Sync first descriptor to hand it off */ 1519 MSK_CDTXSYNC(sc_if, *txidx, 1, 1520 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1521 1522 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1523 1524 #ifdef MSK_DEBUG 1525 if (mskdebug >= 2) { 1526 struct msk_tx_desc *le; 1527 u_int32_t idx; 1528 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1529 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1530 msk_dump_txdesc(le, idx); 1531 } 1532 } 1533 #endif 1534 1535 *txidx = frag; 1536 1537 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1538 1539 return (0); 1540 } 1541 1542 void 1543 msk_start(struct ifnet *ifp) 1544 { 1545 struct sk_if_softc *sc_if = ifp->if_softc; 1546 struct mbuf *m_head = NULL; 1547 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1548 int pkts = 0; 1549 1550 DPRINTFN(2, ("msk_start\n")); 1551 1552 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1553 IFQ_POLL(&ifp->if_snd, m_head); 1554 if (m_head == NULL) 1555 break; 1556 1557 /* 1558 * Pack the data into the transmit ring. If we 1559 * don't have room, set the OACTIVE flag and wait 1560 * for the NIC to drain the ring. 1561 */ 1562 if (msk_encap(sc_if, m_head, &idx)) { 1563 ifp->if_flags |= IFF_OACTIVE; 1564 break; 1565 } 1566 1567 /* now we are committed to transmit the packet */ 1568 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1569 pkts++; 1570 1571 /* 1572 * If there's a BPF listener, bounce a copy of this frame 1573 * to him. 1574 */ 1575 #if NBPFILTER > 0 1576 if (ifp->if_bpf) 1577 bpf_mtap(ifp->if_bpf, m_head); 1578 #endif 1579 } 1580 if (pkts == 0) 1581 return; 1582 1583 /* Transmit */ 1584 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1585 sc_if->sk_cdata.sk_tx_prod = idx; 1586 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1587 1588 /* Set a timeout in case the chip goes out to lunch. */ 1589 ifp->if_timer = 5; 1590 } 1591 } 1592 1593 void 1594 msk_watchdog(struct ifnet *ifp) 1595 { 1596 struct sk_if_softc *sc_if = ifp->if_softc; 1597 u_int32_t reg; 1598 int idx; 1599 1600 /* 1601 * Reclaim first as there is a possibility of losing Tx completion 1602 * interrupts. 1603 */ 1604 if (sc_if->sk_port == SK_PORT_A) 1605 reg = SK_STAT_BMU_TXA1_RIDX; 1606 else 1607 reg = SK_STAT_BMU_TXA2_RIDX; 1608 1609 idx = sk_win_read_2(sc_if->sk_softc, reg); 1610 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1611 msk_txeof(sc_if, idx); 1612 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1613 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1614 1615 ifp->if_oerrors++; 1616 1617 /* XXX Resets both ports; we shouldn't do that. */ 1618 msk_reset(sc_if->sk_softc); 1619 msk_init(ifp); 1620 } 1621 } 1622 } 1623 1624 void 1625 mskc_shutdown(void *v) 1626 { 1627 struct sk_softc *sc = v; 1628 1629 DPRINTFN(2, ("msk_shutdown\n")); 1630 1631 /* Turn off the 'driver is loaded' LED. */ 1632 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1633 1634 msk_reset(sc); 1635 } 1636 1637 __inline int 1638 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1639 { 1640 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1641 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1642 YU_RXSTAT_JABBER)) != 0 || 1643 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1644 YU_RXSTAT_BYTES(stat) != len) 1645 return (0); 1646 1647 return (1); 1648 } 1649 1650 void 1651 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1652 { 1653 struct sk_softc *sc = sc_if->sk_softc; 1654 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1655 struct mbuf *m; 1656 struct sk_chain *cur_rx; 1657 int cur, total_len = len; 1658 bus_dmamap_t dmamap; 1659 1660 DPRINTFN(2, ("msk_rxeof\n")); 1661 1662 cur = sc_if->sk_cdata.sk_rx_cons; 1663 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1664 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1665 1666 /* Sync the descriptor */ 1667 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1668 1669 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1670 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1671 1672 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1673 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1674 1675 m = cur_rx->sk_mbuf; 1676 cur_rx->sk_mbuf = NULL; 1677 1678 if (total_len < SK_MIN_FRAMELEN || 1679 total_len > SK_JUMBO_FRAMELEN || 1680 msk_rxvalid(sc, rxstat, total_len) == 0) { 1681 ifp->if_ierrors++; 1682 msk_newbuf(sc_if, cur, m, dmamap); 1683 return; 1684 } 1685 1686 /* 1687 * Try to allocate a new jumbo buffer. If that fails, copy the 1688 * packet to mbufs and put the jumbo buffer back in the ring 1689 * so it can be re-used. If allocating mbufs fails, then we 1690 * have to drop the packet. 1691 */ 1692 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1693 struct mbuf *m0; 1694 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1695 total_len + ETHER_ALIGN, 0, ifp, NULL); 1696 msk_newbuf(sc_if, cur, m, dmamap); 1697 if (m0 == NULL) { 1698 ifp->if_ierrors++; 1699 return; 1700 } 1701 m_adj(m0, ETHER_ALIGN); 1702 m = m0; 1703 } else { 1704 m->m_pkthdr.rcvif = ifp; 1705 m->m_pkthdr.len = m->m_len = total_len; 1706 } 1707 1708 ifp->if_ipackets++; 1709 1710 #if NBPFILTER > 0 1711 if (ifp->if_bpf) 1712 bpf_mtap(ifp->if_bpf, m); 1713 #endif 1714 1715 /* pass it on. */ 1716 (*ifp->if_input)(ifp, m); 1717 } 1718 1719 void 1720 msk_txeof(struct sk_if_softc *sc_if, int idx) 1721 { 1722 struct sk_softc *sc = sc_if->sk_softc; 1723 struct msk_tx_desc *cur_tx; 1724 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1725 u_int32_t sk_ctl; 1726 struct sk_txmap_entry *entry; 1727 int cons, prog; 1728 1729 DPRINTFN(2, ("msk_txeof\n")); 1730 1731 /* 1732 * Go through our tx ring and free mbufs for those 1733 * frames that have been sent. 1734 */ 1735 cons = sc_if->sk_cdata.sk_tx_cons; 1736 prog = 0; 1737 while (cons != idx) { 1738 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1739 break; 1740 prog++; 1741 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1742 1743 MSK_CDTXSYNC(sc_if, cons, 1, 1744 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1745 sk_ctl = cur_tx->sk_ctl; 1746 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1747 #ifdef MSK_DEBUG 1748 if (mskdebug >= 2) 1749 msk_dump_txdesc(cur_tx, cons); 1750 #endif 1751 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1752 ifp->if_opackets++; 1753 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1754 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1755 1756 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1757 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1758 1759 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1760 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1761 link); 1762 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1763 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1764 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1765 } 1766 sc_if->sk_cdata.sk_tx_cnt--; 1767 SK_INC(cons, MSK_TX_RING_CNT); 1768 } 1769 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1770 1771 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1772 ifp->if_flags &= ~IFF_OACTIVE; 1773 1774 if (prog > 0) 1775 sc_if->sk_cdata.sk_tx_cons = cons; 1776 } 1777 1778 void 1779 msk_tick(void *xsc_if) 1780 { 1781 struct sk_if_softc *sc_if = xsc_if; 1782 struct mii_data *mii = &sc_if->sk_mii; 1783 1784 mii_tick(mii); 1785 callout_schedule(&sc_if->sk_tick_ch, hz); 1786 } 1787 1788 void 1789 msk_intr_yukon(struct sk_if_softc *sc_if) 1790 { 1791 u_int8_t status; 1792 1793 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1794 /* RX overrun */ 1795 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1796 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1797 SK_RFCTL_RX_FIFO_OVER); 1798 } 1799 /* TX underrun */ 1800 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1801 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1802 SK_TFCTL_TX_FIFO_UNDER); 1803 } 1804 1805 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1806 } 1807 1808 int 1809 msk_intr(void *xsc) 1810 { 1811 struct sk_softc *sc = xsc; 1812 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1813 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1814 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1815 int claimed = 0; 1816 u_int32_t status; 1817 uint32_t st_status; 1818 uint16_t st_len; 1819 uint8_t st_opcode, st_link; 1820 struct msk_status_desc *cur_st; 1821 1822 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1823 if (status == 0) { 1824 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1825 return (0); 1826 } 1827 1828 status = CSR_READ_4(sc, SK_ISR); 1829 1830 if (sc_if0 != NULL) 1831 ifp0 = &sc_if0->sk_ethercom.ec_if; 1832 if (sc_if1 != NULL) 1833 ifp1 = &sc_if1->sk_ethercom.ec_if; 1834 1835 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1836 (ifp0->if_flags & IFF_RUNNING)) { 1837 msk_intr_yukon(sc_if0); 1838 } 1839 1840 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1841 (ifp1->if_flags & IFF_RUNNING)) { 1842 msk_intr_yukon(sc_if1); 1843 } 1844 1845 for (;;) { 1846 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1847 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1848 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1849 st_opcode = cur_st->sk_opcode; 1850 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1851 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1852 BUS_DMASYNC_PREREAD); 1853 break; 1854 } 1855 st_status = le32toh(cur_st->sk_status); 1856 st_len = le16toh(cur_st->sk_len); 1857 st_link = cur_st->sk_link; 1858 st_opcode &= ~SK_Y2_STOPC_OWN; 1859 1860 switch (st_opcode) { 1861 case SK_Y2_STOPC_RXSTAT: 1862 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1863 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1864 SK_RXQ1_Y2_PREF_PUTIDX, 1865 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1866 break; 1867 case SK_Y2_STOPC_TXSTAT: 1868 if (sc_if0) 1869 msk_txeof(sc_if0, st_status 1870 & SK_Y2_ST_TXA1_MSKL); 1871 if (sc_if1) 1872 msk_txeof(sc_if1, 1873 ((st_status & SK_Y2_ST_TXA2_MSKL) 1874 >> SK_Y2_ST_TXA2_SHIFTL) 1875 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1876 break; 1877 default: 1878 aprint_error("opcode=0x%x\n", st_opcode); 1879 break; 1880 } 1881 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1882 } 1883 1884 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1885 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1886 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1887 1888 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1889 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1890 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1891 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1892 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1893 1894 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1895 } 1896 1897 if (status & SK_Y2_IMR_BMU) { 1898 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1899 claimed = 1; 1900 } 1901 1902 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1903 1904 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1905 msk_start(ifp0); 1906 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1907 msk_start(ifp1); 1908 1909 #if NRND > 0 1910 if (RND_ENABLED(&sc->rnd_source)) 1911 rnd_add_uint32(&sc->rnd_source, status); 1912 #endif 1913 1914 if (sc->sk_int_mod_pending) 1915 msk_update_int_mod(sc); 1916 1917 return claimed; 1918 } 1919 1920 void 1921 msk_init_yukon(struct sk_if_softc *sc_if) 1922 { 1923 u_int32_t v; 1924 u_int16_t reg; 1925 struct sk_softc *sc; 1926 int i; 1927 1928 sc = sc_if->sk_softc; 1929 1930 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1931 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1932 1933 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1934 1935 /* GMAC and GPHY Reset */ 1936 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1937 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1938 DELAY(1000); 1939 1940 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1941 1942 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1943 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1944 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1945 1946 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1947 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1948 1949 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1950 1951 /* unused read of the interrupt source register */ 1952 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1953 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1954 1955 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1956 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1957 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1958 1959 /* MIB Counter Clear Mode set */ 1960 reg |= YU_PAR_MIB_CLR; 1961 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1962 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1963 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1964 1965 /* MIB Counter Clear Mode clear */ 1966 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1967 reg &= ~YU_PAR_MIB_CLR; 1968 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1969 1970 /* receive control reg */ 1971 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1972 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1973 1974 /* transmit control register */ 1975 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1976 1977 /* transmit flow control register */ 1978 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 1979 1980 /* transmit parameter register */ 1981 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1982 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1983 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 1984 1985 /* serial mode register */ 1986 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1987 reg = YU_SMR_DATA_BLIND(0x1c) | 1988 YU_SMR_MFL_VLAN | 1989 YU_SMR_IPG_DATA(0x1e); 1990 1991 if (sc->sk_type != SK_YUKON_FE) 1992 reg |= YU_SMR_MFL_JUMBO; 1993 1994 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1995 1996 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1997 /* Setup Yukon's address */ 1998 for (i = 0; i < 3; i++) { 1999 /* Write Source Address 1 (unicast filter) */ 2000 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2001 sc_if->sk_enaddr[i * 2] | 2002 sc_if->sk_enaddr[i * 2 + 1] << 8); 2003 } 2004 2005 for (i = 0; i < 3; i++) { 2006 reg = sk_win_read_2(sc_if->sk_softc, 2007 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2008 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2009 } 2010 2011 /* Set promiscuous mode */ 2012 msk_setpromisc(sc_if); 2013 2014 /* Set multicast filter */ 2015 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2016 msk_setmulti(sc_if); 2017 2018 /* enable interrupt mask for counter overflows */ 2019 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2020 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2021 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2022 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2023 2024 /* Configure RX MAC FIFO Flush Mask */ 2025 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2026 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2027 YU_RXSTAT_JABBER; 2028 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2029 2030 /* Configure RX MAC FIFO */ 2031 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2032 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2033 SK_RFCTL_FIFO_FLUSH_ON); 2034 2035 /* Increase flush threshould to 64 bytes */ 2036 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2037 SK_RFCTL_FIFO_THRESHOLD + 1); 2038 2039 /* Configure TX MAC FIFO */ 2040 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2041 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2042 2043 #if 1 2044 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2045 #endif 2046 DPRINTFN(6, ("msk_init_yukon: end\n")); 2047 } 2048 2049 /* 2050 * Note that to properly initialize any part of the GEnesis chip, 2051 * you first have to take it out of reset mode. 2052 */ 2053 int 2054 msk_init(struct ifnet *ifp) 2055 { 2056 struct sk_if_softc *sc_if = ifp->if_softc; 2057 struct sk_softc *sc = sc_if->sk_softc; 2058 int rc = 0, s; 2059 uint32_t imr, imtimer_ticks; 2060 2061 2062 DPRINTFN(2, ("msk_init\n")); 2063 2064 s = splnet(); 2065 2066 /* Cancel pending I/O and free all RX/TX buffers. */ 2067 msk_stop(ifp,0); 2068 2069 /* Configure I2C registers */ 2070 2071 /* Configure XMAC(s) */ 2072 msk_init_yukon(sc_if); 2073 if ((rc = ether_mediachange(ifp)) != 0) 2074 goto out; 2075 2076 /* Configure transmit arbiter(s) */ 2077 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2078 #if 0 2079 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2080 #endif 2081 2082 /* Configure RAMbuffers */ 2083 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2084 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2085 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2086 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2087 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2088 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2089 2090 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2091 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2092 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2093 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2094 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2095 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2096 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2097 2098 /* Configure BMUs */ 2099 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2100 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2101 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2102 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2103 2104 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2105 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2106 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2107 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2108 2109 /* Make sure the sync transmit queue is disabled. */ 2110 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2111 2112 /* Init descriptors */ 2113 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2114 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2115 "memory for rx buffers\n"); 2116 msk_stop(ifp,0); 2117 splx(s); 2118 return ENOBUFS; 2119 } 2120 2121 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2122 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2123 "memory for tx buffers\n"); 2124 msk_stop(ifp,0); 2125 splx(s); 2126 return ENOBUFS; 2127 } 2128 2129 /* Set interrupt moderation if changed via sysctl. */ 2130 switch (sc->sk_type) { 2131 case SK_YUKON_EC: 2132 case SK_YUKON_EC_U: 2133 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2134 break; 2135 case SK_YUKON_FE: 2136 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2137 break; 2138 case SK_YUKON_XL: 2139 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2140 break; 2141 default: 2142 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2143 } 2144 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2145 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2146 sk_win_write_4(sc, SK_IMTIMERINIT, 2147 SK_IM_USECS(sc->sk_int_mod)); 2148 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2149 sc->sk_int_mod); 2150 } 2151 2152 /* Initialize prefetch engine. */ 2153 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2154 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2155 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2156 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2157 MSK_RX_RING_ADDR(sc_if, 0)); 2158 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2159 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2160 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2161 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2162 2163 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2164 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2165 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2166 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2167 MSK_TX_RING_ADDR(sc_if, 0)); 2168 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2169 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2170 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2171 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2172 2173 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2174 sc_if->sk_cdata.sk_rx_prod); 2175 2176 /* Configure interrupt handling */ 2177 if (sc_if->sk_port == SK_PORT_A) 2178 sc->sk_intrmask |= SK_Y2_INTRS1; 2179 else 2180 sc->sk_intrmask |= SK_Y2_INTRS2; 2181 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2182 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2183 2184 ifp->if_flags |= IFF_RUNNING; 2185 ifp->if_flags &= ~IFF_OACTIVE; 2186 2187 callout_schedule(&sc_if->sk_tick_ch, hz); 2188 2189 out: 2190 splx(s); 2191 return rc; 2192 } 2193 2194 void 2195 msk_stop(struct ifnet *ifp, int disable) 2196 { 2197 struct sk_if_softc *sc_if = ifp->if_softc; 2198 struct sk_softc *sc = sc_if->sk_softc; 2199 struct sk_txmap_entry *dma; 2200 int i; 2201 2202 DPRINTFN(2, ("msk_stop\n")); 2203 2204 callout_stop(&sc_if->sk_tick_ch); 2205 2206 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2207 2208 /* Stop transfer of Tx descriptors */ 2209 2210 /* Stop transfer of Rx descriptors */ 2211 2212 /* Turn off various components of this interface. */ 2213 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2214 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2215 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2216 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2217 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2218 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2219 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2220 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2221 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2222 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2223 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2224 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2225 2226 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2227 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2228 2229 /* Disable interrupts */ 2230 if (sc_if->sk_port == SK_PORT_A) 2231 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2232 else 2233 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2234 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2235 2236 SK_XM_READ_2(sc_if, XM_ISR); 2237 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2238 2239 /* Free RX and TX mbufs still in the queues. */ 2240 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2241 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2242 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2243 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2244 } 2245 } 2246 2247 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2248 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2249 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2250 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2251 #if 1 2252 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2253 sc_if->sk_cdata.sk_tx_map[i], link); 2254 sc_if->sk_cdata.sk_tx_map[i] = 0; 2255 #endif 2256 } 2257 } 2258 2259 #if 1 2260 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2261 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2262 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2263 free(dma, M_DEVBUF); 2264 } 2265 #endif 2266 } 2267 2268 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2269 NULL, NULL); 2270 2271 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2272 NULL, NULL); 2273 2274 #ifdef MSK_DEBUG 2275 void 2276 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2277 { 2278 #define DESC_PRINT(X) \ 2279 if (X) \ 2280 printf("txdesc[%d]." #X "=%#x\n", \ 2281 idx, X); 2282 2283 DESC_PRINT(letoh32(le->sk_addr)); 2284 DESC_PRINT(letoh16(le->sk_len)); 2285 DESC_PRINT(le->sk_ctl); 2286 DESC_PRINT(le->sk_opcode); 2287 #undef DESC_PRINT 2288 } 2289 2290 void 2291 msk_dump_bytes(const char *data, int len) 2292 { 2293 int c, i, j; 2294 2295 for (i = 0; i < len; i += 16) { 2296 printf("%08x ", i); 2297 c = len - i; 2298 if (c > 16) c = 16; 2299 2300 for (j = 0; j < c; j++) { 2301 printf("%02x ", data[i + j] & 0xff); 2302 if ((j & 0xf) == 7 && j > 0) 2303 printf(" "); 2304 } 2305 2306 for (; j < 16; j++) 2307 printf(" "); 2308 printf(" "); 2309 2310 for (j = 0; j < c; j++) { 2311 int ch = data[i + j] & 0xff; 2312 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2313 } 2314 2315 printf("\n"); 2316 2317 if (c < 16) 2318 break; 2319 } 2320 } 2321 2322 void 2323 msk_dump_mbuf(struct mbuf *m) 2324 { 2325 int count = m->m_pkthdr.len; 2326 2327 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2328 2329 while (count > 0 && m) { 2330 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2331 m, m->m_data, m->m_len); 2332 msk_dump_bytes(mtod(m, char *), m->m_len); 2333 2334 count -= m->m_len; 2335 m = m->m_next; 2336 } 2337 } 2338 #endif 2339 2340 static int 2341 msk_sysctl_handler(SYSCTLFN_ARGS) 2342 { 2343 int error, t; 2344 struct sysctlnode node; 2345 struct sk_softc *sc; 2346 2347 node = *rnode; 2348 sc = node.sysctl_data; 2349 t = sc->sk_int_mod; 2350 node.sysctl_data = &t; 2351 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2352 if (error || newp == NULL) 2353 return error; 2354 2355 if (t < SK_IM_MIN || t > SK_IM_MAX) 2356 return EINVAL; 2357 2358 /* update the softc with sysctl-changed value, and mark 2359 for hardware update */ 2360 sc->sk_int_mod = t; 2361 sc->sk_int_mod_pending = 1; 2362 return 0; 2363 } 2364 2365 /* 2366 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2367 * set up in skc_attach() 2368 */ 2369 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2370 { 2371 int rc; 2372 const struct sysctlnode *node; 2373 2374 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2375 0, CTLTYPE_NODE, "hw", NULL, 2376 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2377 goto err; 2378 } 2379 2380 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2381 0, CTLTYPE_NODE, "msk", 2382 SYSCTL_DESCR("msk interface controls"), 2383 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2384 goto err; 2385 } 2386 2387 msk_root_num = node->sysctl_num; 2388 return; 2389 2390 err: 2391 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2392 } 2393