1 /* $NetBSD: if_msk.c,v 1.27 2009/05/12 08:23:00 cegger Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.27 2009/05/12 08:23:00 cegger Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/mutex.h> 66 #include <sys/kernel.h> 67 #include <sys/socket.h> 68 #include <sys/device.h> 69 #include <sys/queue.h> 70 #include <sys/callout.h> 71 #include <sys/sysctl.h> 72 #include <sys/endian.h> 73 #ifdef __NetBSD__ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 #endif 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 82 #include <net/if_media.h> 83 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #endif 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 #include <dev/mii/brgphyreg.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/pci/if_skreg.h> 100 #include <dev/pci/if_mskvar.h> 101 102 int mskc_probe(device_t, cfdata_t, void *); 103 void mskc_attach(device_t, device_t self, void *aux); 104 static bool mskc_suspend(device_t PMF_FN_PROTO); 105 static bool mskc_resume(device_t PMF_FN_PROTO); 106 int msk_probe(device_t, cfdata_t, void *); 107 void msk_attach(device_t, device_t self, void *aux); 108 int mskcprint(void *, const char *); 109 int msk_intr(void *); 110 void msk_intr_yukon(struct sk_if_softc *); 111 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 112 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 113 void msk_txeof(struct sk_if_softc *, int); 114 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 115 void msk_start(struct ifnet *); 116 int msk_ioctl(struct ifnet *, u_long, void *); 117 int msk_init(struct ifnet *); 118 void msk_init_yukon(struct sk_if_softc *); 119 void msk_stop(struct ifnet *, int); 120 void msk_watchdog(struct ifnet *); 121 void msk_reset(struct sk_softc *); 122 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 123 int msk_alloc_jumbo_mem(struct sk_if_softc *); 124 void *msk_jalloc(struct sk_if_softc *); 125 void msk_jfree(struct mbuf *, void *, size_t, void *); 126 int msk_init_rx_ring(struct sk_if_softc *); 127 int msk_init_tx_ring(struct sk_if_softc *); 128 129 void msk_update_int_mod(struct sk_softc *); 130 131 int msk_miibus_readreg(device_t, int, int); 132 void msk_miibus_writereg(device_t, int, int, int); 133 void msk_miibus_statchg(device_t); 134 135 void msk_setfilt(struct sk_if_softc *, void *, int); 136 void msk_setmulti(struct sk_if_softc *); 137 void msk_setpromisc(struct sk_if_softc *); 138 void msk_tick(void *); 139 140 /* #define MSK_DEBUG 1 */ 141 #ifdef MSK_DEBUG 142 #define DPRINTF(x) if (mskdebug) printf x 143 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 144 int mskdebug = MSK_DEBUG; 145 146 void msk_dump_txdesc(struct msk_tx_desc *, int); 147 void msk_dump_mbuf(struct mbuf *); 148 void msk_dump_bytes(const char *, int); 149 #else 150 #define DPRINTF(x) 151 #define DPRINTFN(n,x) 152 #endif 153 154 static int msk_sysctl_handler(SYSCTLFN_PROTO); 155 static int msk_root_num; 156 157 /* supported device vendors */ 158 static const struct msk_product { 159 pci_vendor_id_t msk_vendor; 160 pci_product_id_t msk_product; 161 } msk_products[] = { 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 191 }; 192 193 static inline u_int32_t 194 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 195 { 196 return CSR_READ_4(sc, reg); 197 } 198 199 static inline u_int16_t 200 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_2(sc, reg); 203 } 204 205 static inline u_int8_t 206 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_1(sc, reg); 209 } 210 211 static inline void 212 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 213 { 214 CSR_WRITE_4(sc, reg, x); 215 } 216 217 static inline void 218 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 219 { 220 CSR_WRITE_2(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 225 { 226 CSR_WRITE_1(sc, reg, x); 227 } 228 229 int 230 msk_miibus_readreg(device_t dev, int phy, int reg) 231 { 232 struct sk_if_softc *sc_if = device_private(dev); 233 u_int16_t val; 234 int i; 235 236 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 237 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 238 239 for (i = 0; i < SK_TIMEOUT; i++) { 240 DELAY(1); 241 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 242 if (val & YU_SMICR_READ_VALID) 243 break; 244 } 245 246 if (i == SK_TIMEOUT) { 247 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 248 return (0); 249 } 250 251 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 252 SK_TIMEOUT)); 253 254 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 255 256 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 257 phy, reg, val)); 258 259 return (val); 260 } 261 262 void 263 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 264 { 265 struct sk_if_softc *sc_if = device_private(dev); 266 int i; 267 268 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 269 phy, reg, val)); 270 271 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 272 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 273 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 274 275 for (i = 0; i < SK_TIMEOUT; i++) { 276 DELAY(1); 277 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 278 break; 279 } 280 281 if (i == SK_TIMEOUT) 282 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 283 } 284 285 void 286 msk_miibus_statchg(device_t dev) 287 { 288 struct sk_if_softc *sc_if = device_private(dev); 289 struct mii_data *mii = &sc_if->sk_mii; 290 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 291 int gpcr; 292 293 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 294 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 295 296 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 297 /* Set speed. */ 298 gpcr |= YU_GPCR_SPEED_DIS; 299 switch (IFM_SUBTYPE(mii->mii_media_active)) { 300 case IFM_1000_SX: 301 case IFM_1000_LX: 302 case IFM_1000_CX: 303 case IFM_1000_T: 304 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 305 break; 306 case IFM_100_TX: 307 gpcr |= YU_GPCR_SPEED; 308 break; 309 } 310 311 /* Set duplex. */ 312 gpcr |= YU_GPCR_DPLX_DIS; 313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 314 gpcr |= YU_GPCR_DUPLEX; 315 316 /* Disable flow control. */ 317 gpcr |= YU_GPCR_FCTL_DIS; 318 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 319 } 320 321 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 322 323 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 324 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 325 } 326 327 #define HASH_BITS 6 328 329 void 330 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 331 { 332 char *addr = addrv; 333 int base = XM_RXFILT_ENTRY(slot); 334 335 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 336 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 337 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 338 } 339 340 void 341 msk_setmulti(struct sk_if_softc *sc_if) 342 { 343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 344 u_int32_t hashes[2] = { 0, 0 }; 345 int h; 346 struct ethercom *ec = &sc_if->sk_ethercom; 347 struct ether_multi *enm; 348 struct ether_multistep step; 349 u_int16_t reg; 350 351 /* First, zot all the existing filters. */ 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 356 357 358 /* Now program new ones. */ 359 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 360 reg |= YU_RCR_UFLEN; 361 allmulti: 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 if ((ifp->if_flags & IFF_PROMISC) != 0) 364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 366 hashes[0] = 0xFFFFFFFF; 367 hashes[1] = 0xFFFFFFFF; 368 } 369 } else { 370 /* First find the tail of the list. */ 371 ETHER_FIRST_MULTI(step, ec, enm); 372 while (enm != NULL) { 373 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 374 ETHER_ADDR_LEN)) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 goto allmulti; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 379 ((1 << HASH_BITS) - 1); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 reg |= YU_RCR_MUFLEN; 388 } 389 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 395 } 396 397 void 398 msk_setpromisc(struct sk_if_softc *sc_if) 399 { 400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 401 402 if (ifp->if_flags & IFF_PROMISC) 403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 else 406 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 } 409 410 int 411 msk_init_rx_ring(struct sk_if_softc *sc_if) 412 { 413 struct msk_chain_data *cd = &sc_if->sk_cdata; 414 struct msk_ring_data *rd = sc_if->sk_rdata; 415 int i, nexti; 416 417 memset((char *)rd->sk_rx_ring, 0, 418 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 for (i = 0; i < MSK_RX_RING_CNT; i++) { 430 if (msk_newbuf(sc_if, i, NULL, 431 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 432 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 memset((char *)sc_if->sk_rdata->sk_tx_ring, 0, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. 599 */ 600 ptr = sc_if->sk_cdata.sk_jumbo_buf; 601 for (i = 0; i < MSK_JSLOTS; i++) { 602 sc_if->sk_cdata.sk_jslots[i] = ptr; 603 ptr += SK_JLEN; 604 entry = malloc(sizeof(struct sk_jpool_entry), 605 M_DEVBUF, M_NOWAIT); 606 if (entry == NULL) { 607 sc_if->sk_cdata.sk_jumbo_buf = NULL; 608 aprint_error(": no memory for jumbo buffer queue!"); 609 error = ENOBUFS; 610 goto out; 611 } 612 entry->slot = i; 613 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 614 entry, jpool_entries); 615 } 616 out: 617 if (error != 0) { 618 switch (state) { 619 case 4: 620 bus_dmamap_unload(sc->sc_dmatag, 621 sc_if->sk_cdata.sk_rx_jumbo_map); 622 case 3: 623 bus_dmamap_destroy(sc->sc_dmatag, 624 sc_if->sk_cdata.sk_rx_jumbo_map); 625 case 2: 626 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 627 case 1: 628 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 629 break; 630 default: 631 break; 632 } 633 } 634 635 return (error); 636 } 637 638 /* 639 * Allocate a jumbo buffer. 640 */ 641 void * 642 msk_jalloc(struct sk_if_softc *sc_if) 643 { 644 struct sk_jpool_entry *entry; 645 646 mutex_enter(&sc_if->sk_jpool_mtx); 647 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 648 649 if (entry == NULL) { 650 mutex_exit(&sc_if->sk_jpool_mtx); 651 return NULL; 652 } 653 654 LIST_REMOVE(entry, jpool_entries); 655 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 656 mutex_exit(&sc_if->sk_jpool_mtx); 657 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 void 664 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 665 { 666 struct sk_jpool_entry *entry; 667 struct sk_if_softc *sc; 668 int i; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct sk_if_softc *)arg; 672 673 if (sc == NULL) 674 panic("msk_jfree: can't find softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 i = ((vaddr_t)buf 678 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 679 680 if ((i < 0) || (i >= MSK_JSLOTS)) 681 panic("msk_jfree: asked to free buffer that we don't manage!"); 682 683 mutex_enter(&sc->sk_jpool_mtx); 684 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 685 if (entry == NULL) 686 panic("msk_jfree: buffer not in use!"); 687 entry->slot = i; 688 LIST_REMOVE(entry, jpool_entries); 689 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 690 mutex_exit(&sc->sk_jpool_mtx); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc_if = ifp->if_softc; 700 int s, error = 0; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 error = ether_ioctl(ifp, cmd, data); 706 707 if (error == ENETRESET) { 708 error = 0; 709 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 710 ; 711 else if (ifp->if_flags & IFF_RUNNING) { 712 /* 713 * Multicast list has changed; set the hardware 714 * filter accordingly. 715 */ 716 msk_setmulti(sc_if); 717 } 718 } 719 720 splx(s); 721 return (error); 722 } 723 724 void 725 msk_update_int_mod(struct sk_softc *sc) 726 { 727 u_int32_t imtimer_ticks; 728 729 /* 730 * Configure interrupt moderation. The moderation timer 731 * defers interrupts specified in the interrupt moderation 732 * timer mask based on the timeout specified in the interrupt 733 * moderation timer init register. Each bit in the timer 734 * register represents one tick, so to specify a timeout in 735 * microseconds, we have to multiply by the correct number of 736 * ticks-per-microsecond. 737 */ 738 switch (sc->sk_type) { 739 case SK_YUKON_EC: 740 case SK_YUKON_EC_U: 741 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 742 break; 743 case SK_YUKON_FE: 744 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 745 break; 746 case SK_YUKON_XL: 747 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 748 break; 749 default: 750 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 751 } 752 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 753 sc->sk_int_mod); 754 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 755 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 756 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 757 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 758 sc->sk_int_mod_pending = 0; 759 } 760 761 static int 762 msk_lookup(const struct pci_attach_args *pa) 763 { 764 const struct msk_product *pmsk; 765 766 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 767 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 768 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 769 return 1; 770 } 771 return 0; 772 } 773 774 /* 775 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 776 * IDs against our list and return a device name if we find a match. 777 */ 778 int 779 mskc_probe(device_t parent, cfdata_t match, void *aux) 780 { 781 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 782 783 return msk_lookup(pa); 784 } 785 786 /* 787 * Force the GEnesis into reset, then bring it out of reset. 788 */ 789 void msk_reset(struct sk_softc *sc) 790 { 791 u_int32_t imtimer_ticks, reg1; 792 int reg; 793 794 DPRINTFN(2, ("msk_reset\n")); 795 796 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 797 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 798 799 DELAY(1000); 800 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 801 DELAY(2); 802 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 803 sk_win_write_1(sc, SK_TESTCTL1, 2); 804 805 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 806 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 807 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 808 else 809 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 810 811 if (sc->sk_type == SK_YUKON_EC_U) { 812 uint32_t our; 813 814 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 815 816 /* enable all clocks. */ 817 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 818 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 819 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 820 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 821 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 822 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 823 /* Set all bits to 0 except bits 15..12 */ 824 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 825 /* Set to default value */ 826 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 827 } 828 829 /* release PHY from PowerDown/Coma mode. */ 830 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 831 832 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 833 sk_win_write_1(sc, SK_Y2_CLKGATE, 834 SK_Y2_CLKGATE_LINK1_GATE_DIS | 835 SK_Y2_CLKGATE_LINK2_GATE_DIS | 836 SK_Y2_CLKGATE_LINK1_CORE_DIS | 837 SK_Y2_CLKGATE_LINK2_CORE_DIS | 838 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 839 else 840 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 841 842 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 843 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 844 DELAY(1000); 845 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 846 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 847 848 sk_win_write_1(sc, SK_TESTCTL1, 1); 849 850 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 851 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 852 CSR_READ_2(sc, SK_LINK_CTRL))); 853 854 /* Disable ASF */ 855 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 856 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 857 858 /* Clear I2C IRQ noise */ 859 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 860 861 /* Disable hardware timer */ 862 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 863 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 864 865 /* Disable descriptor polling */ 866 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 867 868 /* Disable time stamps */ 869 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 870 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 871 872 /* Enable RAM interface */ 873 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 874 for (reg = SK_TO0;reg <= SK_TO11; reg++) 875 sk_win_write_1(sc, reg, 36); 876 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 877 for (reg = SK_TO0;reg <= SK_TO11; reg++) 878 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 879 880 /* 881 * Configure interrupt moderation. The moderation timer 882 * defers interrupts specified in the interrupt moderation 883 * timer mask based on the timeout specified in the interrupt 884 * moderation timer init register. Each bit in the timer 885 * register represents one tick, so to specify a timeout in 886 * microseconds, we have to multiply by the correct number of 887 * ticks-per-microsecond. 888 */ 889 switch (sc->sk_type) { 890 case SK_YUKON_EC: 891 case SK_YUKON_EC_U: 892 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 893 break; 894 case SK_YUKON_FE: 895 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 896 break; 897 case SK_YUKON_XL: 898 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 899 break; 900 default: 901 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 902 } 903 904 /* Reset status ring. */ 905 memset((char *)sc->sk_status_ring, 0, 906 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 907 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 908 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 909 sc->sk_status_idx = 0; 910 sc->sk_status_own_idx = 0; 911 912 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 913 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 914 915 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 916 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 917 sc->sk_status_map->dm_segs[0].ds_addr); 918 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 919 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 920 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 921 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 922 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 923 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 924 } else { 925 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 926 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 927 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 928 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 929 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 930 } 931 932 #if 0 933 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 934 #endif 935 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 936 937 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 938 939 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 940 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 941 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 942 943 msk_update_int_mod(sc); 944 } 945 946 int 947 msk_probe(device_t parent, cfdata_t match, void *aux) 948 { 949 struct skc_attach_args *sa = aux; 950 951 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 952 return (0); 953 954 switch (sa->skc_type) { 955 case SK_YUKON_XL: 956 case SK_YUKON_EC_U: 957 case SK_YUKON_EC: 958 case SK_YUKON_FE: 959 return (1); 960 } 961 962 return (0); 963 } 964 965 static bool 966 msk_resume(device_t dv PMF_FN_ARGS) 967 { 968 struct sk_if_softc *sc_if = device_private(dv); 969 970 msk_init_yukon(sc_if); 971 return true; 972 } 973 974 /* 975 * Each XMAC chip is attached as a separate logical IP interface. 976 * Single port cards will have only one logical interface of course. 977 */ 978 void 979 msk_attach(device_t parent, device_t self, void *aux) 980 { 981 struct sk_if_softc *sc_if = device_private(self); 982 struct sk_softc *sc = device_private(parent); 983 struct skc_attach_args *sa = aux; 984 struct ifnet *ifp; 985 void *kva; 986 bus_dma_segment_t seg; 987 int i, rseg; 988 u_int32_t chunk, val; 989 990 sc_if->sk_port = sa->skc_port; 991 sc_if->sk_softc = sc; 992 sc->sk_if[sa->skc_port] = sc_if; 993 994 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 995 996 /* 997 * Get station address for this interface. Note that 998 * dual port cards actually come with three station 999 * addresses: one for each port, plus an extra. The 1000 * extra one is used by the SysKonnect driver software 1001 * as a 'virtual' station address for when both ports 1002 * are operating in failover mode. Currently we don't 1003 * use this extra address. 1004 */ 1005 for (i = 0; i < ETHER_ADDR_LEN; i++) 1006 sc_if->sk_enaddr[i] = 1007 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1008 1009 aprint_normal(": Ethernet address %s\n", 1010 ether_sprintf(sc_if->sk_enaddr)); 1011 1012 /* 1013 * Set up RAM buffer addresses. The NIC will have a certain 1014 * amount of SRAM on it, somewhere between 512K and 2MB. We 1015 * need to divide this up a) between the transmitter and 1016 * receiver and b) between the two XMACs, if this is a 1017 * dual port NIC. Our algorithm is to divide up the memory 1018 * evenly so that everyone gets a fair share. 1019 * 1020 * Just to be contrary, Yukon2 appears to have separate memory 1021 * for each MAC. 1022 */ 1023 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1024 val = sc->sk_rboff / sizeof(u_int64_t); 1025 sc_if->sk_rx_ramstart = val; 1026 val += (chunk / sizeof(u_int64_t)); 1027 sc_if->sk_rx_ramend = val - 1; 1028 chunk = sc->sk_ramsize - chunk; 1029 sc_if->sk_tx_ramstart = val; 1030 val += (chunk / sizeof(u_int64_t)); 1031 sc_if->sk_tx_ramend = val - 1; 1032 1033 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1034 " tx_ramstart=%#x tx_ramend=%#x\n", 1035 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1036 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1037 1038 /* Allocate the descriptor queues. */ 1039 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1040 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1041 aprint_error(": can't alloc rx buffers\n"); 1042 goto fail; 1043 } 1044 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1045 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1046 aprint_error(": can't map dma buffers (%zu bytes)\n", 1047 sizeof(struct msk_ring_data)); 1048 goto fail_1; 1049 } 1050 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1051 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1052 &sc_if->sk_ring_map)) { 1053 aprint_error(": can't create dma map\n"); 1054 goto fail_2; 1055 } 1056 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1057 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1058 aprint_error(": can't load dma map\n"); 1059 goto fail_3; 1060 } 1061 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1062 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1063 1064 ifp = &sc_if->sk_ethercom.ec_if; 1065 /* Try to allocate memory for jumbo buffers. */ 1066 if (msk_alloc_jumbo_mem(sc_if)) { 1067 aprint_error(": jumbo buffer allocation failed\n"); 1068 goto fail_3; 1069 } 1070 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1071 if (sc->sk_type != SK_YUKON_FE) 1072 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1073 1074 ifp->if_softc = sc_if; 1075 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1076 ifp->if_ioctl = msk_ioctl; 1077 ifp->if_start = msk_start; 1078 ifp->if_stop = msk_stop; 1079 ifp->if_init = msk_init; 1080 ifp->if_watchdog = msk_watchdog; 1081 ifp->if_baudrate = 1000000000; 1082 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1083 IFQ_SET_READY(&ifp->if_snd); 1084 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1085 1086 /* 1087 * Do miibus setup. 1088 */ 1089 msk_init_yukon(sc_if); 1090 1091 DPRINTFN(2, ("msk_attach: 1\n")); 1092 1093 sc_if->sk_mii.mii_ifp = ifp; 1094 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1095 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1096 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1097 1098 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1099 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1100 ether_mediachange, ether_mediastatus); 1101 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1102 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1103 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1104 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1105 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1106 0, NULL); 1107 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1108 } else 1109 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1110 1111 callout_init(&sc_if->sk_tick_ch, 0); 1112 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1113 callout_schedule(&sc_if->sk_tick_ch, hz); 1114 1115 /* 1116 * Call MI attach routines. 1117 */ 1118 if_attach(ifp); 1119 ether_ifattach(ifp, sc_if->sk_enaddr); 1120 1121 if (!pmf_device_register(self, NULL, msk_resume)) 1122 aprint_error_dev(self, "couldn't establish power handler\n"); 1123 else 1124 pmf_class_network_register(self, ifp); 1125 1126 #if NRND > 0 1127 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1128 RND_TYPE_NET, 0); 1129 #endif 1130 1131 DPRINTFN(2, ("msk_attach: end\n")); 1132 return; 1133 1134 fail_3: 1135 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1136 fail_2: 1137 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1138 fail_1: 1139 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1140 fail: 1141 sc->sk_if[sa->skc_port] = NULL; 1142 } 1143 1144 int 1145 mskcprint(void *aux, const char *pnp) 1146 { 1147 struct skc_attach_args *sa = aux; 1148 1149 if (pnp) 1150 aprint_normal("sk port %c at %s", 1151 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1152 else 1153 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1154 return (UNCONF); 1155 } 1156 1157 /* 1158 * Attach the interface. Allocate softc structures, do ifmedia 1159 * setup and ethernet/BPF attach. 1160 */ 1161 void 1162 mskc_attach(device_t parent, device_t self, void *aux) 1163 { 1164 struct sk_softc *sc = device_private(self); 1165 struct pci_attach_args *pa = aux; 1166 struct skc_attach_args skca; 1167 pci_chipset_tag_t pc = pa->pa_pc; 1168 pcireg_t command, memtype; 1169 pci_intr_handle_t ih; 1170 const char *intrstr = NULL; 1171 bus_size_t size; 1172 int rc, sk_nodenum; 1173 u_int8_t hw, skrs; 1174 const char *revstr = NULL; 1175 const struct sysctlnode *node; 1176 void *kva; 1177 bus_dma_segment_t seg; 1178 int rseg; 1179 1180 DPRINTFN(2, ("begin mskc_attach\n")); 1181 1182 /* 1183 * Handle power management nonsense. 1184 */ 1185 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1186 1187 if (command == 0x01) { 1188 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1189 if (command & SK_PSTATE_MASK) { 1190 u_int32_t iobase, membase, irq; 1191 1192 /* Save important PCI config data. */ 1193 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1194 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1195 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1196 1197 /* Reset the power state. */ 1198 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1199 "-- setting to D0\n", 1200 command & SK_PSTATE_MASK); 1201 command &= 0xFFFFFFFC; 1202 pci_conf_write(pc, pa->pa_tag, 1203 SK_PCI_PWRMGMTCTRL, command); 1204 1205 /* Restore PCI config data. */ 1206 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1207 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1208 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1209 } 1210 } 1211 1212 /* 1213 * Map control/status registers. 1214 */ 1215 1216 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1217 switch (memtype) { 1218 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1219 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1220 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1221 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1222 NULL, &size) == 0) 1223 break; 1224 default: 1225 aprint_error(": can't map mem space\n"); 1226 return; 1227 } 1228 1229 sc->sc_dmatag = pa->pa_dmat; 1230 1231 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1232 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1233 1234 /* bail out here if chip is not recognized */ 1235 if (!(SK_IS_YUKON2(sc))) { 1236 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1237 goto fail_1; 1238 } 1239 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1240 1241 /* Allocate interrupt */ 1242 if (pci_intr_map(pa, &ih)) { 1243 aprint_error(": couldn't map interrupt\n"); 1244 goto fail_1; 1245 } 1246 1247 intrstr = pci_intr_string(pc, ih); 1248 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1249 if (sc->sk_intrhand == NULL) { 1250 aprint_error(": couldn't establish interrupt"); 1251 if (intrstr != NULL) 1252 aprint_error(" at %s", intrstr); 1253 aprint_error("\n"); 1254 goto fail_1; 1255 } 1256 1257 if (bus_dmamem_alloc(sc->sc_dmatag, 1258 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1259 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1260 aprint_error(": can't alloc status buffers\n"); 1261 goto fail_2; 1262 } 1263 1264 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1265 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1266 &kva, BUS_DMA_NOWAIT)) { 1267 aprint_error(": can't map dma buffers (%zu bytes)\n", 1268 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1269 goto fail_3; 1270 } 1271 if (bus_dmamap_create(sc->sc_dmatag, 1272 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1273 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1274 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1275 aprint_error(": can't create dma map\n"); 1276 goto fail_4; 1277 } 1278 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1279 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1280 NULL, BUS_DMA_NOWAIT)) { 1281 aprint_error(": can't load dma map\n"); 1282 goto fail_5; 1283 } 1284 sc->sk_status_ring = (struct msk_status_desc *)kva; 1285 1286 /* Reset the adapter. */ 1287 msk_reset(sc); 1288 1289 skrs = sk_win_read_1(sc, SK_EPROM0); 1290 if (skrs == 0x00) 1291 sc->sk_ramsize = 0x20000; 1292 else 1293 sc->sk_ramsize = skrs * (1<<12); 1294 sc->sk_rboff = SK_RBOFF_0; 1295 1296 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1297 sc->sk_ramsize, sc->sk_ramsize / 1024, 1298 sc->sk_rboff)); 1299 1300 switch (sc->sk_type) { 1301 case SK_YUKON_XL: 1302 sc->sk_name = "Yukon-2 XL"; 1303 break; 1304 case SK_YUKON_EC_U: 1305 sc->sk_name = "Yukon-2 EC Ultra"; 1306 break; 1307 case SK_YUKON_EC: 1308 sc->sk_name = "Yukon-2 EC"; 1309 break; 1310 case SK_YUKON_FE: 1311 sc->sk_name = "Yukon-2 FE"; 1312 break; 1313 default: 1314 sc->sk_name = "Yukon (Unknown)"; 1315 } 1316 1317 if (sc->sk_type == SK_YUKON_XL) { 1318 switch (sc->sk_rev) { 1319 case SK_YUKON_XL_REV_A0: 1320 sc->sk_workaround = 0; 1321 revstr = "A0"; 1322 break; 1323 case SK_YUKON_XL_REV_A1: 1324 sc->sk_workaround = SK_WA_4109; 1325 revstr = "A1"; 1326 break; 1327 case SK_YUKON_XL_REV_A2: 1328 sc->sk_workaround = SK_WA_4109; 1329 revstr = "A2"; 1330 break; 1331 case SK_YUKON_XL_REV_A3: 1332 sc->sk_workaround = SK_WA_4109; 1333 revstr = "A3"; 1334 break; 1335 default: 1336 sc->sk_workaround = 0; 1337 break; 1338 } 1339 } 1340 1341 if (sc->sk_type == SK_YUKON_EC) { 1342 switch (sc->sk_rev) { 1343 case SK_YUKON_EC_REV_A1: 1344 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1345 revstr = "A1"; 1346 break; 1347 case SK_YUKON_EC_REV_A2: 1348 sc->sk_workaround = SK_WA_4109; 1349 revstr = "A2"; 1350 break; 1351 case SK_YUKON_EC_REV_A3: 1352 sc->sk_workaround = SK_WA_4109; 1353 revstr = "A3"; 1354 break; 1355 default: 1356 sc->sk_workaround = 0; 1357 break; 1358 } 1359 } 1360 1361 if (sc->sk_type == SK_YUKON_FE) { 1362 sc->sk_workaround = SK_WA_4109; 1363 switch (sc->sk_rev) { 1364 case SK_YUKON_FE_REV_A1: 1365 revstr = "A1"; 1366 break; 1367 case SK_YUKON_FE_REV_A2: 1368 revstr = "A2"; 1369 break; 1370 default: 1371 sc->sk_workaround = 0; 1372 break; 1373 } 1374 } 1375 1376 if (sc->sk_type == SK_YUKON_EC_U) { 1377 sc->sk_workaround = SK_WA_4109; 1378 switch (sc->sk_rev) { 1379 case SK_YUKON_EC_U_REV_A0: 1380 revstr = "A0"; 1381 break; 1382 case SK_YUKON_EC_U_REV_A1: 1383 revstr = "A1"; 1384 break; 1385 case SK_YUKON_EC_U_REV_B0: 1386 revstr = "B0"; 1387 break; 1388 default: 1389 sc->sk_workaround = 0; 1390 break; 1391 } 1392 } 1393 1394 /* Announce the product name. */ 1395 aprint_normal(", %s", sc->sk_name); 1396 if (revstr != NULL) 1397 aprint_normal(" rev. %s", revstr); 1398 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1399 1400 sc->sk_macs = 1; 1401 1402 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1403 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1404 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1405 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1406 sc->sk_macs++; 1407 } 1408 1409 skca.skc_port = SK_PORT_A; 1410 skca.skc_type = sc->sk_type; 1411 skca.skc_rev = sc->sk_rev; 1412 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1413 1414 if (sc->sk_macs > 1) { 1415 skca.skc_port = SK_PORT_B; 1416 skca.skc_type = sc->sk_type; 1417 skca.skc_rev = sc->sk_rev; 1418 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1419 } 1420 1421 /* Turn on the 'driver is loaded' LED. */ 1422 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1423 1424 /* skc sysctl setup */ 1425 1426 sc->sk_int_mod = SK_IM_DEFAULT; 1427 sc->sk_int_mod_pending = 0; 1428 1429 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1430 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1431 SYSCTL_DESCR("mskc per-controller controls"), 1432 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1433 CTL_EOL)) != 0) { 1434 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1435 goto fail_6; 1436 } 1437 1438 sk_nodenum = node->sysctl_num; 1439 1440 /* interrupt moderation time in usecs */ 1441 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1442 CTLFLAG_READWRITE, 1443 CTLTYPE_INT, "int_mod", 1444 SYSCTL_DESCR("msk interrupt moderation timer"), 1445 msk_sysctl_handler, 0, sc, 1446 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1447 CTL_EOL)) != 0) { 1448 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1449 goto fail_6; 1450 } 1451 1452 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1453 aprint_error_dev(self, "couldn't establish power handler\n"); 1454 1455 return; 1456 1457 fail_6: 1458 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1459 fail_5: 1460 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1461 fail_4: 1462 bus_dmamem_unmap(sc->sc_dmatag, kva, 1463 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1464 fail_3: 1465 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1466 fail_2: 1467 pci_intr_disestablish(pc, sc->sk_intrhand); 1468 fail_1: 1469 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1470 } 1471 1472 int 1473 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1474 { 1475 struct sk_softc *sc = sc_if->sk_softc; 1476 struct msk_tx_desc *f = NULL; 1477 u_int32_t frag, cur; 1478 int i; 1479 struct sk_txmap_entry *entry; 1480 bus_dmamap_t txmap; 1481 1482 DPRINTFN(2, ("msk_encap\n")); 1483 1484 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1485 if (entry == NULL) { 1486 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1487 return (ENOBUFS); 1488 } 1489 txmap = entry->dmamap; 1490 1491 cur = frag = *txidx; 1492 1493 #ifdef MSK_DEBUG 1494 if (mskdebug >= 2) 1495 msk_dump_mbuf(m_head); 1496 #endif 1497 1498 /* 1499 * Start packing the mbufs in this chain into 1500 * the fragment pointers. Stop when we run out 1501 * of fragments or hit the end of the mbuf chain. 1502 */ 1503 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1504 BUS_DMA_NOWAIT)) { 1505 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1506 return (ENOBUFS); 1507 } 1508 1509 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1510 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1511 bus_dmamap_unload(sc->sc_dmatag, txmap); 1512 return (ENOBUFS); 1513 } 1514 1515 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1516 1517 /* Sync the DMA map. */ 1518 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1519 BUS_DMASYNC_PREWRITE); 1520 1521 for (i = 0; i < txmap->dm_nsegs; i++) { 1522 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1523 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1524 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1525 f->sk_ctl = 0; 1526 if (i == 0) 1527 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1528 else 1529 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1530 cur = frag; 1531 SK_INC(frag, MSK_TX_RING_CNT); 1532 } 1533 1534 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1535 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1536 1537 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1538 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1539 1540 /* Sync descriptors before handing to chip */ 1541 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1542 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1543 1544 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1545 1546 /* Sync first descriptor to hand it off */ 1547 MSK_CDTXSYNC(sc_if, *txidx, 1, 1548 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1549 1550 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1551 1552 #ifdef MSK_DEBUG 1553 if (mskdebug >= 2) { 1554 struct msk_tx_desc *le; 1555 u_int32_t idx; 1556 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1557 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1558 msk_dump_txdesc(le, idx); 1559 } 1560 } 1561 #endif 1562 1563 *txidx = frag; 1564 1565 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1566 1567 return (0); 1568 } 1569 1570 void 1571 msk_start(struct ifnet *ifp) 1572 { 1573 struct sk_if_softc *sc_if = ifp->if_softc; 1574 struct mbuf *m_head = NULL; 1575 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1576 int pkts = 0; 1577 1578 DPRINTFN(2, ("msk_start\n")); 1579 1580 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1581 IFQ_POLL(&ifp->if_snd, m_head); 1582 if (m_head == NULL) 1583 break; 1584 1585 /* 1586 * Pack the data into the transmit ring. If we 1587 * don't have room, set the OACTIVE flag and wait 1588 * for the NIC to drain the ring. 1589 */ 1590 if (msk_encap(sc_if, m_head, &idx)) { 1591 ifp->if_flags |= IFF_OACTIVE; 1592 break; 1593 } 1594 1595 /* now we are committed to transmit the packet */ 1596 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1597 pkts++; 1598 1599 /* 1600 * If there's a BPF listener, bounce a copy of this frame 1601 * to him. 1602 */ 1603 #if NBPFILTER > 0 1604 if (ifp->if_bpf) 1605 bpf_mtap(ifp->if_bpf, m_head); 1606 #endif 1607 } 1608 if (pkts == 0) 1609 return; 1610 1611 /* Transmit */ 1612 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1613 sc_if->sk_cdata.sk_tx_prod = idx; 1614 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1615 1616 /* Set a timeout in case the chip goes out to lunch. */ 1617 ifp->if_timer = 5; 1618 } 1619 } 1620 1621 void 1622 msk_watchdog(struct ifnet *ifp) 1623 { 1624 struct sk_if_softc *sc_if = ifp->if_softc; 1625 u_int32_t reg; 1626 int idx; 1627 1628 /* 1629 * Reclaim first as there is a possibility of losing Tx completion 1630 * interrupts. 1631 */ 1632 if (sc_if->sk_port == SK_PORT_A) 1633 reg = SK_STAT_BMU_TXA1_RIDX; 1634 else 1635 reg = SK_STAT_BMU_TXA2_RIDX; 1636 1637 idx = sk_win_read_2(sc_if->sk_softc, reg); 1638 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1639 msk_txeof(sc_if, idx); 1640 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1641 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1642 1643 ifp->if_oerrors++; 1644 1645 /* XXX Resets both ports; we shouldn't do that. */ 1646 msk_reset(sc_if->sk_softc); 1647 msk_init(ifp); 1648 } 1649 } 1650 } 1651 1652 static bool 1653 mskc_suspend(device_t dv PMF_FN_ARGS) 1654 { 1655 struct sk_softc *sc = device_private(dv); 1656 1657 DPRINTFN(2, ("mskc_suspend\n")); 1658 1659 /* Turn off the 'driver is loaded' LED. */ 1660 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1661 1662 return true; 1663 } 1664 1665 static bool 1666 mskc_resume(device_t dv PMF_FN_ARGS) 1667 { 1668 struct sk_softc *sc = device_private(dv); 1669 1670 DPRINTFN(2, ("mskc_resume\n")); 1671 1672 msk_reset(sc); 1673 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1674 1675 return true; 1676 } 1677 1678 __inline int 1679 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1680 { 1681 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1682 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1683 YU_RXSTAT_JABBER)) != 0 || 1684 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1685 YU_RXSTAT_BYTES(stat) != len) 1686 return (0); 1687 1688 return (1); 1689 } 1690 1691 void 1692 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1693 { 1694 struct sk_softc *sc = sc_if->sk_softc; 1695 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1696 struct mbuf *m; 1697 struct sk_chain *cur_rx; 1698 int cur, total_len = len; 1699 bus_dmamap_t dmamap; 1700 1701 DPRINTFN(2, ("msk_rxeof\n")); 1702 1703 cur = sc_if->sk_cdata.sk_rx_cons; 1704 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1705 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1706 1707 /* Sync the descriptor */ 1708 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1709 1710 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1711 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1712 1713 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1714 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1715 1716 m = cur_rx->sk_mbuf; 1717 cur_rx->sk_mbuf = NULL; 1718 1719 if (total_len < SK_MIN_FRAMELEN || 1720 total_len > ETHER_MAX_LEN_JUMBO || 1721 msk_rxvalid(sc, rxstat, total_len) == 0) { 1722 ifp->if_ierrors++; 1723 msk_newbuf(sc_if, cur, m, dmamap); 1724 return; 1725 } 1726 1727 /* 1728 * Try to allocate a new jumbo buffer. If that fails, copy the 1729 * packet to mbufs and put the jumbo buffer back in the ring 1730 * so it can be re-used. If allocating mbufs fails, then we 1731 * have to drop the packet. 1732 */ 1733 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1734 struct mbuf *m0; 1735 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1736 total_len + ETHER_ALIGN, 0, ifp, NULL); 1737 msk_newbuf(sc_if, cur, m, dmamap); 1738 if (m0 == NULL) { 1739 ifp->if_ierrors++; 1740 return; 1741 } 1742 m_adj(m0, ETHER_ALIGN); 1743 m = m0; 1744 } else { 1745 m->m_pkthdr.rcvif = ifp; 1746 m->m_pkthdr.len = m->m_len = total_len; 1747 } 1748 1749 ifp->if_ipackets++; 1750 1751 #if NBPFILTER > 0 1752 if (ifp->if_bpf) 1753 bpf_mtap(ifp->if_bpf, m); 1754 #endif 1755 1756 /* pass it on. */ 1757 (*ifp->if_input)(ifp, m); 1758 } 1759 1760 void 1761 msk_txeof(struct sk_if_softc *sc_if, int idx) 1762 { 1763 struct sk_softc *sc = sc_if->sk_softc; 1764 struct msk_tx_desc *cur_tx; 1765 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1766 u_int32_t sk_ctl; 1767 struct sk_txmap_entry *entry; 1768 int cons, prog; 1769 1770 DPRINTFN(2, ("msk_txeof\n")); 1771 1772 /* 1773 * Go through our tx ring and free mbufs for those 1774 * frames that have been sent. 1775 */ 1776 cons = sc_if->sk_cdata.sk_tx_cons; 1777 prog = 0; 1778 while (cons != idx) { 1779 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1780 break; 1781 prog++; 1782 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1783 1784 MSK_CDTXSYNC(sc_if, cons, 1, 1785 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1786 sk_ctl = cur_tx->sk_ctl; 1787 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1788 #ifdef MSK_DEBUG 1789 if (mskdebug >= 2) 1790 msk_dump_txdesc(cur_tx, cons); 1791 #endif 1792 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1793 ifp->if_opackets++; 1794 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1795 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1796 1797 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1798 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1799 1800 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1801 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1802 link); 1803 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1804 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1805 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1806 } 1807 sc_if->sk_cdata.sk_tx_cnt--; 1808 SK_INC(cons, MSK_TX_RING_CNT); 1809 } 1810 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1811 1812 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1813 ifp->if_flags &= ~IFF_OACTIVE; 1814 1815 if (prog > 0) 1816 sc_if->sk_cdata.sk_tx_cons = cons; 1817 } 1818 1819 void 1820 msk_tick(void *xsc_if) 1821 { 1822 struct sk_if_softc *sc_if = xsc_if; 1823 struct mii_data *mii = &sc_if->sk_mii; 1824 int s; 1825 1826 s = splnet(); 1827 mii_tick(mii); 1828 splx(s); 1829 1830 callout_schedule(&sc_if->sk_tick_ch, hz); 1831 } 1832 1833 void 1834 msk_intr_yukon(struct sk_if_softc *sc_if) 1835 { 1836 u_int8_t status; 1837 1838 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1839 /* RX overrun */ 1840 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1841 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1842 SK_RFCTL_RX_FIFO_OVER); 1843 } 1844 /* TX underrun */ 1845 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1846 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1847 SK_TFCTL_TX_FIFO_UNDER); 1848 } 1849 1850 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1851 } 1852 1853 int 1854 msk_intr(void *xsc) 1855 { 1856 struct sk_softc *sc = xsc; 1857 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1858 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1859 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1860 int claimed = 0; 1861 u_int32_t status; 1862 uint32_t st_status; 1863 uint16_t st_len; 1864 uint8_t st_opcode, st_link; 1865 struct msk_status_desc *cur_st; 1866 1867 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1868 if (status == 0) { 1869 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1870 return (0); 1871 } 1872 1873 status = CSR_READ_4(sc, SK_ISR); 1874 1875 if (sc_if0 != NULL) 1876 ifp0 = &sc_if0->sk_ethercom.ec_if; 1877 if (sc_if1 != NULL) 1878 ifp1 = &sc_if1->sk_ethercom.ec_if; 1879 1880 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1881 (ifp0->if_flags & IFF_RUNNING)) { 1882 msk_intr_yukon(sc_if0); 1883 } 1884 1885 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1886 (ifp1->if_flags & IFF_RUNNING)) { 1887 msk_intr_yukon(sc_if1); 1888 } 1889 1890 for (;;) { 1891 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1892 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1893 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1894 st_opcode = cur_st->sk_opcode; 1895 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1896 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1897 BUS_DMASYNC_PREREAD); 1898 break; 1899 } 1900 st_status = le32toh(cur_st->sk_status); 1901 st_len = le16toh(cur_st->sk_len); 1902 st_link = cur_st->sk_link; 1903 st_opcode &= ~SK_Y2_STOPC_OWN; 1904 1905 switch (st_opcode) { 1906 case SK_Y2_STOPC_RXSTAT: 1907 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1908 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1909 SK_RXQ1_Y2_PREF_PUTIDX, 1910 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1911 break; 1912 case SK_Y2_STOPC_TXSTAT: 1913 if (sc_if0) 1914 msk_txeof(sc_if0, st_status 1915 & SK_Y2_ST_TXA1_MSKL); 1916 if (sc_if1) 1917 msk_txeof(sc_if1, 1918 ((st_status & SK_Y2_ST_TXA2_MSKL) 1919 >> SK_Y2_ST_TXA2_SHIFTL) 1920 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1921 break; 1922 default: 1923 aprint_error("opcode=0x%x\n", st_opcode); 1924 break; 1925 } 1926 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1927 } 1928 1929 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1930 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1931 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1932 1933 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1934 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1935 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1936 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1937 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1938 1939 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1940 } 1941 1942 if (status & SK_Y2_IMR_BMU) { 1943 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1944 claimed = 1; 1945 } 1946 1947 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1948 1949 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1950 msk_start(ifp0); 1951 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1952 msk_start(ifp1); 1953 1954 #if NRND > 0 1955 if (RND_ENABLED(&sc->rnd_source)) 1956 rnd_add_uint32(&sc->rnd_source, status); 1957 #endif 1958 1959 if (sc->sk_int_mod_pending) 1960 msk_update_int_mod(sc); 1961 1962 return claimed; 1963 } 1964 1965 void 1966 msk_init_yukon(struct sk_if_softc *sc_if) 1967 { 1968 u_int32_t v; 1969 u_int16_t reg; 1970 struct sk_softc *sc; 1971 int i; 1972 1973 sc = sc_if->sk_softc; 1974 1975 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1976 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1977 1978 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1979 1980 /* GMAC and GPHY Reset */ 1981 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1982 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1983 DELAY(1000); 1984 1985 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1986 1987 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1988 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1989 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1990 1991 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1992 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1993 1994 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1995 1996 /* unused read of the interrupt source register */ 1997 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1998 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1999 2000 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2001 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2002 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2003 2004 /* MIB Counter Clear Mode set */ 2005 reg |= YU_PAR_MIB_CLR; 2006 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2007 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2008 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2009 2010 /* MIB Counter Clear Mode clear */ 2011 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2012 reg &= ~YU_PAR_MIB_CLR; 2013 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2014 2015 /* receive control reg */ 2016 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2017 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2018 2019 /* transmit control register */ 2020 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2021 2022 /* transmit flow control register */ 2023 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2024 2025 /* transmit parameter register */ 2026 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2027 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2028 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2029 2030 /* serial mode register */ 2031 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2032 reg = YU_SMR_DATA_BLIND(0x1c) | 2033 YU_SMR_MFL_VLAN | 2034 YU_SMR_IPG_DATA(0x1e); 2035 2036 if (sc->sk_type != SK_YUKON_FE) 2037 reg |= YU_SMR_MFL_JUMBO; 2038 2039 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2040 2041 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2042 /* Setup Yukon's address */ 2043 for (i = 0; i < 3; i++) { 2044 /* Write Source Address 1 (unicast filter) */ 2045 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2046 sc_if->sk_enaddr[i * 2] | 2047 sc_if->sk_enaddr[i * 2 + 1] << 8); 2048 } 2049 2050 for (i = 0; i < 3; i++) { 2051 reg = sk_win_read_2(sc_if->sk_softc, 2052 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2053 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2054 } 2055 2056 /* Set promiscuous mode */ 2057 msk_setpromisc(sc_if); 2058 2059 /* Set multicast filter */ 2060 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2061 msk_setmulti(sc_if); 2062 2063 /* enable interrupt mask for counter overflows */ 2064 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2065 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2066 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2067 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2068 2069 /* Configure RX MAC FIFO Flush Mask */ 2070 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2071 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2072 YU_RXSTAT_JABBER; 2073 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2074 2075 /* Configure RX MAC FIFO */ 2076 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2077 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2078 SK_RFCTL_FIFO_FLUSH_ON); 2079 2080 /* Increase flush threshould to 64 bytes */ 2081 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2082 SK_RFCTL_FIFO_THRESHOLD + 1); 2083 2084 /* Configure TX MAC FIFO */ 2085 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2086 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2087 2088 #if 1 2089 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2090 #endif 2091 DPRINTFN(6, ("msk_init_yukon: end\n")); 2092 } 2093 2094 /* 2095 * Note that to properly initialize any part of the GEnesis chip, 2096 * you first have to take it out of reset mode. 2097 */ 2098 int 2099 msk_init(struct ifnet *ifp) 2100 { 2101 struct sk_if_softc *sc_if = ifp->if_softc; 2102 struct sk_softc *sc = sc_if->sk_softc; 2103 int rc = 0, s; 2104 uint32_t imr, imtimer_ticks; 2105 2106 2107 DPRINTFN(2, ("msk_init\n")); 2108 2109 s = splnet(); 2110 2111 /* Cancel pending I/O and free all RX/TX buffers. */ 2112 msk_stop(ifp,0); 2113 2114 /* Configure I2C registers */ 2115 2116 /* Configure XMAC(s) */ 2117 msk_init_yukon(sc_if); 2118 if ((rc = ether_mediachange(ifp)) != 0) 2119 goto out; 2120 2121 /* Configure transmit arbiter(s) */ 2122 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2123 #if 0 2124 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2125 #endif 2126 2127 /* Configure RAMbuffers */ 2128 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2129 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2130 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2134 2135 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2136 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2137 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2141 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2142 2143 /* Configure BMUs */ 2144 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2145 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2146 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2147 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2148 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2150 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2151 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2152 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2153 2154 /* Make sure the sync transmit queue is disabled. */ 2155 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2156 2157 /* Init descriptors */ 2158 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2159 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2160 "memory for rx buffers\n"); 2161 msk_stop(ifp,0); 2162 splx(s); 2163 return ENOBUFS; 2164 } 2165 2166 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2167 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2168 "memory for tx buffers\n"); 2169 msk_stop(ifp,0); 2170 splx(s); 2171 return ENOBUFS; 2172 } 2173 2174 /* Set interrupt moderation if changed via sysctl. */ 2175 switch (sc->sk_type) { 2176 case SK_YUKON_EC: 2177 case SK_YUKON_EC_U: 2178 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2179 break; 2180 case SK_YUKON_FE: 2181 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2182 break; 2183 case SK_YUKON_XL: 2184 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2185 break; 2186 default: 2187 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2188 } 2189 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2190 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2191 sk_win_write_4(sc, SK_IMTIMERINIT, 2192 SK_IM_USECS(sc->sk_int_mod)); 2193 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2194 sc->sk_int_mod); 2195 } 2196 2197 /* Initialize prefetch engine. */ 2198 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2199 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2200 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2201 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2202 MSK_RX_RING_ADDR(sc_if, 0)); 2203 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2204 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2205 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2206 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2207 2208 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2209 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2210 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2211 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2212 MSK_TX_RING_ADDR(sc_if, 0)); 2213 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2214 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2215 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2216 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2217 2218 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2219 sc_if->sk_cdata.sk_rx_prod); 2220 2221 /* Configure interrupt handling */ 2222 if (sc_if->sk_port == SK_PORT_A) 2223 sc->sk_intrmask |= SK_Y2_INTRS1; 2224 else 2225 sc->sk_intrmask |= SK_Y2_INTRS2; 2226 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2227 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2228 2229 ifp->if_flags |= IFF_RUNNING; 2230 ifp->if_flags &= ~IFF_OACTIVE; 2231 2232 callout_schedule(&sc_if->sk_tick_ch, hz); 2233 2234 out: 2235 splx(s); 2236 return rc; 2237 } 2238 2239 void 2240 msk_stop(struct ifnet *ifp, int disable) 2241 { 2242 struct sk_if_softc *sc_if = ifp->if_softc; 2243 struct sk_softc *sc = sc_if->sk_softc; 2244 struct sk_txmap_entry *dma; 2245 int i; 2246 2247 DPRINTFN(2, ("msk_stop\n")); 2248 2249 callout_stop(&sc_if->sk_tick_ch); 2250 2251 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2252 2253 /* Stop transfer of Tx descriptors */ 2254 2255 /* Stop transfer of Rx descriptors */ 2256 2257 /* Turn off various components of this interface. */ 2258 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2259 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2260 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2261 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2262 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2263 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2264 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2265 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2266 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2267 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2268 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2269 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2270 2271 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2272 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2273 2274 /* Disable interrupts */ 2275 if (sc_if->sk_port == SK_PORT_A) 2276 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2277 else 2278 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2279 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2280 2281 SK_XM_READ_2(sc_if, XM_ISR); 2282 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2283 2284 /* Free RX and TX mbufs still in the queues. */ 2285 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2286 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2287 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2288 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2289 } 2290 } 2291 2292 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2293 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2294 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2295 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2296 #if 1 2297 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2298 sc_if->sk_cdata.sk_tx_map[i], link); 2299 sc_if->sk_cdata.sk_tx_map[i] = 0; 2300 #endif 2301 } 2302 } 2303 2304 #if 1 2305 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2306 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2307 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2308 free(dma, M_DEVBUF); 2309 } 2310 #endif 2311 } 2312 2313 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2314 NULL, NULL); 2315 2316 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2317 NULL, NULL); 2318 2319 #ifdef MSK_DEBUG 2320 void 2321 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2322 { 2323 #define DESC_PRINT(X) \ 2324 if (X) \ 2325 printf("txdesc[%d]." #X "=%#x\n", \ 2326 idx, X); 2327 2328 DESC_PRINT(letoh32(le->sk_addr)); 2329 DESC_PRINT(letoh16(le->sk_len)); 2330 DESC_PRINT(le->sk_ctl); 2331 DESC_PRINT(le->sk_opcode); 2332 #undef DESC_PRINT 2333 } 2334 2335 void 2336 msk_dump_bytes(const char *data, int len) 2337 { 2338 int c, i, j; 2339 2340 for (i = 0; i < len; i += 16) { 2341 printf("%08x ", i); 2342 c = len - i; 2343 if (c > 16) c = 16; 2344 2345 for (j = 0; j < c; j++) { 2346 printf("%02x ", data[i + j] & 0xff); 2347 if ((j & 0xf) == 7 && j > 0) 2348 printf(" "); 2349 } 2350 2351 for (; j < 16; j++) 2352 printf(" "); 2353 printf(" "); 2354 2355 for (j = 0; j < c; j++) { 2356 int ch = data[i + j] & 0xff; 2357 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2358 } 2359 2360 printf("\n"); 2361 2362 if (c < 16) 2363 break; 2364 } 2365 } 2366 2367 void 2368 msk_dump_mbuf(struct mbuf *m) 2369 { 2370 int count = m->m_pkthdr.len; 2371 2372 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2373 2374 while (count > 0 && m) { 2375 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2376 m, m->m_data, m->m_len); 2377 msk_dump_bytes(mtod(m, char *), m->m_len); 2378 2379 count -= m->m_len; 2380 m = m->m_next; 2381 } 2382 } 2383 #endif 2384 2385 static int 2386 msk_sysctl_handler(SYSCTLFN_ARGS) 2387 { 2388 int error, t; 2389 struct sysctlnode node; 2390 struct sk_softc *sc; 2391 2392 node = *rnode; 2393 sc = node.sysctl_data; 2394 t = sc->sk_int_mod; 2395 node.sysctl_data = &t; 2396 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2397 if (error || newp == NULL) 2398 return error; 2399 2400 if (t < SK_IM_MIN || t > SK_IM_MAX) 2401 return EINVAL; 2402 2403 /* update the softc with sysctl-changed value, and mark 2404 for hardware update */ 2405 sc->sk_int_mod = t; 2406 sc->sk_int_mod_pending = 1; 2407 return 0; 2408 } 2409 2410 /* 2411 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2412 * set up in skc_attach() 2413 */ 2414 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2415 { 2416 int rc; 2417 const struct sysctlnode *node; 2418 2419 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2420 0, CTLTYPE_NODE, "hw", NULL, 2421 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2422 goto err; 2423 } 2424 2425 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2426 0, CTLTYPE_NODE, "msk", 2427 SYSCTL_DESCR("msk interface controls"), 2428 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2429 goto err; 2430 } 2431 2432 msk_root_num = node->sysctl_num; 2433 return; 2434 2435 err: 2436 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2437 } 2438