1 /* $NetBSD: if_msk.c,v 1.39 2012/02/02 19:43:05 tls Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.39 2012/02/02 19:43:05 tls Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rnd.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 static bool mskc_suspend(device_t, const pmf_qual_t *); 98 static bool mskc_resume(device_t, const pmf_qual_t *); 99 int msk_probe(device_t, cfdata_t, void *); 100 void msk_attach(device_t, device_t, void *); 101 int mskcprint(void *, const char *); 102 int msk_intr(void *); 103 void msk_intr_yukon(struct sk_if_softc *); 104 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 105 void msk_txeof(struct sk_if_softc *, int); 106 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 107 void msk_start(struct ifnet *); 108 int msk_ioctl(struct ifnet *, u_long, void *); 109 int msk_init(struct ifnet *); 110 void msk_init_yukon(struct sk_if_softc *); 111 void msk_stop(struct ifnet *, int); 112 void msk_watchdog(struct ifnet *); 113 void msk_reset(struct sk_softc *); 114 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 115 int msk_alloc_jumbo_mem(struct sk_if_softc *); 116 void *msk_jalloc(struct sk_if_softc *); 117 void msk_jfree(struct mbuf *, void *, size_t, void *); 118 int msk_init_rx_ring(struct sk_if_softc *); 119 int msk_init_tx_ring(struct sk_if_softc *); 120 121 void msk_update_int_mod(struct sk_softc *, int); 122 123 int msk_miibus_readreg(device_t, int, int); 124 void msk_miibus_writereg(device_t, int, int, int); 125 void msk_miibus_statchg(device_t); 126 127 void msk_setfilt(struct sk_if_softc *, void *, int); 128 void msk_setmulti(struct sk_if_softc *); 129 void msk_setpromisc(struct sk_if_softc *); 130 void msk_tick(void *); 131 132 /* #define MSK_DEBUG 1 */ 133 #ifdef MSK_DEBUG 134 #define DPRINTF(x) if (mskdebug) printf x 135 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 136 int mskdebug = MSK_DEBUG; 137 138 void msk_dump_txdesc(struct msk_tx_desc *, int); 139 void msk_dump_mbuf(struct mbuf *); 140 void msk_dump_bytes(const char *, int); 141 #else 142 #define DPRINTF(x) 143 #define DPRINTFN(n,x) 144 #endif 145 146 static int msk_sysctl_handler(SYSCTLFN_PROTO); 147 static int msk_root_num; 148 149 /* supported device vendors */ 150 static const struct msk_product { 151 pci_vendor_id_t msk_vendor; 152 pci_product_id_t msk_product; 153 } msk_products[] = { 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 157 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 158 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 159 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 181 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 182 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 183 }; 184 185 static inline u_int32_t 186 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 187 { 188 return CSR_READ_4(sc, reg); 189 } 190 191 static inline u_int16_t 192 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_2(sc, reg); 195 } 196 197 static inline u_int8_t 198 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 199 { 200 return CSR_READ_1(sc, reg); 201 } 202 203 static inline void 204 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 205 { 206 CSR_WRITE_4(sc, reg, x); 207 } 208 209 static inline void 210 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 211 { 212 CSR_WRITE_2(sc, reg, x); 213 } 214 215 static inline void 216 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 217 { 218 CSR_WRITE_1(sc, reg, x); 219 } 220 221 int 222 msk_miibus_readreg(device_t dev, int phy, int reg) 223 { 224 struct sk_if_softc *sc_if = device_private(dev); 225 u_int16_t val; 226 int i; 227 228 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 229 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 230 231 for (i = 0; i < SK_TIMEOUT; i++) { 232 DELAY(1); 233 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 234 if (val & YU_SMICR_READ_VALID) 235 break; 236 } 237 238 if (i == SK_TIMEOUT) { 239 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 240 return (0); 241 } 242 243 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 244 SK_TIMEOUT)); 245 246 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 247 248 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 249 phy, reg, val)); 250 251 return (val); 252 } 253 254 void 255 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 256 { 257 struct sk_if_softc *sc_if = device_private(dev); 258 int i; 259 260 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 261 phy, reg, val)); 262 263 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 264 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 265 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 266 267 for (i = 0; i < SK_TIMEOUT; i++) { 268 DELAY(1); 269 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 270 break; 271 } 272 273 if (i == SK_TIMEOUT) 274 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 275 } 276 277 void 278 msk_miibus_statchg(device_t dev) 279 { 280 struct sk_if_softc *sc_if = device_private(dev); 281 struct mii_data *mii = &sc_if->sk_mii; 282 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 283 int gpcr; 284 285 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 286 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 287 288 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 289 /* Set speed. */ 290 gpcr |= YU_GPCR_SPEED_DIS; 291 switch (IFM_SUBTYPE(mii->mii_media_active)) { 292 case IFM_1000_SX: 293 case IFM_1000_LX: 294 case IFM_1000_CX: 295 case IFM_1000_T: 296 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 297 break; 298 case IFM_100_TX: 299 gpcr |= YU_GPCR_SPEED; 300 break; 301 } 302 303 /* Set duplex. */ 304 gpcr |= YU_GPCR_DPLX_DIS; 305 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 306 gpcr |= YU_GPCR_DUPLEX; 307 308 /* Disable flow control. */ 309 gpcr |= YU_GPCR_FCTL_DIS; 310 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 311 } 312 313 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 314 315 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 316 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 317 } 318 319 #define HASH_BITS 6 320 321 void 322 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 323 { 324 char *addr = addrv; 325 int base = XM_RXFILT_ENTRY(slot); 326 327 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 328 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 329 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 330 } 331 332 void 333 msk_setmulti(struct sk_if_softc *sc_if) 334 { 335 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 336 u_int32_t hashes[2] = { 0, 0 }; 337 int h; 338 struct ethercom *ec = &sc_if->sk_ethercom; 339 struct ether_multi *enm; 340 struct ether_multistep step; 341 u_int16_t reg; 342 343 /* First, zot all the existing filters. */ 344 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 345 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 346 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 348 349 350 /* Now program new ones. */ 351 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 352 reg |= YU_RCR_UFLEN; 353 allmulti: 354 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 355 if ((ifp->if_flags & IFF_PROMISC) != 0) 356 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 357 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 358 hashes[0] = 0xFFFFFFFF; 359 hashes[1] = 0xFFFFFFFF; 360 } 361 } else { 362 /* First find the tail of the list. */ 363 ETHER_FIRST_MULTI(step, ec, enm); 364 while (enm != NULL) { 365 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 366 ETHER_ADDR_LEN)) { 367 ifp->if_flags |= IFF_ALLMULTI; 368 goto allmulti; 369 } 370 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 371 ((1 << HASH_BITS) - 1); 372 if (h < 32) 373 hashes[0] |= (1 << h); 374 else 375 hashes[1] |= (1 << (h - 32)); 376 377 ETHER_NEXT_MULTI(step, enm); 378 } 379 reg |= YU_RCR_MUFLEN; 380 } 381 382 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 383 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 384 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 387 } 388 389 void 390 msk_setpromisc(struct sk_if_softc *sc_if) 391 { 392 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 393 394 if (ifp->if_flags & IFF_PROMISC) 395 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 396 YU_RCR_UFLEN | YU_RCR_MUFLEN); 397 else 398 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 399 YU_RCR_UFLEN | YU_RCR_MUFLEN); 400 } 401 402 int 403 msk_init_rx_ring(struct sk_if_softc *sc_if) 404 { 405 struct msk_chain_data *cd = &sc_if->sk_cdata; 406 struct msk_ring_data *rd = sc_if->sk_rdata; 407 int i, nexti; 408 409 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 410 411 for (i = 0; i < MSK_RX_RING_CNT; i++) { 412 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 413 if (i == (MSK_RX_RING_CNT - 1)) 414 nexti = 0; 415 else 416 nexti = i + 1; 417 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 418 } 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 if (msk_newbuf(sc_if, i, NULL, 422 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 423 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 424 return (ENOBUFS); 425 } 426 } 427 428 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 429 sc_if->sk_cdata.sk_rx_cons = 0; 430 431 return (0); 432 } 433 434 int 435 msk_init_tx_ring(struct sk_if_softc *sc_if) 436 { 437 struct sk_softc *sc = sc_if->sk_softc; 438 struct msk_chain_data *cd = &sc_if->sk_cdata; 439 struct msk_ring_data *rd = sc_if->sk_rdata; 440 bus_dmamap_t dmamap; 441 struct sk_txmap_entry *entry; 442 int i, nexti; 443 444 memset(sc_if->sk_rdata->sk_tx_ring, 0, 445 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 446 447 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 448 for (i = 0; i < MSK_TX_RING_CNT; i++) { 449 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 450 if (i == (MSK_TX_RING_CNT - 1)) 451 nexti = 0; 452 else 453 nexti = i + 1; 454 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 455 456 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 457 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 458 return (ENOBUFS); 459 460 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 461 if (!entry) { 462 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 463 return (ENOBUFS); 464 } 465 entry->dmamap = dmamap; 466 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 467 } 468 469 sc_if->sk_cdata.sk_tx_prod = 0; 470 sc_if->sk_cdata.sk_tx_cons = 0; 471 sc_if->sk_cdata.sk_tx_cnt = 0; 472 473 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 474 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 475 476 return (0); 477 } 478 479 int 480 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 481 bus_dmamap_t dmamap) 482 { 483 struct mbuf *m_new = NULL; 484 struct sk_chain *c; 485 struct msk_rx_desc *r; 486 487 if (m == NULL) { 488 void *buf = NULL; 489 490 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 491 if (m_new == NULL) 492 return (ENOBUFS); 493 494 /* Allocate the jumbo buffer */ 495 buf = msk_jalloc(sc_if); 496 if (buf == NULL) { 497 m_freem(m_new); 498 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 499 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 500 return (ENOBUFS); 501 } 502 503 /* Attach the buffer to the mbuf */ 504 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 505 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 506 } else { 507 /* 508 * We're re-using a previously allocated mbuf; 509 * be sure to re-init pointers and lengths to 510 * default values. 511 */ 512 m_new = m; 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 m_new->m_data = m_new->m_ext.ext_buf; 515 } 516 m_adj(m_new, ETHER_ALIGN); 517 518 c = &sc_if->sk_cdata.sk_rx_chain[i]; 519 r = c->sk_le; 520 c->sk_mbuf = m_new; 521 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 522 (((vaddr_t)m_new->m_data 523 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 524 r->sk_len = htole16(SK_JLEN); 525 r->sk_ctl = 0; 526 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 527 528 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 529 530 return (0); 531 } 532 533 /* 534 * Memory management for jumbo frames. 535 */ 536 537 int 538 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 539 { 540 struct sk_softc *sc = sc_if->sk_softc; 541 char *ptr, *kva; 542 bus_dma_segment_t seg; 543 int i, rseg, state, error; 544 struct sk_jpool_entry *entry; 545 546 state = error = 0; 547 548 /* Grab a big chunk o' storage. */ 549 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 550 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 551 aprint_error(": can't alloc rx buffers"); 552 return (ENOBUFS); 553 } 554 555 state = 1; 556 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 557 BUS_DMA_NOWAIT)) { 558 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 559 error = ENOBUFS; 560 goto out; 561 } 562 563 state = 2; 564 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 565 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 566 aprint_error(": can't create dma map"); 567 error = ENOBUFS; 568 goto out; 569 } 570 571 state = 3; 572 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 573 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 574 aprint_error(": can't load dma map"); 575 error = ENOBUFS; 576 goto out; 577 } 578 579 state = 4; 580 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 581 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 582 583 LIST_INIT(&sc_if->sk_jfree_listhead); 584 LIST_INIT(&sc_if->sk_jinuse_listhead); 585 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 586 587 /* 588 * Now divide it up into 9K pieces and save the addresses 589 * in an array. 590 */ 591 ptr = sc_if->sk_cdata.sk_jumbo_buf; 592 for (i = 0; i < MSK_JSLOTS; i++) { 593 sc_if->sk_cdata.sk_jslots[i] = ptr; 594 ptr += SK_JLEN; 595 entry = malloc(sizeof(struct sk_jpool_entry), 596 M_DEVBUF, M_NOWAIT); 597 if (entry == NULL) { 598 sc_if->sk_cdata.sk_jumbo_buf = NULL; 599 aprint_error(": no memory for jumbo buffer queue!"); 600 error = ENOBUFS; 601 goto out; 602 } 603 entry->slot = i; 604 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 605 entry, jpool_entries); 606 } 607 out: 608 if (error != 0) { 609 switch (state) { 610 case 4: 611 bus_dmamap_unload(sc->sc_dmatag, 612 sc_if->sk_cdata.sk_rx_jumbo_map); 613 case 3: 614 bus_dmamap_destroy(sc->sc_dmatag, 615 sc_if->sk_cdata.sk_rx_jumbo_map); 616 case 2: 617 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 618 case 1: 619 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 620 break; 621 default: 622 break; 623 } 624 } 625 626 return (error); 627 } 628 629 /* 630 * Allocate a jumbo buffer. 631 */ 632 void * 633 msk_jalloc(struct sk_if_softc *sc_if) 634 { 635 struct sk_jpool_entry *entry; 636 637 mutex_enter(&sc_if->sk_jpool_mtx); 638 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 639 640 if (entry == NULL) { 641 mutex_exit(&sc_if->sk_jpool_mtx); 642 return NULL; 643 } 644 645 LIST_REMOVE(entry, jpool_entries); 646 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 647 mutex_exit(&sc_if->sk_jpool_mtx); 648 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 649 } 650 651 /* 652 * Release a jumbo buffer. 653 */ 654 void 655 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 656 { 657 struct sk_jpool_entry *entry; 658 struct sk_if_softc *sc; 659 int i; 660 661 /* Extract the softc struct pointer. */ 662 sc = (struct sk_if_softc *)arg; 663 664 if (sc == NULL) 665 panic("msk_jfree: can't find softc pointer!"); 666 667 /* calculate the slot this buffer belongs to */ 668 i = ((vaddr_t)buf 669 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 670 671 if ((i < 0) || (i >= MSK_JSLOTS)) 672 panic("msk_jfree: asked to free buffer that we don't manage!"); 673 674 mutex_enter(&sc->sk_jpool_mtx); 675 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 676 if (entry == NULL) 677 panic("msk_jfree: buffer not in use!"); 678 entry->slot = i; 679 LIST_REMOVE(entry, jpool_entries); 680 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 681 mutex_exit(&sc->sk_jpool_mtx); 682 683 if (__predict_true(m != NULL)) 684 pool_cache_put(mb_cache, m); 685 } 686 687 int 688 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 689 { 690 struct sk_if_softc *sc_if = ifp->if_softc; 691 int s, error = 0; 692 693 s = splnet(); 694 695 DPRINTFN(2, ("msk_ioctl ETHER\n")); 696 error = ether_ioctl(ifp, cmd, data); 697 698 if (error == ENETRESET) { 699 error = 0; 700 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 701 ; 702 else if (ifp->if_flags & IFF_RUNNING) { 703 /* 704 * Multicast list has changed; set the hardware 705 * filter accordingly. 706 */ 707 msk_setmulti(sc_if); 708 } 709 } 710 711 splx(s); 712 return (error); 713 } 714 715 void 716 msk_update_int_mod(struct sk_softc *sc, int verbose) 717 { 718 u_int32_t imtimer_ticks; 719 720 /* 721 * Configure interrupt moderation. The moderation timer 722 * defers interrupts specified in the interrupt moderation 723 * timer mask based on the timeout specified in the interrupt 724 * moderation timer init register. Each bit in the timer 725 * register represents one tick, so to specify a timeout in 726 * microseconds, we have to multiply by the correct number of 727 * ticks-per-microsecond. 728 */ 729 switch (sc->sk_type) { 730 case SK_YUKON_EC: 731 case SK_YUKON_EC_U: 732 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 733 break; 734 case SK_YUKON_FE: 735 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 736 break; 737 case SK_YUKON_XL: 738 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 739 break; 740 default: 741 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 742 } 743 if (verbose) 744 aprint_verbose_dev(sc->sk_dev, 745 "interrupt moderation is %d us\n", sc->sk_int_mod); 746 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 747 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 748 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 749 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 750 sc->sk_int_mod_pending = 0; 751 } 752 753 static int 754 msk_lookup(const struct pci_attach_args *pa) 755 { 756 const struct msk_product *pmsk; 757 758 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 759 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 760 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 761 return 1; 762 } 763 return 0; 764 } 765 766 /* 767 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 768 * IDs against our list and return a device name if we find a match. 769 */ 770 int 771 mskc_probe(device_t parent, cfdata_t match, void *aux) 772 { 773 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 774 775 return msk_lookup(pa); 776 } 777 778 /* 779 * Force the GEnesis into reset, then bring it out of reset. 780 */ 781 void msk_reset(struct sk_softc *sc) 782 { 783 u_int32_t imtimer_ticks, reg1; 784 int reg; 785 786 DPRINTFN(2, ("msk_reset\n")); 787 788 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 789 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 790 791 DELAY(1000); 792 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 793 DELAY(2); 794 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 795 sk_win_write_1(sc, SK_TESTCTL1, 2); 796 797 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 798 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 799 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 800 else 801 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 802 803 if (sc->sk_type == SK_YUKON_EC_U) { 804 uint32_t our; 805 806 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 807 808 /* enable all clocks. */ 809 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 810 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 811 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 812 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 813 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 814 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 815 /* Set all bits to 0 except bits 15..12 */ 816 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 817 /* Set to default value */ 818 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 819 } 820 821 /* release PHY from PowerDown/Coma mode. */ 822 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 823 824 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 825 sk_win_write_1(sc, SK_Y2_CLKGATE, 826 SK_Y2_CLKGATE_LINK1_GATE_DIS | 827 SK_Y2_CLKGATE_LINK2_GATE_DIS | 828 SK_Y2_CLKGATE_LINK1_CORE_DIS | 829 SK_Y2_CLKGATE_LINK2_CORE_DIS | 830 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 831 else 832 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 833 834 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 835 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 836 DELAY(1000); 837 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 838 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 839 840 sk_win_write_1(sc, SK_TESTCTL1, 1); 841 842 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 843 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 844 CSR_READ_2(sc, SK_LINK_CTRL))); 845 846 /* Disable ASF */ 847 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 848 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 849 850 /* Clear I2C IRQ noise */ 851 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 852 853 /* Disable hardware timer */ 854 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 855 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 856 857 /* Disable descriptor polling */ 858 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 859 860 /* Disable time stamps */ 861 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 862 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 863 864 /* Enable RAM interface */ 865 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 866 for (reg = SK_TO0;reg <= SK_TO11; reg++) 867 sk_win_write_1(sc, reg, 36); 868 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 869 for (reg = SK_TO0;reg <= SK_TO11; reg++) 870 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 871 872 /* 873 * Configure interrupt moderation. The moderation timer 874 * defers interrupts specified in the interrupt moderation 875 * timer mask based on the timeout specified in the interrupt 876 * moderation timer init register. Each bit in the timer 877 * register represents one tick, so to specify a timeout in 878 * microseconds, we have to multiply by the correct number of 879 * ticks-per-microsecond. 880 */ 881 switch (sc->sk_type) { 882 case SK_YUKON_EC: 883 case SK_YUKON_EC_U: 884 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 885 break; 886 case SK_YUKON_FE: 887 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 888 break; 889 case SK_YUKON_XL: 890 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 891 break; 892 default: 893 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 894 } 895 896 /* Reset status ring. */ 897 memset(sc->sk_status_ring, 0, 898 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 899 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 900 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 901 sc->sk_status_idx = 0; 902 sc->sk_status_own_idx = 0; 903 904 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 905 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 906 907 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 908 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 909 sc->sk_status_map->dm_segs[0].ds_addr); 910 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 911 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 912 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 913 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 914 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 915 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 916 } else { 917 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 918 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 919 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 920 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 921 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 922 } 923 924 #if 0 925 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 926 #endif 927 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 928 929 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 930 931 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 932 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 933 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 934 935 msk_update_int_mod(sc, 0); 936 } 937 938 int 939 msk_probe(device_t parent, cfdata_t match, void *aux) 940 { 941 struct skc_attach_args *sa = aux; 942 943 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 944 return (0); 945 946 switch (sa->skc_type) { 947 case SK_YUKON_XL: 948 case SK_YUKON_EC_U: 949 case SK_YUKON_EC: 950 case SK_YUKON_FE: 951 return (1); 952 } 953 954 return (0); 955 } 956 957 static bool 958 msk_resume(device_t dv, const pmf_qual_t *qual) 959 { 960 struct sk_if_softc *sc_if = device_private(dv); 961 962 msk_init_yukon(sc_if); 963 return true; 964 } 965 966 /* 967 * Each XMAC chip is attached as a separate logical IP interface. 968 * Single port cards will have only one logical interface of course. 969 */ 970 void 971 msk_attach(device_t parent, device_t self, void *aux) 972 { 973 struct sk_if_softc *sc_if = device_private(self); 974 struct sk_softc *sc = device_private(parent); 975 struct skc_attach_args *sa = aux; 976 struct ifnet *ifp; 977 void *kva; 978 bus_dma_segment_t seg; 979 int i, rseg; 980 u_int32_t chunk, val; 981 982 sc_if->sk_dev = self; 983 sc_if->sk_port = sa->skc_port; 984 sc_if->sk_softc = sc; 985 sc->sk_if[sa->skc_port] = sc_if; 986 987 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 988 989 /* 990 * Get station address for this interface. Note that 991 * dual port cards actually come with three station 992 * addresses: one for each port, plus an extra. The 993 * extra one is used by the SysKonnect driver software 994 * as a 'virtual' station address for when both ports 995 * are operating in failover mode. Currently we don't 996 * use this extra address. 997 */ 998 for (i = 0; i < ETHER_ADDR_LEN; i++) 999 sc_if->sk_enaddr[i] = 1000 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1001 1002 aprint_normal(": Ethernet address %s\n", 1003 ether_sprintf(sc_if->sk_enaddr)); 1004 1005 /* 1006 * Set up RAM buffer addresses. The NIC will have a certain 1007 * amount of SRAM on it, somewhere between 512K and 2MB. We 1008 * need to divide this up a) between the transmitter and 1009 * receiver and b) between the two XMACs, if this is a 1010 * dual port NIC. Our algorithm is to divide up the memory 1011 * evenly so that everyone gets a fair share. 1012 * 1013 * Just to be contrary, Yukon2 appears to have separate memory 1014 * for each MAC. 1015 */ 1016 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1017 val = sc->sk_rboff / sizeof(u_int64_t); 1018 sc_if->sk_rx_ramstart = val; 1019 val += (chunk / sizeof(u_int64_t)); 1020 sc_if->sk_rx_ramend = val - 1; 1021 chunk = sc->sk_ramsize - chunk; 1022 sc_if->sk_tx_ramstart = val; 1023 val += (chunk / sizeof(u_int64_t)); 1024 sc_if->sk_tx_ramend = val - 1; 1025 1026 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1027 " tx_ramstart=%#x tx_ramend=%#x\n", 1028 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1029 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1030 1031 /* Allocate the descriptor queues. */ 1032 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1033 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1034 aprint_error(": can't alloc rx buffers\n"); 1035 goto fail; 1036 } 1037 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1038 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1039 aprint_error(": can't map dma buffers (%zu bytes)\n", 1040 sizeof(struct msk_ring_data)); 1041 goto fail_1; 1042 } 1043 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1044 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1045 &sc_if->sk_ring_map)) { 1046 aprint_error(": can't create dma map\n"); 1047 goto fail_2; 1048 } 1049 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1050 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1051 aprint_error(": can't load dma map\n"); 1052 goto fail_3; 1053 } 1054 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1055 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1056 1057 ifp = &sc_if->sk_ethercom.ec_if; 1058 /* Try to allocate memory for jumbo buffers. */ 1059 if (msk_alloc_jumbo_mem(sc_if)) { 1060 aprint_error(": jumbo buffer allocation failed\n"); 1061 goto fail_3; 1062 } 1063 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1064 if (sc->sk_type != SK_YUKON_FE) 1065 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1066 1067 ifp->if_softc = sc_if; 1068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1069 ifp->if_ioctl = msk_ioctl; 1070 ifp->if_start = msk_start; 1071 ifp->if_stop = msk_stop; 1072 ifp->if_init = msk_init; 1073 ifp->if_watchdog = msk_watchdog; 1074 ifp->if_baudrate = 1000000000; 1075 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1076 IFQ_SET_READY(&ifp->if_snd); 1077 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1078 1079 /* 1080 * Do miibus setup. 1081 */ 1082 msk_init_yukon(sc_if); 1083 1084 DPRINTFN(2, ("msk_attach: 1\n")); 1085 1086 sc_if->sk_mii.mii_ifp = ifp; 1087 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1088 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1089 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1090 1091 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1092 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1093 ether_mediachange, ether_mediastatus); 1094 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1095 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1096 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1097 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1098 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1099 0, NULL); 1100 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1101 } else 1102 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1103 1104 callout_init(&sc_if->sk_tick_ch, 0); 1105 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1106 callout_schedule(&sc_if->sk_tick_ch, hz); 1107 1108 /* 1109 * Call MI attach routines. 1110 */ 1111 if_attach(ifp); 1112 ether_ifattach(ifp, sc_if->sk_enaddr); 1113 1114 if (pmf_device_register(self, NULL, msk_resume)) 1115 pmf_class_network_register(self, ifp); 1116 else 1117 aprint_error_dev(self, "couldn't establish power handler\n"); 1118 1119 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1120 RND_TYPE_NET, 0); 1121 1122 DPRINTFN(2, ("msk_attach: end\n")); 1123 return; 1124 1125 fail_3: 1126 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1127 fail_2: 1128 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1129 fail_1: 1130 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1131 fail: 1132 sc->sk_if[sa->skc_port] = NULL; 1133 } 1134 1135 int 1136 mskcprint(void *aux, const char *pnp) 1137 { 1138 struct skc_attach_args *sa = aux; 1139 1140 if (pnp) 1141 aprint_normal("sk port %c at %s", 1142 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1143 else 1144 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1145 return (UNCONF); 1146 } 1147 1148 /* 1149 * Attach the interface. Allocate softc structures, do ifmedia 1150 * setup and ethernet/BPF attach. 1151 */ 1152 void 1153 mskc_attach(device_t parent, device_t self, void *aux) 1154 { 1155 struct sk_softc *sc = device_private(self); 1156 struct pci_attach_args *pa = aux; 1157 struct skc_attach_args skca; 1158 pci_chipset_tag_t pc = pa->pa_pc; 1159 pcireg_t command, memtype; 1160 pci_intr_handle_t ih; 1161 const char *intrstr = NULL; 1162 bus_size_t size; 1163 int rc, sk_nodenum; 1164 u_int8_t hw, skrs; 1165 const char *revstr = NULL; 1166 const struct sysctlnode *node; 1167 void *kva; 1168 bus_dma_segment_t seg; 1169 int rseg; 1170 1171 DPRINTFN(2, ("begin mskc_attach\n")); 1172 1173 sc->sk_dev = self; 1174 /* 1175 * Handle power management nonsense. 1176 */ 1177 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1178 1179 if (command == 0x01) { 1180 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1181 if (command & SK_PSTATE_MASK) { 1182 u_int32_t iobase, membase, irq; 1183 1184 /* Save important PCI config data. */ 1185 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1186 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1187 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1188 1189 /* Reset the power state. */ 1190 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1191 "mode -- setting to D0\n", 1192 command & SK_PSTATE_MASK); 1193 command &= 0xFFFFFFFC; 1194 pci_conf_write(pc, pa->pa_tag, 1195 SK_PCI_PWRMGMTCTRL, command); 1196 1197 /* Restore PCI config data. */ 1198 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1199 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1200 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1201 } 1202 } 1203 1204 /* 1205 * Map control/status registers. 1206 */ 1207 1208 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1209 switch (memtype) { 1210 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1211 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1212 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1213 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1214 NULL, &size) == 0) { 1215 break; 1216 } 1217 default: 1218 aprint_error(": can't map mem space\n"); 1219 return; 1220 } 1221 1222 sc->sc_dmatag = pa->pa_dmat; 1223 1224 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1225 command |= PCI_COMMAND_MASTER_ENABLE; 1226 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1227 1228 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1229 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1230 1231 /* bail out here if chip is not recognized */ 1232 if (!(SK_IS_YUKON2(sc))) { 1233 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1234 goto fail_1; 1235 } 1236 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1237 1238 /* Allocate interrupt */ 1239 if (pci_intr_map(pa, &ih)) { 1240 aprint_error(": couldn't map interrupt\n"); 1241 goto fail_1; 1242 } 1243 1244 intrstr = pci_intr_string(pc, ih); 1245 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1246 if (sc->sk_intrhand == NULL) { 1247 aprint_error(": couldn't establish interrupt"); 1248 if (intrstr != NULL) 1249 aprint_error(" at %s", intrstr); 1250 aprint_error("\n"); 1251 goto fail_1; 1252 } 1253 1254 if (bus_dmamem_alloc(sc->sc_dmatag, 1255 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1256 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1257 aprint_error(": can't alloc status buffers\n"); 1258 goto fail_2; 1259 } 1260 1261 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1262 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1263 &kva, BUS_DMA_NOWAIT)) { 1264 aprint_error(": can't map dma buffers (%zu bytes)\n", 1265 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1266 goto fail_3; 1267 } 1268 if (bus_dmamap_create(sc->sc_dmatag, 1269 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1270 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1271 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1272 aprint_error(": can't create dma map\n"); 1273 goto fail_4; 1274 } 1275 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1276 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1277 NULL, BUS_DMA_NOWAIT)) { 1278 aprint_error(": can't load dma map\n"); 1279 goto fail_5; 1280 } 1281 sc->sk_status_ring = (struct msk_status_desc *)kva; 1282 1283 1284 sc->sk_int_mod = SK_IM_DEFAULT; 1285 sc->sk_int_mod_pending = 0; 1286 1287 /* Reset the adapter. */ 1288 msk_reset(sc); 1289 1290 skrs = sk_win_read_1(sc, SK_EPROM0); 1291 if (skrs == 0x00) 1292 sc->sk_ramsize = 0x20000; 1293 else 1294 sc->sk_ramsize = skrs * (1<<12); 1295 sc->sk_rboff = SK_RBOFF_0; 1296 1297 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1298 sc->sk_ramsize, sc->sk_ramsize / 1024, 1299 sc->sk_rboff)); 1300 1301 switch (sc->sk_type) { 1302 case SK_YUKON_XL: 1303 sc->sk_name = "Yukon-2 XL"; 1304 break; 1305 case SK_YUKON_EC_U: 1306 sc->sk_name = "Yukon-2 EC Ultra"; 1307 break; 1308 case SK_YUKON_EC: 1309 sc->sk_name = "Yukon-2 EC"; 1310 break; 1311 case SK_YUKON_FE: 1312 sc->sk_name = "Yukon-2 FE"; 1313 break; 1314 default: 1315 sc->sk_name = "Yukon (Unknown)"; 1316 } 1317 1318 if (sc->sk_type == SK_YUKON_XL) { 1319 switch (sc->sk_rev) { 1320 case SK_YUKON_XL_REV_A0: 1321 sc->sk_workaround = 0; 1322 revstr = "A0"; 1323 break; 1324 case SK_YUKON_XL_REV_A1: 1325 sc->sk_workaround = SK_WA_4109; 1326 revstr = "A1"; 1327 break; 1328 case SK_YUKON_XL_REV_A2: 1329 sc->sk_workaround = SK_WA_4109; 1330 revstr = "A2"; 1331 break; 1332 case SK_YUKON_XL_REV_A3: 1333 sc->sk_workaround = SK_WA_4109; 1334 revstr = "A3"; 1335 break; 1336 default: 1337 sc->sk_workaround = 0; 1338 break; 1339 } 1340 } 1341 1342 if (sc->sk_type == SK_YUKON_EC) { 1343 switch (sc->sk_rev) { 1344 case SK_YUKON_EC_REV_A1: 1345 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1346 revstr = "A1"; 1347 break; 1348 case SK_YUKON_EC_REV_A2: 1349 sc->sk_workaround = SK_WA_4109; 1350 revstr = "A2"; 1351 break; 1352 case SK_YUKON_EC_REV_A3: 1353 sc->sk_workaround = SK_WA_4109; 1354 revstr = "A3"; 1355 break; 1356 default: 1357 sc->sk_workaround = 0; 1358 break; 1359 } 1360 } 1361 1362 if (sc->sk_type == SK_YUKON_FE) { 1363 sc->sk_workaround = SK_WA_4109; 1364 switch (sc->sk_rev) { 1365 case SK_YUKON_FE_REV_A1: 1366 revstr = "A1"; 1367 break; 1368 case SK_YUKON_FE_REV_A2: 1369 revstr = "A2"; 1370 break; 1371 default: 1372 sc->sk_workaround = 0; 1373 break; 1374 } 1375 } 1376 1377 if (sc->sk_type == SK_YUKON_EC_U) { 1378 sc->sk_workaround = SK_WA_4109; 1379 switch (sc->sk_rev) { 1380 case SK_YUKON_EC_U_REV_A0: 1381 revstr = "A0"; 1382 break; 1383 case SK_YUKON_EC_U_REV_A1: 1384 revstr = "A1"; 1385 break; 1386 case SK_YUKON_EC_U_REV_B0: 1387 revstr = "B0"; 1388 break; 1389 default: 1390 sc->sk_workaround = 0; 1391 break; 1392 } 1393 } 1394 1395 /* Announce the product name. */ 1396 aprint_normal(", %s", sc->sk_name); 1397 if (revstr != NULL) 1398 aprint_normal(" rev. %s", revstr); 1399 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1400 1401 sc->sk_macs = 1; 1402 1403 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1404 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1405 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1406 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1407 sc->sk_macs++; 1408 } 1409 1410 skca.skc_port = SK_PORT_A; 1411 skca.skc_type = sc->sk_type; 1412 skca.skc_rev = sc->sk_rev; 1413 (void)config_found(sc->sk_dev, &skca, mskcprint); 1414 1415 if (sc->sk_macs > 1) { 1416 skca.skc_port = SK_PORT_B; 1417 skca.skc_type = sc->sk_type; 1418 skca.skc_rev = sc->sk_rev; 1419 (void)config_found(sc->sk_dev, &skca, mskcprint); 1420 } 1421 1422 /* Turn on the 'driver is loaded' LED. */ 1423 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1424 1425 /* skc sysctl setup */ 1426 1427 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1428 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1429 SYSCTL_DESCR("mskc per-controller controls"), 1430 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1431 CTL_EOL)) != 0) { 1432 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1433 goto fail_6; 1434 } 1435 1436 sk_nodenum = node->sysctl_num; 1437 1438 /* interrupt moderation time in usecs */ 1439 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1440 CTLFLAG_READWRITE, 1441 CTLTYPE_INT, "int_mod", 1442 SYSCTL_DESCR("msk interrupt moderation timer"), 1443 msk_sysctl_handler, 0, sc, 1444 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1445 CTL_EOL)) != 0) { 1446 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1447 goto fail_6; 1448 } 1449 1450 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1451 aprint_error_dev(self, "couldn't establish power handler\n"); 1452 1453 return; 1454 1455 fail_6: 1456 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1457 fail_5: 1458 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1459 fail_4: 1460 bus_dmamem_unmap(sc->sc_dmatag, kva, 1461 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1462 fail_3: 1463 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1464 fail_2: 1465 pci_intr_disestablish(pc, sc->sk_intrhand); 1466 fail_1: 1467 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1468 } 1469 1470 int 1471 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1472 { 1473 struct sk_softc *sc = sc_if->sk_softc; 1474 struct msk_tx_desc *f = NULL; 1475 u_int32_t frag, cur; 1476 int i; 1477 struct sk_txmap_entry *entry; 1478 bus_dmamap_t txmap; 1479 1480 DPRINTFN(2, ("msk_encap\n")); 1481 1482 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1483 if (entry == NULL) { 1484 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1485 return (ENOBUFS); 1486 } 1487 txmap = entry->dmamap; 1488 1489 cur = frag = *txidx; 1490 1491 #ifdef MSK_DEBUG 1492 if (mskdebug >= 2) 1493 msk_dump_mbuf(m_head); 1494 #endif 1495 1496 /* 1497 * Start packing the mbufs in this chain into 1498 * the fragment pointers. Stop when we run out 1499 * of fragments or hit the end of the mbuf chain. 1500 */ 1501 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1502 BUS_DMA_NOWAIT)) { 1503 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1504 return (ENOBUFS); 1505 } 1506 1507 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1508 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1509 bus_dmamap_unload(sc->sc_dmatag, txmap); 1510 return (ENOBUFS); 1511 } 1512 1513 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1514 1515 /* Sync the DMA map. */ 1516 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1517 BUS_DMASYNC_PREWRITE); 1518 1519 for (i = 0; i < txmap->dm_nsegs; i++) { 1520 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1521 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1522 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1523 f->sk_ctl = 0; 1524 if (i == 0) 1525 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1526 else 1527 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1528 cur = frag; 1529 SK_INC(frag, MSK_TX_RING_CNT); 1530 } 1531 1532 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1533 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1534 1535 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1536 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1537 1538 /* Sync descriptors before handing to chip */ 1539 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1540 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1541 1542 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1543 1544 /* Sync first descriptor to hand it off */ 1545 MSK_CDTXSYNC(sc_if, *txidx, 1, 1546 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1547 1548 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1549 1550 #ifdef MSK_DEBUG 1551 if (mskdebug >= 2) { 1552 struct msk_tx_desc *le; 1553 u_int32_t idx; 1554 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1555 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1556 msk_dump_txdesc(le, idx); 1557 } 1558 } 1559 #endif 1560 1561 *txidx = frag; 1562 1563 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1564 1565 return (0); 1566 } 1567 1568 void 1569 msk_start(struct ifnet *ifp) 1570 { 1571 struct sk_if_softc *sc_if = ifp->if_softc; 1572 struct mbuf *m_head = NULL; 1573 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1574 int pkts = 0; 1575 1576 DPRINTFN(2, ("msk_start\n")); 1577 1578 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1579 IFQ_POLL(&ifp->if_snd, m_head); 1580 if (m_head == NULL) 1581 break; 1582 1583 /* 1584 * Pack the data into the transmit ring. If we 1585 * don't have room, set the OACTIVE flag and wait 1586 * for the NIC to drain the ring. 1587 */ 1588 if (msk_encap(sc_if, m_head, &idx)) { 1589 ifp->if_flags |= IFF_OACTIVE; 1590 break; 1591 } 1592 1593 /* now we are committed to transmit the packet */ 1594 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1595 pkts++; 1596 1597 /* 1598 * If there's a BPF listener, bounce a copy of this frame 1599 * to him. 1600 */ 1601 bpf_mtap(ifp, m_head); 1602 } 1603 if (pkts == 0) 1604 return; 1605 1606 /* Transmit */ 1607 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1608 sc_if->sk_cdata.sk_tx_prod = idx; 1609 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1610 1611 /* Set a timeout in case the chip goes out to lunch. */ 1612 ifp->if_timer = 5; 1613 } 1614 } 1615 1616 void 1617 msk_watchdog(struct ifnet *ifp) 1618 { 1619 struct sk_if_softc *sc_if = ifp->if_softc; 1620 u_int32_t reg; 1621 int idx; 1622 1623 /* 1624 * Reclaim first as there is a possibility of losing Tx completion 1625 * interrupts. 1626 */ 1627 if (sc_if->sk_port == SK_PORT_A) 1628 reg = SK_STAT_BMU_TXA1_RIDX; 1629 else 1630 reg = SK_STAT_BMU_TXA2_RIDX; 1631 1632 idx = sk_win_read_2(sc_if->sk_softc, reg); 1633 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1634 msk_txeof(sc_if, idx); 1635 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1636 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1637 1638 ifp->if_oerrors++; 1639 1640 /* XXX Resets both ports; we shouldn't do that. */ 1641 msk_reset(sc_if->sk_softc); 1642 msk_init(ifp); 1643 } 1644 } 1645 } 1646 1647 static bool 1648 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1649 { 1650 struct sk_softc *sc = device_private(dv); 1651 1652 DPRINTFN(2, ("mskc_suspend\n")); 1653 1654 /* Turn off the 'driver is loaded' LED. */ 1655 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1656 1657 return true; 1658 } 1659 1660 static bool 1661 mskc_resume(device_t dv, const pmf_qual_t *qual) 1662 { 1663 struct sk_softc *sc = device_private(dv); 1664 1665 DPRINTFN(2, ("mskc_resume\n")); 1666 1667 msk_reset(sc); 1668 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1669 1670 return true; 1671 } 1672 1673 static __inline int 1674 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1675 { 1676 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1677 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1678 YU_RXSTAT_JABBER)) != 0 || 1679 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1680 YU_RXSTAT_BYTES(stat) != len) 1681 return (0); 1682 1683 return (1); 1684 } 1685 1686 void 1687 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1688 { 1689 struct sk_softc *sc = sc_if->sk_softc; 1690 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1691 struct mbuf *m; 1692 struct sk_chain *cur_rx; 1693 int cur, total_len = len; 1694 bus_dmamap_t dmamap; 1695 1696 DPRINTFN(2, ("msk_rxeof\n")); 1697 1698 cur = sc_if->sk_cdata.sk_rx_cons; 1699 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1700 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1701 1702 /* Sync the descriptor */ 1703 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1704 1705 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1706 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1707 1708 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1709 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1710 1711 m = cur_rx->sk_mbuf; 1712 cur_rx->sk_mbuf = NULL; 1713 1714 if (total_len < SK_MIN_FRAMELEN || 1715 total_len > ETHER_MAX_LEN_JUMBO || 1716 msk_rxvalid(sc, rxstat, total_len) == 0) { 1717 ifp->if_ierrors++; 1718 msk_newbuf(sc_if, cur, m, dmamap); 1719 return; 1720 } 1721 1722 /* 1723 * Try to allocate a new jumbo buffer. If that fails, copy the 1724 * packet to mbufs and put the jumbo buffer back in the ring 1725 * so it can be re-used. If allocating mbufs fails, then we 1726 * have to drop the packet. 1727 */ 1728 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1729 struct mbuf *m0; 1730 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1731 total_len + ETHER_ALIGN, 0, ifp, NULL); 1732 msk_newbuf(sc_if, cur, m, dmamap); 1733 if (m0 == NULL) { 1734 ifp->if_ierrors++; 1735 return; 1736 } 1737 m_adj(m0, ETHER_ALIGN); 1738 m = m0; 1739 } else { 1740 m->m_pkthdr.rcvif = ifp; 1741 m->m_pkthdr.len = m->m_len = total_len; 1742 } 1743 1744 ifp->if_ipackets++; 1745 1746 bpf_mtap(ifp, m); 1747 1748 /* pass it on. */ 1749 (*ifp->if_input)(ifp, m); 1750 } 1751 1752 void 1753 msk_txeof(struct sk_if_softc *sc_if, int idx) 1754 { 1755 struct sk_softc *sc = sc_if->sk_softc; 1756 struct msk_tx_desc *cur_tx; 1757 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1758 u_int32_t sk_ctl; 1759 struct sk_txmap_entry *entry; 1760 int cons, prog; 1761 1762 DPRINTFN(2, ("msk_txeof\n")); 1763 1764 /* 1765 * Go through our tx ring and free mbufs for those 1766 * frames that have been sent. 1767 */ 1768 cons = sc_if->sk_cdata.sk_tx_cons; 1769 prog = 0; 1770 while (cons != idx) { 1771 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1772 break; 1773 prog++; 1774 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1775 1776 MSK_CDTXSYNC(sc_if, cons, 1, 1777 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1778 sk_ctl = cur_tx->sk_ctl; 1779 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1780 #ifdef MSK_DEBUG 1781 if (mskdebug >= 2) 1782 msk_dump_txdesc(cur_tx, cons); 1783 #endif 1784 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1785 ifp->if_opackets++; 1786 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1787 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1788 1789 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1790 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1791 1792 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1793 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1794 link); 1795 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1796 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1797 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1798 } 1799 sc_if->sk_cdata.sk_tx_cnt--; 1800 SK_INC(cons, MSK_TX_RING_CNT); 1801 } 1802 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1803 1804 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1805 ifp->if_flags &= ~IFF_OACTIVE; 1806 1807 if (prog > 0) 1808 sc_if->sk_cdata.sk_tx_cons = cons; 1809 } 1810 1811 void 1812 msk_tick(void *xsc_if) 1813 { 1814 struct sk_if_softc *sc_if = xsc_if; 1815 struct mii_data *mii = &sc_if->sk_mii; 1816 uint16_t gpsr; 1817 int s; 1818 1819 s = splnet(); 1820 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1821 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1822 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1823 mii_tick(mii); 1824 } 1825 splx(s); 1826 1827 callout_schedule(&sc_if->sk_tick_ch, hz); 1828 } 1829 1830 void 1831 msk_intr_yukon(struct sk_if_softc *sc_if) 1832 { 1833 u_int8_t status; 1834 1835 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1836 /* RX overrun */ 1837 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1838 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1839 SK_RFCTL_RX_FIFO_OVER); 1840 } 1841 /* TX underrun */ 1842 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1843 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1844 SK_TFCTL_TX_FIFO_UNDER); 1845 } 1846 1847 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1848 } 1849 1850 int 1851 msk_intr(void *xsc) 1852 { 1853 struct sk_softc *sc = xsc; 1854 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1855 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1856 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1857 int claimed = 0; 1858 u_int32_t status; 1859 uint32_t st_status; 1860 uint16_t st_len; 1861 uint8_t st_opcode, st_link; 1862 struct msk_status_desc *cur_st; 1863 1864 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1865 if (status == 0) { 1866 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1867 return (0); 1868 } 1869 1870 status = CSR_READ_4(sc, SK_ISR); 1871 1872 if (sc_if0 != NULL) 1873 ifp0 = &sc_if0->sk_ethercom.ec_if; 1874 if (sc_if1 != NULL) 1875 ifp1 = &sc_if1->sk_ethercom.ec_if; 1876 1877 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1878 (ifp0->if_flags & IFF_RUNNING)) { 1879 msk_intr_yukon(sc_if0); 1880 } 1881 1882 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1883 (ifp1->if_flags & IFF_RUNNING)) { 1884 msk_intr_yukon(sc_if1); 1885 } 1886 1887 for (;;) { 1888 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1889 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1890 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1891 st_opcode = cur_st->sk_opcode; 1892 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1893 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1894 BUS_DMASYNC_PREREAD); 1895 break; 1896 } 1897 st_status = le32toh(cur_st->sk_status); 1898 st_len = le16toh(cur_st->sk_len); 1899 st_link = cur_st->sk_link; 1900 st_opcode &= ~SK_Y2_STOPC_OWN; 1901 1902 switch (st_opcode) { 1903 case SK_Y2_STOPC_RXSTAT: 1904 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1905 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1906 SK_RXQ1_Y2_PREF_PUTIDX, 1907 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1908 break; 1909 case SK_Y2_STOPC_TXSTAT: 1910 if (sc_if0) 1911 msk_txeof(sc_if0, st_status 1912 & SK_Y2_ST_TXA1_MSKL); 1913 if (sc_if1) 1914 msk_txeof(sc_if1, 1915 ((st_status & SK_Y2_ST_TXA2_MSKL) 1916 >> SK_Y2_ST_TXA2_SHIFTL) 1917 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1918 break; 1919 default: 1920 aprint_error("opcode=0x%x\n", st_opcode); 1921 break; 1922 } 1923 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1924 } 1925 1926 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1927 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1928 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1929 1930 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1931 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1932 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1933 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1934 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1935 1936 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1937 } 1938 1939 if (status & SK_Y2_IMR_BMU) { 1940 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1941 claimed = 1; 1942 } 1943 1944 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1945 1946 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1947 msk_start(ifp0); 1948 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1949 msk_start(ifp1); 1950 1951 rnd_add_uint32(&sc->rnd_source, status); 1952 1953 if (sc->sk_int_mod_pending) 1954 msk_update_int_mod(sc, 1); 1955 1956 return claimed; 1957 } 1958 1959 void 1960 msk_init_yukon(struct sk_if_softc *sc_if) 1961 { 1962 u_int32_t v; 1963 u_int16_t reg; 1964 struct sk_softc *sc; 1965 int i; 1966 1967 sc = sc_if->sk_softc; 1968 1969 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1970 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1971 1972 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1973 1974 /* GMAC and GPHY Reset */ 1975 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1976 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1977 DELAY(1000); 1978 1979 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1980 1981 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1982 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1983 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1984 1985 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1986 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1987 1988 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1989 1990 /* unused read of the interrupt source register */ 1991 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1992 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1993 1994 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1995 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1996 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1997 1998 /* MIB Counter Clear Mode set */ 1999 reg |= YU_PAR_MIB_CLR; 2000 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2001 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2002 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2003 2004 /* MIB Counter Clear Mode clear */ 2005 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2006 reg &= ~YU_PAR_MIB_CLR; 2007 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2008 2009 /* receive control reg */ 2010 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2011 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2012 2013 /* transmit control register */ 2014 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2015 2016 /* transmit flow control register */ 2017 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2018 2019 /* transmit parameter register */ 2020 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2021 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2022 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2023 2024 /* serial mode register */ 2025 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2026 reg = YU_SMR_DATA_BLIND(0x1c) | 2027 YU_SMR_MFL_VLAN | 2028 YU_SMR_IPG_DATA(0x1e); 2029 2030 if (sc->sk_type != SK_YUKON_FE) 2031 reg |= YU_SMR_MFL_JUMBO; 2032 2033 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2034 2035 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2036 /* Setup Yukon's address */ 2037 for (i = 0; i < 3; i++) { 2038 /* Write Source Address 1 (unicast filter) */ 2039 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2040 sc_if->sk_enaddr[i * 2] | 2041 sc_if->sk_enaddr[i * 2 + 1] << 8); 2042 } 2043 2044 for (i = 0; i < 3; i++) { 2045 reg = sk_win_read_2(sc_if->sk_softc, 2046 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2047 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2048 } 2049 2050 /* Set promiscuous mode */ 2051 msk_setpromisc(sc_if); 2052 2053 /* Set multicast filter */ 2054 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2055 msk_setmulti(sc_if); 2056 2057 /* enable interrupt mask for counter overflows */ 2058 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2059 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2060 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2061 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2062 2063 /* Configure RX MAC FIFO Flush Mask */ 2064 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2065 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2066 YU_RXSTAT_JABBER; 2067 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2068 2069 /* Configure RX MAC FIFO */ 2070 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2071 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2072 SK_RFCTL_FIFO_FLUSH_ON); 2073 2074 /* Increase flush threshould to 64 bytes */ 2075 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2076 SK_RFCTL_FIFO_THRESHOLD + 1); 2077 2078 /* Configure TX MAC FIFO */ 2079 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2080 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2081 2082 #if 1 2083 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2084 #endif 2085 DPRINTFN(6, ("msk_init_yukon: end\n")); 2086 } 2087 2088 /* 2089 * Note that to properly initialize any part of the GEnesis chip, 2090 * you first have to take it out of reset mode. 2091 */ 2092 int 2093 msk_init(struct ifnet *ifp) 2094 { 2095 struct sk_if_softc *sc_if = ifp->if_softc; 2096 struct sk_softc *sc = sc_if->sk_softc; 2097 int rc = 0, s; 2098 uint32_t imr, imtimer_ticks; 2099 2100 2101 DPRINTFN(2, ("msk_init\n")); 2102 2103 s = splnet(); 2104 2105 /* Cancel pending I/O and free all RX/TX buffers. */ 2106 msk_stop(ifp,0); 2107 2108 /* Configure I2C registers */ 2109 2110 /* Configure XMAC(s) */ 2111 msk_init_yukon(sc_if); 2112 if ((rc = ether_mediachange(ifp)) != 0) 2113 goto out; 2114 2115 /* Configure transmit arbiter(s) */ 2116 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2117 #if 0 2118 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2119 #endif 2120 2121 /* Configure RAMbuffers */ 2122 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2123 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2124 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2125 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2126 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2127 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2128 2129 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2130 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2131 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2132 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2133 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2134 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2135 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2136 2137 /* Configure BMUs */ 2138 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2139 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2140 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2141 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2142 2143 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2144 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2145 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2146 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2147 2148 /* Make sure the sync transmit queue is disabled. */ 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2150 2151 /* Init descriptors */ 2152 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2153 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2154 "memory for rx buffers\n"); 2155 msk_stop(ifp,0); 2156 splx(s); 2157 return ENOBUFS; 2158 } 2159 2160 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2161 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2162 "memory for tx buffers\n"); 2163 msk_stop(ifp,0); 2164 splx(s); 2165 return ENOBUFS; 2166 } 2167 2168 /* Set interrupt moderation if changed via sysctl. */ 2169 switch (sc->sk_type) { 2170 case SK_YUKON_EC: 2171 case SK_YUKON_EC_U: 2172 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2173 break; 2174 case SK_YUKON_FE: 2175 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2176 break; 2177 case SK_YUKON_XL: 2178 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2179 break; 2180 default: 2181 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2182 } 2183 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2184 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2185 sk_win_write_4(sc, SK_IMTIMERINIT, 2186 SK_IM_USECS(sc->sk_int_mod)); 2187 aprint_verbose_dev(sc->sk_dev, 2188 "interrupt moderation is %d us\n", sc->sk_int_mod); 2189 } 2190 2191 /* Initialize prefetch engine. */ 2192 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2193 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2194 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2195 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2196 MSK_RX_RING_ADDR(sc_if, 0)); 2197 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2198 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2199 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2200 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2201 2202 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2203 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2204 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2205 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2206 MSK_TX_RING_ADDR(sc_if, 0)); 2207 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2208 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2209 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2210 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2211 2212 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2213 sc_if->sk_cdata.sk_rx_prod); 2214 2215 /* Configure interrupt handling */ 2216 if (sc_if->sk_port == SK_PORT_A) 2217 sc->sk_intrmask |= SK_Y2_INTRS1; 2218 else 2219 sc->sk_intrmask |= SK_Y2_INTRS2; 2220 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2221 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2222 2223 ifp->if_flags |= IFF_RUNNING; 2224 ifp->if_flags &= ~IFF_OACTIVE; 2225 2226 callout_schedule(&sc_if->sk_tick_ch, hz); 2227 2228 out: 2229 splx(s); 2230 return rc; 2231 } 2232 2233 void 2234 msk_stop(struct ifnet *ifp, int disable) 2235 { 2236 struct sk_if_softc *sc_if = ifp->if_softc; 2237 struct sk_softc *sc = sc_if->sk_softc; 2238 struct sk_txmap_entry *dma; 2239 int i; 2240 2241 DPRINTFN(2, ("msk_stop\n")); 2242 2243 callout_stop(&sc_if->sk_tick_ch); 2244 2245 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2246 2247 /* Stop transfer of Tx descriptors */ 2248 2249 /* Stop transfer of Rx descriptors */ 2250 2251 /* Turn off various components of this interface. */ 2252 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2253 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2254 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2255 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2256 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2257 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2258 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2259 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2260 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2261 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2262 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2263 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2264 2265 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2266 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2267 2268 /* Disable interrupts */ 2269 if (sc_if->sk_port == SK_PORT_A) 2270 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2271 else 2272 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2273 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2274 2275 SK_XM_READ_2(sc_if, XM_ISR); 2276 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2277 2278 /* Free RX and TX mbufs still in the queues. */ 2279 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2280 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2281 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2282 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2283 } 2284 } 2285 2286 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2287 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2288 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2289 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2290 #if 1 2291 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2292 sc_if->sk_cdata.sk_tx_map[i], link); 2293 sc_if->sk_cdata.sk_tx_map[i] = 0; 2294 #endif 2295 } 2296 } 2297 2298 #if 1 2299 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2300 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2301 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2302 free(dma, M_DEVBUF); 2303 } 2304 #endif 2305 } 2306 2307 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2308 NULL, NULL); 2309 2310 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2311 NULL, NULL); 2312 2313 #ifdef MSK_DEBUG 2314 void 2315 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2316 { 2317 #define DESC_PRINT(X) \ 2318 if (X) \ 2319 printf("txdesc[%d]." #X "=%#x\n", \ 2320 idx, X); 2321 2322 DESC_PRINT(letoh32(le->sk_addr)); 2323 DESC_PRINT(letoh16(le->sk_len)); 2324 DESC_PRINT(le->sk_ctl); 2325 DESC_PRINT(le->sk_opcode); 2326 #undef DESC_PRINT 2327 } 2328 2329 void 2330 msk_dump_bytes(const char *data, int len) 2331 { 2332 int c, i, j; 2333 2334 for (i = 0; i < len; i += 16) { 2335 printf("%08x ", i); 2336 c = len - i; 2337 if (c > 16) c = 16; 2338 2339 for (j = 0; j < c; j++) { 2340 printf("%02x ", data[i + j] & 0xff); 2341 if ((j & 0xf) == 7 && j > 0) 2342 printf(" "); 2343 } 2344 2345 for (; j < 16; j++) 2346 printf(" "); 2347 printf(" "); 2348 2349 for (j = 0; j < c; j++) { 2350 int ch = data[i + j] & 0xff; 2351 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2352 } 2353 2354 printf("\n"); 2355 2356 if (c < 16) 2357 break; 2358 } 2359 } 2360 2361 void 2362 msk_dump_mbuf(struct mbuf *m) 2363 { 2364 int count = m->m_pkthdr.len; 2365 2366 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2367 2368 while (count > 0 && m) { 2369 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2370 m, m->m_data, m->m_len); 2371 msk_dump_bytes(mtod(m, char *), m->m_len); 2372 2373 count -= m->m_len; 2374 m = m->m_next; 2375 } 2376 } 2377 #endif 2378 2379 static int 2380 msk_sysctl_handler(SYSCTLFN_ARGS) 2381 { 2382 int error, t; 2383 struct sysctlnode node; 2384 struct sk_softc *sc; 2385 2386 node = *rnode; 2387 sc = node.sysctl_data; 2388 t = sc->sk_int_mod; 2389 node.sysctl_data = &t; 2390 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2391 if (error || newp == NULL) 2392 return error; 2393 2394 if (t < SK_IM_MIN || t > SK_IM_MAX) 2395 return EINVAL; 2396 2397 /* update the softc with sysctl-changed value, and mark 2398 for hardware update */ 2399 sc->sk_int_mod = t; 2400 sc->sk_int_mod_pending = 1; 2401 return 0; 2402 } 2403 2404 /* 2405 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2406 * set up in skc_attach() 2407 */ 2408 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2409 { 2410 int rc; 2411 const struct sysctlnode *node; 2412 2413 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2414 0, CTLTYPE_NODE, "hw", NULL, 2415 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2416 goto err; 2417 } 2418 2419 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2420 0, CTLTYPE_NODE, "msk", 2421 SYSCTL_DESCR("msk interface controls"), 2422 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2423 goto err; 2424 } 2425 2426 msk_root_num = node->sysctl_num; 2427 return; 2428 2429 err: 2430 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2431 } 2432