1 /* $NetBSD: if_msk.c,v 1.48 2015/04/13 16:33:25 riastradh Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.48 2015/04/13 16:33:25 riastradh Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 static bool mskc_suspend(device_t, const pmf_qual_t *); 98 static bool mskc_resume(device_t, const pmf_qual_t *); 99 int msk_probe(device_t, cfdata_t, void *); 100 void msk_attach(device_t, device_t, void *); 101 int mskcprint(void *, const char *); 102 int msk_intr(void *); 103 void msk_intr_yukon(struct sk_if_softc *); 104 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 105 void msk_txeof(struct sk_if_softc *, int); 106 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 107 void msk_start(struct ifnet *); 108 int msk_ioctl(struct ifnet *, u_long, void *); 109 int msk_init(struct ifnet *); 110 void msk_init_yukon(struct sk_if_softc *); 111 void msk_stop(struct ifnet *, int); 112 void msk_watchdog(struct ifnet *); 113 void msk_reset(struct sk_softc *); 114 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 115 int msk_alloc_jumbo_mem(struct sk_if_softc *); 116 void *msk_jalloc(struct sk_if_softc *); 117 void msk_jfree(struct mbuf *, void *, size_t, void *); 118 int msk_init_rx_ring(struct sk_if_softc *); 119 int msk_init_tx_ring(struct sk_if_softc *); 120 121 void msk_update_int_mod(struct sk_softc *, int); 122 123 int msk_miibus_readreg(device_t, int, int); 124 void msk_miibus_writereg(device_t, int, int, int); 125 void msk_miibus_statchg(struct ifnet *); 126 127 void msk_setfilt(struct sk_if_softc *, void *, int); 128 void msk_setmulti(struct sk_if_softc *); 129 void msk_setpromisc(struct sk_if_softc *); 130 void msk_tick(void *); 131 132 /* #define MSK_DEBUG 1 */ 133 #ifdef MSK_DEBUG 134 #define DPRINTF(x) if (mskdebug) printf x 135 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 136 int mskdebug = MSK_DEBUG; 137 138 void msk_dump_txdesc(struct msk_tx_desc *, int); 139 void msk_dump_mbuf(struct mbuf *); 140 void msk_dump_bytes(const char *, int); 141 #else 142 #define DPRINTF(x) 143 #define DPRINTFN(n,x) 144 #endif 145 146 static int msk_sysctl_handler(SYSCTLFN_PROTO); 147 static int msk_root_num; 148 149 /* supported device vendors */ 150 static const struct msk_product { 151 pci_vendor_id_t msk_vendor; 152 pci_product_id_t msk_product; 153 } msk_products[] = { 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 157 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 158 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 159 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 182 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 183 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 184 }; 185 186 static inline u_int32_t 187 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 188 { 189 return CSR_READ_4(sc, reg); 190 } 191 192 static inline u_int16_t 193 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 194 { 195 return CSR_READ_2(sc, reg); 196 } 197 198 static inline u_int8_t 199 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 200 { 201 return CSR_READ_1(sc, reg); 202 } 203 204 static inline void 205 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 206 { 207 CSR_WRITE_4(sc, reg, x); 208 } 209 210 static inline void 211 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 212 { 213 CSR_WRITE_2(sc, reg, x); 214 } 215 216 static inline void 217 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 218 { 219 CSR_WRITE_1(sc, reg, x); 220 } 221 222 int 223 msk_miibus_readreg(device_t dev, int phy, int reg) 224 { 225 struct sk_if_softc *sc_if = device_private(dev); 226 u_int16_t val; 227 int i; 228 229 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 230 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 231 232 for (i = 0; i < SK_TIMEOUT; i++) { 233 DELAY(1); 234 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 235 if (val & YU_SMICR_READ_VALID) 236 break; 237 } 238 239 if (i == SK_TIMEOUT) { 240 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 241 return (0); 242 } 243 244 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 245 SK_TIMEOUT)); 246 247 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 248 249 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 250 phy, reg, val)); 251 252 return (val); 253 } 254 255 void 256 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 257 { 258 struct sk_if_softc *sc_if = device_private(dev); 259 int i; 260 261 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 262 phy, reg, val)); 263 264 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 265 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 266 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 267 268 for (i = 0; i < SK_TIMEOUT; i++) { 269 DELAY(1); 270 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 271 break; 272 } 273 274 if (i == SK_TIMEOUT) 275 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 276 } 277 278 void 279 msk_miibus_statchg(struct ifnet *ifp) 280 { 281 struct sk_if_softc *sc_if = ifp->if_softc; 282 struct mii_data *mii = &sc_if->sk_mii; 283 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 284 int gpcr; 285 286 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 287 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 288 289 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 290 /* Set speed. */ 291 gpcr |= YU_GPCR_SPEED_DIS; 292 switch (IFM_SUBTYPE(mii->mii_media_active)) { 293 case IFM_1000_SX: 294 case IFM_1000_LX: 295 case IFM_1000_CX: 296 case IFM_1000_T: 297 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 298 break; 299 case IFM_100_TX: 300 gpcr |= YU_GPCR_SPEED; 301 break; 302 } 303 304 /* Set duplex. */ 305 gpcr |= YU_GPCR_DPLX_DIS; 306 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 307 gpcr |= YU_GPCR_DUPLEX; 308 309 /* Disable flow control. */ 310 gpcr |= YU_GPCR_FCTL_DIS; 311 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 312 } 313 314 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 315 316 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 317 SK_YU_READ_2(sc_if, YUKON_GPCR))); 318 } 319 320 #define HASH_BITS 6 321 322 void 323 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 324 { 325 char *addr = addrv; 326 int base = XM_RXFILT_ENTRY(slot); 327 328 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 329 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 330 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 331 } 332 333 void 334 msk_setmulti(struct sk_if_softc *sc_if) 335 { 336 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 337 u_int32_t hashes[2] = { 0, 0 }; 338 int h; 339 struct ethercom *ec = &sc_if->sk_ethercom; 340 struct ether_multi *enm; 341 struct ether_multistep step; 342 u_int16_t reg; 343 344 /* First, zot all the existing filters. */ 345 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 346 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 349 350 351 /* Now program new ones. */ 352 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 353 reg |= YU_RCR_UFLEN; 354 allmulti: 355 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 356 if ((ifp->if_flags & IFF_PROMISC) != 0) 357 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 358 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 359 hashes[0] = 0xFFFFFFFF; 360 hashes[1] = 0xFFFFFFFF; 361 } 362 } else { 363 /* First find the tail of the list. */ 364 ETHER_FIRST_MULTI(step, ec, enm); 365 while (enm != NULL) { 366 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 367 ETHER_ADDR_LEN)) { 368 ifp->if_flags |= IFF_ALLMULTI; 369 goto allmulti; 370 } 371 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 372 ((1 << HASH_BITS) - 1); 373 if (h < 32) 374 hashes[0] |= (1 << h); 375 else 376 hashes[1] |= (1 << (h - 32)); 377 378 ETHER_NEXT_MULTI(step, enm); 379 } 380 reg |= YU_RCR_MUFLEN; 381 } 382 383 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 384 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 388 } 389 390 void 391 msk_setpromisc(struct sk_if_softc *sc_if) 392 { 393 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 394 395 if (ifp->if_flags & IFF_PROMISC) 396 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 397 YU_RCR_UFLEN | YU_RCR_MUFLEN); 398 else 399 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 } 402 403 int 404 msk_init_rx_ring(struct sk_if_softc *sc_if) 405 { 406 struct msk_chain_data *cd = &sc_if->sk_cdata; 407 struct msk_ring_data *rd = sc_if->sk_rdata; 408 int i, nexti; 409 410 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 411 412 for (i = 0; i < MSK_RX_RING_CNT; i++) { 413 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 414 if (i == (MSK_RX_RING_CNT - 1)) 415 nexti = 0; 416 else 417 nexti = i + 1; 418 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 419 } 420 421 for (i = 0; i < MSK_RX_RING_CNT; i++) { 422 if (msk_newbuf(sc_if, i, NULL, 423 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 424 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 425 return (ENOBUFS); 426 } 427 } 428 429 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 430 sc_if->sk_cdata.sk_rx_cons = 0; 431 432 return (0); 433 } 434 435 int 436 msk_init_tx_ring(struct sk_if_softc *sc_if) 437 { 438 struct sk_softc *sc = sc_if->sk_softc; 439 struct msk_chain_data *cd = &sc_if->sk_cdata; 440 struct msk_ring_data *rd = sc_if->sk_rdata; 441 bus_dmamap_t dmamap; 442 struct sk_txmap_entry *entry; 443 int i, nexti; 444 445 memset(sc_if->sk_rdata->sk_tx_ring, 0, 446 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 447 448 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 449 for (i = 0; i < MSK_TX_RING_CNT; i++) { 450 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 451 if (i == (MSK_TX_RING_CNT - 1)) 452 nexti = 0; 453 else 454 nexti = i + 1; 455 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 456 457 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 458 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 459 return (ENOBUFS); 460 461 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 462 if (!entry) { 463 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 464 return (ENOBUFS); 465 } 466 entry->dmamap = dmamap; 467 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 468 } 469 470 sc_if->sk_cdata.sk_tx_prod = 0; 471 sc_if->sk_cdata.sk_tx_cons = 0; 472 sc_if->sk_cdata.sk_tx_cnt = 0; 473 474 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 475 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 476 477 return (0); 478 } 479 480 int 481 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 482 bus_dmamap_t dmamap) 483 { 484 struct mbuf *m_new = NULL; 485 struct sk_chain *c; 486 struct msk_rx_desc *r; 487 488 if (m == NULL) { 489 void *buf = NULL; 490 491 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 492 if (m_new == NULL) 493 return (ENOBUFS); 494 495 /* Allocate the jumbo buffer */ 496 buf = msk_jalloc(sc_if); 497 if (buf == NULL) { 498 m_freem(m_new); 499 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 500 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 501 return (ENOBUFS); 502 } 503 504 /* Attach the buffer to the mbuf */ 505 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 506 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 507 } else { 508 /* 509 * We're re-using a previously allocated mbuf; 510 * be sure to re-init pointers and lengths to 511 * default values. 512 */ 513 m_new = m; 514 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 515 m_new->m_data = m_new->m_ext.ext_buf; 516 } 517 m_adj(m_new, ETHER_ALIGN); 518 519 c = &sc_if->sk_cdata.sk_rx_chain[i]; 520 r = c->sk_le; 521 c->sk_mbuf = m_new; 522 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 523 (((vaddr_t)m_new->m_data 524 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 525 r->sk_len = htole16(SK_JLEN); 526 r->sk_ctl = 0; 527 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 528 529 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 530 531 return (0); 532 } 533 534 /* 535 * Memory management for jumbo frames. 536 */ 537 538 int 539 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 540 { 541 struct sk_softc *sc = sc_if->sk_softc; 542 char *ptr, *kva; 543 bus_dma_segment_t seg; 544 int i, rseg, state, error; 545 struct sk_jpool_entry *entry; 546 547 state = error = 0; 548 549 /* Grab a big chunk o' storage. */ 550 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 551 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 552 aprint_error(": can't alloc rx buffers"); 553 return (ENOBUFS); 554 } 555 556 state = 1; 557 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 558 BUS_DMA_NOWAIT)) { 559 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 560 error = ENOBUFS; 561 goto out; 562 } 563 564 state = 2; 565 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 566 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 567 aprint_error(": can't create dma map"); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 3; 573 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 574 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 575 aprint_error(": can't load dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 4; 581 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 582 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 583 584 LIST_INIT(&sc_if->sk_jfree_listhead); 585 LIST_INIT(&sc_if->sk_jinuse_listhead); 586 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 587 588 /* 589 * Now divide it up into 9K pieces and save the addresses 590 * in an array. 591 */ 592 ptr = sc_if->sk_cdata.sk_jumbo_buf; 593 for (i = 0; i < MSK_JSLOTS; i++) { 594 sc_if->sk_cdata.sk_jslots[i] = ptr; 595 ptr += SK_JLEN; 596 entry = malloc(sizeof(struct sk_jpool_entry), 597 M_DEVBUF, M_NOWAIT); 598 if (entry == NULL) { 599 sc_if->sk_cdata.sk_jumbo_buf = NULL; 600 aprint_error(": no memory for jumbo buffer queue!"); 601 error = ENOBUFS; 602 goto out; 603 } 604 entry->slot = i; 605 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 606 entry, jpool_entries); 607 } 608 out: 609 if (error != 0) { 610 switch (state) { 611 case 4: 612 bus_dmamap_unload(sc->sc_dmatag, 613 sc_if->sk_cdata.sk_rx_jumbo_map); 614 case 3: 615 bus_dmamap_destroy(sc->sc_dmatag, 616 sc_if->sk_cdata.sk_rx_jumbo_map); 617 case 2: 618 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 619 case 1: 620 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 621 break; 622 default: 623 break; 624 } 625 } 626 627 return (error); 628 } 629 630 /* 631 * Allocate a jumbo buffer. 632 */ 633 void * 634 msk_jalloc(struct sk_if_softc *sc_if) 635 { 636 struct sk_jpool_entry *entry; 637 638 mutex_enter(&sc_if->sk_jpool_mtx); 639 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 640 641 if (entry == NULL) { 642 mutex_exit(&sc_if->sk_jpool_mtx); 643 return NULL; 644 } 645 646 LIST_REMOVE(entry, jpool_entries); 647 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 648 mutex_exit(&sc_if->sk_jpool_mtx); 649 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 650 } 651 652 /* 653 * Release a jumbo buffer. 654 */ 655 void 656 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 657 { 658 struct sk_jpool_entry *entry; 659 struct sk_if_softc *sc; 660 int i; 661 662 /* Extract the softc struct pointer. */ 663 sc = (struct sk_if_softc *)arg; 664 665 if (sc == NULL) 666 panic("msk_jfree: can't find softc pointer!"); 667 668 /* calculate the slot this buffer belongs to */ 669 i = ((vaddr_t)buf 670 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 671 672 if ((i < 0) || (i >= MSK_JSLOTS)) 673 panic("msk_jfree: asked to free buffer that we don't manage!"); 674 675 mutex_enter(&sc->sk_jpool_mtx); 676 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 677 if (entry == NULL) 678 panic("msk_jfree: buffer not in use!"); 679 entry->slot = i; 680 LIST_REMOVE(entry, jpool_entries); 681 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 682 mutex_exit(&sc->sk_jpool_mtx); 683 684 if (__predict_true(m != NULL)) 685 pool_cache_put(mb_cache, m); 686 } 687 688 int 689 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 690 { 691 struct sk_if_softc *sc_if = ifp->if_softc; 692 int s, error = 0; 693 694 s = splnet(); 695 696 DPRINTFN(2, ("msk_ioctl ETHER\n")); 697 error = ether_ioctl(ifp, cmd, data); 698 699 if (error == ENETRESET) { 700 error = 0; 701 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 702 ; 703 else if (ifp->if_flags & IFF_RUNNING) { 704 /* 705 * Multicast list has changed; set the hardware 706 * filter accordingly. 707 */ 708 msk_setmulti(sc_if); 709 } 710 } 711 712 splx(s); 713 return (error); 714 } 715 716 void 717 msk_update_int_mod(struct sk_softc *sc, int verbose) 718 { 719 u_int32_t imtimer_ticks; 720 721 /* 722 * Configure interrupt moderation. The moderation timer 723 * defers interrupts specified in the interrupt moderation 724 * timer mask based on the timeout specified in the interrupt 725 * moderation timer init register. Each bit in the timer 726 * register represents one tick, so to specify a timeout in 727 * microseconds, we have to multiply by the correct number of 728 * ticks-per-microsecond. 729 */ 730 switch (sc->sk_type) { 731 case SK_YUKON_EC: 732 case SK_YUKON_EC_U: 733 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 734 break; 735 case SK_YUKON_FE: 736 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 737 break; 738 case SK_YUKON_XL: 739 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 740 break; 741 default: 742 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 743 } 744 if (verbose) 745 aprint_verbose_dev(sc->sk_dev, 746 "interrupt moderation is %d us\n", sc->sk_int_mod); 747 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 748 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 749 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 750 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 751 sc->sk_int_mod_pending = 0; 752 } 753 754 static int 755 msk_lookup(const struct pci_attach_args *pa) 756 { 757 const struct msk_product *pmsk; 758 759 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 760 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 761 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 762 return 1; 763 } 764 return 0; 765 } 766 767 /* 768 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 769 * IDs against our list and return a device name if we find a match. 770 */ 771 int 772 mskc_probe(device_t parent, cfdata_t match, void *aux) 773 { 774 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 775 776 return msk_lookup(pa); 777 } 778 779 /* 780 * Force the GEnesis into reset, then bring it out of reset. 781 */ 782 void msk_reset(struct sk_softc *sc) 783 { 784 u_int32_t imtimer_ticks, reg1; 785 int reg; 786 787 DPRINTFN(2, ("msk_reset\n")); 788 789 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 790 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 791 792 DELAY(1000); 793 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 794 DELAY(2); 795 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 796 sk_win_write_1(sc, SK_TESTCTL1, 2); 797 798 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 799 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 800 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 801 else 802 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 803 804 if (sc->sk_type == SK_YUKON_EC_U) { 805 uint32_t our; 806 807 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 808 809 /* enable all clocks. */ 810 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 811 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 812 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 813 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 814 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 815 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 816 /* Set all bits to 0 except bits 15..12 */ 817 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 818 /* Set to default value */ 819 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 820 } 821 822 /* release PHY from PowerDown/Coma mode. */ 823 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 824 825 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 826 sk_win_write_1(sc, SK_Y2_CLKGATE, 827 SK_Y2_CLKGATE_LINK1_GATE_DIS | 828 SK_Y2_CLKGATE_LINK2_GATE_DIS | 829 SK_Y2_CLKGATE_LINK1_CORE_DIS | 830 SK_Y2_CLKGATE_LINK2_CORE_DIS | 831 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 832 else 833 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 834 835 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 836 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 837 DELAY(1000); 838 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 839 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 840 841 sk_win_write_1(sc, SK_TESTCTL1, 1); 842 843 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 844 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 845 CSR_READ_2(sc, SK_LINK_CTRL))); 846 847 /* Disable ASF */ 848 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 849 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 850 851 /* Clear I2C IRQ noise */ 852 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 853 854 /* Disable hardware timer */ 855 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 856 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 857 858 /* Disable descriptor polling */ 859 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 860 861 /* Disable time stamps */ 862 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 863 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 864 865 /* Enable RAM interface */ 866 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 867 for (reg = SK_TO0;reg <= SK_TO11; reg++) 868 sk_win_write_1(sc, reg, 36); 869 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 870 for (reg = SK_TO0;reg <= SK_TO11; reg++) 871 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 872 873 /* 874 * Configure interrupt moderation. The moderation timer 875 * defers interrupts specified in the interrupt moderation 876 * timer mask based on the timeout specified in the interrupt 877 * moderation timer init register. Each bit in the timer 878 * register represents one tick, so to specify a timeout in 879 * microseconds, we have to multiply by the correct number of 880 * ticks-per-microsecond. 881 */ 882 switch (sc->sk_type) { 883 case SK_YUKON_EC: 884 case SK_YUKON_EC_U: 885 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 886 break; 887 case SK_YUKON_FE: 888 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 889 break; 890 case SK_YUKON_XL: 891 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 892 break; 893 default: 894 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 895 } 896 897 /* Reset status ring. */ 898 memset(sc->sk_status_ring, 0, 899 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 900 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 901 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 902 sc->sk_status_idx = 0; 903 sc->sk_status_own_idx = 0; 904 905 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 906 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 907 908 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 909 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 910 sc->sk_status_map->dm_segs[0].ds_addr); 911 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 912 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 913 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 914 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 915 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 916 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 917 } else { 918 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 919 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 920 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 921 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 922 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 923 } 924 925 #if 0 926 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 927 #endif 928 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 929 930 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 931 932 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 933 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 934 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 935 936 msk_update_int_mod(sc, 0); 937 } 938 939 int 940 msk_probe(device_t parent, cfdata_t match, void *aux) 941 { 942 struct skc_attach_args *sa = aux; 943 944 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 945 return (0); 946 947 switch (sa->skc_type) { 948 case SK_YUKON_XL: 949 case SK_YUKON_EC_U: 950 case SK_YUKON_EC: 951 case SK_YUKON_FE: 952 case SK_YUKON_FE_P: 953 return (1); 954 } 955 956 return (0); 957 } 958 959 static bool 960 msk_resume(device_t dv, const pmf_qual_t *qual) 961 { 962 struct sk_if_softc *sc_if = device_private(dv); 963 964 msk_init_yukon(sc_if); 965 return true; 966 } 967 968 /* 969 * Each XMAC chip is attached as a separate logical IP interface. 970 * Single port cards will have only one logical interface of course. 971 */ 972 void 973 msk_attach(device_t parent, device_t self, void *aux) 974 { 975 struct sk_if_softc *sc_if = device_private(self); 976 struct sk_softc *sc = device_private(parent); 977 struct skc_attach_args *sa = aux; 978 struct ifnet *ifp; 979 void *kva; 980 bus_dma_segment_t seg; 981 int i, rseg; 982 u_int32_t chunk, val; 983 984 sc_if->sk_dev = self; 985 sc_if->sk_port = sa->skc_port; 986 sc_if->sk_softc = sc; 987 sc->sk_if[sa->skc_port] = sc_if; 988 989 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 990 991 /* 992 * Get station address for this interface. Note that 993 * dual port cards actually come with three station 994 * addresses: one for each port, plus an extra. The 995 * extra one is used by the SysKonnect driver software 996 * as a 'virtual' station address for when both ports 997 * are operating in failover mode. Currently we don't 998 * use this extra address. 999 */ 1000 for (i = 0; i < ETHER_ADDR_LEN; i++) 1001 sc_if->sk_enaddr[i] = 1002 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1003 1004 aprint_normal(": Ethernet address %s\n", 1005 ether_sprintf(sc_if->sk_enaddr)); 1006 1007 /* 1008 * Set up RAM buffer addresses. The NIC will have a certain 1009 * amount of SRAM on it, somewhere between 512K and 2MB. We 1010 * need to divide this up a) between the transmitter and 1011 * receiver and b) between the two XMACs, if this is a 1012 * dual port NIC. Our algorithm is to divide up the memory 1013 * evenly so that everyone gets a fair share. 1014 * 1015 * Just to be contrary, Yukon2 appears to have separate memory 1016 * for each MAC. 1017 */ 1018 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1019 val = sc->sk_rboff / sizeof(u_int64_t); 1020 sc_if->sk_rx_ramstart = val; 1021 val += (chunk / sizeof(u_int64_t)); 1022 sc_if->sk_rx_ramend = val - 1; 1023 chunk = sc->sk_ramsize - chunk; 1024 sc_if->sk_tx_ramstart = val; 1025 val += (chunk / sizeof(u_int64_t)); 1026 sc_if->sk_tx_ramend = val - 1; 1027 1028 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1029 " tx_ramstart=%#x tx_ramend=%#x\n", 1030 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1031 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1032 1033 /* Allocate the descriptor queues. */ 1034 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1035 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1036 aprint_error(": can't alloc rx buffers\n"); 1037 goto fail; 1038 } 1039 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1040 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1041 aprint_error(": can't map dma buffers (%zu bytes)\n", 1042 sizeof(struct msk_ring_data)); 1043 goto fail_1; 1044 } 1045 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1046 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1047 &sc_if->sk_ring_map)) { 1048 aprint_error(": can't create dma map\n"); 1049 goto fail_2; 1050 } 1051 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1052 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1053 aprint_error(": can't load dma map\n"); 1054 goto fail_3; 1055 } 1056 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1057 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1058 1059 ifp = &sc_if->sk_ethercom.ec_if; 1060 /* Try to allocate memory for jumbo buffers. */ 1061 if (msk_alloc_jumbo_mem(sc_if)) { 1062 aprint_error(": jumbo buffer allocation failed\n"); 1063 goto fail_3; 1064 } 1065 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1066 if (sc->sk_type != SK_YUKON_FE) 1067 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1068 1069 ifp->if_softc = sc_if; 1070 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1071 ifp->if_ioctl = msk_ioctl; 1072 ifp->if_start = msk_start; 1073 ifp->if_stop = msk_stop; 1074 ifp->if_init = msk_init; 1075 ifp->if_watchdog = msk_watchdog; 1076 ifp->if_baudrate = 1000000000; 1077 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1078 IFQ_SET_READY(&ifp->if_snd); 1079 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1080 1081 /* 1082 * Do miibus setup. 1083 */ 1084 msk_init_yukon(sc_if); 1085 1086 DPRINTFN(2, ("msk_attach: 1\n")); 1087 1088 sc_if->sk_mii.mii_ifp = ifp; 1089 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1090 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1091 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1092 1093 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1094 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1095 ether_mediachange, ether_mediastatus); 1096 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1097 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1098 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1099 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1100 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1101 0, NULL); 1102 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1103 } else 1104 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1105 1106 callout_init(&sc_if->sk_tick_ch, 0); 1107 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1108 callout_schedule(&sc_if->sk_tick_ch, hz); 1109 1110 /* 1111 * Call MI attach routines. 1112 */ 1113 if_attach(ifp); 1114 ether_ifattach(ifp, sc_if->sk_enaddr); 1115 1116 if (pmf_device_register(self, NULL, msk_resume)) 1117 pmf_class_network_register(self, ifp); 1118 else 1119 aprint_error_dev(self, "couldn't establish power handler\n"); 1120 1121 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1122 RND_TYPE_NET, RND_FLAG_DEFAULT); 1123 1124 DPRINTFN(2, ("msk_attach: end\n")); 1125 return; 1126 1127 fail_3: 1128 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1129 fail_2: 1130 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1131 fail_1: 1132 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1133 fail: 1134 sc->sk_if[sa->skc_port] = NULL; 1135 } 1136 1137 int 1138 mskcprint(void *aux, const char *pnp) 1139 { 1140 struct skc_attach_args *sa = aux; 1141 1142 if (pnp) 1143 aprint_normal("sk port %c at %s", 1144 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1145 else 1146 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1147 return (UNCONF); 1148 } 1149 1150 /* 1151 * Attach the interface. Allocate softc structures, do ifmedia 1152 * setup and ethernet/BPF attach. 1153 */ 1154 void 1155 mskc_attach(device_t parent, device_t self, void *aux) 1156 { 1157 struct sk_softc *sc = device_private(self); 1158 struct pci_attach_args *pa = aux; 1159 struct skc_attach_args skca; 1160 pci_chipset_tag_t pc = pa->pa_pc; 1161 pcireg_t command, memtype; 1162 pci_intr_handle_t ih; 1163 const char *intrstr = NULL; 1164 bus_size_t size; 1165 int rc, sk_nodenum; 1166 u_int8_t hw, skrs; 1167 const char *revstr = NULL; 1168 const struct sysctlnode *node; 1169 void *kva; 1170 bus_dma_segment_t seg; 1171 int rseg; 1172 char intrbuf[PCI_INTRSTR_LEN]; 1173 1174 DPRINTFN(2, ("begin mskc_attach\n")); 1175 1176 sc->sk_dev = self; 1177 /* 1178 * Handle power management nonsense. 1179 */ 1180 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1181 1182 if (command == 0x01) { 1183 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1184 if (command & SK_PSTATE_MASK) { 1185 u_int32_t iobase, membase, irq; 1186 1187 /* Save important PCI config data. */ 1188 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1189 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1190 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1191 1192 /* Reset the power state. */ 1193 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1194 "mode -- setting to D0\n", 1195 command & SK_PSTATE_MASK); 1196 command &= 0xFFFFFFFC; 1197 pci_conf_write(pc, pa->pa_tag, 1198 SK_PCI_PWRMGMTCTRL, command); 1199 1200 /* Restore PCI config data. */ 1201 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1202 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1203 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1204 } 1205 } 1206 1207 /* 1208 * Map control/status registers. 1209 */ 1210 1211 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1212 switch (memtype) { 1213 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1214 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1215 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1216 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1217 NULL, &size) == 0) { 1218 break; 1219 } 1220 default: 1221 aprint_error(": can't map mem space\n"); 1222 return; 1223 } 1224 1225 sc->sc_dmatag = pa->pa_dmat; 1226 1227 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1228 command |= PCI_COMMAND_MASTER_ENABLE; 1229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1230 1231 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1232 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1233 1234 /* bail out here if chip is not recognized */ 1235 if (!(SK_IS_YUKON2(sc))) { 1236 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1237 goto fail_1; 1238 } 1239 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1240 1241 /* Allocate interrupt */ 1242 if (pci_intr_map(pa, &ih)) { 1243 aprint_error(": couldn't map interrupt\n"); 1244 goto fail_1; 1245 } 1246 1247 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1248 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1249 if (sc->sk_intrhand == NULL) { 1250 aprint_error(": couldn't establish interrupt"); 1251 if (intrstr != NULL) 1252 aprint_error(" at %s", intrstr); 1253 aprint_error("\n"); 1254 goto fail_1; 1255 } 1256 1257 if (bus_dmamem_alloc(sc->sc_dmatag, 1258 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1259 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1260 aprint_error(": can't alloc status buffers\n"); 1261 goto fail_2; 1262 } 1263 1264 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1265 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1266 &kva, BUS_DMA_NOWAIT)) { 1267 aprint_error(": can't map dma buffers (%zu bytes)\n", 1268 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1269 goto fail_3; 1270 } 1271 if (bus_dmamap_create(sc->sc_dmatag, 1272 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1273 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1274 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1275 aprint_error(": can't create dma map\n"); 1276 goto fail_4; 1277 } 1278 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1279 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1280 NULL, BUS_DMA_NOWAIT)) { 1281 aprint_error(": can't load dma map\n"); 1282 goto fail_5; 1283 } 1284 sc->sk_status_ring = (struct msk_status_desc *)kva; 1285 1286 1287 sc->sk_int_mod = SK_IM_DEFAULT; 1288 sc->sk_int_mod_pending = 0; 1289 1290 /* Reset the adapter. */ 1291 msk_reset(sc); 1292 1293 skrs = sk_win_read_1(sc, SK_EPROM0); 1294 if (skrs == 0x00) 1295 sc->sk_ramsize = 0x20000; 1296 else 1297 sc->sk_ramsize = skrs * (1<<12); 1298 sc->sk_rboff = SK_RBOFF_0; 1299 1300 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1301 sc->sk_ramsize, sc->sk_ramsize / 1024, 1302 sc->sk_rboff)); 1303 1304 switch (sc->sk_type) { 1305 case SK_YUKON_XL: 1306 sc->sk_name = "Yukon-2 XL"; 1307 break; 1308 case SK_YUKON_EC_U: 1309 sc->sk_name = "Yukon-2 EC Ultra"; 1310 break; 1311 case SK_YUKON_EC: 1312 sc->sk_name = "Yukon-2 EC"; 1313 break; 1314 case SK_YUKON_FE: 1315 sc->sk_name = "Yukon-2 FE"; 1316 break; 1317 default: 1318 sc->sk_name = "Yukon (Unknown)"; 1319 } 1320 1321 if (sc->sk_type == SK_YUKON_XL) { 1322 switch (sc->sk_rev) { 1323 case SK_YUKON_XL_REV_A0: 1324 sc->sk_workaround = 0; 1325 revstr = "A0"; 1326 break; 1327 case SK_YUKON_XL_REV_A1: 1328 sc->sk_workaround = SK_WA_4109; 1329 revstr = "A1"; 1330 break; 1331 case SK_YUKON_XL_REV_A2: 1332 sc->sk_workaround = SK_WA_4109; 1333 revstr = "A2"; 1334 break; 1335 case SK_YUKON_XL_REV_A3: 1336 sc->sk_workaround = SK_WA_4109; 1337 revstr = "A3"; 1338 break; 1339 default: 1340 sc->sk_workaround = 0; 1341 break; 1342 } 1343 } 1344 1345 if (sc->sk_type == SK_YUKON_EC) { 1346 switch (sc->sk_rev) { 1347 case SK_YUKON_EC_REV_A1: 1348 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1349 revstr = "A1"; 1350 break; 1351 case SK_YUKON_EC_REV_A2: 1352 sc->sk_workaround = SK_WA_4109; 1353 revstr = "A2"; 1354 break; 1355 case SK_YUKON_EC_REV_A3: 1356 sc->sk_workaround = SK_WA_4109; 1357 revstr = "A3"; 1358 break; 1359 default: 1360 sc->sk_workaround = 0; 1361 break; 1362 } 1363 } 1364 1365 if (sc->sk_type == SK_YUKON_FE) { 1366 sc->sk_workaround = SK_WA_4109; 1367 switch (sc->sk_rev) { 1368 case SK_YUKON_FE_REV_A1: 1369 revstr = "A1"; 1370 break; 1371 case SK_YUKON_FE_REV_A2: 1372 revstr = "A2"; 1373 break; 1374 default: 1375 sc->sk_workaround = 0; 1376 break; 1377 } 1378 } 1379 1380 if (sc->sk_type == SK_YUKON_EC_U) { 1381 sc->sk_workaround = SK_WA_4109; 1382 switch (sc->sk_rev) { 1383 case SK_YUKON_EC_U_REV_A0: 1384 revstr = "A0"; 1385 break; 1386 case SK_YUKON_EC_U_REV_A1: 1387 revstr = "A1"; 1388 break; 1389 case SK_YUKON_EC_U_REV_B0: 1390 revstr = "B0"; 1391 break; 1392 default: 1393 sc->sk_workaround = 0; 1394 break; 1395 } 1396 } 1397 1398 /* Announce the product name. */ 1399 aprint_normal(", %s", sc->sk_name); 1400 if (revstr != NULL) 1401 aprint_normal(" rev. %s", revstr); 1402 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1403 1404 sc->sk_macs = 1; 1405 1406 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1407 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1408 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1409 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1410 sc->sk_macs++; 1411 } 1412 1413 skca.skc_port = SK_PORT_A; 1414 skca.skc_type = sc->sk_type; 1415 skca.skc_rev = sc->sk_rev; 1416 (void)config_found(sc->sk_dev, &skca, mskcprint); 1417 1418 if (sc->sk_macs > 1) { 1419 skca.skc_port = SK_PORT_B; 1420 skca.skc_type = sc->sk_type; 1421 skca.skc_rev = sc->sk_rev; 1422 (void)config_found(sc->sk_dev, &skca, mskcprint); 1423 } 1424 1425 /* Turn on the 'driver is loaded' LED. */ 1426 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1427 1428 /* skc sysctl setup */ 1429 1430 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1431 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1432 SYSCTL_DESCR("mskc per-controller controls"), 1433 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1434 CTL_EOL)) != 0) { 1435 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1436 goto fail_6; 1437 } 1438 1439 sk_nodenum = node->sysctl_num; 1440 1441 /* interrupt moderation time in usecs */ 1442 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1443 CTLFLAG_READWRITE, 1444 CTLTYPE_INT, "int_mod", 1445 SYSCTL_DESCR("msk interrupt moderation timer"), 1446 msk_sysctl_handler, 0, (void *)sc, 1447 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1448 CTL_EOL)) != 0) { 1449 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1450 goto fail_6; 1451 } 1452 1453 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1454 aprint_error_dev(self, "couldn't establish power handler\n"); 1455 1456 return; 1457 1458 fail_6: 1459 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1460 fail_5: 1461 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1462 fail_4: 1463 bus_dmamem_unmap(sc->sc_dmatag, kva, 1464 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1465 fail_3: 1466 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1467 fail_2: 1468 pci_intr_disestablish(pc, sc->sk_intrhand); 1469 fail_1: 1470 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1471 } 1472 1473 int 1474 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1475 { 1476 struct sk_softc *sc = sc_if->sk_softc; 1477 struct msk_tx_desc *f = NULL; 1478 u_int32_t frag, cur; 1479 int i; 1480 struct sk_txmap_entry *entry; 1481 bus_dmamap_t txmap; 1482 1483 DPRINTFN(2, ("msk_encap\n")); 1484 1485 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1486 if (entry == NULL) { 1487 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1488 return (ENOBUFS); 1489 } 1490 txmap = entry->dmamap; 1491 1492 cur = frag = *txidx; 1493 1494 #ifdef MSK_DEBUG 1495 if (mskdebug >= 2) 1496 msk_dump_mbuf(m_head); 1497 #endif 1498 1499 /* 1500 * Start packing the mbufs in this chain into 1501 * the fragment pointers. Stop when we run out 1502 * of fragments or hit the end of the mbuf chain. 1503 */ 1504 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1505 BUS_DMA_NOWAIT)) { 1506 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1507 return (ENOBUFS); 1508 } 1509 1510 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1511 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1512 bus_dmamap_unload(sc->sc_dmatag, txmap); 1513 return (ENOBUFS); 1514 } 1515 1516 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1517 1518 /* Sync the DMA map. */ 1519 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1520 BUS_DMASYNC_PREWRITE); 1521 1522 for (i = 0; i < txmap->dm_nsegs; i++) { 1523 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1524 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1525 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1526 f->sk_ctl = 0; 1527 if (i == 0) 1528 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1529 else 1530 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1531 cur = frag; 1532 SK_INC(frag, MSK_TX_RING_CNT); 1533 } 1534 1535 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1536 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1537 1538 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1539 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1540 1541 /* Sync descriptors before handing to chip */ 1542 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1543 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1544 1545 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1546 1547 /* Sync first descriptor to hand it off */ 1548 MSK_CDTXSYNC(sc_if, *txidx, 1, 1549 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1550 1551 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1552 1553 #ifdef MSK_DEBUG 1554 if (mskdebug >= 2) { 1555 struct msk_tx_desc *le; 1556 u_int32_t idx; 1557 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1558 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1559 msk_dump_txdesc(le, idx); 1560 } 1561 } 1562 #endif 1563 1564 *txidx = frag; 1565 1566 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1567 1568 return (0); 1569 } 1570 1571 void 1572 msk_start(struct ifnet *ifp) 1573 { 1574 struct sk_if_softc *sc_if = ifp->if_softc; 1575 struct mbuf *m_head = NULL; 1576 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1577 int pkts = 0; 1578 1579 DPRINTFN(2, ("msk_start\n")); 1580 1581 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1582 IFQ_POLL(&ifp->if_snd, m_head); 1583 if (m_head == NULL) 1584 break; 1585 1586 /* 1587 * Pack the data into the transmit ring. If we 1588 * don't have room, set the OACTIVE flag and wait 1589 * for the NIC to drain the ring. 1590 */ 1591 if (msk_encap(sc_if, m_head, &idx)) { 1592 ifp->if_flags |= IFF_OACTIVE; 1593 break; 1594 } 1595 1596 /* now we are committed to transmit the packet */ 1597 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1598 pkts++; 1599 1600 /* 1601 * If there's a BPF listener, bounce a copy of this frame 1602 * to him. 1603 */ 1604 bpf_mtap(ifp, m_head); 1605 } 1606 if (pkts == 0) 1607 return; 1608 1609 /* Transmit */ 1610 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1611 sc_if->sk_cdata.sk_tx_prod = idx; 1612 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1613 1614 /* Set a timeout in case the chip goes out to lunch. */ 1615 ifp->if_timer = 5; 1616 } 1617 } 1618 1619 void 1620 msk_watchdog(struct ifnet *ifp) 1621 { 1622 struct sk_if_softc *sc_if = ifp->if_softc; 1623 u_int32_t reg; 1624 int idx; 1625 1626 /* 1627 * Reclaim first as there is a possibility of losing Tx completion 1628 * interrupts. 1629 */ 1630 if (sc_if->sk_port == SK_PORT_A) 1631 reg = SK_STAT_BMU_TXA1_RIDX; 1632 else 1633 reg = SK_STAT_BMU_TXA2_RIDX; 1634 1635 idx = sk_win_read_2(sc_if->sk_softc, reg); 1636 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1637 msk_txeof(sc_if, idx); 1638 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1639 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1640 1641 ifp->if_oerrors++; 1642 1643 /* XXX Resets both ports; we shouldn't do that. */ 1644 msk_reset(sc_if->sk_softc); 1645 msk_init(ifp); 1646 } 1647 } 1648 } 1649 1650 static bool 1651 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1652 { 1653 struct sk_softc *sc = device_private(dv); 1654 1655 DPRINTFN(2, ("mskc_suspend\n")); 1656 1657 /* Turn off the 'driver is loaded' LED. */ 1658 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1659 1660 return true; 1661 } 1662 1663 static bool 1664 mskc_resume(device_t dv, const pmf_qual_t *qual) 1665 { 1666 struct sk_softc *sc = device_private(dv); 1667 1668 DPRINTFN(2, ("mskc_resume\n")); 1669 1670 msk_reset(sc); 1671 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1672 1673 return true; 1674 } 1675 1676 static __inline int 1677 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1678 { 1679 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1680 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1681 YU_RXSTAT_JABBER)) != 0 || 1682 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1683 YU_RXSTAT_BYTES(stat) != len) 1684 return (0); 1685 1686 return (1); 1687 } 1688 1689 void 1690 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1691 { 1692 struct sk_softc *sc = sc_if->sk_softc; 1693 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1694 struct mbuf *m; 1695 struct sk_chain *cur_rx; 1696 int cur, total_len = len; 1697 bus_dmamap_t dmamap; 1698 1699 DPRINTFN(2, ("msk_rxeof\n")); 1700 1701 cur = sc_if->sk_cdata.sk_rx_cons; 1702 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1703 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1704 1705 /* Sync the descriptor */ 1706 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1707 1708 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1709 if (cur_rx->sk_mbuf == NULL) 1710 return; 1711 1712 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1713 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1714 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1715 1716 m = cur_rx->sk_mbuf; 1717 cur_rx->sk_mbuf = NULL; 1718 1719 if (total_len < SK_MIN_FRAMELEN || 1720 total_len > ETHER_MAX_LEN_JUMBO || 1721 msk_rxvalid(sc, rxstat, total_len) == 0) { 1722 ifp->if_ierrors++; 1723 msk_newbuf(sc_if, cur, m, dmamap); 1724 return; 1725 } 1726 1727 /* 1728 * Try to allocate a new jumbo buffer. If that fails, copy the 1729 * packet to mbufs and put the jumbo buffer back in the ring 1730 * so it can be re-used. If allocating mbufs fails, then we 1731 * have to drop the packet. 1732 */ 1733 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1734 struct mbuf *m0; 1735 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1736 total_len + ETHER_ALIGN, 0, ifp, NULL); 1737 msk_newbuf(sc_if, cur, m, dmamap); 1738 if (m0 == NULL) { 1739 ifp->if_ierrors++; 1740 return; 1741 } 1742 m_adj(m0, ETHER_ALIGN); 1743 m = m0; 1744 } else { 1745 m->m_pkthdr.rcvif = ifp; 1746 m->m_pkthdr.len = m->m_len = total_len; 1747 } 1748 1749 ifp->if_ipackets++; 1750 1751 bpf_mtap(ifp, m); 1752 1753 /* pass it on. */ 1754 (*ifp->if_input)(ifp, m); 1755 } 1756 1757 void 1758 msk_txeof(struct sk_if_softc *sc_if, int idx) 1759 { 1760 struct sk_softc *sc = sc_if->sk_softc; 1761 struct msk_tx_desc *cur_tx; 1762 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1763 u_int32_t sk_ctl; 1764 struct sk_txmap_entry *entry; 1765 int cons, prog; 1766 1767 DPRINTFN(2, ("msk_txeof\n")); 1768 1769 /* 1770 * Go through our tx ring and free mbufs for those 1771 * frames that have been sent. 1772 */ 1773 cons = sc_if->sk_cdata.sk_tx_cons; 1774 prog = 0; 1775 while (cons != idx) { 1776 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1777 break; 1778 prog++; 1779 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1780 1781 MSK_CDTXSYNC(sc_if, cons, 1, 1782 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1783 sk_ctl = cur_tx->sk_ctl; 1784 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1785 #ifdef MSK_DEBUG 1786 if (mskdebug >= 2) 1787 msk_dump_txdesc(cur_tx, cons); 1788 #endif 1789 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1790 ifp->if_opackets++; 1791 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1792 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1793 1794 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1795 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1796 1797 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1798 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1799 link); 1800 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1801 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1802 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1803 } 1804 sc_if->sk_cdata.sk_tx_cnt--; 1805 SK_INC(cons, MSK_TX_RING_CNT); 1806 } 1807 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1808 1809 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1810 ifp->if_flags &= ~IFF_OACTIVE; 1811 1812 if (prog > 0) 1813 sc_if->sk_cdata.sk_tx_cons = cons; 1814 } 1815 1816 void 1817 msk_tick(void *xsc_if) 1818 { 1819 struct sk_if_softc *sc_if = xsc_if; 1820 struct mii_data *mii = &sc_if->sk_mii; 1821 uint16_t gpsr; 1822 int s; 1823 1824 s = splnet(); 1825 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1826 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1827 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1828 mii_tick(mii); 1829 } 1830 splx(s); 1831 1832 callout_schedule(&sc_if->sk_tick_ch, hz); 1833 } 1834 1835 void 1836 msk_intr_yukon(struct sk_if_softc *sc_if) 1837 { 1838 u_int8_t status; 1839 1840 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1841 /* RX overrun */ 1842 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1843 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1844 SK_RFCTL_RX_FIFO_OVER); 1845 } 1846 /* TX underrun */ 1847 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1848 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1849 SK_TFCTL_TX_FIFO_UNDER); 1850 } 1851 1852 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1853 } 1854 1855 int 1856 msk_intr(void *xsc) 1857 { 1858 struct sk_softc *sc = xsc; 1859 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1860 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1861 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1862 int claimed = 0; 1863 u_int32_t status; 1864 uint32_t st_status; 1865 uint16_t st_len; 1866 uint8_t st_opcode, st_link; 1867 struct msk_status_desc *cur_st; 1868 1869 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1870 if (status == 0) { 1871 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1872 return (0); 1873 } 1874 1875 status = CSR_READ_4(sc, SK_ISR); 1876 1877 if (sc_if0 != NULL) 1878 ifp0 = &sc_if0->sk_ethercom.ec_if; 1879 if (sc_if1 != NULL) 1880 ifp1 = &sc_if1->sk_ethercom.ec_if; 1881 1882 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1883 (ifp0->if_flags & IFF_RUNNING)) { 1884 msk_intr_yukon(sc_if0); 1885 } 1886 1887 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1888 (ifp1->if_flags & IFF_RUNNING)) { 1889 msk_intr_yukon(sc_if1); 1890 } 1891 1892 for (;;) { 1893 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1894 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1895 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1896 st_opcode = cur_st->sk_opcode; 1897 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1898 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1899 BUS_DMASYNC_PREREAD); 1900 break; 1901 } 1902 st_status = le32toh(cur_st->sk_status); 1903 st_len = le16toh(cur_st->sk_len); 1904 st_link = cur_st->sk_link; 1905 st_opcode &= ~SK_Y2_STOPC_OWN; 1906 1907 switch (st_opcode) { 1908 case SK_Y2_STOPC_RXSTAT: 1909 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1910 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1911 SK_RXQ1_Y2_PREF_PUTIDX, 1912 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1913 break; 1914 case SK_Y2_STOPC_TXSTAT: 1915 if (sc_if0) 1916 msk_txeof(sc_if0, st_status 1917 & SK_Y2_ST_TXA1_MSKL); 1918 if (sc_if1) 1919 msk_txeof(sc_if1, 1920 ((st_status & SK_Y2_ST_TXA2_MSKL) 1921 >> SK_Y2_ST_TXA2_SHIFTL) 1922 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1923 break; 1924 default: 1925 aprint_error("opcode=0x%x\n", st_opcode); 1926 break; 1927 } 1928 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1929 } 1930 1931 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1932 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1933 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1934 1935 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1936 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1937 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1938 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1939 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1940 1941 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1942 } 1943 1944 if (status & SK_Y2_IMR_BMU) { 1945 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1946 claimed = 1; 1947 } 1948 1949 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1950 1951 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1952 msk_start(ifp0); 1953 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1954 msk_start(ifp1); 1955 1956 rnd_add_uint32(&sc->rnd_source, status); 1957 1958 if (sc->sk_int_mod_pending) 1959 msk_update_int_mod(sc, 1); 1960 1961 return claimed; 1962 } 1963 1964 void 1965 msk_init_yukon(struct sk_if_softc *sc_if) 1966 { 1967 u_int32_t v; 1968 u_int16_t reg; 1969 struct sk_softc *sc; 1970 int i; 1971 1972 sc = sc_if->sk_softc; 1973 1974 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1975 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1976 1977 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1978 1979 /* GMAC and GPHY Reset */ 1980 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1981 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1982 DELAY(1000); 1983 1984 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1985 1986 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1987 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1988 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1989 1990 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1991 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1992 1993 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1994 1995 /* unused read of the interrupt source register */ 1996 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1997 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1998 1999 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2000 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2001 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2002 2003 /* MIB Counter Clear Mode set */ 2004 reg |= YU_PAR_MIB_CLR; 2005 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2006 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2007 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2008 2009 /* MIB Counter Clear Mode clear */ 2010 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2011 reg &= ~YU_PAR_MIB_CLR; 2012 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2013 2014 /* receive control reg */ 2015 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2016 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2017 2018 /* transmit control register */ 2019 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2020 2021 /* transmit flow control register */ 2022 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2023 2024 /* transmit parameter register */ 2025 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2026 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2027 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2028 2029 /* serial mode register */ 2030 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2031 reg = YU_SMR_DATA_BLIND(0x1c) | 2032 YU_SMR_MFL_VLAN | 2033 YU_SMR_IPG_DATA(0x1e); 2034 2035 if (sc->sk_type != SK_YUKON_FE) 2036 reg |= YU_SMR_MFL_JUMBO; 2037 2038 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2039 2040 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2041 /* Setup Yukon's address */ 2042 for (i = 0; i < 3; i++) { 2043 /* Write Source Address 1 (unicast filter) */ 2044 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2045 sc_if->sk_enaddr[i * 2] | 2046 sc_if->sk_enaddr[i * 2 + 1] << 8); 2047 } 2048 2049 for (i = 0; i < 3; i++) { 2050 reg = sk_win_read_2(sc_if->sk_softc, 2051 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2052 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2053 } 2054 2055 /* Set promiscuous mode */ 2056 msk_setpromisc(sc_if); 2057 2058 /* Set multicast filter */ 2059 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2060 msk_setmulti(sc_if); 2061 2062 /* enable interrupt mask for counter overflows */ 2063 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2064 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2065 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2066 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2067 2068 /* Configure RX MAC FIFO Flush Mask */ 2069 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2070 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2071 YU_RXSTAT_JABBER; 2072 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2073 2074 /* Configure RX MAC FIFO */ 2075 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2076 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2077 SK_RFCTL_FIFO_FLUSH_ON); 2078 2079 /* Increase flush threshould to 64 bytes */ 2080 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2081 SK_RFCTL_FIFO_THRESHOLD + 1); 2082 2083 /* Configure TX MAC FIFO */ 2084 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2085 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2086 2087 #if 1 2088 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2089 #endif 2090 DPRINTFN(6, ("msk_init_yukon: end\n")); 2091 } 2092 2093 /* 2094 * Note that to properly initialize any part of the GEnesis chip, 2095 * you first have to take it out of reset mode. 2096 */ 2097 int 2098 msk_init(struct ifnet *ifp) 2099 { 2100 struct sk_if_softc *sc_if = ifp->if_softc; 2101 struct sk_softc *sc = sc_if->sk_softc; 2102 int rc = 0, s; 2103 uint32_t imr, imtimer_ticks; 2104 2105 2106 DPRINTFN(2, ("msk_init\n")); 2107 2108 s = splnet(); 2109 2110 /* Cancel pending I/O and free all RX/TX buffers. */ 2111 msk_stop(ifp,0); 2112 2113 /* Configure I2C registers */ 2114 2115 /* Configure XMAC(s) */ 2116 msk_init_yukon(sc_if); 2117 if ((rc = ether_mediachange(ifp)) != 0) 2118 goto out; 2119 2120 /* Configure transmit arbiter(s) */ 2121 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2122 #if 0 2123 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2124 #endif 2125 2126 /* Configure RAMbuffers */ 2127 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2128 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2129 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2130 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2133 2134 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2135 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2136 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2137 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2141 2142 /* Configure BMUs */ 2143 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2144 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2145 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2146 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2147 2148 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2150 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2151 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2152 2153 /* Make sure the sync transmit queue is disabled. */ 2154 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2155 2156 /* Init descriptors */ 2157 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2158 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2159 "memory for rx buffers\n"); 2160 msk_stop(ifp,0); 2161 splx(s); 2162 return ENOBUFS; 2163 } 2164 2165 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2166 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2167 "memory for tx buffers\n"); 2168 msk_stop(ifp,0); 2169 splx(s); 2170 return ENOBUFS; 2171 } 2172 2173 /* Set interrupt moderation if changed via sysctl. */ 2174 switch (sc->sk_type) { 2175 case SK_YUKON_EC: 2176 case SK_YUKON_EC_U: 2177 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2178 break; 2179 case SK_YUKON_FE: 2180 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2181 break; 2182 case SK_YUKON_XL: 2183 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2184 break; 2185 default: 2186 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2187 } 2188 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2189 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2190 sk_win_write_4(sc, SK_IMTIMERINIT, 2191 SK_IM_USECS(sc->sk_int_mod)); 2192 aprint_verbose_dev(sc->sk_dev, 2193 "interrupt moderation is %d us\n", sc->sk_int_mod); 2194 } 2195 2196 /* Initialize prefetch engine. */ 2197 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2198 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2199 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2200 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2201 MSK_RX_RING_ADDR(sc_if, 0)); 2202 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2203 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2204 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2205 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2206 2207 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2208 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2209 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2210 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2211 MSK_TX_RING_ADDR(sc_if, 0)); 2212 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2213 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2214 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2215 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2216 2217 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2218 sc_if->sk_cdata.sk_rx_prod); 2219 2220 /* Configure interrupt handling */ 2221 if (sc_if->sk_port == SK_PORT_A) 2222 sc->sk_intrmask |= SK_Y2_INTRS1; 2223 else 2224 sc->sk_intrmask |= SK_Y2_INTRS2; 2225 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2226 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2227 2228 ifp->if_flags |= IFF_RUNNING; 2229 ifp->if_flags &= ~IFF_OACTIVE; 2230 2231 callout_schedule(&sc_if->sk_tick_ch, hz); 2232 2233 out: 2234 splx(s); 2235 return rc; 2236 } 2237 2238 void 2239 msk_stop(struct ifnet *ifp, int disable) 2240 { 2241 struct sk_if_softc *sc_if = ifp->if_softc; 2242 struct sk_softc *sc = sc_if->sk_softc; 2243 struct sk_txmap_entry *dma; 2244 int i; 2245 2246 DPRINTFN(2, ("msk_stop\n")); 2247 2248 callout_stop(&sc_if->sk_tick_ch); 2249 2250 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2251 2252 /* Stop transfer of Tx descriptors */ 2253 2254 /* Stop transfer of Rx descriptors */ 2255 2256 /* Turn off various components of this interface. */ 2257 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2258 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2259 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2260 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2261 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2262 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2263 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2264 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2265 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2266 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2267 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2268 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2269 2270 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2271 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2272 2273 /* Disable interrupts */ 2274 if (sc_if->sk_port == SK_PORT_A) 2275 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2276 else 2277 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2278 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2279 2280 SK_XM_READ_2(sc_if, XM_ISR); 2281 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2282 2283 /* Free RX and TX mbufs still in the queues. */ 2284 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2285 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2286 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2287 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2288 } 2289 } 2290 2291 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2292 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2293 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2294 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2295 #if 1 2296 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2297 sc_if->sk_cdata.sk_tx_map[i], link); 2298 sc_if->sk_cdata.sk_tx_map[i] = 0; 2299 #endif 2300 } 2301 } 2302 2303 #if 1 2304 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2305 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2306 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2307 free(dma, M_DEVBUF); 2308 } 2309 #endif 2310 } 2311 2312 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2313 NULL, NULL); 2314 2315 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2316 NULL, NULL); 2317 2318 #ifdef MSK_DEBUG 2319 void 2320 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2321 { 2322 #define DESC_PRINT(X) \ 2323 if (X) \ 2324 printf("txdesc[%d]." #X "=%#x\n", \ 2325 idx, X); 2326 2327 DESC_PRINT(letoh32(le->sk_addr)); 2328 DESC_PRINT(letoh16(le->sk_len)); 2329 DESC_PRINT(le->sk_ctl); 2330 DESC_PRINT(le->sk_opcode); 2331 #undef DESC_PRINT 2332 } 2333 2334 void 2335 msk_dump_bytes(const char *data, int len) 2336 { 2337 int c, i, j; 2338 2339 for (i = 0; i < len; i += 16) { 2340 printf("%08x ", i); 2341 c = len - i; 2342 if (c > 16) c = 16; 2343 2344 for (j = 0; j < c; j++) { 2345 printf("%02x ", data[i + j] & 0xff); 2346 if ((j & 0xf) == 7 && j > 0) 2347 printf(" "); 2348 } 2349 2350 for (; j < 16; j++) 2351 printf(" "); 2352 printf(" "); 2353 2354 for (j = 0; j < c; j++) { 2355 int ch = data[i + j] & 0xff; 2356 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2357 } 2358 2359 printf("\n"); 2360 2361 if (c < 16) 2362 break; 2363 } 2364 } 2365 2366 void 2367 msk_dump_mbuf(struct mbuf *m) 2368 { 2369 int count = m->m_pkthdr.len; 2370 2371 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2372 2373 while (count > 0 && m) { 2374 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2375 m, m->m_data, m->m_len); 2376 msk_dump_bytes(mtod(m, char *), m->m_len); 2377 2378 count -= m->m_len; 2379 m = m->m_next; 2380 } 2381 } 2382 #endif 2383 2384 static int 2385 msk_sysctl_handler(SYSCTLFN_ARGS) 2386 { 2387 int error, t; 2388 struct sysctlnode node; 2389 struct sk_softc *sc; 2390 2391 node = *rnode; 2392 sc = node.sysctl_data; 2393 t = sc->sk_int_mod; 2394 node.sysctl_data = &t; 2395 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2396 if (error || newp == NULL) 2397 return error; 2398 2399 if (t < SK_IM_MIN || t > SK_IM_MAX) 2400 return EINVAL; 2401 2402 /* update the softc with sysctl-changed value, and mark 2403 for hardware update */ 2404 sc->sk_int_mod = t; 2405 sc->sk_int_mod_pending = 1; 2406 return 0; 2407 } 2408 2409 /* 2410 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2411 * set up in skc_attach() 2412 */ 2413 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2414 { 2415 int rc; 2416 const struct sysctlnode *node; 2417 2418 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2419 0, CTLTYPE_NODE, "msk", 2420 SYSCTL_DESCR("msk interface controls"), 2421 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2422 goto err; 2423 } 2424 2425 msk_root_num = node->sysctl_num; 2426 return; 2427 2428 err: 2429 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2430 } 2431