1 /* $NetBSD: if_msk.c,v 1.22 2008/11/18 09:30:43 chris Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.22 2008/11/18 09:30:43 chris Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/mutex.h> 66 #include <sys/kernel.h> 67 #include <sys/socket.h> 68 #include <sys/device.h> 69 #include <sys/queue.h> 70 #include <sys/callout.h> 71 #include <sys/sysctl.h> 72 #include <sys/endian.h> 73 #ifdef __NetBSD__ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 #endif 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 82 #include <net/if_media.h> 83 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #endif 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 #include <dev/mii/brgphyreg.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/pci/if_skreg.h> 100 #include <dev/pci/if_mskvar.h> 101 102 int mskc_probe(struct device *, struct cfdata *, void *); 103 void mskc_attach(struct device *, struct device *self, void *aux); 104 static bool mskc_suspend(device_t PMF_FN_PROTO); 105 static bool mskc_resume(device_t PMF_FN_PROTO); 106 int msk_probe(struct device *, struct cfdata *, void *); 107 void msk_attach(struct device *, struct device *self, void *aux); 108 int mskcprint(void *, const char *); 109 int msk_intr(void *); 110 void msk_intr_yukon(struct sk_if_softc *); 111 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 112 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 113 void msk_txeof(struct sk_if_softc *, int); 114 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 115 void msk_start(struct ifnet *); 116 int msk_ioctl(struct ifnet *, u_long, void *); 117 int msk_init(struct ifnet *); 118 void msk_init_yukon(struct sk_if_softc *); 119 void msk_stop(struct ifnet *, int); 120 void msk_watchdog(struct ifnet *); 121 void msk_reset(struct sk_softc *); 122 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 123 int msk_alloc_jumbo_mem(struct sk_if_softc *); 124 void *msk_jalloc(struct sk_if_softc *); 125 void msk_jfree(struct mbuf *, void *, size_t, void *); 126 int msk_init_rx_ring(struct sk_if_softc *); 127 int msk_init_tx_ring(struct sk_if_softc *); 128 129 void msk_update_int_mod(struct sk_softc *); 130 131 int msk_miibus_readreg(struct device *, int, int); 132 void msk_miibus_writereg(struct device *, int, int, int); 133 void msk_miibus_statchg(struct device *); 134 135 void msk_setfilt(struct sk_if_softc *, void *, int); 136 void msk_setmulti(struct sk_if_softc *); 137 void msk_setpromisc(struct sk_if_softc *); 138 void msk_tick(void *); 139 140 /* #define MSK_DEBUG 1 */ 141 #ifdef MSK_DEBUG 142 #define DPRINTF(x) if (mskdebug) printf x 143 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 144 int mskdebug = MSK_DEBUG; 145 146 void msk_dump_txdesc(struct msk_tx_desc *, int); 147 void msk_dump_mbuf(struct mbuf *); 148 void msk_dump_bytes(const char *, int); 149 #else 150 #define DPRINTF(x) 151 #define DPRINTFN(n,x) 152 #endif 153 154 static int msk_sysctl_handler(SYSCTLFN_PROTO); 155 static int msk_root_num; 156 157 /* supported device vendors */ 158 static const struct msk_product { 159 pci_vendor_id_t msk_vendor; 160 pci_product_id_t msk_product; 161 } msk_products[] = { 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 191 }; 192 193 static inline u_int32_t 194 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 195 { 196 return CSR_READ_4(sc, reg); 197 } 198 199 static inline u_int16_t 200 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_2(sc, reg); 203 } 204 205 static inline u_int8_t 206 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_1(sc, reg); 209 } 210 211 static inline void 212 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 213 { 214 CSR_WRITE_4(sc, reg, x); 215 } 216 217 static inline void 218 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 219 { 220 CSR_WRITE_2(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 225 { 226 CSR_WRITE_1(sc, reg, x); 227 } 228 229 int 230 msk_miibus_readreg(struct device *dev, int phy, int reg) 231 { 232 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 233 u_int16_t val; 234 int i; 235 236 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 237 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 238 239 for (i = 0; i < SK_TIMEOUT; i++) { 240 DELAY(1); 241 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 242 if (val & YU_SMICR_READ_VALID) 243 break; 244 } 245 246 if (i == SK_TIMEOUT) { 247 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 248 return (0); 249 } 250 251 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 252 SK_TIMEOUT)); 253 254 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 255 256 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 257 phy, reg, val)); 258 259 return (val); 260 } 261 262 void 263 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 264 { 265 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 266 int i; 267 268 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 269 phy, reg, val)); 270 271 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 272 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 273 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 274 275 for (i = 0; i < SK_TIMEOUT; i++) { 276 DELAY(1); 277 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 278 break; 279 } 280 281 if (i == SK_TIMEOUT) 282 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 283 } 284 285 void 286 msk_miibus_statchg(struct device *dev) 287 { 288 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 289 struct mii_data *mii = &sc_if->sk_mii; 290 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 291 int gpcr; 292 293 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 294 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 295 296 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 297 /* Set speed. */ 298 gpcr |= YU_GPCR_SPEED_DIS; 299 switch (IFM_SUBTYPE(mii->mii_media_active)) { 300 case IFM_1000_SX: 301 case IFM_1000_LX: 302 case IFM_1000_CX: 303 case IFM_1000_T: 304 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 305 break; 306 case IFM_100_TX: 307 gpcr |= YU_GPCR_SPEED; 308 break; 309 } 310 311 /* Set duplex. */ 312 gpcr |= YU_GPCR_DPLX_DIS; 313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 314 gpcr |= YU_GPCR_DUPLEX; 315 316 /* Disable flow control. */ 317 gpcr |= YU_GPCR_FCTL_DIS; 318 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 319 } 320 321 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 322 323 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 324 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 325 } 326 327 #define HASH_BITS 6 328 329 void 330 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 331 { 332 char *addr = addrv; 333 int base = XM_RXFILT_ENTRY(slot); 334 335 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 336 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 337 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 338 } 339 340 void 341 msk_setmulti(struct sk_if_softc *sc_if) 342 { 343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 344 u_int32_t hashes[2] = { 0, 0 }; 345 int h; 346 struct ethercom *ec = &sc_if->sk_ethercom; 347 struct ether_multi *enm; 348 struct ether_multistep step; 349 u_int16_t reg; 350 351 /* First, zot all the existing filters. */ 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 356 357 358 /* Now program new ones. */ 359 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 360 reg |= YU_RCR_UFLEN; 361 allmulti: 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 if ((ifp->if_flags & IFF_PROMISC) != 0) 364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 366 hashes[0] = 0xFFFFFFFF; 367 hashes[1] = 0xFFFFFFFF; 368 } 369 } else { 370 /* First find the tail of the list. */ 371 ETHER_FIRST_MULTI(step, ec, enm); 372 while (enm != NULL) { 373 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 374 ETHER_ADDR_LEN)) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 goto allmulti; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 379 ((1 << HASH_BITS) - 1); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 reg |= YU_RCR_MUFLEN; 388 } 389 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 395 } 396 397 void 398 msk_setpromisc(struct sk_if_softc *sc_if) 399 { 400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 401 402 if (ifp->if_flags & IFF_PROMISC) 403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 else 406 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 } 409 410 int 411 msk_init_rx_ring(struct sk_if_softc *sc_if) 412 { 413 struct msk_chain_data *cd = &sc_if->sk_cdata; 414 struct msk_ring_data *rd = sc_if->sk_rdata; 415 int i, nexti; 416 417 bzero((char *)rd->sk_rx_ring, 418 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 for (i = 0; i < MSK_RX_RING_CNT; i++) { 430 if (msk_newbuf(sc_if, i, NULL, 431 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 432 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. 599 */ 600 ptr = sc_if->sk_cdata.sk_jumbo_buf; 601 for (i = 0; i < MSK_JSLOTS; i++) { 602 sc_if->sk_cdata.sk_jslots[i] = ptr; 603 ptr += SK_JLEN; 604 entry = malloc(sizeof(struct sk_jpool_entry), 605 M_DEVBUF, M_NOWAIT); 606 if (entry == NULL) { 607 sc_if->sk_cdata.sk_jumbo_buf = NULL; 608 aprint_error(": no memory for jumbo buffer queue!"); 609 error = ENOBUFS; 610 goto out; 611 } 612 entry->slot = i; 613 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 614 entry, jpool_entries); 615 } 616 out: 617 if (error != 0) { 618 switch (state) { 619 case 4: 620 bus_dmamap_unload(sc->sc_dmatag, 621 sc_if->sk_cdata.sk_rx_jumbo_map); 622 case 3: 623 bus_dmamap_destroy(sc->sc_dmatag, 624 sc_if->sk_cdata.sk_rx_jumbo_map); 625 case 2: 626 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 627 case 1: 628 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 629 break; 630 default: 631 break; 632 } 633 } 634 635 return (error); 636 } 637 638 /* 639 * Allocate a jumbo buffer. 640 */ 641 void * 642 msk_jalloc(struct sk_if_softc *sc_if) 643 { 644 struct sk_jpool_entry *entry; 645 646 mutex_enter(&sc_if->sk_jpool_mtx); 647 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 648 649 if (entry == NULL) { 650 mutex_exit(&sc_if->sk_jpool_mtx); 651 return NULL; 652 } 653 654 LIST_REMOVE(entry, jpool_entries); 655 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 656 mutex_exit(&sc_if->sk_jpool_mtx); 657 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 void 664 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 665 { 666 struct sk_jpool_entry *entry; 667 struct sk_if_softc *sc; 668 int i; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct sk_if_softc *)arg; 672 673 if (sc == NULL) 674 panic("msk_jfree: can't find softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 i = ((vaddr_t)buf 678 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 679 680 if ((i < 0) || (i >= MSK_JSLOTS)) 681 panic("msk_jfree: asked to free buffer that we don't manage!"); 682 683 mutex_enter(&sc->sk_jpool_mtx); 684 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 685 if (entry == NULL) 686 panic("msk_jfree: buffer not in use!"); 687 entry->slot = i; 688 LIST_REMOVE(entry, jpool_entries); 689 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 690 mutex_exit(&sc->sk_jpool_mtx); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc_if = ifp->if_softc; 700 int s, error = 0; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 error = ether_ioctl(ifp, cmd, data); 706 707 if (error == ENETRESET) { 708 error = 0; 709 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 710 ; 711 else if (ifp->if_flags & IFF_RUNNING) { 712 /* 713 * Multicast list has changed; set the hardware 714 * filter accordingly. 715 */ 716 msk_setmulti(sc_if); 717 } 718 } 719 720 splx(s); 721 return (error); 722 } 723 724 void 725 msk_update_int_mod(struct sk_softc *sc) 726 { 727 u_int32_t imtimer_ticks; 728 729 /* 730 * Configure interrupt moderation. The moderation timer 731 * defers interrupts specified in the interrupt moderation 732 * timer mask based on the timeout specified in the interrupt 733 * moderation timer init register. Each bit in the timer 734 * register represents one tick, so to specify a timeout in 735 * microseconds, we have to multiply by the correct number of 736 * ticks-per-microsecond. 737 */ 738 switch (sc->sk_type) { 739 case SK_YUKON_EC: 740 case SK_YUKON_EC_U: 741 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 742 break; 743 case SK_YUKON_FE: 744 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 745 break; 746 case SK_YUKON_XL: 747 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 748 break; 749 default: 750 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 751 } 752 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 753 sc->sk_int_mod); 754 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 755 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 756 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 757 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 758 sc->sk_int_mod_pending = 0; 759 } 760 761 static int 762 msk_lookup(const struct pci_attach_args *pa) 763 { 764 const struct msk_product *pmsk; 765 766 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 767 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 768 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 769 return 1; 770 } 771 return 0; 772 } 773 774 /* 775 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 776 * IDs against our list and return a device name if we find a match. 777 */ 778 int 779 mskc_probe(struct device *parent, struct cfdata *match, 780 void *aux) 781 { 782 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 783 784 return msk_lookup(pa); 785 } 786 787 /* 788 * Force the GEnesis into reset, then bring it out of reset. 789 */ 790 void msk_reset(struct sk_softc *sc) 791 { 792 u_int32_t imtimer_ticks, reg1; 793 int reg; 794 795 DPRINTFN(2, ("msk_reset\n")); 796 797 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 798 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 799 800 DELAY(1000); 801 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 802 DELAY(2); 803 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 804 sk_win_write_1(sc, SK_TESTCTL1, 2); 805 806 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 807 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 808 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 809 else 810 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 811 812 if (sc->sk_type == SK_YUKON_EC_U) { 813 uint32_t our; 814 815 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 816 817 /* enable all clocks. */ 818 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 819 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 820 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 821 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 822 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 823 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 824 /* Set all bits to 0 except bits 15..12 */ 825 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 826 /* Set to default value */ 827 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 828 } 829 830 /* release PHY from PowerDown/Coma mode. */ 831 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 832 833 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 834 sk_win_write_1(sc, SK_Y2_CLKGATE, 835 SK_Y2_CLKGATE_LINK1_GATE_DIS | 836 SK_Y2_CLKGATE_LINK2_GATE_DIS | 837 SK_Y2_CLKGATE_LINK1_CORE_DIS | 838 SK_Y2_CLKGATE_LINK2_CORE_DIS | 839 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 840 else 841 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 842 843 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 844 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 845 DELAY(1000); 846 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 847 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 848 849 sk_win_write_1(sc, SK_TESTCTL1, 1); 850 851 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 852 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 853 CSR_READ_2(sc, SK_LINK_CTRL))); 854 855 /* Disable ASF */ 856 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 857 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 858 859 /* Clear I2C IRQ noise */ 860 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 861 862 /* Disable hardware timer */ 863 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 864 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 865 866 /* Disable descriptor polling */ 867 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 868 869 /* Disable time stamps */ 870 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 871 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 872 873 /* Enable RAM interface */ 874 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 875 for (reg = SK_TO0;reg <= SK_TO11; reg++) 876 sk_win_write_1(sc, reg, 36); 877 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 878 for (reg = SK_TO0;reg <= SK_TO11; reg++) 879 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 880 881 /* 882 * Configure interrupt moderation. The moderation timer 883 * defers interrupts specified in the interrupt moderation 884 * timer mask based on the timeout specified in the interrupt 885 * moderation timer init register. Each bit in the timer 886 * register represents one tick, so to specify a timeout in 887 * microseconds, we have to multiply by the correct number of 888 * ticks-per-microsecond. 889 */ 890 switch (sc->sk_type) { 891 case SK_YUKON_EC: 892 case SK_YUKON_EC_U: 893 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 894 break; 895 case SK_YUKON_FE: 896 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 897 break; 898 case SK_YUKON_XL: 899 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 900 break; 901 default: 902 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 903 } 904 905 /* Reset status ring. */ 906 bzero((char *)sc->sk_status_ring, 907 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 908 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 909 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 910 sc->sk_status_idx = 0; 911 sc->sk_status_own_idx = 0; 912 913 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 914 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 915 916 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 917 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 918 sc->sk_status_map->dm_segs[0].ds_addr); 919 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 920 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 921 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 922 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 923 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 924 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 925 } else { 926 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 927 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 928 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 929 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 930 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 931 } 932 933 #if 0 934 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 935 #endif 936 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 937 938 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 939 940 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 941 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 942 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 943 944 msk_update_int_mod(sc); 945 } 946 947 int 948 msk_probe(struct device *parent, struct cfdata *match, 949 void *aux) 950 { 951 struct skc_attach_args *sa = aux; 952 953 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 954 return (0); 955 956 switch (sa->skc_type) { 957 case SK_YUKON_XL: 958 case SK_YUKON_EC_U: 959 case SK_YUKON_EC: 960 case SK_YUKON_FE: 961 return (1); 962 } 963 964 return (0); 965 } 966 967 static bool 968 msk_resume(device_t dv PMF_FN_ARGS) 969 { 970 struct sk_if_softc *sc_if = device_private(dv); 971 972 msk_init_yukon(sc_if); 973 return true; 974 } 975 976 /* 977 * Each XMAC chip is attached as a separate logical IP interface. 978 * Single port cards will have only one logical interface of course. 979 */ 980 void 981 msk_attach(struct device *parent, struct device *self, void *aux) 982 { 983 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 984 struct sk_softc *sc = (struct sk_softc *)parent; 985 struct skc_attach_args *sa = aux; 986 struct ifnet *ifp; 987 void *kva; 988 bus_dma_segment_t seg; 989 int i, rseg; 990 u_int32_t chunk, val; 991 992 sc_if->sk_port = sa->skc_port; 993 sc_if->sk_softc = sc; 994 sc->sk_if[sa->skc_port] = sc_if; 995 996 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 997 998 /* 999 * Get station address for this interface. Note that 1000 * dual port cards actually come with three station 1001 * addresses: one for each port, plus an extra. The 1002 * extra one is used by the SysKonnect driver software 1003 * as a 'virtual' station address for when both ports 1004 * are operating in failover mode. Currently we don't 1005 * use this extra address. 1006 */ 1007 for (i = 0; i < ETHER_ADDR_LEN; i++) 1008 sc_if->sk_enaddr[i] = 1009 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1010 1011 aprint_normal(": Ethernet address %s\n", 1012 ether_sprintf(sc_if->sk_enaddr)); 1013 1014 /* 1015 * Set up RAM buffer addresses. The NIC will have a certain 1016 * amount of SRAM on it, somewhere between 512K and 2MB. We 1017 * need to divide this up a) between the transmitter and 1018 * receiver and b) between the two XMACs, if this is a 1019 * dual port NIC. Our algorithm is to divide up the memory 1020 * evenly so that everyone gets a fair share. 1021 * 1022 * Just to be contrary, Yukon2 appears to have separate memory 1023 * for each MAC. 1024 */ 1025 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1026 val = sc->sk_rboff / sizeof(u_int64_t); 1027 sc_if->sk_rx_ramstart = val; 1028 val += (chunk / sizeof(u_int64_t)); 1029 sc_if->sk_rx_ramend = val - 1; 1030 chunk = sc->sk_ramsize - chunk; 1031 sc_if->sk_tx_ramstart = val; 1032 val += (chunk / sizeof(u_int64_t)); 1033 sc_if->sk_tx_ramend = val - 1; 1034 1035 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1036 " tx_ramstart=%#x tx_ramend=%#x\n", 1037 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1038 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1039 1040 /* Allocate the descriptor queues. */ 1041 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1042 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1043 aprint_error(": can't alloc rx buffers\n"); 1044 goto fail; 1045 } 1046 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1047 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1048 aprint_error(": can't map dma buffers (%zu bytes)\n", 1049 sizeof(struct msk_ring_data)); 1050 goto fail_1; 1051 } 1052 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1053 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1054 &sc_if->sk_ring_map)) { 1055 aprint_error(": can't create dma map\n"); 1056 goto fail_2; 1057 } 1058 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1059 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1060 aprint_error(": can't load dma map\n"); 1061 goto fail_3; 1062 } 1063 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1064 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1065 1066 ifp = &sc_if->sk_ethercom.ec_if; 1067 /* Try to allocate memory for jumbo buffers. */ 1068 if (msk_alloc_jumbo_mem(sc_if)) { 1069 aprint_error(": jumbo buffer allocation failed\n"); 1070 goto fail_3; 1071 } 1072 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1073 if (sc->sk_type != SK_YUKON_FE) 1074 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1075 1076 ifp->if_softc = sc_if; 1077 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1078 ifp->if_ioctl = msk_ioctl; 1079 ifp->if_start = msk_start; 1080 ifp->if_stop = msk_stop; 1081 ifp->if_init = msk_init; 1082 ifp->if_watchdog = msk_watchdog; 1083 ifp->if_baudrate = 1000000000; 1084 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1085 IFQ_SET_READY(&ifp->if_snd); 1086 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1087 1088 /* 1089 * Do miibus setup. 1090 */ 1091 msk_init_yukon(sc_if); 1092 1093 DPRINTFN(2, ("msk_attach: 1\n")); 1094 1095 sc_if->sk_mii.mii_ifp = ifp; 1096 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1097 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1098 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1099 1100 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1101 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1102 ether_mediachange, ether_mediastatus); 1103 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1104 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1105 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1106 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1107 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1108 0, NULL); 1109 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1110 } else 1111 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1112 1113 callout_init(&sc_if->sk_tick_ch, 0); 1114 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1115 callout_schedule(&sc_if->sk_tick_ch, hz); 1116 1117 /* 1118 * Call MI attach routines. 1119 */ 1120 if_attach(ifp); 1121 ether_ifattach(ifp, sc_if->sk_enaddr); 1122 1123 if (!pmf_device_register(self, NULL, msk_resume)) 1124 aprint_error_dev(self, "couldn't establish power handler\n"); 1125 else 1126 pmf_class_network_register(self, ifp); 1127 1128 #if NRND > 0 1129 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1130 RND_TYPE_NET, 0); 1131 #endif 1132 1133 DPRINTFN(2, ("msk_attach: end\n")); 1134 return; 1135 1136 fail_3: 1137 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1138 fail_2: 1139 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1140 fail_1: 1141 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1142 fail: 1143 sc->sk_if[sa->skc_port] = NULL; 1144 } 1145 1146 int 1147 mskcprint(void *aux, const char *pnp) 1148 { 1149 struct skc_attach_args *sa = aux; 1150 1151 if (pnp) 1152 aprint_normal("sk port %c at %s", 1153 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1154 else 1155 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1156 return (UNCONF); 1157 } 1158 1159 /* 1160 * Attach the interface. Allocate softc structures, do ifmedia 1161 * setup and ethernet/BPF attach. 1162 */ 1163 void 1164 mskc_attach(struct device *parent, struct device *self, void *aux) 1165 { 1166 struct sk_softc *sc = (struct sk_softc *)self; 1167 struct pci_attach_args *pa = aux; 1168 struct skc_attach_args skca; 1169 pci_chipset_tag_t pc = pa->pa_pc; 1170 pcireg_t command, memtype; 1171 pci_intr_handle_t ih; 1172 const char *intrstr = NULL; 1173 bus_size_t size; 1174 int rc, sk_nodenum; 1175 u_int8_t hw, skrs; 1176 const char *revstr = NULL; 1177 const struct sysctlnode *node; 1178 void *kva; 1179 bus_dma_segment_t seg; 1180 int rseg; 1181 1182 DPRINTFN(2, ("begin mskc_attach\n")); 1183 1184 /* 1185 * Handle power management nonsense. 1186 */ 1187 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1188 1189 if (command == 0x01) { 1190 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1191 if (command & SK_PSTATE_MASK) { 1192 u_int32_t iobase, membase, irq; 1193 1194 /* Save important PCI config data. */ 1195 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1196 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1197 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1198 1199 /* Reset the power state. */ 1200 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1201 "-- setting to D0\n", 1202 command & SK_PSTATE_MASK); 1203 command &= 0xFFFFFFFC; 1204 pci_conf_write(pc, pa->pa_tag, 1205 SK_PCI_PWRMGMTCTRL, command); 1206 1207 /* Restore PCI config data. */ 1208 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1209 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1210 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1211 } 1212 } 1213 1214 /* 1215 * Map control/status registers. 1216 */ 1217 1218 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1219 switch (memtype) { 1220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1222 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1223 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1224 NULL, &size) == 0) 1225 break; 1226 default: 1227 aprint_error(": can't map mem space\n"); 1228 return; 1229 } 1230 1231 sc->sc_dmatag = pa->pa_dmat; 1232 1233 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1234 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1235 1236 /* bail out here if chip is not recognized */ 1237 if (!(SK_IS_YUKON2(sc))) { 1238 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1239 goto fail_1; 1240 } 1241 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1242 1243 /* Allocate interrupt */ 1244 if (pci_intr_map(pa, &ih)) { 1245 aprint_error(": couldn't map interrupt\n"); 1246 goto fail_1; 1247 } 1248 1249 intrstr = pci_intr_string(pc, ih); 1250 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1251 if (sc->sk_intrhand == NULL) { 1252 aprint_error(": couldn't establish interrupt"); 1253 if (intrstr != NULL) 1254 aprint_error(" at %s", intrstr); 1255 aprint_error("\n"); 1256 goto fail_1; 1257 } 1258 1259 if (bus_dmamem_alloc(sc->sc_dmatag, 1260 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1261 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1262 aprint_error(": can't alloc status buffers\n"); 1263 goto fail_2; 1264 } 1265 1266 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1267 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1268 &kva, BUS_DMA_NOWAIT)) { 1269 aprint_error(": can't map dma buffers (%zu bytes)\n", 1270 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1271 goto fail_3; 1272 } 1273 if (bus_dmamap_create(sc->sc_dmatag, 1274 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1275 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1276 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1277 aprint_error(": can't create dma map\n"); 1278 goto fail_4; 1279 } 1280 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1281 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1282 NULL, BUS_DMA_NOWAIT)) { 1283 aprint_error(": can't load dma map\n"); 1284 goto fail_5; 1285 } 1286 sc->sk_status_ring = (struct msk_status_desc *)kva; 1287 1288 /* Reset the adapter. */ 1289 msk_reset(sc); 1290 1291 skrs = sk_win_read_1(sc, SK_EPROM0); 1292 if (skrs == 0x00) 1293 sc->sk_ramsize = 0x20000; 1294 else 1295 sc->sk_ramsize = skrs * (1<<12); 1296 sc->sk_rboff = SK_RBOFF_0; 1297 1298 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1299 sc->sk_ramsize, sc->sk_ramsize / 1024, 1300 sc->sk_rboff)); 1301 1302 switch (sc->sk_type) { 1303 case SK_YUKON_XL: 1304 sc->sk_name = "Yukon-2 XL"; 1305 break; 1306 case SK_YUKON_EC_U: 1307 sc->sk_name = "Yukon-2 EC Ultra"; 1308 break; 1309 case SK_YUKON_EC: 1310 sc->sk_name = "Yukon-2 EC"; 1311 break; 1312 case SK_YUKON_FE: 1313 sc->sk_name = "Yukon-2 FE"; 1314 break; 1315 default: 1316 sc->sk_name = "Yukon (Unknown)"; 1317 } 1318 1319 if (sc->sk_type == SK_YUKON_XL) { 1320 switch (sc->sk_rev) { 1321 case SK_YUKON_XL_REV_A0: 1322 sc->sk_workaround = 0; 1323 revstr = "A0"; 1324 break; 1325 case SK_YUKON_XL_REV_A1: 1326 sc->sk_workaround = SK_WA_4109; 1327 revstr = "A1"; 1328 break; 1329 case SK_YUKON_XL_REV_A2: 1330 sc->sk_workaround = SK_WA_4109; 1331 revstr = "A2"; 1332 break; 1333 case SK_YUKON_XL_REV_A3: 1334 sc->sk_workaround = SK_WA_4109; 1335 revstr = "A3"; 1336 break; 1337 default: 1338 sc->sk_workaround = 0; 1339 break; 1340 } 1341 } 1342 1343 if (sc->sk_type == SK_YUKON_EC) { 1344 switch (sc->sk_rev) { 1345 case SK_YUKON_EC_REV_A1: 1346 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1347 revstr = "A1"; 1348 break; 1349 case SK_YUKON_EC_REV_A2: 1350 sc->sk_workaround = SK_WA_4109; 1351 revstr = "A2"; 1352 break; 1353 case SK_YUKON_EC_REV_A3: 1354 sc->sk_workaround = SK_WA_4109; 1355 revstr = "A3"; 1356 break; 1357 default: 1358 sc->sk_workaround = 0; 1359 break; 1360 } 1361 } 1362 1363 if (sc->sk_type == SK_YUKON_FE) { 1364 sc->sk_workaround = SK_WA_4109; 1365 switch (sc->sk_rev) { 1366 case SK_YUKON_FE_REV_A1: 1367 revstr = "A1"; 1368 break; 1369 case SK_YUKON_FE_REV_A2: 1370 revstr = "A2"; 1371 break; 1372 default: 1373 sc->sk_workaround = 0; 1374 break; 1375 } 1376 } 1377 1378 if (sc->sk_type == SK_YUKON_EC_U) { 1379 sc->sk_workaround = SK_WA_4109; 1380 switch (sc->sk_rev) { 1381 case SK_YUKON_EC_U_REV_A0: 1382 revstr = "A0"; 1383 break; 1384 case SK_YUKON_EC_U_REV_A1: 1385 revstr = "A1"; 1386 break; 1387 case SK_YUKON_EC_U_REV_B0: 1388 revstr = "B0"; 1389 break; 1390 default: 1391 sc->sk_workaround = 0; 1392 break; 1393 } 1394 } 1395 1396 /* Announce the product name. */ 1397 aprint_normal(", %s", sc->sk_name); 1398 if (revstr != NULL) 1399 aprint_normal(" rev. %s", revstr); 1400 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1401 1402 sc->sk_macs = 1; 1403 1404 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1405 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1406 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1407 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1408 sc->sk_macs++; 1409 } 1410 1411 skca.skc_port = SK_PORT_A; 1412 skca.skc_type = sc->sk_type; 1413 skca.skc_rev = sc->sk_rev; 1414 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1415 1416 if (sc->sk_macs > 1) { 1417 skca.skc_port = SK_PORT_B; 1418 skca.skc_type = sc->sk_type; 1419 skca.skc_rev = sc->sk_rev; 1420 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1421 } 1422 1423 /* Turn on the 'driver is loaded' LED. */ 1424 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1425 1426 /* skc sysctl setup */ 1427 1428 sc->sk_int_mod = SK_IM_DEFAULT; 1429 sc->sk_int_mod_pending = 0; 1430 1431 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1432 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1433 SYSCTL_DESCR("mskc per-controller controls"), 1434 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1435 CTL_EOL)) != 0) { 1436 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1437 goto fail_6; 1438 } 1439 1440 sk_nodenum = node->sysctl_num; 1441 1442 /* interrupt moderation time in usecs */ 1443 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1444 CTLFLAG_READWRITE, 1445 CTLTYPE_INT, "int_mod", 1446 SYSCTL_DESCR("msk interrupt moderation timer"), 1447 msk_sysctl_handler, 0, sc, 1448 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1449 CTL_EOL)) != 0) { 1450 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1451 goto fail_6; 1452 } 1453 1454 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1455 aprint_error_dev(self, "couldn't establish power handler\n"); 1456 1457 return; 1458 1459 fail_6: 1460 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1461 fail_5: 1462 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1463 fail_4: 1464 bus_dmamem_unmap(sc->sc_dmatag, kva, 1465 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1466 fail_3: 1467 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1468 fail_2: 1469 pci_intr_disestablish(pc, sc->sk_intrhand); 1470 fail_1: 1471 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1472 } 1473 1474 int 1475 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1476 { 1477 struct sk_softc *sc = sc_if->sk_softc; 1478 struct msk_tx_desc *f = NULL; 1479 u_int32_t frag, cur; 1480 int i; 1481 struct sk_txmap_entry *entry; 1482 bus_dmamap_t txmap; 1483 1484 DPRINTFN(2, ("msk_encap\n")); 1485 1486 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1487 if (entry == NULL) { 1488 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1489 return (ENOBUFS); 1490 } 1491 txmap = entry->dmamap; 1492 1493 cur = frag = *txidx; 1494 1495 #ifdef MSK_DEBUG 1496 if (mskdebug >= 2) 1497 msk_dump_mbuf(m_head); 1498 #endif 1499 1500 /* 1501 * Start packing the mbufs in this chain into 1502 * the fragment pointers. Stop when we run out 1503 * of fragments or hit the end of the mbuf chain. 1504 */ 1505 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1506 BUS_DMA_NOWAIT)) { 1507 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1508 return (ENOBUFS); 1509 } 1510 1511 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1512 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1513 bus_dmamap_unload(sc->sc_dmatag, txmap); 1514 return (ENOBUFS); 1515 } 1516 1517 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1518 1519 /* Sync the DMA map. */ 1520 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1521 BUS_DMASYNC_PREWRITE); 1522 1523 for (i = 0; i < txmap->dm_nsegs; i++) { 1524 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1525 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1526 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1527 f->sk_ctl = 0; 1528 if (i == 0) 1529 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1530 else 1531 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1532 cur = frag; 1533 SK_INC(frag, MSK_TX_RING_CNT); 1534 } 1535 1536 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1537 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1538 1539 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1540 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1541 1542 /* Sync descriptors before handing to chip */ 1543 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1544 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1545 1546 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1547 1548 /* Sync first descriptor to hand it off */ 1549 MSK_CDTXSYNC(sc_if, *txidx, 1, 1550 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1551 1552 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1553 1554 #ifdef MSK_DEBUG 1555 if (mskdebug >= 2) { 1556 struct msk_tx_desc *le; 1557 u_int32_t idx; 1558 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1559 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1560 msk_dump_txdesc(le, idx); 1561 } 1562 } 1563 #endif 1564 1565 *txidx = frag; 1566 1567 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1568 1569 return (0); 1570 } 1571 1572 void 1573 msk_start(struct ifnet *ifp) 1574 { 1575 struct sk_if_softc *sc_if = ifp->if_softc; 1576 struct mbuf *m_head = NULL; 1577 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1578 int pkts = 0; 1579 1580 DPRINTFN(2, ("msk_start\n")); 1581 1582 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1583 IFQ_POLL(&ifp->if_snd, m_head); 1584 if (m_head == NULL) 1585 break; 1586 1587 /* 1588 * Pack the data into the transmit ring. If we 1589 * don't have room, set the OACTIVE flag and wait 1590 * for the NIC to drain the ring. 1591 */ 1592 if (msk_encap(sc_if, m_head, &idx)) { 1593 ifp->if_flags |= IFF_OACTIVE; 1594 break; 1595 } 1596 1597 /* now we are committed to transmit the packet */ 1598 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1599 pkts++; 1600 1601 /* 1602 * If there's a BPF listener, bounce a copy of this frame 1603 * to him. 1604 */ 1605 #if NBPFILTER > 0 1606 if (ifp->if_bpf) 1607 bpf_mtap(ifp->if_bpf, m_head); 1608 #endif 1609 } 1610 if (pkts == 0) 1611 return; 1612 1613 /* Transmit */ 1614 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1615 sc_if->sk_cdata.sk_tx_prod = idx; 1616 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1617 1618 /* Set a timeout in case the chip goes out to lunch. */ 1619 ifp->if_timer = 5; 1620 } 1621 } 1622 1623 void 1624 msk_watchdog(struct ifnet *ifp) 1625 { 1626 struct sk_if_softc *sc_if = ifp->if_softc; 1627 u_int32_t reg; 1628 int idx; 1629 1630 /* 1631 * Reclaim first as there is a possibility of losing Tx completion 1632 * interrupts. 1633 */ 1634 if (sc_if->sk_port == SK_PORT_A) 1635 reg = SK_STAT_BMU_TXA1_RIDX; 1636 else 1637 reg = SK_STAT_BMU_TXA2_RIDX; 1638 1639 idx = sk_win_read_2(sc_if->sk_softc, reg); 1640 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1641 msk_txeof(sc_if, idx); 1642 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1643 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1644 1645 ifp->if_oerrors++; 1646 1647 /* XXX Resets both ports; we shouldn't do that. */ 1648 msk_reset(sc_if->sk_softc); 1649 msk_init(ifp); 1650 } 1651 } 1652 } 1653 1654 static bool 1655 mskc_suspend(device_t dv PMF_FN_ARGS) 1656 { 1657 struct sk_softc *sc = device_private(dv); 1658 1659 DPRINTFN(2, ("mskc_suspend\n")); 1660 1661 /* Turn off the 'driver is loaded' LED. */ 1662 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1663 1664 return true; 1665 } 1666 1667 static bool 1668 mskc_resume(device_t dv PMF_FN_ARGS) 1669 { 1670 struct sk_softc *sc = device_private(dv); 1671 1672 DPRINTFN(2, ("mskc_resume\n")); 1673 1674 msk_reset(sc); 1675 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1676 1677 return true; 1678 } 1679 1680 __inline int 1681 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1682 { 1683 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1684 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1685 YU_RXSTAT_JABBER)) != 0 || 1686 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1687 YU_RXSTAT_BYTES(stat) != len) 1688 return (0); 1689 1690 return (1); 1691 } 1692 1693 void 1694 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1695 { 1696 struct sk_softc *sc = sc_if->sk_softc; 1697 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1698 struct mbuf *m; 1699 struct sk_chain *cur_rx; 1700 int cur, total_len = len; 1701 bus_dmamap_t dmamap; 1702 1703 DPRINTFN(2, ("msk_rxeof\n")); 1704 1705 cur = sc_if->sk_cdata.sk_rx_cons; 1706 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1707 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1708 1709 /* Sync the descriptor */ 1710 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1711 1712 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1713 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1714 1715 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1716 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1717 1718 m = cur_rx->sk_mbuf; 1719 cur_rx->sk_mbuf = NULL; 1720 1721 if (total_len < SK_MIN_FRAMELEN || 1722 total_len > ETHER_MAX_LEN_JUMBO || 1723 msk_rxvalid(sc, rxstat, total_len) == 0) { 1724 ifp->if_ierrors++; 1725 msk_newbuf(sc_if, cur, m, dmamap); 1726 return; 1727 } 1728 1729 /* 1730 * Try to allocate a new jumbo buffer. If that fails, copy the 1731 * packet to mbufs and put the jumbo buffer back in the ring 1732 * so it can be re-used. If allocating mbufs fails, then we 1733 * have to drop the packet. 1734 */ 1735 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1736 struct mbuf *m0; 1737 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1738 total_len + ETHER_ALIGN, 0, ifp, NULL); 1739 msk_newbuf(sc_if, cur, m, dmamap); 1740 if (m0 == NULL) { 1741 ifp->if_ierrors++; 1742 return; 1743 } 1744 m_adj(m0, ETHER_ALIGN); 1745 m = m0; 1746 } else { 1747 m->m_pkthdr.rcvif = ifp; 1748 m->m_pkthdr.len = m->m_len = total_len; 1749 } 1750 1751 ifp->if_ipackets++; 1752 1753 #if NBPFILTER > 0 1754 if (ifp->if_bpf) 1755 bpf_mtap(ifp->if_bpf, m); 1756 #endif 1757 1758 /* pass it on. */ 1759 (*ifp->if_input)(ifp, m); 1760 } 1761 1762 void 1763 msk_txeof(struct sk_if_softc *sc_if, int idx) 1764 { 1765 struct sk_softc *sc = sc_if->sk_softc; 1766 struct msk_tx_desc *cur_tx; 1767 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1768 u_int32_t sk_ctl; 1769 struct sk_txmap_entry *entry; 1770 int cons, prog; 1771 1772 DPRINTFN(2, ("msk_txeof\n")); 1773 1774 /* 1775 * Go through our tx ring and free mbufs for those 1776 * frames that have been sent. 1777 */ 1778 cons = sc_if->sk_cdata.sk_tx_cons; 1779 prog = 0; 1780 while (cons != idx) { 1781 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1782 break; 1783 prog++; 1784 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1785 1786 MSK_CDTXSYNC(sc_if, cons, 1, 1787 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1788 sk_ctl = cur_tx->sk_ctl; 1789 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1790 #ifdef MSK_DEBUG 1791 if (mskdebug >= 2) 1792 msk_dump_txdesc(cur_tx, cons); 1793 #endif 1794 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1795 ifp->if_opackets++; 1796 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1797 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1798 1799 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1800 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1801 1802 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1803 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1804 link); 1805 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1806 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1807 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1808 } 1809 sc_if->sk_cdata.sk_tx_cnt--; 1810 SK_INC(cons, MSK_TX_RING_CNT); 1811 } 1812 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1813 1814 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1815 ifp->if_flags &= ~IFF_OACTIVE; 1816 1817 if (prog > 0) 1818 sc_if->sk_cdata.sk_tx_cons = cons; 1819 } 1820 1821 void 1822 msk_tick(void *xsc_if) 1823 { 1824 struct sk_if_softc *sc_if = xsc_if; 1825 struct mii_data *mii = &sc_if->sk_mii; 1826 int s; 1827 1828 s = splnet(); 1829 mii_tick(mii); 1830 splx(s); 1831 1832 callout_schedule(&sc_if->sk_tick_ch, hz); 1833 } 1834 1835 void 1836 msk_intr_yukon(struct sk_if_softc *sc_if) 1837 { 1838 u_int8_t status; 1839 1840 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1841 /* RX overrun */ 1842 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1843 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1844 SK_RFCTL_RX_FIFO_OVER); 1845 } 1846 /* TX underrun */ 1847 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1848 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1849 SK_TFCTL_TX_FIFO_UNDER); 1850 } 1851 1852 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1853 } 1854 1855 int 1856 msk_intr(void *xsc) 1857 { 1858 struct sk_softc *sc = xsc; 1859 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1860 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1861 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1862 int claimed = 0; 1863 u_int32_t status; 1864 uint32_t st_status; 1865 uint16_t st_len; 1866 uint8_t st_opcode, st_link; 1867 struct msk_status_desc *cur_st; 1868 1869 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1870 if (status == 0) { 1871 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1872 return (0); 1873 } 1874 1875 status = CSR_READ_4(sc, SK_ISR); 1876 1877 if (sc_if0 != NULL) 1878 ifp0 = &sc_if0->sk_ethercom.ec_if; 1879 if (sc_if1 != NULL) 1880 ifp1 = &sc_if1->sk_ethercom.ec_if; 1881 1882 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1883 (ifp0->if_flags & IFF_RUNNING)) { 1884 msk_intr_yukon(sc_if0); 1885 } 1886 1887 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1888 (ifp1->if_flags & IFF_RUNNING)) { 1889 msk_intr_yukon(sc_if1); 1890 } 1891 1892 for (;;) { 1893 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1894 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1895 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1896 st_opcode = cur_st->sk_opcode; 1897 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1898 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1899 BUS_DMASYNC_PREREAD); 1900 break; 1901 } 1902 st_status = le32toh(cur_st->sk_status); 1903 st_len = le16toh(cur_st->sk_len); 1904 st_link = cur_st->sk_link; 1905 st_opcode &= ~SK_Y2_STOPC_OWN; 1906 1907 switch (st_opcode) { 1908 case SK_Y2_STOPC_RXSTAT: 1909 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1910 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1911 SK_RXQ1_Y2_PREF_PUTIDX, 1912 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1913 break; 1914 case SK_Y2_STOPC_TXSTAT: 1915 if (sc_if0) 1916 msk_txeof(sc_if0, st_status 1917 & SK_Y2_ST_TXA1_MSKL); 1918 if (sc_if1) 1919 msk_txeof(sc_if1, 1920 ((st_status & SK_Y2_ST_TXA2_MSKL) 1921 >> SK_Y2_ST_TXA2_SHIFTL) 1922 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1923 break; 1924 default: 1925 aprint_error("opcode=0x%x\n", st_opcode); 1926 break; 1927 } 1928 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1929 } 1930 1931 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1932 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1933 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1934 1935 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1936 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1937 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1938 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1939 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1940 1941 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1942 } 1943 1944 if (status & SK_Y2_IMR_BMU) { 1945 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1946 claimed = 1; 1947 } 1948 1949 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1950 1951 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1952 msk_start(ifp0); 1953 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1954 msk_start(ifp1); 1955 1956 #if NRND > 0 1957 if (RND_ENABLED(&sc->rnd_source)) 1958 rnd_add_uint32(&sc->rnd_source, status); 1959 #endif 1960 1961 if (sc->sk_int_mod_pending) 1962 msk_update_int_mod(sc); 1963 1964 return claimed; 1965 } 1966 1967 void 1968 msk_init_yukon(struct sk_if_softc *sc_if) 1969 { 1970 u_int32_t v; 1971 u_int16_t reg; 1972 struct sk_softc *sc; 1973 int i; 1974 1975 sc = sc_if->sk_softc; 1976 1977 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1978 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1979 1980 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1981 1982 /* GMAC and GPHY Reset */ 1983 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1984 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1985 DELAY(1000); 1986 1987 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1988 1989 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1990 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1991 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1992 1993 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1994 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1995 1996 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1997 1998 /* unused read of the interrupt source register */ 1999 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2000 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2001 2002 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2003 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2004 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2005 2006 /* MIB Counter Clear Mode set */ 2007 reg |= YU_PAR_MIB_CLR; 2008 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2009 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2010 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2011 2012 /* MIB Counter Clear Mode clear */ 2013 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2014 reg &= ~YU_PAR_MIB_CLR; 2015 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2016 2017 /* receive control reg */ 2018 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2019 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2020 2021 /* transmit control register */ 2022 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2023 2024 /* transmit flow control register */ 2025 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2026 2027 /* transmit parameter register */ 2028 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2029 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2030 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2031 2032 /* serial mode register */ 2033 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2034 reg = YU_SMR_DATA_BLIND(0x1c) | 2035 YU_SMR_MFL_VLAN | 2036 YU_SMR_IPG_DATA(0x1e); 2037 2038 if (sc->sk_type != SK_YUKON_FE) 2039 reg |= YU_SMR_MFL_JUMBO; 2040 2041 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2042 2043 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2044 /* Setup Yukon's address */ 2045 for (i = 0; i < 3; i++) { 2046 /* Write Source Address 1 (unicast filter) */ 2047 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2048 sc_if->sk_enaddr[i * 2] | 2049 sc_if->sk_enaddr[i * 2 + 1] << 8); 2050 } 2051 2052 for (i = 0; i < 3; i++) { 2053 reg = sk_win_read_2(sc_if->sk_softc, 2054 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2055 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2056 } 2057 2058 /* Set promiscuous mode */ 2059 msk_setpromisc(sc_if); 2060 2061 /* Set multicast filter */ 2062 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2063 msk_setmulti(sc_if); 2064 2065 /* enable interrupt mask for counter overflows */ 2066 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2067 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2068 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2069 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2070 2071 /* Configure RX MAC FIFO Flush Mask */ 2072 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2073 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2074 YU_RXSTAT_JABBER; 2075 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2076 2077 /* Configure RX MAC FIFO */ 2078 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2079 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2080 SK_RFCTL_FIFO_FLUSH_ON); 2081 2082 /* Increase flush threshould to 64 bytes */ 2083 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2084 SK_RFCTL_FIFO_THRESHOLD + 1); 2085 2086 /* Configure TX MAC FIFO */ 2087 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2088 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2089 2090 #if 1 2091 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2092 #endif 2093 DPRINTFN(6, ("msk_init_yukon: end\n")); 2094 } 2095 2096 /* 2097 * Note that to properly initialize any part of the GEnesis chip, 2098 * you first have to take it out of reset mode. 2099 */ 2100 int 2101 msk_init(struct ifnet *ifp) 2102 { 2103 struct sk_if_softc *sc_if = ifp->if_softc; 2104 struct sk_softc *sc = sc_if->sk_softc; 2105 int rc = 0, s; 2106 uint32_t imr, imtimer_ticks; 2107 2108 2109 DPRINTFN(2, ("msk_init\n")); 2110 2111 s = splnet(); 2112 2113 /* Cancel pending I/O and free all RX/TX buffers. */ 2114 msk_stop(ifp,0); 2115 2116 /* Configure I2C registers */ 2117 2118 /* Configure XMAC(s) */ 2119 msk_init_yukon(sc_if); 2120 if ((rc = ether_mediachange(ifp)) != 0) 2121 goto out; 2122 2123 /* Configure transmit arbiter(s) */ 2124 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2125 #if 0 2126 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2127 #endif 2128 2129 /* Configure RAMbuffers */ 2130 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2134 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2135 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2136 2137 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2141 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2142 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2143 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2144 2145 /* Configure BMUs */ 2146 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2147 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2148 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2149 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2150 2151 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2152 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2153 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2154 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2155 2156 /* Make sure the sync transmit queue is disabled. */ 2157 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2158 2159 /* Init descriptors */ 2160 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2161 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2162 "memory for rx buffers\n"); 2163 msk_stop(ifp,0); 2164 splx(s); 2165 return ENOBUFS; 2166 } 2167 2168 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2169 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2170 "memory for tx buffers\n"); 2171 msk_stop(ifp,0); 2172 splx(s); 2173 return ENOBUFS; 2174 } 2175 2176 /* Set interrupt moderation if changed via sysctl. */ 2177 switch (sc->sk_type) { 2178 case SK_YUKON_EC: 2179 case SK_YUKON_EC_U: 2180 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2181 break; 2182 case SK_YUKON_FE: 2183 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2184 break; 2185 case SK_YUKON_XL: 2186 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2187 break; 2188 default: 2189 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2190 } 2191 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2192 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2193 sk_win_write_4(sc, SK_IMTIMERINIT, 2194 SK_IM_USECS(sc->sk_int_mod)); 2195 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2196 sc->sk_int_mod); 2197 } 2198 2199 /* Initialize prefetch engine. */ 2200 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2201 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2202 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2203 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2204 MSK_RX_RING_ADDR(sc_if, 0)); 2205 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2206 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2207 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2208 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2209 2210 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2211 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2212 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2213 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2214 MSK_TX_RING_ADDR(sc_if, 0)); 2215 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2216 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2217 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2218 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2219 2220 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2221 sc_if->sk_cdata.sk_rx_prod); 2222 2223 /* Configure interrupt handling */ 2224 if (sc_if->sk_port == SK_PORT_A) 2225 sc->sk_intrmask |= SK_Y2_INTRS1; 2226 else 2227 sc->sk_intrmask |= SK_Y2_INTRS2; 2228 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2229 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2230 2231 ifp->if_flags |= IFF_RUNNING; 2232 ifp->if_flags &= ~IFF_OACTIVE; 2233 2234 callout_schedule(&sc_if->sk_tick_ch, hz); 2235 2236 out: 2237 splx(s); 2238 return rc; 2239 } 2240 2241 void 2242 msk_stop(struct ifnet *ifp, int disable) 2243 { 2244 struct sk_if_softc *sc_if = ifp->if_softc; 2245 struct sk_softc *sc = sc_if->sk_softc; 2246 struct sk_txmap_entry *dma; 2247 int i; 2248 2249 DPRINTFN(2, ("msk_stop\n")); 2250 2251 callout_stop(&sc_if->sk_tick_ch); 2252 2253 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2254 2255 /* Stop transfer of Tx descriptors */ 2256 2257 /* Stop transfer of Rx descriptors */ 2258 2259 /* Turn off various components of this interface. */ 2260 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2261 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2262 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2263 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2264 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2265 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2266 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2267 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2268 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2269 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2270 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2271 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2272 2273 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2274 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2275 2276 /* Disable interrupts */ 2277 if (sc_if->sk_port == SK_PORT_A) 2278 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2279 else 2280 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2281 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2282 2283 SK_XM_READ_2(sc_if, XM_ISR); 2284 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2285 2286 /* Free RX and TX mbufs still in the queues. */ 2287 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2288 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2289 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2290 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2291 } 2292 } 2293 2294 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2295 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2296 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2297 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2298 #if 1 2299 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2300 sc_if->sk_cdata.sk_tx_map[i], link); 2301 sc_if->sk_cdata.sk_tx_map[i] = 0; 2302 #endif 2303 } 2304 } 2305 2306 #if 1 2307 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2308 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2309 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2310 free(dma, M_DEVBUF); 2311 } 2312 #endif 2313 } 2314 2315 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2316 NULL, NULL); 2317 2318 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2319 NULL, NULL); 2320 2321 #ifdef MSK_DEBUG 2322 void 2323 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2324 { 2325 #define DESC_PRINT(X) \ 2326 if (X) \ 2327 printf("txdesc[%d]." #X "=%#x\n", \ 2328 idx, X); 2329 2330 DESC_PRINT(letoh32(le->sk_addr)); 2331 DESC_PRINT(letoh16(le->sk_len)); 2332 DESC_PRINT(le->sk_ctl); 2333 DESC_PRINT(le->sk_opcode); 2334 #undef DESC_PRINT 2335 } 2336 2337 void 2338 msk_dump_bytes(const char *data, int len) 2339 { 2340 int c, i, j; 2341 2342 for (i = 0; i < len; i += 16) { 2343 printf("%08x ", i); 2344 c = len - i; 2345 if (c > 16) c = 16; 2346 2347 for (j = 0; j < c; j++) { 2348 printf("%02x ", data[i + j] & 0xff); 2349 if ((j & 0xf) == 7 && j > 0) 2350 printf(" "); 2351 } 2352 2353 for (; j < 16; j++) 2354 printf(" "); 2355 printf(" "); 2356 2357 for (j = 0; j < c; j++) { 2358 int ch = data[i + j] & 0xff; 2359 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2360 } 2361 2362 printf("\n"); 2363 2364 if (c < 16) 2365 break; 2366 } 2367 } 2368 2369 void 2370 msk_dump_mbuf(struct mbuf *m) 2371 { 2372 int count = m->m_pkthdr.len; 2373 2374 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2375 2376 while (count > 0 && m) { 2377 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2378 m, m->m_data, m->m_len); 2379 msk_dump_bytes(mtod(m, char *), m->m_len); 2380 2381 count -= m->m_len; 2382 m = m->m_next; 2383 } 2384 } 2385 #endif 2386 2387 static int 2388 msk_sysctl_handler(SYSCTLFN_ARGS) 2389 { 2390 int error, t; 2391 struct sysctlnode node; 2392 struct sk_softc *sc; 2393 2394 node = *rnode; 2395 sc = node.sysctl_data; 2396 t = sc->sk_int_mod; 2397 node.sysctl_data = &t; 2398 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2399 if (error || newp == NULL) 2400 return error; 2401 2402 if (t < SK_IM_MIN || t > SK_IM_MAX) 2403 return EINVAL; 2404 2405 /* update the softc with sysctl-changed value, and mark 2406 for hardware update */ 2407 sc->sk_int_mod = t; 2408 sc->sk_int_mod_pending = 1; 2409 return 0; 2410 } 2411 2412 /* 2413 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2414 * set up in skc_attach() 2415 */ 2416 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2417 { 2418 int rc; 2419 const struct sysctlnode *node; 2420 2421 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2422 0, CTLTYPE_NODE, "hw", NULL, 2423 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2424 goto err; 2425 } 2426 2427 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2428 0, CTLTYPE_NODE, "msk", 2429 SYSCTL_DESCR("msk interface controls"), 2430 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2431 goto err; 2432 } 2433 2434 msk_root_num = node->sysctl_num; 2435 return; 2436 2437 err: 2438 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2439 } 2440