1 /* $NetBSD: if_msk.c,v 1.16 2008/02/07 01:21:56 dyoung Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.16 2008/02/07 01:21:56 dyoung Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/device.h> 68 #include <sys/queue.h> 69 #include <sys/callout.h> 70 #include <sys/sysctl.h> 71 #include <sys/endian.h> 72 #ifdef __NetBSD__ 73 #define letoh16 htole16 74 #define letoh32 htole32 75 #endif 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 81 #include <net/if_media.h> 82 83 #if NBPFILTER > 0 84 #include <net/bpf.h> 85 #endif 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 #include <dev/mii/brgphyreg.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/pci/if_skreg.h> 99 #include <dev/pci/if_mskvar.h> 100 101 int mskc_probe(struct device *, struct cfdata *, void *); 102 void mskc_attach(struct device *, struct device *self, void *aux); 103 void mskc_shutdown(void *); 104 int msk_probe(struct device *, struct cfdata *, void *); 105 void msk_attach(struct device *, struct device *self, void *aux); 106 int mskcprint(void *, const char *); 107 int msk_intr(void *); 108 void msk_intr_yukon(struct sk_if_softc *); 109 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 110 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 111 void msk_txeof(struct sk_if_softc *, int); 112 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 113 void msk_start(struct ifnet *); 114 int msk_ioctl(struct ifnet *, u_long, void *); 115 int msk_init(struct ifnet *); 116 void msk_init_yukon(struct sk_if_softc *); 117 void msk_stop(struct ifnet *, int); 118 void msk_watchdog(struct ifnet *); 119 void msk_reset(struct sk_softc *); 120 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 121 int msk_alloc_jumbo_mem(struct sk_if_softc *); 122 void *msk_jalloc(struct sk_if_softc *); 123 void msk_jfree(struct mbuf *, void *, size_t, void *); 124 int msk_init_rx_ring(struct sk_if_softc *); 125 int msk_init_tx_ring(struct sk_if_softc *); 126 127 void msk_update_int_mod(struct sk_softc *); 128 129 int msk_miibus_readreg(struct device *, int, int); 130 void msk_miibus_writereg(struct device *, int, int, int); 131 void msk_miibus_statchg(struct device *); 132 133 void msk_setfilt(struct sk_if_softc *, void *, int); 134 void msk_setmulti(struct sk_if_softc *); 135 void msk_setpromisc(struct sk_if_softc *); 136 void msk_tick(void *); 137 138 /* #define MSK_DEBUG 1 */ 139 #ifdef MSK_DEBUG 140 #define DPRINTF(x) if (mskdebug) printf x 141 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 142 int mskdebug = MSK_DEBUG; 143 144 void msk_dump_txdesc(struct msk_tx_desc *, int); 145 void msk_dump_mbuf(struct mbuf *); 146 void msk_dump_bytes(const char *, int); 147 #else 148 #define DPRINTF(x) 149 #define DPRINTFN(n,x) 150 #endif 151 152 static int msk_sysctl_handler(SYSCTLFN_PROTO); 153 static int msk_root_num; 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 187 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 188 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 189 }; 190 191 static inline u_int32_t 192 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_4(sc, reg); 195 } 196 197 static inline u_int16_t 198 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 199 { 200 return CSR_READ_2(sc, reg); 201 } 202 203 static inline u_int8_t 204 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 205 { 206 return CSR_READ_1(sc, reg); 207 } 208 209 static inline void 210 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 211 { 212 CSR_WRITE_4(sc, reg, x); 213 } 214 215 static inline void 216 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 217 { 218 CSR_WRITE_2(sc, reg, x); 219 } 220 221 static inline void 222 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 223 { 224 CSR_WRITE_1(sc, reg, x); 225 } 226 227 int 228 msk_miibus_readreg(struct device *dev, int phy, int reg) 229 { 230 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 231 u_int16_t val; 232 int i; 233 234 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 235 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 236 237 for (i = 0; i < SK_TIMEOUT; i++) { 238 DELAY(1); 239 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 240 if (val & YU_SMICR_READ_VALID) 241 break; 242 } 243 244 if (i == SK_TIMEOUT) { 245 aprint_error("%s: phy failed to come ready\n", 246 sc_if->sk_dev.dv_xname); 247 return (0); 248 } 249 250 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 251 SK_TIMEOUT)); 252 253 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 254 255 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 256 phy, reg, val)); 257 258 return (val); 259 } 260 261 void 262 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 263 { 264 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 265 int i; 266 267 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 268 phy, reg, val)); 269 270 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 271 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 272 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 273 274 for (i = 0; i < SK_TIMEOUT; i++) { 275 DELAY(1); 276 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 277 break; 278 } 279 280 if (i == SK_TIMEOUT) 281 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 282 } 283 284 void 285 msk_miibus_statchg(struct device *dev) 286 { 287 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 288 struct mii_data *mii = &sc_if->sk_mii; 289 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 290 int gpcr; 291 292 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 293 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 294 295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 296 /* Set speed. */ 297 gpcr |= YU_GPCR_SPEED_DIS; 298 switch (IFM_SUBTYPE(mii->mii_media_active)) { 299 case IFM_1000_SX: 300 case IFM_1000_LX: 301 case IFM_1000_CX: 302 case IFM_1000_T: 303 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 304 break; 305 case IFM_100_TX: 306 gpcr |= YU_GPCR_SPEED; 307 break; 308 } 309 310 /* Set duplex. */ 311 gpcr |= YU_GPCR_DPLX_DIS; 312 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 313 gpcr |= YU_GPCR_DUPLEX; 314 315 /* Disable flow control. */ 316 gpcr |= YU_GPCR_FCTL_DIS; 317 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 318 } 319 320 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 321 322 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 323 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 324 } 325 326 #define HASH_BITS 6 327 328 void 329 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 330 { 331 char *addr = addrv; 332 int base = XM_RXFILT_ENTRY(slot); 333 334 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 335 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 336 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 337 } 338 339 void 340 msk_setmulti(struct sk_if_softc *sc_if) 341 { 342 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 343 u_int32_t hashes[2] = { 0, 0 }; 344 int h; 345 struct ethercom *ec = &sc_if->sk_ethercom; 346 struct ether_multi *enm; 347 struct ether_multistep step; 348 u_int16_t reg; 349 350 /* First, zot all the existing filters. */ 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 355 356 357 /* Now program new ones. */ 358 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 359 reg |= YU_RCR_UFLEN; 360 allmulti: 361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 362 if ((ifp->if_flags & IFF_PROMISC) != 0) 363 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 364 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 365 hashes[0] = 0xFFFFFFFF; 366 hashes[1] = 0xFFFFFFFF; 367 } 368 } else { 369 /* First find the tail of the list. */ 370 ETHER_FIRST_MULTI(step, ec, enm); 371 while (enm != NULL) { 372 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 373 ETHER_ADDR_LEN)) { 374 ifp->if_flags |= IFF_ALLMULTI; 375 goto allmulti; 376 } 377 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 378 ((1 << HASH_BITS) - 1); 379 if (h < 32) 380 hashes[0] |= (1 << h); 381 else 382 hashes[1] |= (1 << (h - 32)); 383 384 ETHER_NEXT_MULTI(step, enm); 385 } 386 reg |= YU_RCR_MUFLEN; 387 } 388 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 394 } 395 396 void 397 msk_setpromisc(struct sk_if_softc *sc_if) 398 { 399 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 400 401 if (ifp->if_flags & IFF_PROMISC) 402 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 else 405 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 406 YU_RCR_UFLEN | YU_RCR_MUFLEN); 407 } 408 409 int 410 msk_init_rx_ring(struct sk_if_softc *sc_if) 411 { 412 struct msk_chain_data *cd = &sc_if->sk_cdata; 413 struct msk_ring_data *rd = sc_if->sk_rdata; 414 int i, nexti; 415 416 bzero((char *)rd->sk_rx_ring, 417 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 418 419 for (i = 0; i < MSK_RX_RING_CNT; i++) { 420 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 421 if (i == (MSK_RX_RING_CNT - 1)) 422 nexti = 0; 423 else 424 nexti = i + 1; 425 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 426 } 427 428 for (i = 0; i < MSK_RX_RING_CNT; i++) { 429 if (msk_newbuf(sc_if, i, NULL, 430 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 431 aprint_error("%s: failed alloc of %dth mbuf\n", 432 sc_if->sk_dev.dv_xname, i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 595 /* 596 * Now divide it up into 9K pieces and save the addresses 597 * in an array. 598 */ 599 ptr = sc_if->sk_cdata.sk_jumbo_buf; 600 for (i = 0; i < MSK_JSLOTS; i++) { 601 sc_if->sk_cdata.sk_jslots[i] = ptr; 602 ptr += SK_JLEN; 603 entry = malloc(sizeof(struct sk_jpool_entry), 604 M_DEVBUF, M_NOWAIT); 605 if (entry == NULL) { 606 sc_if->sk_cdata.sk_jumbo_buf = NULL; 607 aprint_error(": no memory for jumbo buffer queue!"); 608 error = ENOBUFS; 609 goto out; 610 } 611 entry->slot = i; 612 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 613 entry, jpool_entries); 614 } 615 out: 616 if (error != 0) { 617 switch (state) { 618 case 4: 619 bus_dmamap_unload(sc->sc_dmatag, 620 sc_if->sk_cdata.sk_rx_jumbo_map); 621 case 3: 622 bus_dmamap_destroy(sc->sc_dmatag, 623 sc_if->sk_cdata.sk_rx_jumbo_map); 624 case 2: 625 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 626 case 1: 627 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 628 break; 629 default: 630 break; 631 } 632 } 633 634 return (error); 635 } 636 637 /* 638 * Allocate a jumbo buffer. 639 */ 640 void * 641 msk_jalloc(struct sk_if_softc *sc_if) 642 { 643 struct sk_jpool_entry *entry; 644 645 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 646 647 if (entry == NULL) 648 return (NULL); 649 650 LIST_REMOVE(entry, jpool_entries); 651 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 652 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 void 659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 660 { 661 struct sk_jpool_entry *entry; 662 struct sk_if_softc *sc; 663 int i, s; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct sk_if_softc *)arg; 667 668 if (sc == NULL) 669 panic("msk_jfree: can't find softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 i = ((vaddr_t)buf 673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 674 675 if ((i < 0) || (i >= MSK_JSLOTS)) 676 panic("msk_jfree: asked to free buffer that we don't manage!"); 677 678 s = splvm(); 679 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 680 if (entry == NULL) 681 panic("msk_jfree: buffer not in use!"); 682 entry->slot = i; 683 LIST_REMOVE(entry, jpool_entries); 684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 685 686 if (__predict_true(m != NULL)) 687 pool_cache_put(mb_cache, m); 688 splx(s); 689 } 690 691 int 692 msk_ioctl(struct ifnet *ifp, u_long command, void *data) 693 { 694 struct sk_if_softc *sc_if = ifp->if_softc; 695 struct ifreq *ifr = (struct ifreq *) data; 696 int s, error = 0; 697 698 s = splnet(); 699 700 switch(command) { 701 case SIOCSIFMTU: 702 if (ifr->ifr_mtu < ETHERMIN) 703 return EINVAL; 704 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) { 705 if (ifr->ifr_mtu > SK_JUMBO_MTU) 706 error = EINVAL; 707 } else if (ifr->ifr_mtu > ETHERMTU) 708 error = EINVAL; 709 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET) 710 error = 0; 711 break; 712 default: 713 DPRINTFN(2, ("msk_ioctl ETHER\n")); 714 error = ether_ioctl(ifp, command, data); 715 716 if (error == ENETRESET) { 717 /* 718 * Multicast list has changed; set the hardware 719 * filter accordingly. 720 */ 721 if (ifp->if_flags & IFF_RUNNING) 722 msk_setmulti(sc_if); 723 error = 0; 724 } 725 break; 726 } 727 728 splx(s); 729 return (error); 730 } 731 732 void 733 msk_update_int_mod(struct sk_softc *sc) 734 { 735 u_int32_t imtimer_ticks; 736 737 /* 738 * Configure interrupt moderation. The moderation timer 739 * defers interrupts specified in the interrupt moderation 740 * timer mask based on the timeout specified in the interrupt 741 * moderation timer init register. Each bit in the timer 742 * register represents one tick, so to specify a timeout in 743 * microseconds, we have to multiply by the correct number of 744 * ticks-per-microsecond. 745 */ 746 switch (sc->sk_type) { 747 case SK_YUKON_EC: 748 case SK_YUKON_EC_U: 749 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 750 break; 751 case SK_YUKON_FE: 752 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 753 break; 754 case SK_YUKON_XL: 755 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 756 break; 757 default: 758 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 759 } 760 aprint_verbose("%s: interrupt moderation is %d us\n", 761 sc->sk_dev.dv_xname, sc->sk_int_mod); 762 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 763 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 764 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 765 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 766 sc->sk_int_mod_pending = 0; 767 } 768 769 static int 770 msk_lookup(const struct pci_attach_args *pa) 771 { 772 const struct msk_product *pmsk; 773 774 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 775 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 776 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 777 return 1; 778 } 779 return 0; 780 } 781 782 /* 783 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 784 * IDs against our list and return a device name if we find a match. 785 */ 786 int 787 mskc_probe(struct device *parent, struct cfdata *match, 788 void *aux) 789 { 790 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 791 792 return msk_lookup(pa); 793 } 794 795 /* 796 * Force the GEnesis into reset, then bring it out of reset. 797 */ 798 void msk_reset(struct sk_softc *sc) 799 { 800 u_int32_t imtimer_ticks, reg1; 801 int reg; 802 803 DPRINTFN(2, ("msk_reset\n")); 804 805 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 806 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 807 808 DELAY(1000); 809 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 810 DELAY(2); 811 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 812 sk_win_write_1(sc, SK_TESTCTL1, 2); 813 814 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 815 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 816 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 817 else 818 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 819 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 820 821 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 822 sk_win_write_1(sc, SK_Y2_CLKGATE, 823 SK_Y2_CLKGATE_LINK1_GATE_DIS | 824 SK_Y2_CLKGATE_LINK2_GATE_DIS | 825 SK_Y2_CLKGATE_LINK1_CORE_DIS | 826 SK_Y2_CLKGATE_LINK2_CORE_DIS | 827 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 828 else 829 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 830 831 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 832 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 833 DELAY(1000); 834 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 835 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 836 837 sk_win_write_1(sc, SK_TESTCTL1, 1); 838 839 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 840 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 841 CSR_READ_2(sc, SK_LINK_CTRL))); 842 843 /* Disable ASF */ 844 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 845 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 846 847 /* Clear I2C IRQ noise */ 848 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 849 850 /* Disable hardware timer */ 851 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 852 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 853 854 /* Disable descriptor polling */ 855 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 856 857 /* Disable time stamps */ 858 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 859 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 860 861 /* Enable RAM interface */ 862 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 863 for (reg = SK_TO0;reg <= SK_TO11; reg++) 864 sk_win_write_1(sc, reg, 36); 865 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 866 for (reg = SK_TO0;reg <= SK_TO11; reg++) 867 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 868 869 /* 870 * Configure interrupt moderation. The moderation timer 871 * defers interrupts specified in the interrupt moderation 872 * timer mask based on the timeout specified in the interrupt 873 * moderation timer init register. Each bit in the timer 874 * register represents one tick, so to specify a timeout in 875 * microseconds, we have to multiply by the correct number of 876 * ticks-per-microsecond. 877 */ 878 switch (sc->sk_type) { 879 case SK_YUKON_EC: 880 case SK_YUKON_EC_U: 881 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 882 break; 883 case SK_YUKON_FE: 884 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 885 break; 886 case SK_YUKON_XL: 887 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 888 break; 889 default: 890 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 891 } 892 893 /* Reset status ring. */ 894 bzero((char *)sc->sk_status_ring, 895 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 896 sc->sk_status_idx = 0; 897 898 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 899 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 900 901 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 902 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 903 sc->sk_status_map->dm_segs[0].ds_addr); 904 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 905 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 906 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 907 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 908 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 909 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 910 } else { 911 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 912 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 913 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 914 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 915 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 916 } 917 918 #if 0 919 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 920 #endif 921 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 922 923 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 924 925 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 926 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 927 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 928 929 msk_update_int_mod(sc); 930 } 931 932 int 933 msk_probe(struct device *parent, struct cfdata *match, 934 void *aux) 935 { 936 struct skc_attach_args *sa = aux; 937 938 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 939 return (0); 940 941 switch (sa->skc_type) { 942 case SK_YUKON_XL: 943 case SK_YUKON_EC_U: 944 case SK_YUKON_EC: 945 case SK_YUKON_FE: 946 return (1); 947 } 948 949 return (0); 950 } 951 952 /* 953 * Each XMAC chip is attached as a separate logical IP interface. 954 * Single port cards will have only one logical interface of course. 955 */ 956 void 957 msk_attach(struct device *parent, struct device *self, void *aux) 958 { 959 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 960 struct sk_softc *sc = (struct sk_softc *)parent; 961 struct skc_attach_args *sa = aux; 962 struct ifnet *ifp; 963 void *kva; 964 bus_dma_segment_t seg; 965 int i, rseg; 966 u_int32_t chunk, val; 967 968 sc_if->sk_port = sa->skc_port; 969 sc_if->sk_softc = sc; 970 sc->sk_if[sa->skc_port] = sc_if; 971 972 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 973 974 /* 975 * Get station address for this interface. Note that 976 * dual port cards actually come with three station 977 * addresses: one for each port, plus an extra. The 978 * extra one is used by the SysKonnect driver software 979 * as a 'virtual' station address for when both ports 980 * are operating in failover mode. Currently we don't 981 * use this extra address. 982 */ 983 for (i = 0; i < ETHER_ADDR_LEN; i++) 984 sc_if->sk_enaddr[i] = 985 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 986 987 aprint_normal(": Ethernet address %s\n", 988 ether_sprintf(sc_if->sk_enaddr)); 989 990 /* 991 * Set up RAM buffer addresses. The NIC will have a certain 992 * amount of SRAM on it, somewhere between 512K and 2MB. We 993 * need to divide this up a) between the transmitter and 994 * receiver and b) between the two XMACs, if this is a 995 * dual port NIC. Our algorithm is to divide up the memory 996 * evenly so that everyone gets a fair share. 997 * 998 * Just to be contrary, Yukon2 appears to have separate memory 999 * for each MAC. 1000 */ 1001 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1002 val = sc->sk_rboff / sizeof(u_int64_t); 1003 sc_if->sk_rx_ramstart = val; 1004 val += (chunk / sizeof(u_int64_t)); 1005 sc_if->sk_rx_ramend = val - 1; 1006 chunk = sc->sk_ramsize - chunk; 1007 sc_if->sk_tx_ramstart = val; 1008 val += (chunk / sizeof(u_int64_t)); 1009 sc_if->sk_tx_ramend = val - 1; 1010 1011 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1012 " tx_ramstart=%#x tx_ramend=%#x\n", 1013 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1014 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1015 1016 /* Allocate the descriptor queues. */ 1017 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1018 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1019 aprint_error(": can't alloc rx buffers\n"); 1020 goto fail; 1021 } 1022 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1023 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1024 aprint_error(": can't map dma buffers (%zu bytes)\n", 1025 sizeof(struct msk_ring_data)); 1026 goto fail_1; 1027 } 1028 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1029 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1030 &sc_if->sk_ring_map)) { 1031 aprint_error(": can't create dma map\n"); 1032 goto fail_2; 1033 } 1034 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1035 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1036 aprint_error(": can't load dma map\n"); 1037 goto fail_3; 1038 } 1039 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1040 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1041 1042 ifp = &sc_if->sk_ethercom.ec_if; 1043 /* Try to allocate memory for jumbo buffers. */ 1044 if (msk_alloc_jumbo_mem(sc_if)) { 1045 aprint_error(": jumbo buffer allocation failed\n"); 1046 goto fail_3; 1047 } 1048 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1049 | ETHERCAP_JUMBO_MTU; 1050 1051 ifp->if_softc = sc_if; 1052 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1053 ifp->if_ioctl = msk_ioctl; 1054 ifp->if_start = msk_start; 1055 ifp->if_stop = msk_stop; 1056 ifp->if_init = msk_init; 1057 ifp->if_watchdog = msk_watchdog; 1058 ifp->if_baudrate = 1000000000; 1059 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1060 IFQ_SET_READY(&ifp->if_snd); 1061 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1062 1063 /* 1064 * Do miibus setup. 1065 */ 1066 msk_init_yukon(sc_if); 1067 1068 DPRINTFN(2, ("msk_attach: 1\n")); 1069 1070 sc_if->sk_mii.mii_ifp = ifp; 1071 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1072 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1073 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1074 1075 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1076 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1077 ether_mediachange, ether_mediastatus); 1078 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1079 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1080 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1081 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1082 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1083 0, NULL); 1084 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1085 } else 1086 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1087 1088 callout_init(&sc_if->sk_tick_ch, 0); 1089 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1090 callout_schedule(&sc_if->sk_tick_ch, hz); 1091 1092 /* 1093 * Call MI attach routines. 1094 */ 1095 if_attach(ifp); 1096 ether_ifattach(ifp, sc_if->sk_enaddr); 1097 1098 shutdownhook_establish(mskc_shutdown, sc); 1099 1100 #if NRND > 0 1101 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1102 RND_TYPE_NET, 0); 1103 #endif 1104 1105 DPRINTFN(2, ("msk_attach: end\n")); 1106 return; 1107 1108 fail_3: 1109 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1110 fail_2: 1111 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1112 fail_1: 1113 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1114 fail: 1115 sc->sk_if[sa->skc_port] = NULL; 1116 } 1117 1118 int 1119 mskcprint(void *aux, const char *pnp) 1120 { 1121 struct skc_attach_args *sa = aux; 1122 1123 if (pnp) 1124 aprint_normal("sk port %c at %s", 1125 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1126 else 1127 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1128 return (UNCONF); 1129 } 1130 1131 /* 1132 * Attach the interface. Allocate softc structures, do ifmedia 1133 * setup and ethernet/BPF attach. 1134 */ 1135 void 1136 mskc_attach(struct device *parent, struct device *self, void *aux) 1137 { 1138 struct sk_softc *sc = (struct sk_softc *)self; 1139 struct pci_attach_args *pa = aux; 1140 struct skc_attach_args skca; 1141 pci_chipset_tag_t pc = pa->pa_pc; 1142 pcireg_t command, memtype; 1143 pci_intr_handle_t ih; 1144 const char *intrstr = NULL; 1145 bus_size_t size; 1146 int rc, sk_nodenum; 1147 u_int8_t hw, skrs; 1148 const char *revstr = NULL; 1149 const struct sysctlnode *node; 1150 void *kva; 1151 bus_dma_segment_t seg; 1152 int rseg; 1153 1154 DPRINTFN(2, ("begin mskc_attach\n")); 1155 1156 /* 1157 * Handle power management nonsense. 1158 */ 1159 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1160 1161 if (command == 0x01) { 1162 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1163 if (command & SK_PSTATE_MASK) { 1164 u_int32_t iobase, membase, irq; 1165 1166 /* Save important PCI config data. */ 1167 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1168 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1169 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1170 1171 /* Reset the power state. */ 1172 aprint_normal("%s chip is in D%d power mode " 1173 "-- setting to D0\n", sc->sk_dev.dv_xname, 1174 command & SK_PSTATE_MASK); 1175 command &= 0xFFFFFFFC; 1176 pci_conf_write(pc, pa->pa_tag, 1177 SK_PCI_PWRMGMTCTRL, command); 1178 1179 /* Restore PCI config data. */ 1180 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1181 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1182 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1183 } 1184 } 1185 1186 /* 1187 * Map control/status registers. 1188 */ 1189 1190 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1191 switch (memtype) { 1192 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1193 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1194 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1195 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1196 NULL, &size) == 0) 1197 break; 1198 default: 1199 aprint_error(": can't map mem space\n"); 1200 return; 1201 } 1202 1203 sc->sc_dmatag = pa->pa_dmat; 1204 1205 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1206 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1207 1208 /* bail out here if chip is not recognized */ 1209 if (!(SK_IS_YUKON2(sc))) { 1210 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1211 goto fail_1; 1212 } 1213 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1214 1215 /* Allocate interrupt */ 1216 if (pci_intr_map(pa, &ih)) { 1217 aprint_error(": couldn't map interrupt\n"); 1218 goto fail_1; 1219 } 1220 1221 intrstr = pci_intr_string(pc, ih); 1222 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1223 if (sc->sk_intrhand == NULL) { 1224 aprint_error(": couldn't establish interrupt"); 1225 if (intrstr != NULL) 1226 aprint_error(" at %s", intrstr); 1227 aprint_error("\n"); 1228 goto fail_1; 1229 } 1230 1231 if (bus_dmamem_alloc(sc->sc_dmatag, 1232 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1233 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1234 aprint_error(": can't alloc status buffers\n"); 1235 goto fail_2; 1236 } 1237 1238 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1239 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1240 &kva, BUS_DMA_NOWAIT)) { 1241 aprint_error(": can't map dma buffers (%zu bytes)\n", 1242 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1243 goto fail_3; 1244 } 1245 if (bus_dmamap_create(sc->sc_dmatag, 1246 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1247 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1248 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1249 aprint_error(": can't create dma map\n"); 1250 goto fail_4; 1251 } 1252 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1253 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1254 NULL, BUS_DMA_NOWAIT)) { 1255 aprint_error(": can't load dma map\n"); 1256 goto fail_5; 1257 } 1258 sc->sk_status_ring = (struct msk_status_desc *)kva; 1259 bzero(sc->sk_status_ring, 1260 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1261 1262 /* Reset the adapter. */ 1263 msk_reset(sc); 1264 1265 skrs = sk_win_read_1(sc, SK_EPROM0); 1266 if (skrs == 0x00) 1267 sc->sk_ramsize = 0x20000; 1268 else 1269 sc->sk_ramsize = skrs * (1<<12); 1270 sc->sk_rboff = SK_RBOFF_0; 1271 1272 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1273 sc->sk_ramsize, sc->sk_ramsize / 1024, 1274 sc->sk_rboff)); 1275 1276 switch (sc->sk_type) { 1277 case SK_YUKON_XL: 1278 sc->sk_name = "Yukon-2 XL"; 1279 break; 1280 case SK_YUKON_EC_U: 1281 sc->sk_name = "Yukon-2 EC Ultra"; 1282 break; 1283 case SK_YUKON_EC: 1284 sc->sk_name = "Yukon-2 EC"; 1285 break; 1286 case SK_YUKON_FE: 1287 sc->sk_name = "Yukon-2 FE"; 1288 break; 1289 default: 1290 sc->sk_name = "Yukon (Unknown)"; 1291 } 1292 1293 if (sc->sk_type == SK_YUKON_XL) { 1294 switch (sc->sk_rev) { 1295 case SK_YUKON_XL_REV_A0: 1296 sc->sk_workaround = 0; 1297 revstr = "A0"; 1298 break; 1299 case SK_YUKON_XL_REV_A1: 1300 sc->sk_workaround = SK_WA_4109; 1301 revstr = "A1"; 1302 break; 1303 case SK_YUKON_XL_REV_A2: 1304 sc->sk_workaround = SK_WA_4109; 1305 revstr = "A2"; 1306 break; 1307 case SK_YUKON_XL_REV_A3: 1308 sc->sk_workaround = SK_WA_4109; 1309 revstr = "A3"; 1310 break; 1311 default: 1312 sc->sk_workaround = 0; 1313 break; 1314 } 1315 } 1316 1317 if (sc->sk_type == SK_YUKON_EC) { 1318 switch (sc->sk_rev) { 1319 case SK_YUKON_EC_REV_A1: 1320 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1321 revstr = "A1"; 1322 break; 1323 case SK_YUKON_EC_REV_A2: 1324 sc->sk_workaround = SK_WA_4109; 1325 revstr = "A2"; 1326 break; 1327 case SK_YUKON_EC_REV_A3: 1328 sc->sk_workaround = SK_WA_4109; 1329 revstr = "A3"; 1330 break; 1331 default: 1332 sc->sk_workaround = 0; 1333 break; 1334 } 1335 } 1336 1337 if (sc->sk_type == SK_YUKON_FE) { 1338 sc->sk_workaround = SK_WA_4109; 1339 switch (sc->sk_rev) { 1340 case SK_YUKON_FE_REV_A1: 1341 revstr = "A1"; 1342 break; 1343 case SK_YUKON_FE_REV_A2: 1344 revstr = "A2"; 1345 break; 1346 default: 1347 sc->sk_workaround = 0; 1348 break; 1349 } 1350 } 1351 1352 if (sc->sk_type == SK_YUKON_EC_U) { 1353 sc->sk_workaround = SK_WA_4109; 1354 switch (sc->sk_rev) { 1355 case SK_YUKON_EC_U_REV_A0: 1356 revstr = "A0"; 1357 break; 1358 case SK_YUKON_EC_U_REV_A1: 1359 revstr = "A1"; 1360 break; 1361 case SK_YUKON_EC_U_REV_B0: 1362 revstr = "B0"; 1363 break; 1364 default: 1365 sc->sk_workaround = 0; 1366 break; 1367 } 1368 } 1369 1370 /* Announce the product name. */ 1371 aprint_normal(", %s", sc->sk_name); 1372 if (revstr != NULL) 1373 aprint_normal(" rev. %s", revstr); 1374 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1375 1376 sc->sk_macs = 1; 1377 1378 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1379 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1380 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1381 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1382 sc->sk_macs++; 1383 } 1384 1385 skca.skc_port = SK_PORT_A; 1386 skca.skc_type = sc->sk_type; 1387 skca.skc_rev = sc->sk_rev; 1388 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1389 1390 if (sc->sk_macs > 1) { 1391 skca.skc_port = SK_PORT_B; 1392 skca.skc_type = sc->sk_type; 1393 skca.skc_rev = sc->sk_rev; 1394 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1395 } 1396 1397 /* Turn on the 'driver is loaded' LED. */ 1398 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1399 1400 /* skc sysctl setup */ 1401 1402 sc->sk_int_mod = SK_IM_DEFAULT; 1403 sc->sk_int_mod_pending = 0; 1404 1405 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1406 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1407 SYSCTL_DESCR("mskc per-controller controls"), 1408 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1409 CTL_EOL)) != 0) { 1410 aprint_normal("%s: couldn't create sysctl node\n", 1411 sc->sk_dev.dv_xname); 1412 goto fail_6; 1413 } 1414 1415 sk_nodenum = node->sysctl_num; 1416 1417 /* interrupt moderation time in usecs */ 1418 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1419 CTLFLAG_READWRITE, 1420 CTLTYPE_INT, "int_mod", 1421 SYSCTL_DESCR("msk interrupt moderation timer"), 1422 msk_sysctl_handler, 0, sc, 1423 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1424 CTL_EOL)) != 0) { 1425 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1426 sc->sk_dev.dv_xname); 1427 goto fail_6; 1428 } 1429 1430 return; 1431 1432 fail_6: 1433 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1434 fail_5: 1435 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1436 fail_4: 1437 bus_dmamem_unmap(sc->sc_dmatag, kva, 1438 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1439 fail_3: 1440 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1441 fail_2: 1442 pci_intr_disestablish(pc, sc->sk_intrhand); 1443 fail_1: 1444 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1445 } 1446 1447 int 1448 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1449 { 1450 struct sk_softc *sc = sc_if->sk_softc; 1451 struct msk_tx_desc *f = NULL; 1452 u_int32_t frag, cur; 1453 int i; 1454 struct sk_txmap_entry *entry; 1455 bus_dmamap_t txmap; 1456 1457 DPRINTFN(2, ("msk_encap\n")); 1458 1459 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1460 if (entry == NULL) { 1461 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1462 return (ENOBUFS); 1463 } 1464 txmap = entry->dmamap; 1465 1466 cur = frag = *txidx; 1467 1468 #ifdef MSK_DEBUG 1469 if (mskdebug >= 2) 1470 msk_dump_mbuf(m_head); 1471 #endif 1472 1473 /* 1474 * Start packing the mbufs in this chain into 1475 * the fragment pointers. Stop when we run out 1476 * of fragments or hit the end of the mbuf chain. 1477 */ 1478 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1479 BUS_DMA_NOWAIT)) { 1480 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1481 return (ENOBUFS); 1482 } 1483 1484 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1485 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1486 bus_dmamap_unload(sc->sc_dmatag, txmap); 1487 return (ENOBUFS); 1488 } 1489 1490 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1491 1492 /* Sync the DMA map. */ 1493 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1494 BUS_DMASYNC_PREWRITE); 1495 1496 for (i = 0; i < txmap->dm_nsegs; i++) { 1497 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1498 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1499 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1500 f->sk_ctl = 0; 1501 if (i == 0) 1502 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1503 else 1504 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1505 cur = frag; 1506 SK_INC(frag, MSK_TX_RING_CNT); 1507 } 1508 1509 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1510 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1511 1512 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1513 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1514 1515 /* Sync descriptors before handing to chip */ 1516 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1517 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1518 1519 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1520 1521 /* Sync first descriptor to hand it off */ 1522 MSK_CDTXSYNC(sc_if, *txidx, 1, 1523 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1524 1525 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1526 1527 #ifdef MSK_DEBUG 1528 if (mskdebug >= 2) { 1529 struct msk_tx_desc *le; 1530 u_int32_t idx; 1531 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1532 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1533 msk_dump_txdesc(le, idx); 1534 } 1535 } 1536 #endif 1537 1538 *txidx = frag; 1539 1540 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1541 1542 return (0); 1543 } 1544 1545 void 1546 msk_start(struct ifnet *ifp) 1547 { 1548 struct sk_if_softc *sc_if = ifp->if_softc; 1549 struct mbuf *m_head = NULL; 1550 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1551 int pkts = 0; 1552 1553 DPRINTFN(2, ("msk_start\n")); 1554 1555 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1556 IFQ_POLL(&ifp->if_snd, m_head); 1557 if (m_head == NULL) 1558 break; 1559 1560 /* 1561 * Pack the data into the transmit ring. If we 1562 * don't have room, set the OACTIVE flag and wait 1563 * for the NIC to drain the ring. 1564 */ 1565 if (msk_encap(sc_if, m_head, &idx)) { 1566 ifp->if_flags |= IFF_OACTIVE; 1567 break; 1568 } 1569 1570 /* now we are committed to transmit the packet */ 1571 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1572 pkts++; 1573 1574 /* 1575 * If there's a BPF listener, bounce a copy of this frame 1576 * to him. 1577 */ 1578 #if NBPFILTER > 0 1579 if (ifp->if_bpf) 1580 bpf_mtap(ifp->if_bpf, m_head); 1581 #endif 1582 } 1583 if (pkts == 0) 1584 return; 1585 1586 /* Transmit */ 1587 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1588 sc_if->sk_cdata.sk_tx_prod = idx; 1589 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1590 1591 /* Set a timeout in case the chip goes out to lunch. */ 1592 ifp->if_timer = 5; 1593 } 1594 } 1595 1596 void 1597 msk_watchdog(struct ifnet *ifp) 1598 { 1599 struct sk_if_softc *sc_if = ifp->if_softc; 1600 u_int32_t reg; 1601 int idx; 1602 1603 /* 1604 * Reclaim first as there is a possibility of losing Tx completion 1605 * interrupts. 1606 */ 1607 if (sc_if->sk_port == SK_PORT_A) 1608 reg = SK_STAT_BMU_TXA1_RIDX; 1609 else 1610 reg = SK_STAT_BMU_TXA2_RIDX; 1611 1612 idx = sk_win_read_2(sc_if->sk_softc, reg); 1613 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1614 msk_txeof(sc_if, idx); 1615 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1616 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1617 1618 ifp->if_oerrors++; 1619 1620 /* XXX Resets both ports; we shouldn't do that. */ 1621 msk_reset(sc_if->sk_softc); 1622 msk_init(ifp); 1623 } 1624 } 1625 } 1626 1627 void 1628 mskc_shutdown(void *v) 1629 { 1630 struct sk_softc *sc = v; 1631 1632 DPRINTFN(2, ("msk_shutdown\n")); 1633 1634 /* Turn off the 'driver is loaded' LED. */ 1635 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1636 1637 msk_reset(sc); 1638 } 1639 1640 __inline int 1641 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1642 { 1643 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1644 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1645 YU_RXSTAT_JABBER)) != 0 || 1646 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1647 YU_RXSTAT_BYTES(stat) != len) 1648 return (0); 1649 1650 return (1); 1651 } 1652 1653 void 1654 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1655 { 1656 struct sk_softc *sc = sc_if->sk_softc; 1657 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1658 struct mbuf *m; 1659 struct sk_chain *cur_rx; 1660 int cur, total_len = len; 1661 bus_dmamap_t dmamap; 1662 1663 DPRINTFN(2, ("msk_rxeof\n")); 1664 1665 cur = sc_if->sk_cdata.sk_rx_cons; 1666 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1667 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1668 1669 /* Sync the descriptor */ 1670 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1671 1672 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1673 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1674 1675 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1676 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1677 1678 m = cur_rx->sk_mbuf; 1679 cur_rx->sk_mbuf = NULL; 1680 1681 if (total_len < SK_MIN_FRAMELEN || 1682 total_len > SK_JUMBO_FRAMELEN || 1683 msk_rxvalid(sc, rxstat, total_len) == 0) { 1684 ifp->if_ierrors++; 1685 msk_newbuf(sc_if, cur, m, dmamap); 1686 return; 1687 } 1688 1689 /* 1690 * Try to allocate a new jumbo buffer. If that fails, copy the 1691 * packet to mbufs and put the jumbo buffer back in the ring 1692 * so it can be re-used. If allocating mbufs fails, then we 1693 * have to drop the packet. 1694 */ 1695 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1696 struct mbuf *m0; 1697 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1698 total_len + ETHER_ALIGN, 0, ifp, NULL); 1699 msk_newbuf(sc_if, cur, m, dmamap); 1700 if (m0 == NULL) { 1701 ifp->if_ierrors++; 1702 return; 1703 } 1704 m_adj(m0, ETHER_ALIGN); 1705 m = m0; 1706 } else { 1707 m->m_pkthdr.rcvif = ifp; 1708 m->m_pkthdr.len = m->m_len = total_len; 1709 } 1710 1711 ifp->if_ipackets++; 1712 1713 #if NBPFILTER > 0 1714 if (ifp->if_bpf) 1715 bpf_mtap(ifp->if_bpf, m); 1716 #endif 1717 1718 /* pass it on. */ 1719 (*ifp->if_input)(ifp, m); 1720 } 1721 1722 void 1723 msk_txeof(struct sk_if_softc *sc_if, int idx) 1724 { 1725 struct sk_softc *sc = sc_if->sk_softc; 1726 struct msk_tx_desc *cur_tx; 1727 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1728 u_int32_t sk_ctl; 1729 struct sk_txmap_entry *entry; 1730 int cons, prog; 1731 1732 DPRINTFN(2, ("msk_txeof\n")); 1733 1734 /* 1735 * Go through our tx ring and free mbufs for those 1736 * frames that have been sent. 1737 */ 1738 cons = sc_if->sk_cdata.sk_tx_cons; 1739 prog = 0; 1740 while (cons != idx) { 1741 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1742 break; 1743 prog++; 1744 MSK_CDTXSYNC(sc_if, cons, 1, 1745 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1746 1747 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1748 sk_ctl = cur_tx->sk_ctl; 1749 #ifdef MSK_DEBUG 1750 if (mskdebug >= 2) 1751 msk_dump_txdesc(cur_tx, cons); 1752 #endif 1753 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1754 ifp->if_opackets++; 1755 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1756 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1757 1758 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1759 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1760 1761 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1762 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1763 link); 1764 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1765 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1766 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1767 } 1768 sc_if->sk_cdata.sk_tx_cnt--; 1769 SK_INC(cons, MSK_TX_RING_CNT); 1770 } 1771 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1772 1773 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1774 ifp->if_flags &= ~IFF_OACTIVE; 1775 1776 if (prog > 0) 1777 sc_if->sk_cdata.sk_tx_cons = cons; 1778 } 1779 1780 void 1781 msk_tick(void *xsc_if) 1782 { 1783 struct sk_if_softc *sc_if = xsc_if; 1784 struct mii_data *mii = &sc_if->sk_mii; 1785 1786 mii_tick(mii); 1787 callout_schedule(&sc_if->sk_tick_ch, hz); 1788 } 1789 1790 void 1791 msk_intr_yukon(struct sk_if_softc *sc_if) 1792 { 1793 u_int8_t status; 1794 1795 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1796 /* RX overrun */ 1797 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1798 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1799 SK_RFCTL_RX_FIFO_OVER); 1800 } 1801 /* TX underrun */ 1802 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1803 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1804 SK_TFCTL_TX_FIFO_UNDER); 1805 } 1806 1807 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1808 } 1809 1810 int 1811 msk_intr(void *xsc) 1812 { 1813 struct sk_softc *sc = xsc; 1814 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1815 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1816 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1817 int claimed = 0; 1818 u_int32_t status; 1819 struct msk_status_desc *cur_st; 1820 1821 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1822 if (status == 0) { 1823 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1824 return (0); 1825 } 1826 1827 status = CSR_READ_4(sc, SK_ISR); 1828 1829 if (sc_if0 != NULL) 1830 ifp0 = &sc_if0->sk_ethercom.ec_if; 1831 if (sc_if1 != NULL) 1832 ifp1 = &sc_if1->sk_ethercom.ec_if; 1833 1834 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1835 (ifp0->if_flags & IFF_RUNNING)) { 1836 msk_intr_yukon(sc_if0); 1837 } 1838 1839 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1840 (ifp1->if_flags & IFF_RUNNING)) { 1841 msk_intr_yukon(sc_if1); 1842 } 1843 1844 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1845 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1846 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1847 1848 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1849 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1850 switch (cur_st->sk_opcode) { 1851 case SK_Y2_STOPC_RXSTAT: 1852 msk_rxeof(sc->sk_if[cur_st->sk_link], 1853 letoh16(cur_st->sk_len), 1854 letoh32(cur_st->sk_status)); 1855 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1856 SK_RXQ1_Y2_PREF_PUTIDX, 1857 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1858 break; 1859 case SK_Y2_STOPC_TXSTAT: 1860 if (sc_if0) 1861 msk_txeof(sc_if0, 1862 letoh32(cur_st->sk_status) 1863 & SK_Y2_ST_TXA1_MSKL); 1864 if (sc_if1) 1865 msk_txeof(sc_if1, 1866 ((letoh32(cur_st->sk_status) 1867 & SK_Y2_ST_TXA2_MSKL) 1868 >> SK_Y2_ST_TXA2_SHIFTL) 1869 | ((letoh16(cur_st->sk_len) & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1870 break; 1871 default: 1872 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1873 break; 1874 } 1875 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1876 1877 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1878 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1879 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1880 } 1881 1882 if (status & SK_Y2_IMR_BMU) { 1883 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1884 claimed = 1; 1885 } 1886 1887 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1888 1889 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1890 msk_start(ifp0); 1891 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1892 msk_start(ifp1); 1893 1894 #if NRND > 0 1895 if (RND_ENABLED(&sc->rnd_source)) 1896 rnd_add_uint32(&sc->rnd_source, status); 1897 #endif 1898 1899 if (sc->sk_int_mod_pending) 1900 msk_update_int_mod(sc); 1901 1902 return claimed; 1903 } 1904 1905 void 1906 msk_init_yukon(struct sk_if_softc *sc_if) 1907 { 1908 u_int32_t v; 1909 u_int16_t reg; 1910 struct sk_softc *sc; 1911 int i; 1912 1913 sc = sc_if->sk_softc; 1914 1915 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1916 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1917 1918 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1919 1920 /* GMAC and GPHY Reset */ 1921 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1922 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1923 DELAY(1000); 1924 1925 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1926 1927 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1928 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1929 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1930 1931 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1932 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1933 1934 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1935 1936 /* unused read of the interrupt source register */ 1937 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1938 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1939 1940 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1941 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1942 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1943 1944 /* MIB Counter Clear Mode set */ 1945 reg |= YU_PAR_MIB_CLR; 1946 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1947 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1948 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1949 1950 /* MIB Counter Clear Mode clear */ 1951 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1952 reg &= ~YU_PAR_MIB_CLR; 1953 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1954 1955 /* receive control reg */ 1956 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1957 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1958 1959 /* transmit control register */ 1960 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1961 1962 /* transmit flow control register */ 1963 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 1964 1965 /* transmit parameter register */ 1966 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1967 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1968 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 1969 1970 /* serial mode register */ 1971 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1972 reg = YU_SMR_DATA_BLIND(0x1c) | 1973 YU_SMR_MFL_VLAN | 1974 YU_SMR_IPG_DATA(0x1e); 1975 1976 if (sc->sk_type != SK_YUKON_FE) 1977 reg |= YU_SMR_MFL_JUMBO; 1978 1979 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1980 1981 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1982 /* Setup Yukon's address */ 1983 for (i = 0; i < 3; i++) { 1984 /* Write Source Address 1 (unicast filter) */ 1985 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1986 sc_if->sk_enaddr[i * 2] | 1987 sc_if->sk_enaddr[i * 2 + 1] << 8); 1988 } 1989 1990 for (i = 0; i < 3; i++) { 1991 reg = sk_win_read_2(sc_if->sk_softc, 1992 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1993 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1994 } 1995 1996 /* Set promiscuous mode */ 1997 msk_setpromisc(sc_if); 1998 1999 /* Set multicast filter */ 2000 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2001 msk_setmulti(sc_if); 2002 2003 /* enable interrupt mask for counter overflows */ 2004 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2005 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2006 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2007 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2008 2009 /* Configure RX MAC FIFO Flush Mask */ 2010 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2011 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2012 YU_RXSTAT_JABBER; 2013 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2014 2015 /* Configure RX MAC FIFO */ 2016 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2017 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2018 SK_RFCTL_FIFO_FLUSH_ON); 2019 2020 /* Increase flush threshould to 64 bytes */ 2021 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2022 SK_RFCTL_FIFO_THRESHOLD + 1); 2023 2024 /* Configure TX MAC FIFO */ 2025 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2026 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2027 2028 #if 1 2029 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2030 #endif 2031 DPRINTFN(6, ("msk_init_yukon: end\n")); 2032 } 2033 2034 /* 2035 * Note that to properly initialize any part of the GEnesis chip, 2036 * you first have to take it out of reset mode. 2037 */ 2038 int 2039 msk_init(struct ifnet *ifp) 2040 { 2041 struct sk_if_softc *sc_if = ifp->if_softc; 2042 struct sk_softc *sc = sc_if->sk_softc; 2043 int rc = 0, s; 2044 uint32_t imr, imtimer_ticks; 2045 2046 2047 DPRINTFN(2, ("msk_init\n")); 2048 2049 s = splnet(); 2050 2051 /* Cancel pending I/O and free all RX/TX buffers. */ 2052 msk_stop(ifp,0); 2053 2054 /* Configure I2C registers */ 2055 2056 /* Configure XMAC(s) */ 2057 msk_init_yukon(sc_if); 2058 if ((rc = ether_mediachange(ifp)) != 0) 2059 goto out; 2060 2061 /* Configure transmit arbiter(s) */ 2062 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2063 #if 0 2064 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2065 #endif 2066 2067 /* Configure RAMbuffers */ 2068 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2069 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2070 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2071 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2072 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2073 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2074 2075 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2076 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2077 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2078 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2079 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2080 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2081 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2082 2083 /* Configure BMUs */ 2084 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2085 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2086 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2087 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2088 2089 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2090 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2091 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2092 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2093 2094 /* Make sure the sync transmit queue is disabled. */ 2095 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2096 2097 /* Init descriptors */ 2098 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2099 aprint_error("%s: initialization failed: no " 2100 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2101 msk_stop(ifp,0); 2102 splx(s); 2103 return ENOBUFS; 2104 } 2105 2106 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2107 aprint_error("%s: initialization failed: no " 2108 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2109 msk_stop(ifp,0); 2110 splx(s); 2111 return ENOBUFS; 2112 } 2113 2114 /* Set interrupt moderation if changed via sysctl. */ 2115 switch (sc->sk_type) { 2116 case SK_YUKON_EC: 2117 case SK_YUKON_EC_U: 2118 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2119 break; 2120 case SK_YUKON_FE: 2121 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2122 break; 2123 case SK_YUKON_XL: 2124 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2125 break; 2126 default: 2127 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2128 } 2129 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2130 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2131 sk_win_write_4(sc, SK_IMTIMERINIT, 2132 SK_IM_USECS(sc->sk_int_mod)); 2133 aprint_verbose("%s: interrupt moderation is %d us\n", 2134 sc->sk_dev.dv_xname, sc->sk_int_mod); 2135 } 2136 2137 /* Initialize prefetch engine. */ 2138 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2139 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2140 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2141 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2142 MSK_RX_RING_ADDR(sc_if, 0)); 2143 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2144 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2145 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2146 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2147 2148 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2150 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2151 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2152 MSK_TX_RING_ADDR(sc_if, 0)); 2153 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2154 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2155 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2156 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2157 2158 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2159 sc_if->sk_cdata.sk_rx_prod); 2160 2161 /* Configure interrupt handling */ 2162 if (sc_if->sk_port == SK_PORT_A) 2163 sc->sk_intrmask |= SK_Y2_INTRS1; 2164 else 2165 sc->sk_intrmask |= SK_Y2_INTRS2; 2166 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2167 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2168 2169 ifp->if_flags |= IFF_RUNNING; 2170 ifp->if_flags &= ~IFF_OACTIVE; 2171 2172 callout_schedule(&sc_if->sk_tick_ch, hz); 2173 2174 out: 2175 splx(s); 2176 return rc; 2177 } 2178 2179 void 2180 msk_stop(struct ifnet *ifp, int disable) 2181 { 2182 struct sk_if_softc *sc_if = ifp->if_softc; 2183 struct sk_softc *sc = sc_if->sk_softc; 2184 struct sk_txmap_entry *dma; 2185 int i; 2186 2187 DPRINTFN(2, ("msk_stop\n")); 2188 2189 callout_stop(&sc_if->sk_tick_ch); 2190 2191 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2192 2193 /* Stop transfer of Tx descriptors */ 2194 2195 /* Stop transfer of Rx descriptors */ 2196 2197 /* Turn off various components of this interface. */ 2198 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2199 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2200 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2201 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2202 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2203 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2204 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2205 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2206 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2207 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2208 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2209 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2210 2211 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2212 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2213 2214 /* Disable interrupts */ 2215 if (sc_if->sk_port == SK_PORT_A) 2216 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2217 else 2218 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2219 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2220 2221 SK_XM_READ_2(sc_if, XM_ISR); 2222 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2223 2224 /* Free RX and TX mbufs still in the queues. */ 2225 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2226 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2227 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2228 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2229 } 2230 } 2231 2232 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2233 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2234 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2235 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2236 #if 1 2237 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2238 sc_if->sk_cdata.sk_tx_map[i], link); 2239 sc_if->sk_cdata.sk_tx_map[i] = 0; 2240 #endif 2241 } 2242 } 2243 2244 #if 1 2245 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2246 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2247 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2248 free(dma, M_DEVBUF); 2249 } 2250 #endif 2251 } 2252 2253 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2254 NULL, NULL); 2255 2256 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2257 NULL, NULL); 2258 2259 #ifdef MSK_DEBUG 2260 void 2261 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2262 { 2263 #define DESC_PRINT(X) \ 2264 if (X) \ 2265 printf("txdesc[%d]." #X "=%#x\n", \ 2266 idx, X); 2267 2268 DESC_PRINT(letoh32(le->sk_addr)); 2269 DESC_PRINT(letoh16(le->sk_len)); 2270 DESC_PRINT(le->sk_ctl); 2271 DESC_PRINT(le->sk_opcode); 2272 #undef DESC_PRINT 2273 } 2274 2275 void 2276 msk_dump_bytes(const char *data, int len) 2277 { 2278 int c, i, j; 2279 2280 for (i = 0; i < len; i += 16) { 2281 printf("%08x ", i); 2282 c = len - i; 2283 if (c > 16) c = 16; 2284 2285 for (j = 0; j < c; j++) { 2286 printf("%02x ", data[i + j] & 0xff); 2287 if ((j & 0xf) == 7 && j > 0) 2288 printf(" "); 2289 } 2290 2291 for (; j < 16; j++) 2292 printf(" "); 2293 printf(" "); 2294 2295 for (j = 0; j < c; j++) { 2296 int ch = data[i + j] & 0xff; 2297 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2298 } 2299 2300 printf("\n"); 2301 2302 if (c < 16) 2303 break; 2304 } 2305 } 2306 2307 void 2308 msk_dump_mbuf(struct mbuf *m) 2309 { 2310 int count = m->m_pkthdr.len; 2311 2312 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2313 2314 while (count > 0 && m) { 2315 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2316 m, m->m_data, m->m_len); 2317 msk_dump_bytes(mtod(m, char *), m->m_len); 2318 2319 count -= m->m_len; 2320 m = m->m_next; 2321 } 2322 } 2323 #endif 2324 2325 static int 2326 msk_sysctl_handler(SYSCTLFN_ARGS) 2327 { 2328 int error, t; 2329 struct sysctlnode node; 2330 struct sk_softc *sc; 2331 2332 node = *rnode; 2333 sc = node.sysctl_data; 2334 t = sc->sk_int_mod; 2335 node.sysctl_data = &t; 2336 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2337 if (error || newp == NULL) 2338 return error; 2339 2340 if (t < SK_IM_MIN || t > SK_IM_MAX) 2341 return EINVAL; 2342 2343 /* update the softc with sysctl-changed value, and mark 2344 for hardware update */ 2345 sc->sk_int_mod = t; 2346 sc->sk_int_mod_pending = 1; 2347 return 0; 2348 } 2349 2350 /* 2351 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2352 * set up in skc_attach() 2353 */ 2354 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2355 { 2356 int rc; 2357 const struct sysctlnode *node; 2358 2359 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2360 0, CTLTYPE_NODE, "hw", NULL, 2361 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2362 goto err; 2363 } 2364 2365 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2366 0, CTLTYPE_NODE, "msk", 2367 SYSCTL_DESCR("msk interface controls"), 2368 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2369 goto err; 2370 } 2371 2372 msk_root_num = node->sysctl_num; 2373 return; 2374 2375 err: 2376 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2377 } 2378