1 /* $NetBSD: if_lii.c,v 1.18 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.18 2018/06/26 06:48:01 msaitoh Exp $"); 35 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/device.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/sockio.h> 44 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 49 #include <net/bpf.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/pci/if_liireg.h> 59 60 /* #define LII_DEBUG */ 61 #ifdef LII_DEBUG 62 #define DPRINTF(x) printf x 63 #else 64 #define DPRINTF(x) 65 #endif 66 67 struct lii_softc { 68 device_t sc_dev; 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_tag; 71 72 bus_space_tag_t sc_mmiot; 73 bus_space_handle_t sc_mmioh; 74 75 /* 76 * We allocate a big chunk of DMA-safe memory for all data exchanges. 77 * It is unfortunate that this chip doesn't seem to do scatter-gather. 78 */ 79 bus_dma_tag_t sc_dmat; 80 bus_dmamap_t sc_ringmap; 81 bus_dma_segment_t sc_ringseg; 82 83 uint8_t *sc_ring; /* the whole area */ 84 size_t sc_ringsize; 85 86 struct rx_pkt *sc_rxp; /* the part used for RX */ 87 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 88 bus_addr_t sc_txsp; 89 char *sc_txdbase; 90 bus_addr_t sc_txdp; 91 92 unsigned int sc_rxcur; 93 /* the active area is [ack; cur[ */ 94 int sc_txs_cur; 95 int sc_txs_ack; 96 int sc_txd_cur; 97 int sc_txd_ack; 98 bool sc_free_tx_slots; 99 100 void *sc_ih; 101 102 struct ethercom sc_ec; 103 struct mii_data sc_mii; 104 callout_t sc_tick_ch; 105 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 106 107 int (*sc_memread)(struct lii_softc *, uint32_t, 108 uint32_t *); 109 }; 110 111 static int lii_match(device_t, cfdata_t, void *); 112 static void lii_attach(device_t, device_t, void *); 113 114 static int lii_reset(struct lii_softc *); 115 static bool lii_eeprom_present(struct lii_softc *); 116 static int lii_read_macaddr(struct lii_softc *, uint8_t *); 117 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 118 static void lii_spi_configure(struct lii_softc *); 119 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 120 static void lii_setmulti(struct lii_softc *); 121 static void lii_tick(void *); 122 123 static int lii_alloc_rings(struct lii_softc *); 124 static int lii_free_tx_space(struct lii_softc *); 125 126 static int lii_mii_readreg(device_t, int, int); 127 static void lii_mii_writereg(device_t, int, int, int); 128 static void lii_mii_statchg(struct ifnet *); 129 130 static int lii_media_change(struct ifnet *); 131 static void lii_media_status(struct ifnet *, struct ifmediareq *); 132 133 static int lii_init(struct ifnet *); 134 static void lii_start(struct ifnet *); 135 static void lii_stop(struct ifnet *, int); 136 static void lii_watchdog(struct ifnet *); 137 static int lii_ioctl(struct ifnet *, u_long, void *); 138 139 static int lii_intr(void *); 140 static void lii_rxintr(struct lii_softc *); 141 static void lii_txintr(struct lii_softc *); 142 143 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 144 lii_match, lii_attach, NULL, NULL); 145 146 /* #define LII_DEBUG_REGS */ 147 #ifndef LII_DEBUG_REGS 148 #define AT_READ_4(sc,reg) \ 149 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 150 #define AT_READ_2(sc,reg) \ 151 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 152 #define AT_READ_1(sc,reg) \ 153 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 154 #define AT_WRITE_4(sc,reg,val) \ 155 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 156 #define AT_WRITE_2(sc,reg,val) \ 157 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 158 #define AT_WRITE_1(sc,reg,val) \ 159 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 160 #else 161 static inline uint32_t 162 AT_READ_4(struct lii_softc *sc, bus_size_t reg) 163 { 164 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 165 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 166 return r; 167 } 168 169 static inline uint16_t 170 AT_READ_2(struct lii_softc *sc, bus_size_t reg) 171 { 172 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 173 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 174 return r; 175 } 176 177 static inline uint8_t 178 AT_READ_1(struct lii_softc *sc, bus_size_t reg) 179 { 180 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 181 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 182 return r; 183 } 184 185 static inline void 186 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 187 { 188 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 189 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 190 } 191 192 static inline void 193 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 194 { 195 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 196 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 197 } 198 199 static inline void 200 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 201 { 202 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 203 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 204 } 205 #endif 206 207 /* 208 * Those are the default Linux parameters. 209 */ 210 211 #define AT_TXD_NUM 64 212 #define AT_TXD_BUFFER_SIZE 8192 213 #define AT_RXD_NUM 64 214 215 /* 216 * Assuming (you know what that word makes of you) the chunk of memory 217 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 218 * first 120 bytes of it, so that the space for the packets, and not the 219 * whole descriptors themselves, are on a 128-byte boundary. 220 */ 221 222 #define AT_RXD_PADDING 120 223 224 static int 225 lii_match(device_t parent, cfdata_t cfmatch, void *aux) 226 { 227 struct pci_attach_args *pa = aux; 228 229 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 231 } 232 233 static void 234 lii_attach(device_t parent, device_t self, void *aux) 235 { 236 struct lii_softc *sc = device_private(self); 237 struct pci_attach_args *pa = aux; 238 uint8_t eaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp = &sc->sc_ec.ec_if; 240 pci_intr_handle_t ih; 241 const char *intrstr; 242 pcireg_t cmd; 243 bus_size_t memsize = 0; 244 char intrbuf[PCI_INTRSTR_LEN]; 245 246 aprint_naive("\n"); 247 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 248 249 sc->sc_dev = self; 250 sc->sc_pc = pa->pa_pc; 251 sc->sc_tag = pa->pa_tag; 252 sc->sc_dmat = pa->pa_dmat; 253 254 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 255 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 256 cmd &= ~PCI_COMMAND_IO_ENABLE; 257 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 258 259 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 260 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 261 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 262 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 263 break; 264 default: 265 aprint_error_dev(self, "invalid base address register\n"); 266 break; 267 } 268 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 269 &sc->sc_mmiot, &sc->sc_mmioh, NULL, &memsize) != 0) { 270 aprint_error_dev(self, "failed to map registers\n"); 271 return; 272 } 273 274 if (lii_reset(sc)) 275 return; 276 277 lii_spi_configure(sc); 278 279 if (lii_eeprom_present(sc)) 280 sc->sc_memread = lii_eeprom_read; 281 else 282 sc->sc_memread = lii_spi_read; 283 284 if (lii_read_macaddr(sc, eaddr)) 285 return; 286 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 287 288 aprint_normal_dev(self, "Ethernet address %s\n", 289 ether_sprintf(eaddr)); 290 291 if (pci_intr_map(pa, &ih) != 0) { 292 aprint_error_dev(self, "failed to map interrupt\n"); 293 goto fail; 294 } 295 intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf)); 296 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 297 if (sc->sc_ih == NULL) { 298 aprint_error_dev(self, "failed to establish interrupt"); 299 if (intrstr != NULL) 300 aprint_error(" at %s", intrstr); 301 aprint_error("\n"); 302 goto fail; 303 } 304 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 305 306 if (lii_alloc_rings(sc)) 307 goto fail; 308 309 callout_init(&sc->sc_tick_ch, 0); 310 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 311 312 sc->sc_mii.mii_ifp = ifp; 313 sc->sc_mii.mii_readreg = lii_mii_readreg; 314 sc->sc_mii.mii_writereg = lii_mii_writereg; 315 sc->sc_mii.mii_statchg = lii_mii_statchg; 316 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 317 lii_media_status); 318 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 319 MII_OFFSET_ANY, 0); 320 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 321 322 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 323 ifp->if_softc = sc; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_ioctl = lii_ioctl; 326 ifp->if_start = lii_start; 327 ifp->if_watchdog = lii_watchdog; 328 ifp->if_init = lii_init; 329 ifp->if_stop = lii_stop; 330 IFQ_SET_READY(&ifp->if_snd); 331 332 /* 333 * While the device does support HW VLAN tagging, there is no 334 * real point using that feature. 335 */ 336 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 337 338 if_attach(ifp); 339 if_deferred_start_init(ifp, NULL); 340 ether_ifattach(ifp, eaddr); 341 342 if (pmf_device_register(self, NULL, NULL)) 343 pmf_class_network_register(self, ifp); 344 else 345 aprint_error_dev(self, "couldn't establish power handler\n"); 346 347 return; 348 349 fail: 350 if (sc->sc_ih != NULL) { 351 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 352 sc->sc_ih = NULL; 353 } 354 if (memsize) 355 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, memsize); 356 } 357 358 static int 359 lii_reset(struct lii_softc *sc) 360 { 361 int i; 362 363 DPRINTF(("lii_reset\n")); 364 365 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 366 DELAY(1000); 367 368 for (i = 0; i < 10; ++i) { 369 if (AT_READ_4(sc, ATL2_BIS) == 0) 370 break; 371 DELAY(1000); 372 } 373 374 if (i == 10) { 375 aprint_error_dev(sc->sc_dev, "reset failed\n"); 376 return 1; 377 } 378 379 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 380 DELAY(10); 381 382 /* Init PCI-Express module */ 383 /* Magic Numbers Warning */ 384 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 385 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 386 387 return 0; 388 } 389 390 static bool 391 lii_eeprom_present(struct lii_softc *sc) 392 { 393 /* 394 * The Linux driver does this, but then it has a very weird way of 395 * checking whether the PCI configuration space exposes the Vital 396 * Product Data capability, so maybe it's not really needed. 397 */ 398 399 #ifdef weirdloonix 400 uint32_t val; 401 402 val = AT_READ_4(sc, ATL2_SFC); 403 if (val & SFC_EN_VPD) 404 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 405 #endif 406 407 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 408 NULL, NULL) == 1; 409 } 410 411 static int 412 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 413 { 414 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 415 416 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 417 418 return r; 419 } 420 421 static void 422 lii_spi_configure(struct lii_softc *sc) 423 { 424 /* 425 * We don't offer a way to configure the SPI Flash vendor parameter, so 426 * the table is given for reference 427 */ 428 static const struct lii_spi_flash_vendor { 429 const char *sfv_name; 430 const uint8_t sfv_opcodes[9]; 431 } lii_sfv[] = { 432 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 433 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 434 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 435 }; 436 #define SF_OPCODE_WRSR 0 437 #define SF_OPCODE_READ 1 438 #define SF_OPCODE_PRGM 2 439 #define SF_OPCODE_WREN 3 440 #define SF_OPCODE_WRDI 4 441 #define SF_OPCODE_RDSR 5 442 #define SF_OPCODE_RDID 6 443 #define SF_OPCODE_SECT_ER 7 444 #define SF_OPCODE_CHIP_ER 8 445 446 #define SF_DEFAULT_VENDOR 0 447 static const uint8_t vendor = SF_DEFAULT_VENDOR; 448 449 /* 450 * Why isn't WRDI used? Heck if I know. 451 */ 452 453 AT_WRITE_1(sc, ATL2_SFOP_WRSR, 454 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 455 AT_WRITE_1(sc, ATL2_SFOP_READ, 456 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 457 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 458 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 459 AT_WRITE_1(sc, ATL2_SFOP_WREN, 460 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 461 AT_WRITE_1(sc, ATL2_SFOP_RDSR, 462 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 463 AT_WRITE_1(sc, ATL2_SFOP_RDID, 464 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 465 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 466 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 467 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 468 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 469 } 470 471 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 472 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 473 << SFC_CS_SETUP_SHIFT) \ 474 | (((clkhi) & SFC_CLK_HI_MASK) \ 475 << SFC_CLK_HI_SHIFT) \ 476 | (((clklo) & SFC_CLK_LO_MASK) \ 477 << SFC_CLK_LO_SHIFT) \ 478 | (((cshold) & SFC_CS_HOLD_MASK) \ 479 << SFC_CS_HOLD_SHIFT) \ 480 | (((cshi) & SFC_CS_HI_MASK) \ 481 << SFC_CS_HI_SHIFT) \ 482 | (((ins) & SFC_INS_MASK) \ 483 << SFC_INS_SHIFT)) 484 485 /* Magic settings from the Linux driver */ 486 487 #define CUSTOM_SPI_CS_SETUP 2 488 #define CUSTOM_SPI_CLK_HI 2 489 #define CUSTOM_SPI_CLK_LO 2 490 #define CUSTOM_SPI_CS_HOLD 2 491 #define CUSTOM_SPI_CS_HI 3 492 493 static int 494 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 495 { 496 uint32_t v; 497 int i; 498 499 AT_WRITE_4(sc, ATL2_SF_DATA, 0); 500 AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 501 502 v = SFC_WAIT_READY | 503 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 504 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 505 506 AT_WRITE_4(sc, ATL2_SFC, v); 507 v |= SFC_START; 508 AT_WRITE_4(sc, ATL2_SFC, v); 509 510 for (i = 0; i < 10; ++i) { 511 DELAY(1000); 512 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 513 break; 514 } 515 if (i == 10) 516 return EBUSY; 517 518 *val = AT_READ_4(sc, ATL2_SF_DATA); 519 return 0; 520 } 521 522 static int 523 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 524 { 525 uint32_t offset = 0x100; 526 uint32_t val, val1, addr0 = 0, addr1 = 0; 527 uint8_t found = 0; 528 529 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 530 offset += 4; 531 532 /* Each chunk of data starts with a signature */ 533 if ((val & 0xff) != 0x5a) 534 break; 535 if ((*sc->sc_memread)(sc, offset, &val1)) 536 break; 537 538 offset += 4; 539 540 val >>= 16; 541 switch (val) { 542 case ATL2_MAC_ADDR_0: 543 addr0 = val1; 544 ++found; 545 break; 546 case ATL2_MAC_ADDR_1: 547 addr1 = val1; 548 ++found; 549 break; 550 default: 551 continue; 552 } 553 } 554 555 if (found < 2) { 556 /* Make sure we try the BIOS method before giving up */ 557 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 558 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 559 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 560 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 561 aprint_error_dev(sc->sc_dev, 562 "error reading MAC address\n"); 563 return 1; 564 } 565 } else { 566 addr0 = htole32(addr0); 567 addr1 = htole32(addr1); 568 } 569 570 ea[0] = (addr1 & 0x0000ff00) >> 8; 571 ea[1] = (addr1 & 0x000000ff); 572 ea[2] = (addr0 & 0xff000000) >> 24; 573 ea[3] = (addr0 & 0x00ff0000) >> 16; 574 ea[4] = (addr0 & 0x0000ff00) >> 8; 575 ea[5] = (addr0 & 0x000000ff); 576 577 return 0; 578 } 579 580 static int 581 lii_mii_readreg(device_t dev, int phy, int reg) 582 { 583 struct lii_softc *sc = device_private(dev); 584 uint32_t val; 585 int i; 586 587 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 588 589 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 590 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 591 592 val |= MDIOC_READ; 593 594 AT_WRITE_4(sc, ATL2_MDIOC, val); 595 596 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 597 DELAY(2); 598 val = AT_READ_4(sc, ATL2_MDIOC); 599 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 600 break; 601 } 602 603 if (i == MDIO_WAIT_TIMES) 604 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 605 reg); 606 607 return (val & 0x0000ffff); 608 } 609 610 static void 611 lii_mii_writereg(device_t dev, int phy, int reg, int data) 612 { 613 struct lii_softc *sc = device_private(dev); 614 uint32_t val; 615 int i; 616 617 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 618 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 619 620 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 621 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 622 623 /* val |= MDIOC_WRITE; */ 624 625 AT_WRITE_4(sc, ATL2_MDIOC, val); 626 627 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 628 DELAY(2); 629 val = AT_READ_4(sc, ATL2_MDIOC); 630 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 631 break; 632 } 633 634 if (i == MDIO_WAIT_TIMES) 635 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 636 reg); 637 } 638 639 static void 640 lii_mii_statchg(struct ifnet *ifp) 641 { 642 struct lii_softc *sc = ifp->if_softc; 643 uint32_t val; 644 645 DPRINTF(("lii_mii_statchg\n")); 646 647 val = AT_READ_4(sc, ATL2_MACC); 648 649 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 650 val |= MACC_FDX; 651 else 652 val &= ~MACC_FDX; 653 654 AT_WRITE_4(sc, ATL2_MACC, val); 655 } 656 657 static int 658 lii_media_change(struct ifnet *ifp) 659 { 660 struct lii_softc *sc = ifp->if_softc; 661 662 DPRINTF(("lii_media_change\n")); 663 664 if (ifp->if_flags & IFF_UP) 665 mii_mediachg(&sc->sc_mii); 666 return 0; 667 } 668 669 static void 670 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 671 { 672 struct lii_softc *sc = ifp->if_softc; 673 674 DPRINTF(("lii_media_status\n")); 675 676 mii_pollstat(&sc->sc_mii); 677 imr->ifm_status = sc->sc_mii.mii_media_status; 678 imr->ifm_active = sc->sc_mii.mii_media_active; 679 } 680 681 static int 682 lii_init(struct ifnet *ifp) 683 { 684 struct lii_softc *sc = ifp->if_softc; 685 uint32_t val; 686 int error; 687 688 DPRINTF(("lii_init\n")); 689 690 lii_stop(ifp, 0); 691 692 memset(sc->sc_ring, 0, sc->sc_ringsize); 693 694 /* Disable all interrupts */ 695 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 696 697 /* XXX endianness */ 698 AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 699 sc->sc_eaddr[2] << 24 | 700 sc->sc_eaddr[3] << 16 | 701 sc->sc_eaddr[4] << 8 | 702 sc->sc_eaddr[5]); 703 AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 704 sc->sc_eaddr[0] << 8 | 705 sc->sc_eaddr[1]); 706 707 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 708 /* XXX 709 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 710 */ 711 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 712 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 713 + AT_RXD_PADDING); 714 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 715 sc->sc_txsp & 0xffffffff); 716 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 717 sc->sc_txdp & 0xffffffff); 718 719 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 720 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 721 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 722 723 /* 724 * Inter Paket Gap Time = 0x60 (IPGT) 725 * Minimum inter-frame gap for RX = 0x50 (MIFG) 726 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 727 * 96-bit IPG window = 0x60 (IPGR2) 728 */ 729 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 730 731 /* 732 * Collision window = 0x37 (LCOL) 733 * Maximum # of retrans = 0xf (RETRY) 734 * Maximum binary expansion # = 0xa (ABEBT) 735 * IPG to start jam = 0x7 (JAMIPG) 736 */ 737 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 738 MHDC_EXC_DEF_EN); 739 740 /* 100 means 200us */ 741 AT_WRITE_2(sc, ATL2_IMTIV, 100); 742 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 743 744 /* 500000 means 100ms */ 745 AT_WRITE_2(sc, ATL2_IALTIV, 50000); 746 747 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 748 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 749 750 /* unit unknown for TX cur-through threshold */ 751 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 752 753 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 754 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 755 756 sc->sc_rxcur = 0; 757 sc->sc_txs_cur = sc->sc_txs_ack = 0; 758 sc->sc_txd_cur = sc->sc_txd_ack = 0; 759 sc->sc_free_tx_slots = true; 760 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 761 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 762 763 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 764 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 765 766 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 767 768 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 769 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 770 AT_WRITE_4(sc, ATL2_ISR, 0); 771 if (error) { 772 aprint_error_dev(sc->sc_dev, "init failed\n"); 773 goto out; 774 } 775 776 lii_setmulti(sc); 777 778 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 779 780 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 781 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 782 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 783 784 if (ifp->if_flags & IFF_PROMISC) 785 val |= MACC_PROMISC_EN; 786 else if (ifp->if_flags & IFF_ALLMULTI) 787 val |= MACC_ALLMULTI_EN; 788 789 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 790 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 791 792 AT_WRITE_4(sc, ATL2_MACC, val); 793 794 mii_mediachg(&sc->sc_mii); 795 796 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 797 798 callout_schedule(&sc->sc_tick_ch, hz); 799 800 ifp->if_flags |= IFF_RUNNING; 801 ifp->if_flags &= ~IFF_OACTIVE; 802 803 out: 804 return error; 805 } 806 807 static void 808 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 809 { 810 int left; 811 struct tx_pkt_header *tph = 812 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 813 814 memset(tph, 0, sizeof *tph); 815 tph->txph_size = m->m_pkthdr.len; 816 817 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 818 819 /* 820 * We already know we have enough space, so if there is a part of the 821 * space ahead of txd_cur that is active, it doesn't matter because 822 * left will be large enough even without it. 823 */ 824 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 825 826 if (left > m->m_pkthdr.len) { 827 m_copydata(m, 0, m->m_pkthdr.len, 828 sc->sc_txdbase + sc->sc_txd_cur); 829 sc->sc_txd_cur += m->m_pkthdr.len; 830 } else { 831 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 832 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 833 sc->sc_txd_cur = m->m_pkthdr.len - left; 834 } 835 836 /* Round to a 32-bit boundary */ 837 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 838 if (sc->sc_txd_cur == sc->sc_txd_ack) 839 sc->sc_free_tx_slots = false; 840 } 841 842 static int 843 lii_free_tx_space(struct lii_softc *sc) 844 { 845 int space; 846 847 if (sc->sc_txd_cur >= sc->sc_txd_ack) 848 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 849 sc->sc_txd_ack; 850 else 851 space = sc->sc_txd_ack - sc->sc_txd_cur; 852 853 /* Account for the tx_pkt_header */ 854 return (space - 4); 855 } 856 857 static void 858 lii_start(struct ifnet *ifp) 859 { 860 struct lii_softc *sc = ifp->if_softc; 861 struct mbuf *m0; 862 863 DPRINTF(("lii_start\n")); 864 865 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 866 return; 867 868 for (;;) { 869 IFQ_POLL(&ifp->if_snd, m0); 870 if (m0 == NULL) 871 break; 872 873 if (!sc->sc_free_tx_slots || 874 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 875 ifp->if_flags |= IFF_OACTIVE; 876 break; 877 } 878 879 lii_tx_put(sc, m0); 880 881 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 882 883 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 884 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 885 if (sc->sc_txs_cur == sc->sc_txs_ack) 886 sc->sc_free_tx_slots = false; 887 888 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 889 890 IFQ_DEQUEUE(&ifp->if_snd, m0); 891 892 bpf_mtap(ifp, m0, BPF_D_OUT); 893 m_freem(m0); 894 } 895 } 896 897 static void 898 lii_stop(struct ifnet *ifp, int disable) 899 { 900 struct lii_softc *sc = ifp->if_softc; 901 902 callout_stop(&sc->sc_tick_ch); 903 904 ifp->if_timer = 0; 905 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 906 907 mii_down(&sc->sc_mii); 908 909 lii_reset(sc); 910 911 AT_WRITE_4(sc, ATL2_IMR, 0); 912 } 913 914 static int 915 lii_intr(void *v) 916 { 917 struct lii_softc *sc = v; 918 uint32_t status; 919 920 status = AT_READ_4(sc, ATL2_ISR); 921 if (status == 0) 922 return 0; 923 924 DPRINTF(("lii_intr (%x)\n", status)); 925 926 /* Clear the interrupt and disable them */ 927 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 928 929 if (status & (ISR_PHY | ISR_MANUAL)) { 930 /* Ack PHY interrupt. Magic register */ 931 if (status & ISR_PHY) 932 (void)lii_mii_readreg(sc->sc_dev, 1, 19); 933 mii_mediachg(&sc->sc_mii); 934 } 935 936 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 937 lii_init(&sc->sc_ec.ec_if); 938 return 1; 939 } 940 941 if (status & ISR_RX_EVENT) { 942 #ifdef LII_DEBUG 943 if (!(status & ISR_RS_UPDATE)) 944 printf("rxintr %08x\n", status); 945 #endif 946 lii_rxintr(sc); 947 } 948 949 if (status & ISR_TX_EVENT) 950 lii_txintr(sc); 951 952 /* Re-enable interrupts */ 953 AT_WRITE_4(sc, ATL2_ISR, 0); 954 955 return 1; 956 } 957 958 static void 959 lii_rxintr(struct lii_softc *sc) 960 { 961 struct ifnet *ifp = &sc->sc_ec.ec_if; 962 struct rx_pkt *rxp; 963 struct mbuf *m; 964 uint16_t size; 965 966 DPRINTF(("lii_rxintr\n")); 967 968 for (;;) { 969 rxp = &sc->sc_rxp[sc->sc_rxcur]; 970 if (rxp->rxp_update == 0) 971 break; 972 973 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 974 rxp->rxp_size, rxp->rxp_flags)); 975 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 976 rxp->rxp_update = 0; 977 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 978 ++ifp->if_ierrors; 979 continue; 980 } 981 982 MGETHDR(m, M_DONTWAIT, MT_DATA); 983 if (m == NULL) { 984 ++ifp->if_ierrors; 985 continue; 986 } 987 size = rxp->rxp_size - ETHER_CRC_LEN; 988 if (size > MHLEN) { 989 MCLGET(m, M_DONTWAIT); 990 if ((m->m_flags & M_EXT) == 0) { 991 m_freem(m); 992 ++ifp->if_ierrors; 993 continue; 994 } 995 } 996 997 m_set_rcvif(m, ifp); 998 /* Copy the packet withhout the FCS */ 999 m->m_pkthdr.len = m->m_len = size; 1000 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 1001 1002 if_percpuq_enqueue(ifp->if_percpuq, m); 1003 } 1004 1005 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1006 } 1007 1008 static void 1009 lii_txintr(struct lii_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->sc_ec.ec_if; 1012 struct tx_pkt_status *txs; 1013 struct tx_pkt_header *txph; 1014 1015 DPRINTF(("lii_txintr\n")); 1016 1017 for (;;) { 1018 txs = &sc->sc_txs[sc->sc_txs_ack]; 1019 if (txs->txps_update == 0) 1020 break; 1021 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1022 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1023 sc->sc_free_tx_slots = true; 1024 1025 txs->txps_update = 0; 1026 1027 txph = (struct tx_pkt_header *) 1028 (sc->sc_txdbase + sc->sc_txd_ack); 1029 1030 if (txph->txph_size != txs->txps_size) 1031 aprint_error_dev(sc->sc_dev, 1032 "mismatched status and packet\n"); 1033 /* 1034 * Move ack by the packet size, taking the packet header in 1035 * account and round to the next 32-bit boundary 1036 * (7 = sizeof(header) + 3) 1037 */ 1038 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1039 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1040 1041 if (txs->txps_flags & ATL2_TXF_SUCCESS) 1042 ++ifp->if_opackets; 1043 else 1044 ++ifp->if_oerrors; 1045 ifp->if_flags &= ~IFF_OACTIVE; 1046 } 1047 1048 if (sc->sc_free_tx_slots) 1049 if_schedule_deferred_start(ifp); 1050 } 1051 1052 static int 1053 lii_alloc_rings(struct lii_softc *sc) 1054 { 1055 int nsegs; 1056 bus_size_t bs; 1057 1058 /* 1059 * We need a big chunk of DMA-friendly memory because descriptors 1060 * are not separate from data on that crappy hardware, which means 1061 * we'll have to copy data from and to that memory zone to and from 1062 * the mbufs. 1063 * 1064 * How lame is that? Using the default values from the Linux driver, 1065 * we allocate space for receiving up to 64 full-size Ethernet frames, 1066 * and only 8kb for transmitting up to 64 Ethernet frames. 1067 */ 1068 1069 sc->sc_ringsize = bs = AT_RXD_PADDING 1070 + AT_RXD_NUM * sizeof(struct rx_pkt) 1071 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1072 + AT_TXD_BUFFER_SIZE; 1073 1074 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1075 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1076 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1077 return 1; 1078 } 1079 1080 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1081 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1082 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1083 goto fail; 1084 } 1085 1086 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1087 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1088 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1089 goto fail1; 1090 } 1091 1092 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1093 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1094 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1095 goto fail2; 1096 } 1097 1098 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1099 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1100 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1101 sc->sc_txdbase = ((char *)sc->sc_txs) 1102 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1103 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1104 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1105 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1106 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1107 1108 return 0; 1109 1110 fail2: 1111 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1112 fail1: 1113 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1114 fail: 1115 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1116 return 1; 1117 } 1118 1119 static void 1120 lii_watchdog(struct ifnet *ifp) 1121 { 1122 struct lii_softc *sc = ifp->if_softc; 1123 1124 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1125 ++ifp->if_oerrors; 1126 lii_init(ifp); 1127 } 1128 1129 static int 1130 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1131 { 1132 struct lii_softc *sc = ifp->if_softc; 1133 int s, error; 1134 1135 s = splnet(); 1136 1137 switch(cmd) { 1138 case SIOCADDMULTI: 1139 case SIOCDELMULTI: 1140 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1141 if (ifp->if_flags & IFF_RUNNING) 1142 lii_setmulti(sc); 1143 error = 0; 1144 } 1145 break; 1146 case SIOCSIFMEDIA: 1147 case SIOCGIFMEDIA: 1148 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1149 &sc->sc_mii.mii_media, cmd); 1150 break; 1151 default: 1152 error = ether_ioctl(ifp, cmd, data); 1153 if (error == ENETRESET) { 1154 if (ifp->if_flags & IFF_RUNNING) 1155 lii_setmulti(sc); 1156 error = 0; 1157 } 1158 break; 1159 } 1160 1161 splx(s); 1162 1163 return error; 1164 } 1165 1166 static void 1167 lii_setmulti(struct lii_softc *sc) 1168 { 1169 struct ethercom *ec = &sc->sc_ec; 1170 struct ifnet *ifp = &ec->ec_if; 1171 uint32_t mht0 = 0, mht1 = 0, crc; 1172 struct ether_multi *enm; 1173 struct ether_multistep step; 1174 1175 /* Clear multicast hash table */ 1176 AT_WRITE_4(sc, ATL2_MHT, 0); 1177 AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1178 1179 ifp->if_flags &= ~IFF_ALLMULTI; 1180 1181 ETHER_FIRST_MULTI(step, ec, enm); 1182 while (enm != NULL) { 1183 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1184 ifp->if_flags |= IFF_ALLMULTI; 1185 mht0 = mht1 = 0; 1186 goto alldone; 1187 } 1188 1189 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1190 1191 if (crc & (1 << 31)) 1192 mht1 |= (1 << ((crc >> 26) & 0x0000001f)); 1193 else 1194 mht0 |= (1 << ((crc >> 26) & 0x0000001f)); 1195 1196 ETHER_NEXT_MULTI(step, enm); 1197 } 1198 1199 alldone: 1200 AT_WRITE_4(sc, ATL2_MHT, mht0); 1201 AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1202 } 1203 1204 static void 1205 lii_tick(void *v) 1206 { 1207 struct lii_softc *sc = v; 1208 int s; 1209 1210 s = splnet(); 1211 mii_tick(&sc->sc_mii); 1212 splx(s); 1213 1214 callout_schedule(&sc->sc_tick_ch, hz); 1215 } 1216