1 /* $NetBSD: if_lii.c,v 1.3 2008/04/06 23:21:01 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.3 2008/04/06 23:21:01 mjf Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/device.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/sockio.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 #include <net/if_ether.h> 52 53 #if NBPFILTER > 0 54 #include <net/bpf.h> 55 #endif 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/if_liireg.h> 65 66 /* #define LII_DEBUG */ 67 #ifdef LII_DEBUG 68 #define DPRINTF(x) printf x 69 #else 70 #define DPRINTF(x) 71 #endif 72 73 struct lii_softc { 74 device_t sc_dev; 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_tag; 77 78 bus_space_tag_t sc_mmiot; 79 bus_space_handle_t sc_mmioh; 80 81 /* 82 * We allocate a big chunk of DMA-safe memory for all data exchanges. 83 * It is unfortunate that this chip doesn't seem to do scatter-gather. 84 */ 85 bus_dma_tag_t sc_dmat; 86 bus_dmamap_t sc_ringmap; 87 bus_dma_segment_t sc_ringseg; 88 89 uint8_t *sc_ring; /* the whole area */ 90 size_t sc_ringsize; 91 92 struct rx_pkt *sc_rxp; /* the part used for RX */ 93 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 94 bus_addr_t sc_txsp; 95 char *sc_txdbase; 96 bus_addr_t sc_txdp; 97 98 unsigned int sc_rxcur; 99 /* the active area is [ack; cur[ */ 100 int sc_txs_cur; 101 int sc_txs_ack; 102 int sc_txd_cur; 103 int sc_txd_ack; 104 bool sc_free_tx_slots; 105 106 void *sc_ih; 107 108 struct ethercom sc_ec; 109 struct mii_data sc_mii; 110 callout_t sc_tick_ch; 111 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 112 113 int (*sc_memread)(struct lii_softc *, uint32_t, 114 uint32_t *); 115 }; 116 117 static int lii_match(device_t, cfdata_t, void *); 118 static void lii_attach(device_t, device_t, void *); 119 120 static int lii_reset(struct lii_softc *); 121 static bool lii_eeprom_present(struct lii_softc *); 122 static int lii_read_macaddr(struct lii_softc *, uint8_t *); 123 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 124 static void lii_spi_configure(struct lii_softc *); 125 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 126 static void lii_setmulti(struct lii_softc *); 127 static void lii_tick(void *); 128 129 static int lii_alloc_rings(struct lii_softc *); 130 static int lii_free_tx_space(struct lii_softc *); 131 132 static int lii_mii_readreg(device_t, int, int); 133 static void lii_mii_writereg(device_t, int, int, int); 134 static void lii_mii_statchg(device_t); 135 136 static int lii_media_change(struct ifnet *); 137 static void lii_media_status(struct ifnet *, struct ifmediareq *); 138 139 static int lii_init(struct ifnet *); 140 static void lii_start(struct ifnet *); 141 static void lii_stop(struct ifnet *, int); 142 static void lii_watchdog(struct ifnet *); 143 static int lii_ioctl(struct ifnet *, u_long, void *); 144 145 static int lii_intr(void *); 146 static void lii_rxintr(struct lii_softc *); 147 static void lii_txintr(struct lii_softc *); 148 149 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 150 lii_match, lii_attach, NULL, NULL); 151 152 /* #define LII_DEBUG_REGS */ 153 #ifndef LII_DEBUG_REGS 154 #define AT_READ_4(sc,reg) \ 155 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 156 #define AT_READ_2(sc,reg) \ 157 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 158 #define AT_READ_1(sc,reg) \ 159 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 160 #define AT_WRITE_4(sc,reg,val) \ 161 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 162 #define AT_WRITE_2(sc,reg,val) \ 163 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 164 #define AT_WRITE_1(sc,reg,val) \ 165 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 166 #else 167 static inline uint32_t 168 AT_READ_4(struct lii_softc *sc, bus_size_t reg) 169 { 170 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 171 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 172 return r; 173 } 174 175 static inline uint16_t 176 AT_READ_2(struct lii_softc *sc, bus_size_t reg) 177 { 178 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 179 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 180 return r; 181 } 182 183 static inline uint8_t 184 AT_READ_1(struct lii_softc *sc, bus_size_t reg) 185 { 186 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 187 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 188 return r; 189 } 190 191 static inline void 192 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 193 { 194 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 195 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 196 } 197 198 static inline void 199 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 200 { 201 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 202 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 203 } 204 205 static inline void 206 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 207 { 208 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 209 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 210 } 211 #endif 212 213 /* 214 * Those are the default Linux parameters. 215 */ 216 217 #define AT_TXD_NUM 64 218 #define AT_TXD_BUFFER_SIZE 8192 219 #define AT_RXD_NUM 64 220 221 /* 222 * Assuming (you know what that word makes of you) the chunk of memory 223 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 224 * first 120 bytes of it, so that the space for the packets, and not the 225 * whole descriptors themselves, are on a 128-byte boundary. 226 */ 227 228 #define AT_RXD_PADDING 120 229 230 static int 231 lii_match(device_t parent, cfdata_t cfmatch, void *aux) 232 { 233 struct pci_attach_args *pa = aux; 234 235 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 236 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 237 } 238 239 static void 240 lii_attach(device_t parent, device_t self, void *aux) 241 { 242 struct lii_softc *sc = device_private(self); 243 struct pci_attach_args *pa = aux; 244 uint8_t eaddr[ETHER_ADDR_LEN]; 245 struct ifnet *ifp = &sc->sc_ec.ec_if; 246 pci_intr_handle_t ih; 247 const char *intrstr; 248 pcireg_t cmd; 249 250 aprint_naive("\n"); 251 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 252 253 sc->sc_dev = self; 254 sc->sc_pc = pa->pa_pc; 255 sc->sc_tag = pa->pa_tag; 256 sc->sc_dmat = pa->pa_dmat; 257 258 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 259 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 260 cmd &= ~PCI_COMMAND_IO_ENABLE; 261 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 262 263 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 264 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 265 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 266 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 267 break; 268 default: 269 aprint_error_dev(self, "invalid base address register\n"); 270 break; 271 } 272 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 273 &sc->sc_mmiot, &sc->sc_mmioh, NULL, NULL) != 0) { 274 aprint_error_dev(self, "failed to map registers\n"); 275 return; 276 } 277 278 if (lii_reset(sc)) 279 return; 280 281 lii_spi_configure(sc); 282 283 if (lii_eeprom_present(sc)) 284 sc->sc_memread = lii_eeprom_read; 285 else 286 sc->sc_memread = lii_spi_read; 287 288 if (lii_read_macaddr(sc, eaddr)) 289 return; 290 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 291 292 aprint_normal_dev(self, "Ethernet address %s\n", 293 ether_sprintf(eaddr)); 294 295 if (pci_intr_map(pa, &ih) != 0) { 296 aprint_error_dev(self, "failed to map interrupt\n"); 297 return; 298 } 299 intrstr = pci_intr_string(sc->sc_pc, ih); 300 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 301 if (sc->sc_ih == NULL) { 302 aprint_error_dev(self, "failed to establish interrupt"); 303 if (intrstr != NULL) 304 aprint_error(" at %s", intrstr); 305 aprint_error("\n"); 306 return; 307 } 308 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 309 310 if (lii_alloc_rings(sc)) { 311 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 312 return; 313 } 314 315 callout_init(&sc->sc_tick_ch, 0); 316 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 317 318 sc->sc_mii.mii_ifp = ifp; 319 sc->sc_mii.mii_readreg = lii_mii_readreg; 320 sc->sc_mii.mii_writereg = lii_mii_writereg; 321 sc->sc_mii.mii_statchg = lii_mii_statchg; 322 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 323 lii_media_status); 324 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 325 MII_OFFSET_ANY, 0); 326 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 327 328 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = lii_ioctl; 332 ifp->if_start = lii_start; 333 ifp->if_watchdog = lii_watchdog; 334 ifp->if_init = lii_init; 335 ifp->if_stop = lii_stop; 336 IFQ_SET_READY(&ifp->if_snd); 337 338 /* 339 * While the device does support HW VLAN tagging, there is no 340 * real point using that feature. 341 */ 342 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 343 344 if_attach(ifp); 345 ether_ifattach(ifp, eaddr); 346 347 if (!pmf_device_register(self, NULL, NULL)) 348 aprint_error_dev(self, "couldn't establish power handler\n"); 349 else 350 pmf_class_network_register(self, ifp); 351 352 return; 353 } 354 355 static int 356 lii_reset(struct lii_softc *sc) 357 { 358 int i; 359 360 DPRINTF(("lii_reset\n")); 361 362 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 363 DELAY(1000); 364 365 for (i = 0; i < 10; ++i) { 366 if (AT_READ_4(sc, ATL2_BIS) == 0) 367 break; 368 DELAY(1000); 369 } 370 371 if (i == 10) { 372 aprint_error_dev(sc->sc_dev, "reset failed\n"); 373 return 1; 374 } 375 376 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 377 DELAY(10); 378 379 /* Init PCI-Express module */ 380 /* Magic Numbers Warning */ 381 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 382 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 383 384 return 0; 385 } 386 387 static bool 388 lii_eeprom_present(struct lii_softc *sc) 389 { 390 /* 391 * The Linux driver does this, but then it has a very weird way of 392 * checking whether the PCI configuration space exposes the Vital 393 * Product Data capability, so maybe it's not really needed. 394 */ 395 396 #ifdef weirdloonix 397 uint32_t val; 398 399 val = AT_READ_4(sc, ATL2_SFC); 400 if (val & SFC_EN_VPD) 401 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 402 #endif 403 404 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 405 NULL, NULL) == 1; 406 } 407 408 static int 409 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 410 { 411 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 412 413 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 414 415 return r; 416 } 417 418 static void 419 lii_spi_configure(struct lii_softc *sc) 420 { 421 /* 422 * We don't offer a way to configure the SPI Flash vendor parameter, so 423 * the table is given for reference 424 */ 425 static const struct lii_spi_flash_vendor { 426 const char *sfv_name; 427 const uint8_t sfv_opcodes[9]; 428 } lii_sfv[] = { 429 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 430 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 431 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 432 }; 433 #define SF_OPCODE_WRSR 0 434 #define SF_OPCODE_READ 1 435 #define SF_OPCODE_PRGM 2 436 #define SF_OPCODE_WREN 3 437 #define SF_OPCODE_WRDI 4 438 #define SF_OPCODE_RDSR 5 439 #define SF_OPCODE_RDID 6 440 #define SF_OPCODE_SECT_ER 7 441 #define SF_OPCODE_CHIP_ER 8 442 443 #define SF_DEFAULT_VENDOR 0 444 static const uint8_t vendor = SF_DEFAULT_VENDOR; 445 446 /* 447 * Why isn't WRDI used? Heck if I know. 448 */ 449 450 AT_WRITE_1(sc, ATL2_SFOP_WRSR, 451 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 452 AT_WRITE_1(sc, ATL2_SFOP_READ, 453 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 454 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 455 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 456 AT_WRITE_1(sc, ATL2_SFOP_WREN, 457 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 458 AT_WRITE_1(sc, ATL2_SFOP_RDSR, 459 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 460 AT_WRITE_1(sc, ATL2_SFOP_RDID, 461 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 462 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 463 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 464 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 465 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 466 } 467 468 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 469 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 470 << SFC_CS_SETUP_SHIFT) \ 471 | (((clkhi) & SFC_CLK_HI_MASK) \ 472 << SFC_CLK_HI_SHIFT) \ 473 | (((clklo) & SFC_CLK_LO_MASK) \ 474 << SFC_CLK_LO_SHIFT) \ 475 | (((cshold) & SFC_CS_HOLD_MASK) \ 476 << SFC_CS_HOLD_SHIFT) \ 477 | (((cshi) & SFC_CS_HI_MASK) \ 478 << SFC_CS_HI_SHIFT) \ 479 | (((ins) & SFC_INS_MASK) \ 480 << SFC_INS_SHIFT)) 481 482 /* Magic settings from the Linux driver */ 483 484 #define CUSTOM_SPI_CS_SETUP 2 485 #define CUSTOM_SPI_CLK_HI 2 486 #define CUSTOM_SPI_CLK_LO 2 487 #define CUSTOM_SPI_CS_HOLD 2 488 #define CUSTOM_SPI_CS_HI 3 489 490 static int 491 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 492 { 493 uint32_t v; 494 int i; 495 496 AT_WRITE_4(sc, ATL2_SF_DATA, 0); 497 AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 498 499 v = SFC_WAIT_READY | 500 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 501 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 502 503 AT_WRITE_4(sc, ATL2_SFC, v); 504 v |= SFC_START; 505 AT_WRITE_4(sc, ATL2_SFC, v); 506 507 for (i = 0; i < 10; ++i) { 508 DELAY(1000); 509 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 510 break; 511 } 512 if (i == 10) 513 return EBUSY; 514 515 *val = AT_READ_4(sc, ATL2_SF_DATA); 516 return 0; 517 } 518 519 static int 520 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 521 { 522 uint32_t offset = 0x100; 523 uint32_t val, val1, addr0 = 0, addr1 = 0; 524 uint8_t found = 0; 525 526 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 527 offset += 4; 528 529 /* Each chunk of data starts with a signature */ 530 if ((val & 0xff) != 0x5a) 531 break; 532 if ((*sc->sc_memread)(sc, offset, &val1)) 533 break; 534 535 offset += 4; 536 537 val >>= 16; 538 switch (val) { 539 case ATL2_MAC_ADDR_0: 540 addr0 = val1; 541 ++found; 542 break; 543 case ATL2_MAC_ADDR_1: 544 addr1 = val1; 545 ++found; 546 break; 547 default: 548 continue; 549 } 550 } 551 552 if (found < 2) { 553 aprint_error_dev(sc->sc_dev, "error reading MAC address\n"); 554 return 1; 555 } 556 557 addr0 = htole32(addr0); 558 addr1 = htole32(addr1); 559 560 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 561 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 562 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 563 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 564 } 565 566 ea[0] = (addr1 & 0x0000ff00) >> 8; 567 ea[1] = (addr1 & 0x000000ff); 568 ea[2] = (addr0 & 0xff000000) >> 24; 569 ea[3] = (addr0 & 0x00ff0000) >> 16; 570 ea[4] = (addr0 & 0x0000ff00) >> 8; 571 ea[5] = (addr0 & 0x000000ff); 572 573 return 0; 574 } 575 576 static int 577 lii_mii_readreg(device_t dev, int phy, int reg) 578 { 579 struct lii_softc *sc = device_private(dev); 580 uint32_t val; 581 int i; 582 583 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 584 585 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 586 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 587 588 val |= MDIOC_READ; 589 590 AT_WRITE_4(sc, ATL2_MDIOC, val); 591 592 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 593 DELAY(2); 594 val = AT_READ_4(sc, ATL2_MDIOC); 595 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 596 break; 597 } 598 599 if (i == MDIO_WAIT_TIMES) 600 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 601 reg); 602 603 return (val & 0x0000ffff); 604 } 605 606 static void 607 lii_mii_writereg(device_t dev, int phy, int reg, int data) 608 { 609 struct lii_softc *sc = device_private(dev); 610 uint32_t val; 611 int i; 612 613 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 614 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 615 616 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 617 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 618 619 /* val |= MDIOC_WRITE; */ 620 621 AT_WRITE_4(sc, ATL2_MDIOC, val); 622 623 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 624 DELAY(2); 625 val = AT_READ_4(sc, ATL2_MDIOC); 626 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 627 break; 628 } 629 630 if (i == MDIO_WAIT_TIMES) 631 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 632 reg); 633 } 634 635 static void 636 lii_mii_statchg(device_t dev) 637 { 638 struct lii_softc *sc = device_private(dev); 639 uint32_t val; 640 641 DPRINTF(("lii_mii_statchg\n")); 642 643 val = AT_READ_4(sc, ATL2_MACC); 644 645 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 646 val |= MACC_FDX; 647 else 648 val &= ~MACC_FDX; 649 650 AT_WRITE_4(sc, ATL2_MACC, val); 651 } 652 653 static int 654 lii_media_change(struct ifnet *ifp) 655 { 656 struct lii_softc *sc = ifp->if_softc; 657 658 DPRINTF(("lii_media_change\n")); 659 660 if (ifp->if_flags & IFF_UP) 661 mii_mediachg(&sc->sc_mii); 662 return 0; 663 } 664 665 static void 666 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 667 { 668 struct lii_softc *sc = ifp->if_softc; 669 670 DPRINTF(("lii_media_status\n")); 671 672 mii_pollstat(&sc->sc_mii); 673 imr->ifm_status = sc->sc_mii.mii_media_status; 674 imr->ifm_active = sc->sc_mii.mii_media_active; 675 } 676 677 static int 678 lii_init(struct ifnet *ifp) 679 { 680 struct lii_softc *sc = ifp->if_softc; 681 uint32_t val; 682 int error; 683 684 DPRINTF(("lii_init\n")); 685 686 lii_stop(ifp, 0); 687 688 memset(sc->sc_ring, 0, sc->sc_ringsize); 689 690 /* Disable all interrupts */ 691 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 692 693 /* XXX endianness */ 694 AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 695 sc->sc_eaddr[2] << 24 | 696 sc->sc_eaddr[3] << 16 | 697 sc->sc_eaddr[4] << 8 | 698 sc->sc_eaddr[5]); 699 AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 700 sc->sc_eaddr[0] << 8 | 701 sc->sc_eaddr[1]); 702 703 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 704 /* XXX 705 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 706 */ 707 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 708 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 709 + AT_RXD_PADDING); 710 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 711 sc->sc_txsp & 0xffffffff); 712 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 713 sc->sc_txdp & 0xffffffff); 714 715 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 716 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 717 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 718 719 /* 720 * Inter Paket Gap Time = 0x60 (IPGT) 721 * Minimum inter-frame gap for RX = 0x50 (MIFG) 722 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 723 * 96-bit IPG window = 0x60 (IPGR2) 724 */ 725 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 726 727 /* 728 * Collision window = 0x37 (LCOL) 729 * Maximum # of retrans = 0xf (RETRY) 730 * Maximum binary expansion # = 0xa (ABEBT) 731 * IPG to start jam = 0x7 (JAMIPG) 732 */ 733 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 734 MHDC_EXC_DEF_EN); 735 736 /* 100 means 200us */ 737 AT_WRITE_2(sc, ATL2_IMTIV, 100); 738 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 739 740 /* 500000 means 100ms */ 741 AT_WRITE_2(sc, ATL2_IALTIV, 50000); 742 743 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 744 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 745 746 /* unit unknown for TX cur-through threshold */ 747 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 748 749 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 750 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 751 752 sc->sc_rxcur = 0; 753 sc->sc_txs_cur = sc->sc_txs_ack = 0; 754 sc->sc_txd_cur = sc->sc_txd_ack = 0; 755 sc->sc_free_tx_slots = true; 756 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 757 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 758 759 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 760 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 761 762 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 763 764 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 765 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 766 AT_WRITE_4(sc, ATL2_ISR, 0); 767 if (error) { 768 aprint_error_dev(sc->sc_dev, "init failed\n"); 769 goto out; 770 } 771 772 lii_setmulti(sc); 773 774 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 775 776 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 777 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 778 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 779 780 if (ifp->if_flags & IFF_PROMISC) 781 val |= MACC_PROMISC_EN; 782 else if (ifp->if_flags & IFF_ALLMULTI) 783 val |= MACC_ALLMULTI_EN; 784 785 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 786 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 787 788 AT_WRITE_4(sc, ATL2_MACC, val); 789 790 mii_mediachg(&sc->sc_mii); 791 792 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 793 794 callout_schedule(&sc->sc_tick_ch, hz); 795 796 ifp->if_flags |= IFF_RUNNING; 797 ifp->if_flags &= ~IFF_OACTIVE; 798 799 out: 800 return error; 801 } 802 803 static void 804 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 805 { 806 int left; 807 struct tx_pkt_header *tph = 808 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 809 810 memset(tph, 0, sizeof *tph); 811 tph->txph_size = m->m_pkthdr.len; 812 813 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 814 815 /* 816 * We already know we have enough space, so if there is a part of the 817 * space ahead of txd_cur that is active, it doesn't matter because 818 * left will be large enough even without it. 819 */ 820 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 821 822 if (left > m->m_pkthdr.len) { 823 m_copydata(m, 0, m->m_pkthdr.len, 824 sc->sc_txdbase + sc->sc_txd_cur); 825 sc->sc_txd_cur += m->m_pkthdr.len; 826 } else { 827 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 828 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 829 sc->sc_txd_cur = m->m_pkthdr.len - left; 830 } 831 832 /* Round to a 32-bit boundary */ 833 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 834 if (sc->sc_txd_cur == sc->sc_txd_ack) 835 sc->sc_free_tx_slots = false; 836 } 837 838 static int 839 lii_free_tx_space(struct lii_softc *sc) 840 { 841 int space; 842 843 if (sc->sc_txd_cur >= sc->sc_txd_ack) 844 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 845 sc->sc_txd_ack; 846 else 847 space = sc->sc_txd_ack - sc->sc_txd_cur; 848 849 /* Account for the tx_pkt_header */ 850 return (space - 4); 851 } 852 853 static void 854 lii_start(struct ifnet *ifp) 855 { 856 struct lii_softc *sc = ifp->if_softc; 857 struct mbuf *m0; 858 859 DPRINTF(("lii_start\n")); 860 861 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 862 return; 863 864 for (;;) { 865 IFQ_POLL(&ifp->if_snd, m0); 866 if (m0 == NULL) 867 break; 868 869 if (!sc->sc_free_tx_slots || 870 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 871 ifp->if_flags |= IFF_OACTIVE; 872 break; 873 } 874 875 lii_tx_put(sc, m0); 876 877 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 878 879 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 880 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 881 if (sc->sc_txs_cur == sc->sc_txs_ack) 882 sc->sc_free_tx_slots = false; 883 884 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 885 886 IFQ_DEQUEUE(&ifp->if_snd, m0); 887 888 #if NBPFILTER > 0 889 if (ifp->if_bpf != NULL) 890 bpf_mtap(ifp->if_bpf, m0); 891 #endif 892 m_freem(m0); 893 } 894 } 895 896 static void 897 lii_stop(struct ifnet *ifp, int disable) 898 { 899 struct lii_softc *sc = ifp->if_softc; 900 901 callout_stop(&sc->sc_tick_ch); 902 903 ifp->if_timer = 0; 904 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 905 906 mii_down(&sc->sc_mii); 907 908 lii_reset(sc); 909 910 AT_WRITE_4(sc, ATL2_IMR, 0); 911 } 912 913 static int 914 lii_intr(void *v) 915 { 916 struct lii_softc *sc = v; 917 uint32_t status; 918 919 status = AT_READ_4(sc, ATL2_ISR); 920 if (status == 0) 921 return 0; 922 923 DPRINTF(("lii_intr (%x)\n", status)); 924 925 /* Clear the interrupt and disable them */ 926 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 927 928 if (status & (ISR_PHY | ISR_MANUAL)) { 929 /* Ack PHY interrupt. Magic register */ 930 if (status & ISR_PHY) 931 (void)lii_mii_readreg(sc->sc_dev, 1, 19); 932 mii_mediachg(&sc->sc_mii); 933 } 934 935 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 936 lii_init(&sc->sc_ec.ec_if); 937 return 1; 938 } 939 940 if (status & ISR_RX_EVENT) { 941 #ifdef LII_DEBUG 942 if (!(status & ISR_RS_UPDATE)) 943 printf("rxintr %08x\n", status); 944 #endif 945 lii_rxintr(sc); 946 } 947 948 if (status & ISR_TX_EVENT) 949 lii_txintr(sc); 950 951 /* Re-enable interrupts */ 952 AT_WRITE_4(sc, ATL2_ISR, 0); 953 954 return 1; 955 } 956 957 static void 958 lii_rxintr(struct lii_softc *sc) 959 { 960 struct ifnet *ifp = &sc->sc_ec.ec_if; 961 struct rx_pkt *rxp; 962 struct mbuf *m; 963 uint16_t size; 964 965 DPRINTF(("lii_rxintr\n")); 966 967 for (;;) { 968 rxp = &sc->sc_rxp[sc->sc_rxcur]; 969 if (rxp->rxp_update == 0) 970 break; 971 972 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 973 rxp->rxp_size, rxp->rxp_flags)); 974 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 975 rxp->rxp_update = 0; 976 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 977 ++ifp->if_ierrors; 978 continue; 979 } 980 981 MGETHDR(m, M_DONTWAIT, MT_DATA); 982 if (m == NULL) { 983 ++ifp->if_ierrors; 984 continue; 985 } 986 size = rxp->rxp_size - ETHER_CRC_LEN; 987 if (size > MHLEN) { 988 MCLGET(m, M_DONTWAIT); 989 if ((m->m_flags & M_EXT) == 0) { 990 m_freem(m); 991 ++ifp->if_ierrors; 992 continue; 993 } 994 } 995 996 m->m_pkthdr.rcvif = ifp; 997 /* Copy the packet withhout the FCS */ 998 m->m_pkthdr.len = m->m_len = size; 999 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 1000 ++ifp->if_ipackets; 1001 1002 #if NBPFILTER > 0 1003 if (ifp->if_bpf) 1004 bpf_mtap(ifp->if_bpf, m); 1005 #endif 1006 1007 (*ifp->if_input)(ifp, m); 1008 } 1009 1010 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1011 } 1012 1013 static void 1014 lii_txintr(struct lii_softc *sc) 1015 { 1016 struct ifnet *ifp = &sc->sc_ec.ec_if; 1017 struct tx_pkt_status *txs; 1018 struct tx_pkt_header *txph; 1019 1020 DPRINTF(("lii_txintr\n")); 1021 1022 for (;;) { 1023 txs = &sc->sc_txs[sc->sc_txs_ack]; 1024 if (txs->txps_update == 0) 1025 break; 1026 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1027 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1028 sc->sc_free_tx_slots = true; 1029 1030 txs->txps_update = 0; 1031 1032 txph = (struct tx_pkt_header *) 1033 (sc->sc_txdbase + sc->sc_txd_ack); 1034 1035 if (txph->txph_size != txs->txps_size) 1036 aprint_error_dev(sc->sc_dev, 1037 "mismatched status and packet\n"); 1038 /* 1039 * Move ack by the packet size, taking the packet header in 1040 * account and round to the next 32-bit boundary 1041 * (7 = sizeof(header) + 3) 1042 */ 1043 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1044 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1045 1046 if (txs->txps_flags & ATL2_TXF_SUCCESS) 1047 ++ifp->if_opackets; 1048 else 1049 ++ifp->if_oerrors; 1050 ifp->if_flags &= ~IFF_OACTIVE; 1051 } 1052 1053 if (sc->sc_free_tx_slots) 1054 lii_start(ifp); 1055 } 1056 1057 static int 1058 lii_alloc_rings(struct lii_softc *sc) 1059 { 1060 int nsegs; 1061 bus_size_t bs; 1062 1063 /* 1064 * We need a big chunk of DMA-friendly memory because descriptors 1065 * are not separate from data on that crappy hardware, which means 1066 * we'll have to copy data from and to that memory zone to and from 1067 * the mbufs. 1068 * 1069 * How lame is that? Using the default values from the Linux driver, 1070 * we allocate space for receiving up to 64 full-size Ethernet frames, 1071 * and only 8kb for transmitting up to 64 Ethernet frames. 1072 */ 1073 1074 sc->sc_ringsize = bs = AT_RXD_PADDING 1075 + AT_RXD_NUM * sizeof(struct rx_pkt) 1076 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1077 + AT_TXD_BUFFER_SIZE; 1078 1079 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1080 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1081 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1082 return 1; 1083 } 1084 1085 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1086 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1087 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1088 goto fail; 1089 } 1090 1091 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1092 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1093 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1094 goto fail1; 1095 } 1096 1097 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1098 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1099 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1100 goto fail2; 1101 } 1102 1103 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1104 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1105 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1106 sc->sc_txdbase = ((char *)sc->sc_txs) 1107 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1108 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1109 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1110 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1111 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1112 1113 return 0; 1114 1115 fail2: 1116 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1117 fail1: 1118 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1119 fail: 1120 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1121 return 1; 1122 } 1123 1124 static void 1125 lii_watchdog(struct ifnet *ifp) 1126 { 1127 struct lii_softc *sc = ifp->if_softc; 1128 1129 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1130 ++ifp->if_oerrors; 1131 lii_init(ifp); 1132 } 1133 1134 static int 1135 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1136 { 1137 struct lii_softc *sc = ifp->if_softc; 1138 int s, error; 1139 1140 s = splnet(); 1141 1142 switch(cmd) { 1143 case SIOCADDMULTI: 1144 case SIOCDELMULTI: 1145 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1146 if (ifp->if_flags & IFF_RUNNING) 1147 lii_setmulti(sc); 1148 error = 0; 1149 } 1150 break; 1151 case SIOCSIFMEDIA: 1152 case SIOCGIFMEDIA: 1153 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1154 &sc->sc_mii.mii_media, cmd); 1155 break; 1156 default: 1157 error = ether_ioctl(ifp, cmd, data); 1158 if (error == ENETRESET) { 1159 if (ifp->if_flags & IFF_RUNNING) 1160 lii_setmulti(sc); 1161 error = 0; 1162 } 1163 break; 1164 } 1165 1166 splx(s); 1167 1168 return error; 1169 } 1170 1171 static void 1172 lii_setmulti(struct lii_softc *sc) 1173 { 1174 struct ethercom *ec = &sc->sc_ec; 1175 struct ifnet *ifp = &ec->ec_if; 1176 uint32_t mht0 = 0, mht1 = 0, crc; 1177 struct ether_multi *enm; 1178 struct ether_multistep step; 1179 1180 /* Clear multicast hash table */ 1181 AT_WRITE_4(sc, ATL2_MHT, 0); 1182 AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1183 1184 ifp->if_flags &= ~IFF_ALLMULTI; 1185 1186 ETHER_FIRST_MULTI(step, ec, enm); 1187 while (enm != NULL) { 1188 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1189 ifp->if_flags |= IFF_ALLMULTI; 1190 mht0 = mht1 = 0; 1191 goto alldone; 1192 } 1193 1194 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1195 1196 if (crc & (1 << 31)) 1197 mht1 |= (1 << (crc & 0x0000001f)); 1198 else 1199 mht0 |= (1 << (crc & 0x0000001f)); 1200 1201 ETHER_NEXT_MULTI(step, enm); 1202 } 1203 1204 alldone: 1205 AT_WRITE_4(sc, ATL2_MHT, mht0); 1206 AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1207 } 1208 1209 static void 1210 lii_tick(void *v) 1211 { 1212 struct lii_softc *sc = v; 1213 int s; 1214 1215 s = splnet(); 1216 mii_tick(&sc->sc_mii); 1217 splx(s); 1218 1219 callout_schedule(&sc->sc_tick_ch, hz); 1220 } 1221