1 /* $NetBSD: if_lii.c,v 1.5 2008/07/08 12:39:27 sborrill Exp $ */ 2 3 /* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.5 2008/07/08 12:39:27 sborrill Exp $"); 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/kernel.h> 44 #include <sys/sockio.h> 45 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 50 #if NBPFILTER > 0 51 #include <net/bpf.h> 52 #endif 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcidevs.h> 60 61 #include <dev/pci/if_liireg.h> 62 63 /* #define LII_DEBUG */ 64 #ifdef LII_DEBUG 65 #define DPRINTF(x) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 struct lii_softc { 71 device_t sc_dev; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 75 bus_space_tag_t sc_mmiot; 76 bus_space_handle_t sc_mmioh; 77 78 /* 79 * We allocate a big chunk of DMA-safe memory for all data exchanges. 80 * It is unfortunate that this chip doesn't seem to do scatter-gather. 81 */ 82 bus_dma_tag_t sc_dmat; 83 bus_dmamap_t sc_ringmap; 84 bus_dma_segment_t sc_ringseg; 85 86 uint8_t *sc_ring; /* the whole area */ 87 size_t sc_ringsize; 88 89 struct rx_pkt *sc_rxp; /* the part used for RX */ 90 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 91 bus_addr_t sc_txsp; 92 char *sc_txdbase; 93 bus_addr_t sc_txdp; 94 95 unsigned int sc_rxcur; 96 /* the active area is [ack; cur[ */ 97 int sc_txs_cur; 98 int sc_txs_ack; 99 int sc_txd_cur; 100 int sc_txd_ack; 101 bool sc_free_tx_slots; 102 103 void *sc_ih; 104 105 struct ethercom sc_ec; 106 struct mii_data sc_mii; 107 callout_t sc_tick_ch; 108 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 109 110 int (*sc_memread)(struct lii_softc *, uint32_t, 111 uint32_t *); 112 }; 113 114 static int lii_match(device_t, cfdata_t, void *); 115 static void lii_attach(device_t, device_t, void *); 116 117 static int lii_reset(struct lii_softc *); 118 static bool lii_eeprom_present(struct lii_softc *); 119 static int lii_read_macaddr(struct lii_softc *, uint8_t *); 120 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 121 static void lii_spi_configure(struct lii_softc *); 122 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 123 static void lii_setmulti(struct lii_softc *); 124 static void lii_tick(void *); 125 126 static int lii_alloc_rings(struct lii_softc *); 127 static int lii_free_tx_space(struct lii_softc *); 128 129 static int lii_mii_readreg(device_t, int, int); 130 static void lii_mii_writereg(device_t, int, int, int); 131 static void lii_mii_statchg(device_t); 132 133 static int lii_media_change(struct ifnet *); 134 static void lii_media_status(struct ifnet *, struct ifmediareq *); 135 136 static int lii_init(struct ifnet *); 137 static void lii_start(struct ifnet *); 138 static void lii_stop(struct ifnet *, int); 139 static void lii_watchdog(struct ifnet *); 140 static int lii_ioctl(struct ifnet *, u_long, void *); 141 142 static int lii_intr(void *); 143 static void lii_rxintr(struct lii_softc *); 144 static void lii_txintr(struct lii_softc *); 145 146 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 147 lii_match, lii_attach, NULL, NULL); 148 149 /* #define LII_DEBUG_REGS */ 150 #ifndef LII_DEBUG_REGS 151 #define AT_READ_4(sc,reg) \ 152 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 153 #define AT_READ_2(sc,reg) \ 154 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 155 #define AT_READ_1(sc,reg) \ 156 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 157 #define AT_WRITE_4(sc,reg,val) \ 158 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 159 #define AT_WRITE_2(sc,reg,val) \ 160 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 161 #define AT_WRITE_1(sc,reg,val) \ 162 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 163 #else 164 static inline uint32_t 165 AT_READ_4(struct lii_softc *sc, bus_size_t reg) 166 { 167 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 168 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 169 return r; 170 } 171 172 static inline uint16_t 173 AT_READ_2(struct lii_softc *sc, bus_size_t reg) 174 { 175 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 176 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 177 return r; 178 } 179 180 static inline uint8_t 181 AT_READ_1(struct lii_softc *sc, bus_size_t reg) 182 { 183 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 184 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 185 return r; 186 } 187 188 static inline void 189 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 190 { 191 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 192 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 193 } 194 195 static inline void 196 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 197 { 198 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 199 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 200 } 201 202 static inline void 203 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 204 { 205 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 206 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 207 } 208 #endif 209 210 /* 211 * Those are the default Linux parameters. 212 */ 213 214 #define AT_TXD_NUM 64 215 #define AT_TXD_BUFFER_SIZE 8192 216 #define AT_RXD_NUM 64 217 218 /* 219 * Assuming (you know what that word makes of you) the chunk of memory 220 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 221 * first 120 bytes of it, so that the space for the packets, and not the 222 * whole descriptors themselves, are on a 128-byte boundary. 223 */ 224 225 #define AT_RXD_PADDING 120 226 227 static int 228 lii_match(device_t parent, cfdata_t cfmatch, void *aux) 229 { 230 struct pci_attach_args *pa = aux; 231 232 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 233 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 234 } 235 236 static void 237 lii_attach(device_t parent, device_t self, void *aux) 238 { 239 struct lii_softc *sc = device_private(self); 240 struct pci_attach_args *pa = aux; 241 uint8_t eaddr[ETHER_ADDR_LEN]; 242 struct ifnet *ifp = &sc->sc_ec.ec_if; 243 pci_intr_handle_t ih; 244 const char *intrstr; 245 pcireg_t cmd; 246 247 aprint_naive("\n"); 248 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 249 250 sc->sc_dev = self; 251 sc->sc_pc = pa->pa_pc; 252 sc->sc_tag = pa->pa_tag; 253 sc->sc_dmat = pa->pa_dmat; 254 255 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 256 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 257 cmd &= ~PCI_COMMAND_IO_ENABLE; 258 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 259 260 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 261 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 262 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 263 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 264 break; 265 default: 266 aprint_error_dev(self, "invalid base address register\n"); 267 break; 268 } 269 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 270 &sc->sc_mmiot, &sc->sc_mmioh, NULL, NULL) != 0) { 271 aprint_error_dev(self, "failed to map registers\n"); 272 return; 273 } 274 275 if (lii_reset(sc)) 276 return; 277 278 lii_spi_configure(sc); 279 280 if (lii_eeprom_present(sc)) 281 sc->sc_memread = lii_eeprom_read; 282 else 283 sc->sc_memread = lii_spi_read; 284 285 if (lii_read_macaddr(sc, eaddr)) 286 return; 287 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 288 289 aprint_normal_dev(self, "Ethernet address %s\n", 290 ether_sprintf(eaddr)); 291 292 if (pci_intr_map(pa, &ih) != 0) { 293 aprint_error_dev(self, "failed to map interrupt\n"); 294 return; 295 } 296 intrstr = pci_intr_string(sc->sc_pc, ih); 297 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 298 if (sc->sc_ih == NULL) { 299 aprint_error_dev(self, "failed to establish interrupt"); 300 if (intrstr != NULL) 301 aprint_error(" at %s", intrstr); 302 aprint_error("\n"); 303 return; 304 } 305 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 306 307 if (lii_alloc_rings(sc)) { 308 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 309 return; 310 } 311 312 callout_init(&sc->sc_tick_ch, 0); 313 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 314 315 sc->sc_mii.mii_ifp = ifp; 316 sc->sc_mii.mii_readreg = lii_mii_readreg; 317 sc->sc_mii.mii_writereg = lii_mii_writereg; 318 sc->sc_mii.mii_statchg = lii_mii_statchg; 319 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 320 lii_media_status); 321 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 322 MII_OFFSET_ANY, 0); 323 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 324 325 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 326 ifp->if_softc = sc; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = lii_ioctl; 329 ifp->if_start = lii_start; 330 ifp->if_watchdog = lii_watchdog; 331 ifp->if_init = lii_init; 332 ifp->if_stop = lii_stop; 333 IFQ_SET_READY(&ifp->if_snd); 334 335 /* 336 * While the device does support HW VLAN tagging, there is no 337 * real point using that feature. 338 */ 339 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 340 341 if_attach(ifp); 342 ether_ifattach(ifp, eaddr); 343 344 if (!pmf_device_register(self, NULL, NULL)) 345 aprint_error_dev(self, "couldn't establish power handler\n"); 346 else 347 pmf_class_network_register(self, ifp); 348 349 return; 350 } 351 352 static int 353 lii_reset(struct lii_softc *sc) 354 { 355 int i; 356 357 DPRINTF(("lii_reset\n")); 358 359 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 360 DELAY(1000); 361 362 for (i = 0; i < 10; ++i) { 363 if (AT_READ_4(sc, ATL2_BIS) == 0) 364 break; 365 DELAY(1000); 366 } 367 368 if (i == 10) { 369 aprint_error_dev(sc->sc_dev, "reset failed\n"); 370 return 1; 371 } 372 373 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 374 DELAY(10); 375 376 /* Init PCI-Express module */ 377 /* Magic Numbers Warning */ 378 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 379 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 380 381 return 0; 382 } 383 384 static bool 385 lii_eeprom_present(struct lii_softc *sc) 386 { 387 /* 388 * The Linux driver does this, but then it has a very weird way of 389 * checking whether the PCI configuration space exposes the Vital 390 * Product Data capability, so maybe it's not really needed. 391 */ 392 393 #ifdef weirdloonix 394 uint32_t val; 395 396 val = AT_READ_4(sc, ATL2_SFC); 397 if (val & SFC_EN_VPD) 398 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 399 #endif 400 401 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 402 NULL, NULL) == 1; 403 } 404 405 static int 406 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 407 { 408 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 409 410 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 411 412 return r; 413 } 414 415 static void 416 lii_spi_configure(struct lii_softc *sc) 417 { 418 /* 419 * We don't offer a way to configure the SPI Flash vendor parameter, so 420 * the table is given for reference 421 */ 422 static const struct lii_spi_flash_vendor { 423 const char *sfv_name; 424 const uint8_t sfv_opcodes[9]; 425 } lii_sfv[] = { 426 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 427 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 428 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 429 }; 430 #define SF_OPCODE_WRSR 0 431 #define SF_OPCODE_READ 1 432 #define SF_OPCODE_PRGM 2 433 #define SF_OPCODE_WREN 3 434 #define SF_OPCODE_WRDI 4 435 #define SF_OPCODE_RDSR 5 436 #define SF_OPCODE_RDID 6 437 #define SF_OPCODE_SECT_ER 7 438 #define SF_OPCODE_CHIP_ER 8 439 440 #define SF_DEFAULT_VENDOR 0 441 static const uint8_t vendor = SF_DEFAULT_VENDOR; 442 443 /* 444 * Why isn't WRDI used? Heck if I know. 445 */ 446 447 AT_WRITE_1(sc, ATL2_SFOP_WRSR, 448 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 449 AT_WRITE_1(sc, ATL2_SFOP_READ, 450 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 451 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 452 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 453 AT_WRITE_1(sc, ATL2_SFOP_WREN, 454 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 455 AT_WRITE_1(sc, ATL2_SFOP_RDSR, 456 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 457 AT_WRITE_1(sc, ATL2_SFOP_RDID, 458 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 459 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 460 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 461 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 462 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 463 } 464 465 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 466 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 467 << SFC_CS_SETUP_SHIFT) \ 468 | (((clkhi) & SFC_CLK_HI_MASK) \ 469 << SFC_CLK_HI_SHIFT) \ 470 | (((clklo) & SFC_CLK_LO_MASK) \ 471 << SFC_CLK_LO_SHIFT) \ 472 | (((cshold) & SFC_CS_HOLD_MASK) \ 473 << SFC_CS_HOLD_SHIFT) \ 474 | (((cshi) & SFC_CS_HI_MASK) \ 475 << SFC_CS_HI_SHIFT) \ 476 | (((ins) & SFC_INS_MASK) \ 477 << SFC_INS_SHIFT)) 478 479 /* Magic settings from the Linux driver */ 480 481 #define CUSTOM_SPI_CS_SETUP 2 482 #define CUSTOM_SPI_CLK_HI 2 483 #define CUSTOM_SPI_CLK_LO 2 484 #define CUSTOM_SPI_CS_HOLD 2 485 #define CUSTOM_SPI_CS_HI 3 486 487 static int 488 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 489 { 490 uint32_t v; 491 int i; 492 493 AT_WRITE_4(sc, ATL2_SF_DATA, 0); 494 AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 495 496 v = SFC_WAIT_READY | 497 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 498 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 499 500 AT_WRITE_4(sc, ATL2_SFC, v); 501 v |= SFC_START; 502 AT_WRITE_4(sc, ATL2_SFC, v); 503 504 for (i = 0; i < 10; ++i) { 505 DELAY(1000); 506 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 507 break; 508 } 509 if (i == 10) 510 return EBUSY; 511 512 *val = AT_READ_4(sc, ATL2_SF_DATA); 513 return 0; 514 } 515 516 static int 517 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 518 { 519 uint32_t offset = 0x100; 520 uint32_t val, val1, addr0 = 0, addr1 = 0; 521 uint8_t found = 0; 522 523 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 524 offset += 4; 525 526 /* Each chunk of data starts with a signature */ 527 if ((val & 0xff) != 0x5a) 528 break; 529 if ((*sc->sc_memread)(sc, offset, &val1)) 530 break; 531 532 offset += 4; 533 534 val >>= 16; 535 switch (val) { 536 case ATL2_MAC_ADDR_0: 537 addr0 = val1; 538 ++found; 539 break; 540 case ATL2_MAC_ADDR_1: 541 addr1 = val1; 542 ++found; 543 break; 544 default: 545 continue; 546 } 547 } 548 549 if (found < 2) { 550 aprint_error_dev(sc->sc_dev, "error reading MAC address\n"); 551 return 1; 552 } 553 554 addr0 = htole32(addr0); 555 addr1 = htole32(addr1); 556 557 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 558 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 559 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 560 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 561 } 562 563 ea[0] = (addr1 & 0x0000ff00) >> 8; 564 ea[1] = (addr1 & 0x000000ff); 565 ea[2] = (addr0 & 0xff000000) >> 24; 566 ea[3] = (addr0 & 0x00ff0000) >> 16; 567 ea[4] = (addr0 & 0x0000ff00) >> 8; 568 ea[5] = (addr0 & 0x000000ff); 569 570 return 0; 571 } 572 573 static int 574 lii_mii_readreg(device_t dev, int phy, int reg) 575 { 576 struct lii_softc *sc = device_private(dev); 577 uint32_t val; 578 int i; 579 580 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 581 582 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 583 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 584 585 val |= MDIOC_READ; 586 587 AT_WRITE_4(sc, ATL2_MDIOC, val); 588 589 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 590 DELAY(2); 591 val = AT_READ_4(sc, ATL2_MDIOC); 592 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 593 break; 594 } 595 596 if (i == MDIO_WAIT_TIMES) 597 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 598 reg); 599 600 return (val & 0x0000ffff); 601 } 602 603 static void 604 lii_mii_writereg(device_t dev, int phy, int reg, int data) 605 { 606 struct lii_softc *sc = device_private(dev); 607 uint32_t val; 608 int i; 609 610 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 611 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 612 613 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 614 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 615 616 /* val |= MDIOC_WRITE; */ 617 618 AT_WRITE_4(sc, ATL2_MDIOC, val); 619 620 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 621 DELAY(2); 622 val = AT_READ_4(sc, ATL2_MDIOC); 623 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 624 break; 625 } 626 627 if (i == MDIO_WAIT_TIMES) 628 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 629 reg); 630 } 631 632 static void 633 lii_mii_statchg(device_t dev) 634 { 635 struct lii_softc *sc = device_private(dev); 636 uint32_t val; 637 638 DPRINTF(("lii_mii_statchg\n")); 639 640 val = AT_READ_4(sc, ATL2_MACC); 641 642 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 643 val |= MACC_FDX; 644 else 645 val &= ~MACC_FDX; 646 647 AT_WRITE_4(sc, ATL2_MACC, val); 648 } 649 650 static int 651 lii_media_change(struct ifnet *ifp) 652 { 653 struct lii_softc *sc = ifp->if_softc; 654 655 DPRINTF(("lii_media_change\n")); 656 657 if (ifp->if_flags & IFF_UP) 658 mii_mediachg(&sc->sc_mii); 659 return 0; 660 } 661 662 static void 663 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 664 { 665 struct lii_softc *sc = ifp->if_softc; 666 667 DPRINTF(("lii_media_status\n")); 668 669 mii_pollstat(&sc->sc_mii); 670 imr->ifm_status = sc->sc_mii.mii_media_status; 671 imr->ifm_active = sc->sc_mii.mii_media_active; 672 } 673 674 static int 675 lii_init(struct ifnet *ifp) 676 { 677 struct lii_softc *sc = ifp->if_softc; 678 uint32_t val; 679 int error; 680 681 DPRINTF(("lii_init\n")); 682 683 lii_stop(ifp, 0); 684 685 memset(sc->sc_ring, 0, sc->sc_ringsize); 686 687 /* Disable all interrupts */ 688 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 689 690 /* XXX endianness */ 691 AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 692 sc->sc_eaddr[2] << 24 | 693 sc->sc_eaddr[3] << 16 | 694 sc->sc_eaddr[4] << 8 | 695 sc->sc_eaddr[5]); 696 AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 697 sc->sc_eaddr[0] << 8 | 698 sc->sc_eaddr[1]); 699 700 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 701 /* XXX 702 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 703 */ 704 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 705 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 706 + AT_RXD_PADDING); 707 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 708 sc->sc_txsp & 0xffffffff); 709 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 710 sc->sc_txdp & 0xffffffff); 711 712 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 713 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 714 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 715 716 /* 717 * Inter Paket Gap Time = 0x60 (IPGT) 718 * Minimum inter-frame gap for RX = 0x50 (MIFG) 719 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 720 * 96-bit IPG window = 0x60 (IPGR2) 721 */ 722 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 723 724 /* 725 * Collision window = 0x37 (LCOL) 726 * Maximum # of retrans = 0xf (RETRY) 727 * Maximum binary expansion # = 0xa (ABEBT) 728 * IPG to start jam = 0x7 (JAMIPG) 729 */ 730 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 731 MHDC_EXC_DEF_EN); 732 733 /* 100 means 200us */ 734 AT_WRITE_2(sc, ATL2_IMTIV, 100); 735 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 736 737 /* 500000 means 100ms */ 738 AT_WRITE_2(sc, ATL2_IALTIV, 50000); 739 740 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 741 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 742 743 /* unit unknown for TX cur-through threshold */ 744 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 745 746 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 747 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 748 749 sc->sc_rxcur = 0; 750 sc->sc_txs_cur = sc->sc_txs_ack = 0; 751 sc->sc_txd_cur = sc->sc_txd_ack = 0; 752 sc->sc_free_tx_slots = true; 753 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 754 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 755 756 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 757 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 758 759 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 760 761 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 762 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 763 AT_WRITE_4(sc, ATL2_ISR, 0); 764 if (error) { 765 aprint_error_dev(sc->sc_dev, "init failed\n"); 766 goto out; 767 } 768 769 lii_setmulti(sc); 770 771 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 772 773 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 774 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 775 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 776 777 if (ifp->if_flags & IFF_PROMISC) 778 val |= MACC_PROMISC_EN; 779 else if (ifp->if_flags & IFF_ALLMULTI) 780 val |= MACC_ALLMULTI_EN; 781 782 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 783 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 784 785 AT_WRITE_4(sc, ATL2_MACC, val); 786 787 mii_mediachg(&sc->sc_mii); 788 789 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 790 791 callout_schedule(&sc->sc_tick_ch, hz); 792 793 ifp->if_flags |= IFF_RUNNING; 794 ifp->if_flags &= ~IFF_OACTIVE; 795 796 out: 797 return error; 798 } 799 800 static void 801 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 802 { 803 int left; 804 struct tx_pkt_header *tph = 805 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 806 807 memset(tph, 0, sizeof *tph); 808 tph->txph_size = m->m_pkthdr.len; 809 810 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 811 812 /* 813 * We already know we have enough space, so if there is a part of the 814 * space ahead of txd_cur that is active, it doesn't matter because 815 * left will be large enough even without it. 816 */ 817 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 818 819 if (left > m->m_pkthdr.len) { 820 m_copydata(m, 0, m->m_pkthdr.len, 821 sc->sc_txdbase + sc->sc_txd_cur); 822 sc->sc_txd_cur += m->m_pkthdr.len; 823 } else { 824 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 825 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 826 sc->sc_txd_cur = m->m_pkthdr.len - left; 827 } 828 829 /* Round to a 32-bit boundary */ 830 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 831 if (sc->sc_txd_cur == sc->sc_txd_ack) 832 sc->sc_free_tx_slots = false; 833 } 834 835 static int 836 lii_free_tx_space(struct lii_softc *sc) 837 { 838 int space; 839 840 if (sc->sc_txd_cur >= sc->sc_txd_ack) 841 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 842 sc->sc_txd_ack; 843 else 844 space = sc->sc_txd_ack - sc->sc_txd_cur; 845 846 /* Account for the tx_pkt_header */ 847 return (space - 4); 848 } 849 850 static void 851 lii_start(struct ifnet *ifp) 852 { 853 struct lii_softc *sc = ifp->if_softc; 854 struct mbuf *m0; 855 856 DPRINTF(("lii_start\n")); 857 858 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 859 return; 860 861 for (;;) { 862 IFQ_POLL(&ifp->if_snd, m0); 863 if (m0 == NULL) 864 break; 865 866 if (!sc->sc_free_tx_slots || 867 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 868 ifp->if_flags |= IFF_OACTIVE; 869 break; 870 } 871 872 lii_tx_put(sc, m0); 873 874 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 875 876 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 877 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 878 if (sc->sc_txs_cur == sc->sc_txs_ack) 879 sc->sc_free_tx_slots = false; 880 881 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 882 883 IFQ_DEQUEUE(&ifp->if_snd, m0); 884 885 #if NBPFILTER > 0 886 if (ifp->if_bpf != NULL) 887 bpf_mtap(ifp->if_bpf, m0); 888 #endif 889 m_freem(m0); 890 } 891 } 892 893 static void 894 lii_stop(struct ifnet *ifp, int disable) 895 { 896 struct lii_softc *sc = ifp->if_softc; 897 898 callout_stop(&sc->sc_tick_ch); 899 900 ifp->if_timer = 0; 901 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 902 903 mii_down(&sc->sc_mii); 904 905 lii_reset(sc); 906 907 AT_WRITE_4(sc, ATL2_IMR, 0); 908 } 909 910 static int 911 lii_intr(void *v) 912 { 913 struct lii_softc *sc = v; 914 uint32_t status; 915 916 status = AT_READ_4(sc, ATL2_ISR); 917 if (status == 0) 918 return 0; 919 920 DPRINTF(("lii_intr (%x)\n", status)); 921 922 /* Clear the interrupt and disable them */ 923 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 924 925 if (status & (ISR_PHY | ISR_MANUAL)) { 926 /* Ack PHY interrupt. Magic register */ 927 if (status & ISR_PHY) 928 (void)lii_mii_readreg(sc->sc_dev, 1, 19); 929 mii_mediachg(&sc->sc_mii); 930 } 931 932 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 933 lii_init(&sc->sc_ec.ec_if); 934 return 1; 935 } 936 937 if (status & ISR_RX_EVENT) { 938 #ifdef LII_DEBUG 939 if (!(status & ISR_RS_UPDATE)) 940 printf("rxintr %08x\n", status); 941 #endif 942 lii_rxintr(sc); 943 } 944 945 if (status & ISR_TX_EVENT) 946 lii_txintr(sc); 947 948 /* Re-enable interrupts */ 949 AT_WRITE_4(sc, ATL2_ISR, 0); 950 951 return 1; 952 } 953 954 static void 955 lii_rxintr(struct lii_softc *sc) 956 { 957 struct ifnet *ifp = &sc->sc_ec.ec_if; 958 struct rx_pkt *rxp; 959 struct mbuf *m; 960 uint16_t size; 961 962 DPRINTF(("lii_rxintr\n")); 963 964 for (;;) { 965 rxp = &sc->sc_rxp[sc->sc_rxcur]; 966 if (rxp->rxp_update == 0) 967 break; 968 969 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 970 rxp->rxp_size, rxp->rxp_flags)); 971 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 972 rxp->rxp_update = 0; 973 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 974 ++ifp->if_ierrors; 975 continue; 976 } 977 978 MGETHDR(m, M_DONTWAIT, MT_DATA); 979 if (m == NULL) { 980 ++ifp->if_ierrors; 981 continue; 982 } 983 size = rxp->rxp_size - ETHER_CRC_LEN; 984 if (size > MHLEN) { 985 MCLGET(m, M_DONTWAIT); 986 if ((m->m_flags & M_EXT) == 0) { 987 m_freem(m); 988 ++ifp->if_ierrors; 989 continue; 990 } 991 } 992 993 m->m_pkthdr.rcvif = ifp; 994 /* Copy the packet withhout the FCS */ 995 m->m_pkthdr.len = m->m_len = size; 996 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 997 ++ifp->if_ipackets; 998 999 #if NBPFILTER > 0 1000 if (ifp->if_bpf) 1001 bpf_mtap(ifp->if_bpf, m); 1002 #endif 1003 1004 (*ifp->if_input)(ifp, m); 1005 } 1006 1007 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1008 } 1009 1010 static void 1011 lii_txintr(struct lii_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->sc_ec.ec_if; 1014 struct tx_pkt_status *txs; 1015 struct tx_pkt_header *txph; 1016 1017 DPRINTF(("lii_txintr\n")); 1018 1019 for (;;) { 1020 txs = &sc->sc_txs[sc->sc_txs_ack]; 1021 if (txs->txps_update == 0) 1022 break; 1023 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1024 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1025 sc->sc_free_tx_slots = true; 1026 1027 txs->txps_update = 0; 1028 1029 txph = (struct tx_pkt_header *) 1030 (sc->sc_txdbase + sc->sc_txd_ack); 1031 1032 if (txph->txph_size != txs->txps_size) 1033 aprint_error_dev(sc->sc_dev, 1034 "mismatched status and packet\n"); 1035 /* 1036 * Move ack by the packet size, taking the packet header in 1037 * account and round to the next 32-bit boundary 1038 * (7 = sizeof(header) + 3) 1039 */ 1040 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1041 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1042 1043 if (txs->txps_flags & ATL2_TXF_SUCCESS) 1044 ++ifp->if_opackets; 1045 else 1046 ++ifp->if_oerrors; 1047 ifp->if_flags &= ~IFF_OACTIVE; 1048 } 1049 1050 if (sc->sc_free_tx_slots) 1051 lii_start(ifp); 1052 } 1053 1054 static int 1055 lii_alloc_rings(struct lii_softc *sc) 1056 { 1057 int nsegs; 1058 bus_size_t bs; 1059 1060 /* 1061 * We need a big chunk of DMA-friendly memory because descriptors 1062 * are not separate from data on that crappy hardware, which means 1063 * we'll have to copy data from and to that memory zone to and from 1064 * the mbufs. 1065 * 1066 * How lame is that? Using the default values from the Linux driver, 1067 * we allocate space for receiving up to 64 full-size Ethernet frames, 1068 * and only 8kb for transmitting up to 64 Ethernet frames. 1069 */ 1070 1071 sc->sc_ringsize = bs = AT_RXD_PADDING 1072 + AT_RXD_NUM * sizeof(struct rx_pkt) 1073 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1074 + AT_TXD_BUFFER_SIZE; 1075 1076 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1077 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1078 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1079 return 1; 1080 } 1081 1082 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1083 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1084 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1085 goto fail; 1086 } 1087 1088 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1089 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1090 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1091 goto fail1; 1092 } 1093 1094 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1095 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1096 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1097 goto fail2; 1098 } 1099 1100 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1101 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1102 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1103 sc->sc_txdbase = ((char *)sc->sc_txs) 1104 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1105 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1106 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1107 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1108 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1109 1110 return 0; 1111 1112 fail2: 1113 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1114 fail1: 1115 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1116 fail: 1117 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1118 return 1; 1119 } 1120 1121 static void 1122 lii_watchdog(struct ifnet *ifp) 1123 { 1124 struct lii_softc *sc = ifp->if_softc; 1125 1126 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1127 ++ifp->if_oerrors; 1128 lii_init(ifp); 1129 } 1130 1131 static int 1132 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1133 { 1134 struct lii_softc *sc = ifp->if_softc; 1135 int s, error; 1136 1137 s = splnet(); 1138 1139 switch(cmd) { 1140 case SIOCADDMULTI: 1141 case SIOCDELMULTI: 1142 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1143 if (ifp->if_flags & IFF_RUNNING) 1144 lii_setmulti(sc); 1145 error = 0; 1146 } 1147 break; 1148 case SIOCSIFMEDIA: 1149 case SIOCGIFMEDIA: 1150 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1151 &sc->sc_mii.mii_media, cmd); 1152 break; 1153 default: 1154 error = ether_ioctl(ifp, cmd, data); 1155 if (error == ENETRESET) { 1156 if (ifp->if_flags & IFF_RUNNING) 1157 lii_setmulti(sc); 1158 error = 0; 1159 } 1160 break; 1161 } 1162 1163 splx(s); 1164 1165 return error; 1166 } 1167 1168 static void 1169 lii_setmulti(struct lii_softc *sc) 1170 { 1171 struct ethercom *ec = &sc->sc_ec; 1172 struct ifnet *ifp = &ec->ec_if; 1173 uint32_t mht0 = 0, mht1 = 0, crc; 1174 struct ether_multi *enm; 1175 struct ether_multistep step; 1176 1177 /* Clear multicast hash table */ 1178 AT_WRITE_4(sc, ATL2_MHT, 0); 1179 AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1180 1181 ifp->if_flags &= ~IFF_ALLMULTI; 1182 1183 ETHER_FIRST_MULTI(step, ec, enm); 1184 while (enm != NULL) { 1185 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1186 ifp->if_flags |= IFF_ALLMULTI; 1187 mht0 = mht1 = 0; 1188 goto alldone; 1189 } 1190 1191 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1192 1193 if (crc & (1 << 31)) 1194 mht1 |= (1 << ((crc >> 26) & 0x0000001f)); 1195 else 1196 mht0 |= (1 << ((crc >> 26) & 0x0000001f)); 1197 1198 ETHER_NEXT_MULTI(step, enm); 1199 } 1200 1201 alldone: 1202 AT_WRITE_4(sc, ATL2_MHT, mht0); 1203 AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1204 } 1205 1206 static void 1207 lii_tick(void *v) 1208 { 1209 struct lii_softc *sc = v; 1210 int s; 1211 1212 s = splnet(); 1213 mii_tick(&sc->sc_mii); 1214 splx(s); 1215 1216 callout_schedule(&sc->sc_tick_ch, hz); 1217 } 1218