1 /* $NetBSD: if_lii.c,v 1.7 2009/09/05 14:09:55 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.7 2009/09/05 14:09:55 tsutsui Exp $"); 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/kernel.h> 44 #include <sys/sockio.h> 45 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 50 #if NBPFILTER > 0 51 #include <net/bpf.h> 52 #endif 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcidevs.h> 60 61 #include <dev/pci/if_liireg.h> 62 63 /* #define LII_DEBUG */ 64 #ifdef LII_DEBUG 65 #define DPRINTF(x) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 struct lii_softc { 71 device_t sc_dev; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 75 bus_space_tag_t sc_mmiot; 76 bus_space_handle_t sc_mmioh; 77 78 /* 79 * We allocate a big chunk of DMA-safe memory for all data exchanges. 80 * It is unfortunate that this chip doesn't seem to do scatter-gather. 81 */ 82 bus_dma_tag_t sc_dmat; 83 bus_dmamap_t sc_ringmap; 84 bus_dma_segment_t sc_ringseg; 85 86 uint8_t *sc_ring; /* the whole area */ 87 size_t sc_ringsize; 88 89 struct rx_pkt *sc_rxp; /* the part used for RX */ 90 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 91 bus_addr_t sc_txsp; 92 char *sc_txdbase; 93 bus_addr_t sc_txdp; 94 95 unsigned int sc_rxcur; 96 /* the active area is [ack; cur[ */ 97 int sc_txs_cur; 98 int sc_txs_ack; 99 int sc_txd_cur; 100 int sc_txd_ack; 101 bool sc_free_tx_slots; 102 103 void *sc_ih; 104 105 struct ethercom sc_ec; 106 struct mii_data sc_mii; 107 callout_t sc_tick_ch; 108 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 109 110 int (*sc_memread)(struct lii_softc *, uint32_t, 111 uint32_t *); 112 }; 113 114 static int lii_match(device_t, cfdata_t, void *); 115 static void lii_attach(device_t, device_t, void *); 116 117 static int lii_reset(struct lii_softc *); 118 static bool lii_eeprom_present(struct lii_softc *); 119 static int lii_read_macaddr(struct lii_softc *, uint8_t *); 120 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 121 static void lii_spi_configure(struct lii_softc *); 122 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 123 static void lii_setmulti(struct lii_softc *); 124 static void lii_tick(void *); 125 126 static int lii_alloc_rings(struct lii_softc *); 127 static int lii_free_tx_space(struct lii_softc *); 128 129 static int lii_mii_readreg(device_t, int, int); 130 static void lii_mii_writereg(device_t, int, int, int); 131 static void lii_mii_statchg(device_t); 132 133 static int lii_media_change(struct ifnet *); 134 static void lii_media_status(struct ifnet *, struct ifmediareq *); 135 136 static int lii_init(struct ifnet *); 137 static void lii_start(struct ifnet *); 138 static void lii_stop(struct ifnet *, int); 139 static void lii_watchdog(struct ifnet *); 140 static int lii_ioctl(struct ifnet *, u_long, void *); 141 142 static int lii_intr(void *); 143 static void lii_rxintr(struct lii_softc *); 144 static void lii_txintr(struct lii_softc *); 145 146 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 147 lii_match, lii_attach, NULL, NULL); 148 149 /* #define LII_DEBUG_REGS */ 150 #ifndef LII_DEBUG_REGS 151 #define AT_READ_4(sc,reg) \ 152 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 153 #define AT_READ_2(sc,reg) \ 154 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 155 #define AT_READ_1(sc,reg) \ 156 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 157 #define AT_WRITE_4(sc,reg,val) \ 158 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 159 #define AT_WRITE_2(sc,reg,val) \ 160 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 161 #define AT_WRITE_1(sc,reg,val) \ 162 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 163 #else 164 static inline uint32_t 165 AT_READ_4(struct lii_softc *sc, bus_size_t reg) 166 { 167 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 168 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 169 return r; 170 } 171 172 static inline uint16_t 173 AT_READ_2(struct lii_softc *sc, bus_size_t reg) 174 { 175 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 176 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 177 return r; 178 } 179 180 static inline uint8_t 181 AT_READ_1(struct lii_softc *sc, bus_size_t reg) 182 { 183 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 184 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 185 return r; 186 } 187 188 static inline void 189 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 190 { 191 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 192 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 193 } 194 195 static inline void 196 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 197 { 198 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 199 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 200 } 201 202 static inline void 203 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 204 { 205 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 206 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 207 } 208 #endif 209 210 /* 211 * Those are the default Linux parameters. 212 */ 213 214 #define AT_TXD_NUM 64 215 #define AT_TXD_BUFFER_SIZE 8192 216 #define AT_RXD_NUM 64 217 218 /* 219 * Assuming (you know what that word makes of you) the chunk of memory 220 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 221 * first 120 bytes of it, so that the space for the packets, and not the 222 * whole descriptors themselves, are on a 128-byte boundary. 223 */ 224 225 #define AT_RXD_PADDING 120 226 227 static int 228 lii_match(device_t parent, cfdata_t cfmatch, void *aux) 229 { 230 struct pci_attach_args *pa = aux; 231 232 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 233 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 234 } 235 236 static void 237 lii_attach(device_t parent, device_t self, void *aux) 238 { 239 struct lii_softc *sc = device_private(self); 240 struct pci_attach_args *pa = aux; 241 uint8_t eaddr[ETHER_ADDR_LEN]; 242 struct ifnet *ifp = &sc->sc_ec.ec_if; 243 pci_intr_handle_t ih; 244 const char *intrstr; 245 pcireg_t cmd; 246 bus_size_t memsize = 0; 247 248 aprint_naive("\n"); 249 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 250 251 sc->sc_dev = self; 252 sc->sc_pc = pa->pa_pc; 253 sc->sc_tag = pa->pa_tag; 254 sc->sc_dmat = pa->pa_dmat; 255 256 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 257 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 258 cmd &= ~PCI_COMMAND_IO_ENABLE; 259 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 260 261 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 262 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 263 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 264 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 265 break; 266 default: 267 aprint_error_dev(self, "invalid base address register\n"); 268 break; 269 } 270 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 271 &sc->sc_mmiot, &sc->sc_mmioh, NULL, &memsize) != 0) { 272 aprint_error_dev(self, "failed to map registers\n"); 273 return; 274 } 275 276 if (lii_reset(sc)) 277 return; 278 279 lii_spi_configure(sc); 280 281 if (lii_eeprom_present(sc)) 282 sc->sc_memread = lii_eeprom_read; 283 else 284 sc->sc_memread = lii_spi_read; 285 286 if (lii_read_macaddr(sc, eaddr)) 287 return; 288 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 289 290 aprint_normal_dev(self, "Ethernet address %s\n", 291 ether_sprintf(eaddr)); 292 293 if (pci_intr_map(pa, &ih) != 0) { 294 aprint_error_dev(self, "failed to map interrupt\n"); 295 goto fail; 296 } 297 intrstr = pci_intr_string(sc->sc_pc, ih); 298 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 299 if (sc->sc_ih == NULL) { 300 aprint_error_dev(self, "failed to establish interrupt"); 301 if (intrstr != NULL) 302 aprint_error(" at %s", intrstr); 303 aprint_error("\n"); 304 goto fail; 305 } 306 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 307 308 if (lii_alloc_rings(sc)) 309 goto fail; 310 311 callout_init(&sc->sc_tick_ch, 0); 312 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 313 314 sc->sc_mii.mii_ifp = ifp; 315 sc->sc_mii.mii_readreg = lii_mii_readreg; 316 sc->sc_mii.mii_writereg = lii_mii_writereg; 317 sc->sc_mii.mii_statchg = lii_mii_statchg; 318 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 319 lii_media_status); 320 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 321 MII_OFFSET_ANY, 0); 322 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 323 324 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 325 ifp->if_softc = sc; 326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 327 ifp->if_ioctl = lii_ioctl; 328 ifp->if_start = lii_start; 329 ifp->if_watchdog = lii_watchdog; 330 ifp->if_init = lii_init; 331 ifp->if_stop = lii_stop; 332 IFQ_SET_READY(&ifp->if_snd); 333 334 /* 335 * While the device does support HW VLAN tagging, there is no 336 * real point using that feature. 337 */ 338 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 339 340 if_attach(ifp); 341 ether_ifattach(ifp, eaddr); 342 343 if (pmf_device_register(self, NULL, NULL)) 344 pmf_class_network_register(self, ifp); 345 else 346 aprint_error_dev(self, "couldn't establish power handler\n"); 347 348 return; 349 350 fail: 351 if (sc->sc_ih != NULL) { 352 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 353 sc->sc_ih = NULL; 354 } 355 if (memsize) 356 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, memsize); 357 } 358 359 static int 360 lii_reset(struct lii_softc *sc) 361 { 362 int i; 363 364 DPRINTF(("lii_reset\n")); 365 366 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 367 DELAY(1000); 368 369 for (i = 0; i < 10; ++i) { 370 if (AT_READ_4(sc, ATL2_BIS) == 0) 371 break; 372 DELAY(1000); 373 } 374 375 if (i == 10) { 376 aprint_error_dev(sc->sc_dev, "reset failed\n"); 377 return 1; 378 } 379 380 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 381 DELAY(10); 382 383 /* Init PCI-Express module */ 384 /* Magic Numbers Warning */ 385 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 386 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 387 388 return 0; 389 } 390 391 static bool 392 lii_eeprom_present(struct lii_softc *sc) 393 { 394 /* 395 * The Linux driver does this, but then it has a very weird way of 396 * checking whether the PCI configuration space exposes the Vital 397 * Product Data capability, so maybe it's not really needed. 398 */ 399 400 #ifdef weirdloonix 401 uint32_t val; 402 403 val = AT_READ_4(sc, ATL2_SFC); 404 if (val & SFC_EN_VPD) 405 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 406 #endif 407 408 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 409 NULL, NULL) == 1; 410 } 411 412 static int 413 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 414 { 415 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 416 417 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 418 419 return r; 420 } 421 422 static void 423 lii_spi_configure(struct lii_softc *sc) 424 { 425 /* 426 * We don't offer a way to configure the SPI Flash vendor parameter, so 427 * the table is given for reference 428 */ 429 static const struct lii_spi_flash_vendor { 430 const char *sfv_name; 431 const uint8_t sfv_opcodes[9]; 432 } lii_sfv[] = { 433 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 434 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 435 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 436 }; 437 #define SF_OPCODE_WRSR 0 438 #define SF_OPCODE_READ 1 439 #define SF_OPCODE_PRGM 2 440 #define SF_OPCODE_WREN 3 441 #define SF_OPCODE_WRDI 4 442 #define SF_OPCODE_RDSR 5 443 #define SF_OPCODE_RDID 6 444 #define SF_OPCODE_SECT_ER 7 445 #define SF_OPCODE_CHIP_ER 8 446 447 #define SF_DEFAULT_VENDOR 0 448 static const uint8_t vendor = SF_DEFAULT_VENDOR; 449 450 /* 451 * Why isn't WRDI used? Heck if I know. 452 */ 453 454 AT_WRITE_1(sc, ATL2_SFOP_WRSR, 455 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 456 AT_WRITE_1(sc, ATL2_SFOP_READ, 457 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 458 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 459 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 460 AT_WRITE_1(sc, ATL2_SFOP_WREN, 461 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 462 AT_WRITE_1(sc, ATL2_SFOP_RDSR, 463 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 464 AT_WRITE_1(sc, ATL2_SFOP_RDID, 465 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 466 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 467 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 468 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 469 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 470 } 471 472 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 473 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 474 << SFC_CS_SETUP_SHIFT) \ 475 | (((clkhi) & SFC_CLK_HI_MASK) \ 476 << SFC_CLK_HI_SHIFT) \ 477 | (((clklo) & SFC_CLK_LO_MASK) \ 478 << SFC_CLK_LO_SHIFT) \ 479 | (((cshold) & SFC_CS_HOLD_MASK) \ 480 << SFC_CS_HOLD_SHIFT) \ 481 | (((cshi) & SFC_CS_HI_MASK) \ 482 << SFC_CS_HI_SHIFT) \ 483 | (((ins) & SFC_INS_MASK) \ 484 << SFC_INS_SHIFT)) 485 486 /* Magic settings from the Linux driver */ 487 488 #define CUSTOM_SPI_CS_SETUP 2 489 #define CUSTOM_SPI_CLK_HI 2 490 #define CUSTOM_SPI_CLK_LO 2 491 #define CUSTOM_SPI_CS_HOLD 2 492 #define CUSTOM_SPI_CS_HI 3 493 494 static int 495 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 496 { 497 uint32_t v; 498 int i; 499 500 AT_WRITE_4(sc, ATL2_SF_DATA, 0); 501 AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 502 503 v = SFC_WAIT_READY | 504 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 505 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 506 507 AT_WRITE_4(sc, ATL2_SFC, v); 508 v |= SFC_START; 509 AT_WRITE_4(sc, ATL2_SFC, v); 510 511 for (i = 0; i < 10; ++i) { 512 DELAY(1000); 513 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 514 break; 515 } 516 if (i == 10) 517 return EBUSY; 518 519 *val = AT_READ_4(sc, ATL2_SF_DATA); 520 return 0; 521 } 522 523 static int 524 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 525 { 526 uint32_t offset = 0x100; 527 uint32_t val, val1, addr0 = 0, addr1 = 0; 528 uint8_t found = 0; 529 530 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 531 offset += 4; 532 533 /* Each chunk of data starts with a signature */ 534 if ((val & 0xff) != 0x5a) 535 break; 536 if ((*sc->sc_memread)(sc, offset, &val1)) 537 break; 538 539 offset += 4; 540 541 val >>= 16; 542 switch (val) { 543 case ATL2_MAC_ADDR_0: 544 addr0 = val1; 545 ++found; 546 break; 547 case ATL2_MAC_ADDR_1: 548 addr1 = val1; 549 ++found; 550 break; 551 default: 552 continue; 553 } 554 } 555 556 if (found < 2) { 557 aprint_error_dev(sc->sc_dev, "error reading MAC address\n"); 558 return 1; 559 } 560 561 addr0 = htole32(addr0); 562 addr1 = htole32(addr1); 563 564 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 565 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 566 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 567 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 568 } 569 570 ea[0] = (addr1 & 0x0000ff00) >> 8; 571 ea[1] = (addr1 & 0x000000ff); 572 ea[2] = (addr0 & 0xff000000) >> 24; 573 ea[3] = (addr0 & 0x00ff0000) >> 16; 574 ea[4] = (addr0 & 0x0000ff00) >> 8; 575 ea[5] = (addr0 & 0x000000ff); 576 577 return 0; 578 } 579 580 static int 581 lii_mii_readreg(device_t dev, int phy, int reg) 582 { 583 struct lii_softc *sc = device_private(dev); 584 uint32_t val; 585 int i; 586 587 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 588 589 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 590 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 591 592 val |= MDIOC_READ; 593 594 AT_WRITE_4(sc, ATL2_MDIOC, val); 595 596 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 597 DELAY(2); 598 val = AT_READ_4(sc, ATL2_MDIOC); 599 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 600 break; 601 } 602 603 if (i == MDIO_WAIT_TIMES) 604 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 605 reg); 606 607 return (val & 0x0000ffff); 608 } 609 610 static void 611 lii_mii_writereg(device_t dev, int phy, int reg, int data) 612 { 613 struct lii_softc *sc = device_private(dev); 614 uint32_t val; 615 int i; 616 617 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 618 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 619 620 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 621 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 622 623 /* val |= MDIOC_WRITE; */ 624 625 AT_WRITE_4(sc, ATL2_MDIOC, val); 626 627 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 628 DELAY(2); 629 val = AT_READ_4(sc, ATL2_MDIOC); 630 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 631 break; 632 } 633 634 if (i == MDIO_WAIT_TIMES) 635 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 636 reg); 637 } 638 639 static void 640 lii_mii_statchg(device_t dev) 641 { 642 struct lii_softc *sc = device_private(dev); 643 uint32_t val; 644 645 DPRINTF(("lii_mii_statchg\n")); 646 647 val = AT_READ_4(sc, ATL2_MACC); 648 649 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 650 val |= MACC_FDX; 651 else 652 val &= ~MACC_FDX; 653 654 AT_WRITE_4(sc, ATL2_MACC, val); 655 } 656 657 static int 658 lii_media_change(struct ifnet *ifp) 659 { 660 struct lii_softc *sc = ifp->if_softc; 661 662 DPRINTF(("lii_media_change\n")); 663 664 if (ifp->if_flags & IFF_UP) 665 mii_mediachg(&sc->sc_mii); 666 return 0; 667 } 668 669 static void 670 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 671 { 672 struct lii_softc *sc = ifp->if_softc; 673 674 DPRINTF(("lii_media_status\n")); 675 676 mii_pollstat(&sc->sc_mii); 677 imr->ifm_status = sc->sc_mii.mii_media_status; 678 imr->ifm_active = sc->sc_mii.mii_media_active; 679 } 680 681 static int 682 lii_init(struct ifnet *ifp) 683 { 684 struct lii_softc *sc = ifp->if_softc; 685 uint32_t val; 686 int error; 687 688 DPRINTF(("lii_init\n")); 689 690 lii_stop(ifp, 0); 691 692 memset(sc->sc_ring, 0, sc->sc_ringsize); 693 694 /* Disable all interrupts */ 695 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 696 697 /* XXX endianness */ 698 AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 699 sc->sc_eaddr[2] << 24 | 700 sc->sc_eaddr[3] << 16 | 701 sc->sc_eaddr[4] << 8 | 702 sc->sc_eaddr[5]); 703 AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 704 sc->sc_eaddr[0] << 8 | 705 sc->sc_eaddr[1]); 706 707 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 708 /* XXX 709 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 710 */ 711 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 712 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 713 + AT_RXD_PADDING); 714 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 715 sc->sc_txsp & 0xffffffff); 716 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 717 sc->sc_txdp & 0xffffffff); 718 719 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 720 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 721 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 722 723 /* 724 * Inter Paket Gap Time = 0x60 (IPGT) 725 * Minimum inter-frame gap for RX = 0x50 (MIFG) 726 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 727 * 96-bit IPG window = 0x60 (IPGR2) 728 */ 729 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 730 731 /* 732 * Collision window = 0x37 (LCOL) 733 * Maximum # of retrans = 0xf (RETRY) 734 * Maximum binary expansion # = 0xa (ABEBT) 735 * IPG to start jam = 0x7 (JAMIPG) 736 */ 737 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 738 MHDC_EXC_DEF_EN); 739 740 /* 100 means 200us */ 741 AT_WRITE_2(sc, ATL2_IMTIV, 100); 742 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 743 744 /* 500000 means 100ms */ 745 AT_WRITE_2(sc, ATL2_IALTIV, 50000); 746 747 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 748 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 749 750 /* unit unknown for TX cur-through threshold */ 751 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 752 753 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 754 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 755 756 sc->sc_rxcur = 0; 757 sc->sc_txs_cur = sc->sc_txs_ack = 0; 758 sc->sc_txd_cur = sc->sc_txd_ack = 0; 759 sc->sc_free_tx_slots = true; 760 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 761 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 762 763 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 764 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 765 766 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 767 768 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 769 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 770 AT_WRITE_4(sc, ATL2_ISR, 0); 771 if (error) { 772 aprint_error_dev(sc->sc_dev, "init failed\n"); 773 goto out; 774 } 775 776 lii_setmulti(sc); 777 778 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 779 780 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 781 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 782 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 783 784 if (ifp->if_flags & IFF_PROMISC) 785 val |= MACC_PROMISC_EN; 786 else if (ifp->if_flags & IFF_ALLMULTI) 787 val |= MACC_ALLMULTI_EN; 788 789 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 790 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 791 792 AT_WRITE_4(sc, ATL2_MACC, val); 793 794 mii_mediachg(&sc->sc_mii); 795 796 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 797 798 callout_schedule(&sc->sc_tick_ch, hz); 799 800 ifp->if_flags |= IFF_RUNNING; 801 ifp->if_flags &= ~IFF_OACTIVE; 802 803 out: 804 return error; 805 } 806 807 static void 808 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 809 { 810 int left; 811 struct tx_pkt_header *tph = 812 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 813 814 memset(tph, 0, sizeof *tph); 815 tph->txph_size = m->m_pkthdr.len; 816 817 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 818 819 /* 820 * We already know we have enough space, so if there is a part of the 821 * space ahead of txd_cur that is active, it doesn't matter because 822 * left will be large enough even without it. 823 */ 824 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 825 826 if (left > m->m_pkthdr.len) { 827 m_copydata(m, 0, m->m_pkthdr.len, 828 sc->sc_txdbase + sc->sc_txd_cur); 829 sc->sc_txd_cur += m->m_pkthdr.len; 830 } else { 831 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 832 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 833 sc->sc_txd_cur = m->m_pkthdr.len - left; 834 } 835 836 /* Round to a 32-bit boundary */ 837 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 838 if (sc->sc_txd_cur == sc->sc_txd_ack) 839 sc->sc_free_tx_slots = false; 840 } 841 842 static int 843 lii_free_tx_space(struct lii_softc *sc) 844 { 845 int space; 846 847 if (sc->sc_txd_cur >= sc->sc_txd_ack) 848 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 849 sc->sc_txd_ack; 850 else 851 space = sc->sc_txd_ack - sc->sc_txd_cur; 852 853 /* Account for the tx_pkt_header */ 854 return (space - 4); 855 } 856 857 static void 858 lii_start(struct ifnet *ifp) 859 { 860 struct lii_softc *sc = ifp->if_softc; 861 struct mbuf *m0; 862 863 DPRINTF(("lii_start\n")); 864 865 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 866 return; 867 868 for (;;) { 869 IFQ_POLL(&ifp->if_snd, m0); 870 if (m0 == NULL) 871 break; 872 873 if (!sc->sc_free_tx_slots || 874 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 875 ifp->if_flags |= IFF_OACTIVE; 876 break; 877 } 878 879 lii_tx_put(sc, m0); 880 881 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 882 883 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 884 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 885 if (sc->sc_txs_cur == sc->sc_txs_ack) 886 sc->sc_free_tx_slots = false; 887 888 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 889 890 IFQ_DEQUEUE(&ifp->if_snd, m0); 891 892 #if NBPFILTER > 0 893 if (ifp->if_bpf != NULL) 894 bpf_mtap(ifp->if_bpf, m0); 895 #endif 896 m_freem(m0); 897 } 898 } 899 900 static void 901 lii_stop(struct ifnet *ifp, int disable) 902 { 903 struct lii_softc *sc = ifp->if_softc; 904 905 callout_stop(&sc->sc_tick_ch); 906 907 ifp->if_timer = 0; 908 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 909 910 mii_down(&sc->sc_mii); 911 912 lii_reset(sc); 913 914 AT_WRITE_4(sc, ATL2_IMR, 0); 915 } 916 917 static int 918 lii_intr(void *v) 919 { 920 struct lii_softc *sc = v; 921 uint32_t status; 922 923 status = AT_READ_4(sc, ATL2_ISR); 924 if (status == 0) 925 return 0; 926 927 DPRINTF(("lii_intr (%x)\n", status)); 928 929 /* Clear the interrupt and disable them */ 930 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 931 932 if (status & (ISR_PHY | ISR_MANUAL)) { 933 /* Ack PHY interrupt. Magic register */ 934 if (status & ISR_PHY) 935 (void)lii_mii_readreg(sc->sc_dev, 1, 19); 936 mii_mediachg(&sc->sc_mii); 937 } 938 939 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 940 lii_init(&sc->sc_ec.ec_if); 941 return 1; 942 } 943 944 if (status & ISR_RX_EVENT) { 945 #ifdef LII_DEBUG 946 if (!(status & ISR_RS_UPDATE)) 947 printf("rxintr %08x\n", status); 948 #endif 949 lii_rxintr(sc); 950 } 951 952 if (status & ISR_TX_EVENT) 953 lii_txintr(sc); 954 955 /* Re-enable interrupts */ 956 AT_WRITE_4(sc, ATL2_ISR, 0); 957 958 return 1; 959 } 960 961 static void 962 lii_rxintr(struct lii_softc *sc) 963 { 964 struct ifnet *ifp = &sc->sc_ec.ec_if; 965 struct rx_pkt *rxp; 966 struct mbuf *m; 967 uint16_t size; 968 969 DPRINTF(("lii_rxintr\n")); 970 971 for (;;) { 972 rxp = &sc->sc_rxp[sc->sc_rxcur]; 973 if (rxp->rxp_update == 0) 974 break; 975 976 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 977 rxp->rxp_size, rxp->rxp_flags)); 978 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 979 rxp->rxp_update = 0; 980 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 981 ++ifp->if_ierrors; 982 continue; 983 } 984 985 MGETHDR(m, M_DONTWAIT, MT_DATA); 986 if (m == NULL) { 987 ++ifp->if_ierrors; 988 continue; 989 } 990 size = rxp->rxp_size - ETHER_CRC_LEN; 991 if (size > MHLEN) { 992 MCLGET(m, M_DONTWAIT); 993 if ((m->m_flags & M_EXT) == 0) { 994 m_freem(m); 995 ++ifp->if_ierrors; 996 continue; 997 } 998 } 999 1000 m->m_pkthdr.rcvif = ifp; 1001 /* Copy the packet withhout the FCS */ 1002 m->m_pkthdr.len = m->m_len = size; 1003 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 1004 ++ifp->if_ipackets; 1005 1006 #if NBPFILTER > 0 1007 if (ifp->if_bpf) 1008 bpf_mtap(ifp->if_bpf, m); 1009 #endif 1010 1011 (*ifp->if_input)(ifp, m); 1012 } 1013 1014 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1015 } 1016 1017 static void 1018 lii_txintr(struct lii_softc *sc) 1019 { 1020 struct ifnet *ifp = &sc->sc_ec.ec_if; 1021 struct tx_pkt_status *txs; 1022 struct tx_pkt_header *txph; 1023 1024 DPRINTF(("lii_txintr\n")); 1025 1026 for (;;) { 1027 txs = &sc->sc_txs[sc->sc_txs_ack]; 1028 if (txs->txps_update == 0) 1029 break; 1030 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1031 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1032 sc->sc_free_tx_slots = true; 1033 1034 txs->txps_update = 0; 1035 1036 txph = (struct tx_pkt_header *) 1037 (sc->sc_txdbase + sc->sc_txd_ack); 1038 1039 if (txph->txph_size != txs->txps_size) 1040 aprint_error_dev(sc->sc_dev, 1041 "mismatched status and packet\n"); 1042 /* 1043 * Move ack by the packet size, taking the packet header in 1044 * account and round to the next 32-bit boundary 1045 * (7 = sizeof(header) + 3) 1046 */ 1047 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1048 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1049 1050 if (txs->txps_flags & ATL2_TXF_SUCCESS) 1051 ++ifp->if_opackets; 1052 else 1053 ++ifp->if_oerrors; 1054 ifp->if_flags &= ~IFF_OACTIVE; 1055 } 1056 1057 if (sc->sc_free_tx_slots) 1058 lii_start(ifp); 1059 } 1060 1061 static int 1062 lii_alloc_rings(struct lii_softc *sc) 1063 { 1064 int nsegs; 1065 bus_size_t bs; 1066 1067 /* 1068 * We need a big chunk of DMA-friendly memory because descriptors 1069 * are not separate from data on that crappy hardware, which means 1070 * we'll have to copy data from and to that memory zone to and from 1071 * the mbufs. 1072 * 1073 * How lame is that? Using the default values from the Linux driver, 1074 * we allocate space for receiving up to 64 full-size Ethernet frames, 1075 * and only 8kb for transmitting up to 64 Ethernet frames. 1076 */ 1077 1078 sc->sc_ringsize = bs = AT_RXD_PADDING 1079 + AT_RXD_NUM * sizeof(struct rx_pkt) 1080 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1081 + AT_TXD_BUFFER_SIZE; 1082 1083 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1084 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1085 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1086 return 1; 1087 } 1088 1089 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1090 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1091 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1092 goto fail; 1093 } 1094 1095 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1096 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1097 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1098 goto fail1; 1099 } 1100 1101 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1102 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1103 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1104 goto fail2; 1105 } 1106 1107 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1108 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1109 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1110 sc->sc_txdbase = ((char *)sc->sc_txs) 1111 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1112 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1113 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1114 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1115 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1116 1117 return 0; 1118 1119 fail2: 1120 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1121 fail1: 1122 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1123 fail: 1124 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1125 return 1; 1126 } 1127 1128 static void 1129 lii_watchdog(struct ifnet *ifp) 1130 { 1131 struct lii_softc *sc = ifp->if_softc; 1132 1133 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1134 ++ifp->if_oerrors; 1135 lii_init(ifp); 1136 } 1137 1138 static int 1139 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1140 { 1141 struct lii_softc *sc = ifp->if_softc; 1142 int s, error; 1143 1144 s = splnet(); 1145 1146 switch(cmd) { 1147 case SIOCADDMULTI: 1148 case SIOCDELMULTI: 1149 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1150 if (ifp->if_flags & IFF_RUNNING) 1151 lii_setmulti(sc); 1152 error = 0; 1153 } 1154 break; 1155 case SIOCSIFMEDIA: 1156 case SIOCGIFMEDIA: 1157 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1158 &sc->sc_mii.mii_media, cmd); 1159 break; 1160 default: 1161 error = ether_ioctl(ifp, cmd, data); 1162 if (error == ENETRESET) { 1163 if (ifp->if_flags & IFF_RUNNING) 1164 lii_setmulti(sc); 1165 error = 0; 1166 } 1167 break; 1168 } 1169 1170 splx(s); 1171 1172 return error; 1173 } 1174 1175 static void 1176 lii_setmulti(struct lii_softc *sc) 1177 { 1178 struct ethercom *ec = &sc->sc_ec; 1179 struct ifnet *ifp = &ec->ec_if; 1180 uint32_t mht0 = 0, mht1 = 0, crc; 1181 struct ether_multi *enm; 1182 struct ether_multistep step; 1183 1184 /* Clear multicast hash table */ 1185 AT_WRITE_4(sc, ATL2_MHT, 0); 1186 AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1187 1188 ifp->if_flags &= ~IFF_ALLMULTI; 1189 1190 ETHER_FIRST_MULTI(step, ec, enm); 1191 while (enm != NULL) { 1192 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1193 ifp->if_flags |= IFF_ALLMULTI; 1194 mht0 = mht1 = 0; 1195 goto alldone; 1196 } 1197 1198 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1199 1200 if (crc & (1 << 31)) 1201 mht1 |= (1 << ((crc >> 26) & 0x0000001f)); 1202 else 1203 mht0 |= (1 << ((crc >> 26) & 0x0000001f)); 1204 1205 ETHER_NEXT_MULTI(step, enm); 1206 } 1207 1208 alldone: 1209 AT_WRITE_4(sc, ATL2_MHT, mht0); 1210 AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1211 } 1212 1213 static void 1214 lii_tick(void *v) 1215 { 1216 struct lii_softc *sc = v; 1217 int s; 1218 1219 s = splnet(); 1220 mii_tick(&sc->sc_mii); 1221 splx(s); 1222 1223 callout_schedule(&sc->sc_tick_ch, hz); 1224 } 1225