1 /* $NetBSD: if_jme.c,v 1.43 2019/05/28 07:41:49 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.43 2019/05/28 07:41:49 msaitoh Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/if_dl.h> 82 #include <net/route.h> 83 #include <net/netisr.h> 84 #include <net/bpf.h> 85 86 #include <sys/rndsource.h> 87 88 #include <netinet/in.h> 89 #include <netinet/in_systm.h> 90 #include <netinet/ip.h> 91 92 #ifdef INET 93 #include <netinet/in_var.h> 94 #endif 95 96 #include <netinet/tcp.h> 97 98 #include <net/if_ether.h> 99 #if defined(INET) 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/if_jmereg.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 struct jme_product_desc { 115 uint32_t jme_product; 116 const char *jme_desc; 117 }; 118 119 /* number of entries in transmit and receive rings */ 120 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 121 122 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 123 124 /* Water mark to kick reclaiming Tx buffers. */ 125 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 126 127 128 struct jme_softc { 129 device_t jme_dev; /* base device */ 130 bus_space_tag_t jme_bt_mac; 131 bus_space_handle_t jme_bh_mac; /* Mac registers */ 132 bus_space_tag_t jme_bt_phy; 133 bus_space_handle_t jme_bh_phy; /* PHY registers */ 134 bus_space_tag_t jme_bt_misc; 135 bus_space_handle_t jme_bh_misc; /* Misc registers */ 136 bus_dma_tag_t jme_dmatag; 137 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 138 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 139 struct jme_desc* jme_txring; /* transmit ring */ 140 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 141 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 142 int jme_tx_cons; /* transmit ring consumer */ 143 int jme_tx_prod; /* transmit ring producer */ 144 int jme_tx_cnt; /* transmit ring active count */ 145 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 146 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 147 struct jme_desc* jme_rxring; /* receive ring */ 148 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 149 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 150 int jme_rx_cons; /* receive ring consumer */ 151 int jme_rx_prod; /* receive ring producer */ 152 void* jme_ih; /* our interrupt */ 153 struct ethercom jme_ec; 154 struct callout jme_tick_ch; /* tick callout */ 155 uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 156 uint8_t jme_phyaddr; /* address of integrated phy */ 157 uint8_t jme_chip_rev; /* chip revision */ 158 uint8_t jme_rev; /* PCI revision */ 159 mii_data_t jme_mii; /* mii bus */ 160 uint32_t jme_flags; /* device features, see below */ 161 uint32_t jme_txcsr; /* TX config register */ 162 uint32_t jme_rxcsr; /* RX config register */ 163 krndsource_t rnd_source; 164 /* interrupt coalition parameters */ 165 struct sysctllog *jme_clog; 166 int jme_intrxto; /* interrupt RX timeout */ 167 int jme_intrxct; /* interrupt RX packets counter */ 168 int jme_inttxto; /* interrupt TX timeout */ 169 int jme_inttxct; /* interrupt TX packets counter */ 170 }; 171 172 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 173 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 174 175 176 #define jme_if jme_ec.ec_if 177 #define jme_bpf jme_if.if_bpf 178 179 typedef struct jme_softc jme_softc_t; 180 typedef u_long ioctl_cmd_t; 181 182 static int jme_pci_match(device_t, cfdata_t, void *); 183 static void jme_pci_attach(device_t, device_t, void *); 184 static void jme_intr_rx(jme_softc_t *); 185 static int jme_intr(void *); 186 187 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 188 static int jme_mediachange(struct ifnet *); 189 static void jme_ifwatchdog(struct ifnet *); 190 static bool jme_shutdown(device_t, int); 191 192 static void jme_txeof(struct jme_softc *); 193 static void jme_ifstart(struct ifnet *); 194 static void jme_reset(jme_softc_t *); 195 static int jme_ifinit(struct ifnet *); 196 static int jme_init(struct ifnet *, int); 197 static void jme_stop(struct ifnet *, int); 198 // static void jme_restart(void *); 199 static void jme_ticks(void *); 200 static void jme_mac_config(jme_softc_t *); 201 static void jme_set_filter(jme_softc_t *); 202 203 int jme_mii_read(device_t, int, int, uint16_t *); 204 int jme_mii_write(device_t, int, int, uint16_t); 205 void jme_statchg(struct ifnet *); 206 207 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 208 static int jme_eeprom_macaddr(struct jme_softc *); 209 static int jme_reg_macaddr(struct jme_softc *); 210 211 #define JME_TIMEOUT 1000 212 #define JME_PHY_TIMEOUT 1000 213 #define JME_EEPROM_TIMEOUT 1000 214 215 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 216 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 217 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 218 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 219 static int jme_root_num; 220 221 222 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 223 jme_pci_match, jme_pci_attach, NULL, NULL); 224 225 static const struct jme_product_desc jme_products[] = { 226 { PCI_PRODUCT_JMICRON_JMC250, 227 "JMicron JMC250 Gigabit Ethernet Controller" }, 228 { PCI_PRODUCT_JMICRON_JMC260, 229 "JMicron JMC260 Gigabit Ethernet Controller" }, 230 { 0, NULL }, 231 }; 232 233 static const struct jme_product_desc *jme_lookup_product(uint32_t); 234 235 static const struct jme_product_desc * 236 jme_lookup_product(uint32_t id) 237 { 238 const struct jme_product_desc *jp; 239 240 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 241 if (PCI_PRODUCT(id) == jp->jme_product) 242 return jp; 243 244 return NULL; 245 } 246 247 static int 248 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 249 { 250 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 251 252 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 253 return 0; 254 255 if (jme_lookup_product(pa->pa_id) != NULL) 256 return 1; 257 258 return 0; 259 } 260 261 static void 262 jme_pci_attach(device_t parent, device_t self, void *aux) 263 { 264 jme_softc_t *sc = device_private(self); 265 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 266 const struct jme_product_desc *jp; 267 struct ifnet * const ifp = &sc->jme_if; 268 struct mii_data * const mii = &sc->jme_mii; 269 bus_space_tag_t iot1, iot2, memt; 270 bus_space_handle_t ioh1, ioh2, memh; 271 bus_size_t size, size2; 272 pci_intr_handle_t intrhandle; 273 const char *intrstr; 274 pcireg_t csr; 275 int nsegs, i; 276 const struct sysctlnode *node; 277 int jme_nodenum; 278 char intrbuf[PCI_INTRSTR_LEN]; 279 280 sc->jme_dev = self; 281 aprint_normal("\n"); 282 callout_init(&sc->jme_tick_ch, 0); 283 284 jp = jme_lookup_product(pa->pa_id); 285 if (jp == NULL) 286 panic("jme_pci_attach: impossible"); 287 288 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 289 sc->jme_flags = JME_FLAG_GIGA; 290 291 /* 292 * Map the card space. Try Mem first. 293 */ 294 if (pci_mapreg_map(pa, JME_PCI_BAR0, 295 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 296 0, &memt, &memh, NULL, &size) == 0) { 297 sc->jme_bt_mac = memt; 298 sc->jme_bh_mac = memh; 299 sc->jme_bt_phy = memt; 300 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 301 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 302 aprint_error_dev(self, "can't subregion PHY space\n"); 303 bus_space_unmap(memt, memh, size); 304 return; 305 } 306 sc->jme_bt_misc = memt; 307 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 308 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 309 aprint_error_dev(self, "can't subregion misc space\n"); 310 bus_space_unmap(memt, memh, size); 311 return; 312 } 313 } else { 314 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 315 0, &iot1, &ioh1, NULL, &size) != 0) { 316 aprint_error_dev(self, "can't map I/O space 1\n"); 317 return; 318 } 319 sc->jme_bt_mac = iot1; 320 sc->jme_bh_mac = ioh1; 321 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 322 0, &iot2, &ioh2, NULL, &size2) != 0) { 323 aprint_error_dev(self, "can't map I/O space 2\n"); 324 bus_space_unmap(iot1, ioh1, size); 325 return; 326 } 327 sc->jme_bt_phy = iot2; 328 sc->jme_bh_phy = ioh2; 329 sc->jme_bt_misc = iot2; 330 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 331 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 332 aprint_error_dev(self, "can't subregion misc space\n"); 333 bus_space_unmap(iot1, ioh1, size); 334 bus_space_unmap(iot2, ioh2, size2); 335 return; 336 } 337 } 338 339 if (pci_dma64_available(pa)) 340 sc->jme_dmatag = pa->pa_dmat64; 341 else 342 sc->jme_dmatag = pa->pa_dmat; 343 344 /* Enable the device. */ 345 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 346 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 347 csr | PCI_COMMAND_MASTER_ENABLE); 348 349 aprint_normal_dev(self, "%s\n", jp->jme_desc); 350 351 sc->jme_rev = PCI_REVISION(pa->pa_class); 352 353 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 354 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 355 CHIPMODE_NOT_FPGA) 356 sc->jme_flags |= JME_FLAG_FPGA; 357 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 358 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 359 "0x%x", sc->jme_rev, sc->jme_chip_rev); 360 if (sc->jme_flags & JME_FLAG_FPGA) 361 aprint_verbose(" FPGA revision: 0x%x", 362 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 363 aprint_verbose("\n"); 364 365 /* 366 * Save PHY address. 367 * Integrated JR0211 has fixed PHY address whereas FPGA version 368 * requires PHY probing to get correct PHY address. 369 */ 370 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 371 sc->jme_phyaddr = 372 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 373 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 374 } else 375 sc->jme_phyaddr = 0; 376 377 378 jme_reset(sc); 379 380 /* read mac addr */ 381 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 382 aprint_error_dev(self, "error reading Ethernet address\n"); 383 /* return; */ 384 } 385 aprint_normal_dev(self, "Ethernet address %s\n", 386 ether_sprintf(sc->jme_enaddr)); 387 388 /* Map and establish interrupts */ 389 if (pci_intr_map(pa, &intrhandle)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 394 sc->jme_if.if_softc = sc; 395 sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 396 jme_intr, sc, device_xname(self)); 397 if (sc->jme_ih == NULL) { 398 aprint_error_dev(self, "couldn't establish interrupt"); 399 if (intrstr != NULL) 400 aprint_error(" at %s", intrstr); 401 aprint_error("\n"); 402 return; 403 } 404 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 405 406 /* allocate and map DMA-safe memory for transmit ring */ 407 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 408 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 409 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 410 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 411 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 412 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 413 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 414 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 415 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 416 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 417 return; 418 } 419 /* allocate and map DMA-safe memory for receive ring */ 420 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 421 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 422 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 423 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 424 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 425 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 426 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 427 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 428 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 429 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 430 return; 431 } 432 for (i = 0; i < JME_NBUFS; i++) { 433 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 434 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 435 JME_NBUFS, JME_MAX_TX_LEN, 0, 436 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 437 &sc->jme_txmbufm[i]) != 0) { 438 aprint_error_dev(self, "can't allocate DMA TX map\n"); 439 return; 440 } 441 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 442 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 443 &sc->jme_rxmbufm[i]) != 0) { 444 aprint_error_dev(self, "can't allocate DMA RX map\n"); 445 return; 446 } 447 } 448 /* 449 * Initialize our media structures and probe the MII. 450 * 451 * Note that we don't care about the media instance. We 452 * are expecting to have multiple PHYs on the 10/100 cards, 453 * and on those cards we exclude the internal PHY from providing 454 * 10baseT. By ignoring the instance, it allows us to not have 455 * to specify it on the command line when switching media. 456 */ 457 mii->mii_ifp = ifp; 458 mii->mii_readreg = jme_mii_read; 459 mii->mii_writereg = jme_mii_write; 460 mii->mii_statchg = jme_statchg; 461 sc->jme_ec.ec_mii = mii; 462 ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange, 463 ether_mediastatus); 464 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 465 if (LIST_FIRST(&mii->mii_phys) == NULL) { 466 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 467 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 468 } else 469 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 470 471 /* 472 * We can support 802.1Q VLAN-sized frames. 473 */ 474 sc->jme_ec.ec_capabilities |= 475 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 476 477 if (sc->jme_flags & JME_FLAG_GIGA) 478 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 479 480 481 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 482 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 483 ifp->if_ioctl = jme_ifioctl; 484 ifp->if_start = jme_ifstart; 485 ifp->if_watchdog = jme_ifwatchdog; 486 ifp->if_init = jme_ifinit; 487 ifp->if_stop = jme_stop; 488 ifp->if_timer = 0; 489 ifp->if_capabilities |= 490 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 491 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 492 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 493 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 494 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 495 IFCAP_TSOv4 | IFCAP_TSOv6; 496 IFQ_SET_READY(&ifp->if_snd); 497 if_attach(ifp); 498 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 499 500 /* 501 * Add shutdown hook so that DMA is disabled prior to reboot. 502 */ 503 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 504 pmf_class_network_register(self, ifp); 505 else 506 aprint_error_dev(self, "couldn't establish power handler\n"); 507 508 rnd_attach_source(&sc->rnd_source, device_xname(self), 509 RND_TYPE_NET, RND_FLAG_DEFAULT); 510 511 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 512 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 513 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 514 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 515 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 516 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 517 SYSCTL_DESCR("jme per-controller controls"), 518 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 519 CTL_EOL) != 0) { 520 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 521 return; 522 } 523 jme_nodenum = node->sysctl_num; 524 525 /* interrupt moderation sysctls */ 526 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 527 CTLFLAG_READWRITE, 528 CTLTYPE_INT, "int_rxto", 529 SYSCTL_DESCR("jme RX interrupt moderation timer"), 530 jme_sysctl_intrxto, 0, (void *)sc, 531 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 532 CTL_EOL) != 0) { 533 aprint_normal_dev(sc->jme_dev, 534 "couldn't create int_rxto sysctl node\n"); 535 } 536 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 537 CTLFLAG_READWRITE, 538 CTLTYPE_INT, "int_rxct", 539 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 540 jme_sysctl_intrxct, 0, (void *)sc, 541 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 542 CTL_EOL) != 0) { 543 aprint_normal_dev(sc->jme_dev, 544 "couldn't create int_rxct sysctl node\n"); 545 } 546 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 547 CTLFLAG_READWRITE, 548 CTLTYPE_INT, "int_txto", 549 SYSCTL_DESCR("jme TX interrupt moderation timer"), 550 jme_sysctl_inttxto, 0, (void *)sc, 551 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 552 CTL_EOL) != 0) { 553 aprint_normal_dev(sc->jme_dev, 554 "couldn't create int_txto sysctl node\n"); 555 } 556 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 557 CTLFLAG_READWRITE, 558 CTLTYPE_INT, "int_txct", 559 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 560 jme_sysctl_inttxct, 0, (void *)sc, 561 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 562 CTL_EOL) != 0) { 563 aprint_normal_dev(sc->jme_dev, 564 "couldn't create int_txct sysctl node\n"); 565 } 566 } 567 568 static void 569 jme_stop_rx(jme_softc_t *sc) 570 { 571 uint32_t reg; 572 int i; 573 574 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 575 if ((reg & RXCSR_RX_ENB) == 0) 576 return; 577 reg &= ~RXCSR_RX_ENB; 578 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 579 for (i = JME_TIMEOUT / 10; i > 0; i--) { 580 DELAY(10); 581 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 582 JME_RXCSR) & RXCSR_RX_ENB) == 0) 583 break; 584 } 585 if (i == 0) 586 aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n"); 587 588 } 589 590 static void 591 jme_stop_tx(jme_softc_t *sc) 592 { 593 uint32_t reg; 594 int i; 595 596 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 597 if ((reg & TXCSR_TX_ENB) == 0) 598 return; 599 reg &= ~TXCSR_TX_ENB; 600 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 601 for (i = JME_TIMEOUT / 10; i > 0; i--) { 602 DELAY(10); 603 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 604 JME_TXCSR) & TXCSR_TX_ENB) == 0) 605 break; 606 } 607 if (i == 0) 608 aprint_error_dev(sc->jme_dev, 609 "stopping transmitter timeout!\n"); 610 } 611 612 static void 613 jme_reset(jme_softc_t *sc) 614 { 615 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 616 DELAY(10); 617 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 618 } 619 620 static bool 621 jme_shutdown(device_t self, int howto) 622 { 623 jme_softc_t *sc; 624 struct ifnet *ifp; 625 626 sc = device_private(self); 627 ifp = &sc->jme_if; 628 jme_stop(ifp, 1); 629 630 return true; 631 } 632 633 static void 634 jme_stop(struct ifnet *ifp, int disable) 635 { 636 jme_softc_t *sc = ifp->if_softc; 637 int i; 638 /* Stop receiver, transmitter. */ 639 jme_stop_rx(sc); 640 jme_stop_tx(sc); 641 /* free receive mbufs */ 642 for (i = 0; i < JME_NBUFS; i++) { 643 if (sc->jme_rxmbuf[i]) { 644 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 645 m_freem(sc->jme_rxmbuf[i]); 646 } 647 sc->jme_rxmbuf[i] = NULL; 648 } 649 /* process completed transmits */ 650 jme_txeof(sc); 651 /* free abort pending transmits */ 652 for (i = 0; i < JME_NBUFS; i++) { 653 if (sc->jme_txmbuf[i]) { 654 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 655 m_freem(sc->jme_txmbuf[i]); 656 sc->jme_txmbuf[i] = NULL; 657 } 658 } 659 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 660 ifp->if_timer = 0; 661 } 662 663 #if 0 664 static void 665 jme_restart(void *v) 666 { 667 668 jme_init(v); 669 } 670 #endif 671 672 static int 673 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 674 { 675 int error; 676 bus_dmamap_t map; 677 int i = sc->jme_rx_prod; 678 679 if (sc->jme_rxmbuf[i] != NULL) { 680 aprint_error_dev(sc->jme_dev, 681 "mbuf already here: rxprod %d rxcons %d\n", 682 sc->jme_rx_prod, sc->jme_rx_cons); 683 if (m) 684 m_freem(m); 685 return EINVAL; 686 } 687 688 if (m == NULL) { 689 sc->jme_rxmbuf[i] = NULL; 690 MGETHDR(m, M_DONTWAIT, MT_DATA); 691 if (m == NULL) 692 return (ENOBUFS); 693 MCLGET(m, M_DONTWAIT); 694 if ((m->m_flags & M_EXT) == 0) { 695 m_freem(m); 696 return (ENOBUFS); 697 } 698 } 699 map = sc->jme_rxmbufm[i]; 700 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 701 KASSERT(m->m_len == MCLBYTES); 702 703 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 704 BUS_DMA_READ | BUS_DMA_NOWAIT); 705 if (error) { 706 sc->jme_rxmbuf[i] = NULL; 707 aprint_error_dev(sc->jme_dev, 708 "unable to load rx DMA map %d, error = %d\n", 709 i, error); 710 m_freem(m); 711 return (error); 712 } 713 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 714 BUS_DMASYNC_PREREAD); 715 716 sc->jme_rxmbuf[i] = m; 717 718 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 719 sc->jme_rxring[i].addr_lo = 720 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 721 sc->jme_rxring[i].addr_hi = 722 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 723 sc->jme_rxring[i].flags = 724 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 725 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 726 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 728 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 729 return (0); 730 } 731 732 static int 733 jme_ifinit(struct ifnet *ifp) 734 { 735 return jme_init(ifp, 1); 736 } 737 738 static int 739 jme_init(struct ifnet *ifp, int do_ifinit) 740 { 741 jme_softc_t *sc = ifp->if_softc; 742 int i, s; 743 uint8_t eaddr[ETHER_ADDR_LEN]; 744 uint32_t reg; 745 746 s = splnet(); 747 /* cancel any pending IO */ 748 jme_stop(ifp, 1); 749 jme_reset(sc); 750 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 751 splx(s); 752 return 0; 753 } 754 /* allocate receive ring */ 755 sc->jme_rx_prod = 0; 756 for (i = 0; i < JME_NBUFS; i++) { 757 if (jme_add_rxbuf(sc, NULL) < 0) { 758 aprint_error_dev(sc->jme_dev, 759 "can't allocate rx mbuf\n"); 760 for (i--; i >= 0; i--) { 761 bus_dmamap_unload(sc->jme_dmatag, 762 sc->jme_rxmbufm[i]); 763 m_freem(sc->jme_rxmbuf[i]); 764 sc->jme_rxmbuf[i] = NULL; 765 } 766 splx(s); 767 return ENOMEM; 768 } 769 } 770 /* init TX ring */ 771 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 772 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 773 0, JME_NBUFS * sizeof(struct jme_desc), 774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 775 for (i = 0; i < JME_NBUFS; i++) 776 sc->jme_txmbuf[i] = NULL; 777 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 778 779 /* Reprogram the station address. */ 780 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 781 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 782 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 783 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 784 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 785 786 /* 787 * Configure Tx queue. 788 * Tx priority queue weight value : 0 789 * Tx FIFO threshold for processing next packet : 16QW 790 * Maximum Tx DMA length : 512 791 * Allow Tx DMA burst. 792 */ 793 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 794 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 795 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 796 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 797 sc->jme_txcsr |= TXCSR_DMA_BURST; 798 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 799 JME_TXCSR, sc->jme_txcsr); 800 801 /* Set Tx descriptor counter. */ 802 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 803 JME_TXQDC, JME_NBUFS); 804 805 /* Set Tx ring address to the hardware. */ 806 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 807 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 808 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 809 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 810 811 /* Configure TxMAC parameters. */ 812 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 813 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 814 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 815 816 /* 817 * Configure Rx queue. 818 * FIFO full threshold for transmitting Tx pause packet : 128T 819 * FIFO threshold for processing next packet : 128QW 820 * Rx queue 0 select 821 * Max Rx DMA length : 128 822 * Rx descriptor retry : 32 823 * Rx descriptor retry time gap : 256ns 824 * Don't receive runt/bad frame. 825 */ 826 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 827 /* 828 * Since Rx FIFO size is 4K bytes, receiving frames larger 829 * than 4K bytes will suffer from Rx FIFO overruns. So 830 * decrease FIFO threshold to reduce the FIFO overruns for 831 * frames larger than 4000 bytes. 832 * For best performance of standard MTU sized frames use 833 * maximum allowable FIFO threshold, 128QW. 834 */ 835 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 836 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 837 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 838 else 839 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 840 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 841 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 842 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 843 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 844 JME_RXCSR, sc->jme_rxcsr); 845 846 /* Set Rx descriptor counter. */ 847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 848 JME_RXQDC, JME_NBUFS); 849 850 /* Set Rx ring address to the hardware. */ 851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 852 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 853 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 854 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 855 856 /* Clear receive filter. */ 857 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 858 /* Set up the receive filter. */ 859 jme_set_filter(sc); 860 861 /* 862 * Disable all WOL bits as WOL can interfere normal Rx 863 * operation. Also clear WOL detection status bits. 864 */ 865 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 866 reg &= ~PMCS_WOL_ENB_MASK; 867 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 868 869 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 870 /* 871 * Pad 10bytes right before received frame. This will greatly 872 * help Rx performance on strict-alignment architectures as 873 * it does not need to copy the frame to align the payload. 874 */ 875 reg |= RXMAC_PAD_10BYTES; 876 if ((ifp->if_capenable & 877 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 878 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0) 879 reg |= RXMAC_CSUM_ENB; 880 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 881 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 882 883 /* Configure general purpose reg0 */ 884 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 885 reg &= ~GPREG0_PCC_UNIT_MASK; 886 /* Set PCC timer resolution to micro-seconds unit. */ 887 reg |= GPREG0_PCC_UNIT_US; 888 /* 889 * Disable all shadow register posting as we have to read 890 * JME_INTR_STATUS register in jme_int_task. Also it seems 891 * that it's hard to synchronize interrupt status between 892 * hardware and software with shadow posting due to 893 * requirements of bus_dmamap_sync(9). 894 */ 895 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 896 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 897 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 898 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 899 /* Disable posting of DW0. */ 900 reg &= ~GPREG0_POST_DW0_ENB; 901 /* Clear PME message. */ 902 reg &= ~GPREG0_PME_ENB; 903 /* Set PHY address. */ 904 reg &= ~GPREG0_PHY_ADDR_MASK; 905 reg |= sc->jme_phyaddr; 906 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 907 908 /* Configure Tx queue 0 packet completion coalescing. */ 909 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 910 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 911 reg |= PCCTX_COAL_TXQ0; 912 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 913 914 /* Configure Rx queue 0 packet completion coalescing. */ 915 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 916 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 917 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 918 919 /* Disable Timers */ 920 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 922 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 923 924 /* Configure retry transmit period, retry limit value. */ 925 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 926 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 927 TXTRHD_RT_PERIOD_MASK) | 928 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 929 TXTRHD_RT_LIMIT_SHIFT)); 930 931 /* Disable RSS. */ 932 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 933 JME_RSSC, RSSC_DIS_RSS); 934 935 /* Initialize the interrupt mask. */ 936 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 937 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 938 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 939 JME_INTR_STATUS, 0xFFFFFFFF); 940 941 /* set media, if not already handling a media change */ 942 if (do_ifinit) { 943 int error; 944 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 945 error = 0; 946 else if (error != 0) { 947 aprint_error_dev(sc->jme_dev, "could not set media\n"); 948 splx(s); 949 return error; 950 } 951 } 952 953 /* Program MAC with resolved speed/duplex/flow-control. */ 954 jme_mac_config(sc); 955 956 /* Start receiver/transmitter. */ 957 sc->jme_rx_cons = 0; 958 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 959 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 960 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 961 sc->jme_txcsr | TXCSR_TX_ENB); 962 963 /* start ticks calls */ 964 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 965 sc->jme_if.if_flags |= IFF_RUNNING; 966 sc->jme_if.if_flags &= ~IFF_OACTIVE; 967 splx(s); 968 return 0; 969 } 970 971 972 int 973 jme_mii_read(device_t self, int phy, int reg, uint16_t *val) 974 { 975 struct jme_softc *sc = device_private(self); 976 int data, i; 977 978 /* For FPGA version, PHY address 0 should be ignored. */ 979 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 980 if (phy == 0) 981 return -1; 982 } else { 983 if (sc->jme_phyaddr != phy) 984 return -1; 985 } 986 987 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 988 SMI_OP_READ | SMI_OP_EXECUTE | 989 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 990 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 991 delay(10); 992 if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 993 JME_SMI)) & SMI_OP_EXECUTE) == 0) 994 break; 995 } 996 997 if (i == 0) { 998 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 999 return ETIMEDOUT; 1000 } 1001 1002 *val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 1003 return 0; 1004 } 1005 1006 int 1007 jme_mii_write(device_t self, int phy, int reg, uint16_t val) 1008 { 1009 struct jme_softc *sc = device_private(self); 1010 int i; 1011 1012 /* For FPGA version, PHY address 0 should be ignored. */ 1013 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1014 if (phy == 0) 1015 return -1; 1016 } else { 1017 if (sc->jme_phyaddr != phy) 1018 return -1; 1019 } 1020 1021 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1022 SMI_OP_WRITE | SMI_OP_EXECUTE | 1023 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1024 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1025 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1026 delay(10); 1027 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1028 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1029 break; 1030 } 1031 1032 if (i == 0) { 1033 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1034 return ETIMEDOUT; 1035 } 1036 1037 return 0; 1038 } 1039 1040 void 1041 jme_statchg(struct ifnet *ifp) 1042 { 1043 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1044 jme_init(ifp, 0); 1045 } 1046 1047 static void 1048 jme_intr_rx(jme_softc_t *sc) { 1049 struct mbuf *m, *mhead; 1050 bus_dmamap_t mmap; 1051 struct ifnet *ifp = &sc->jme_if; 1052 uint32_t flags, buflen; 1053 int i, ipackets, nsegs, seg, error; 1054 struct jme_desc *desc; 1055 1056 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1057 sizeof(struct jme_desc) * JME_NBUFS, 1058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1059 #ifdef JMEDEBUG_RX 1060 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1061 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1062 #endif 1063 ipackets = 0; 1064 while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1065 == 0) { 1066 i = sc->jme_rx_cons; 1067 desc = &sc->jme_rxring[i]; 1068 #ifdef JMEDEBUG_RX 1069 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1070 i, le32toh(desc->flags), le32toh(desc->buflen)); 1071 #endif 1072 if (sc->jme_rxmbuf[i] == NULL) { 1073 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1074 aprint_error_dev(sc->jme_dev, 1075 "can't add new mbuf to empty slot: %d\n", 1076 error); 1077 break; 1078 } 1079 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1080 i = sc->jme_rx_cons; 1081 continue; 1082 } 1083 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1084 break; 1085 1086 buflen = le32toh(desc->buflen); 1087 nsegs = JME_RX_NSEGS(buflen); 1088 flags = le32toh(desc->flags); 1089 if ((buflen & JME_RX_ERR_STAT) != 0 || 1090 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1091 JME_RX_BYTES(buflen) > 1092 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1093 #ifdef JMEDEBUG_RX 1094 printf("rx error flags 0x%x buflen 0x%x\n", 1095 flags, buflen); 1096 #endif 1097 ifp->if_ierrors++; 1098 /* reuse the mbufs */ 1099 for (seg = 0; seg < nsegs; seg++) { 1100 m = sc->jme_rxmbuf[i]; 1101 sc->jme_rxmbuf[i] = NULL; 1102 mmap = sc->jme_rxmbufm[i]; 1103 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1104 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1105 bus_dmamap_unload(sc->jme_dmatag, mmap); 1106 if ((error = jme_add_rxbuf(sc, m)) != 0) 1107 aprint_error_dev(sc->jme_dev, 1108 "can't reuse mbuf: %d\n", error); 1109 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1110 i = sc->jme_rx_cons; 1111 } 1112 continue; 1113 } 1114 /* receive this packet */ 1115 mhead = m = sc->jme_rxmbuf[i]; 1116 sc->jme_rxmbuf[i] = NULL; 1117 mmap = sc->jme_rxmbufm[i]; 1118 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1119 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1120 bus_dmamap_unload(sc->jme_dmatag, mmap); 1121 /* add a new buffer to chain */ 1122 if (jme_add_rxbuf(sc, NULL) != 0) { 1123 if ((error = jme_add_rxbuf(sc, m)) != 0) 1124 aprint_error_dev(sc->jme_dev, 1125 "can't reuse mbuf: %d\n", error); 1126 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1127 i = sc->jme_rx_cons; 1128 for (seg = 1; seg < nsegs; seg++) { 1129 m = sc->jme_rxmbuf[i]; 1130 sc->jme_rxmbuf[i] = NULL; 1131 mmap = sc->jme_rxmbufm[i]; 1132 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1133 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1134 bus_dmamap_unload(sc->jme_dmatag, mmap); 1135 if ((error = jme_add_rxbuf(sc, m)) != 0) 1136 aprint_error_dev(sc->jme_dev, 1137 "can't reuse mbuf: %d\n", error); 1138 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1139 i = sc->jme_rx_cons; 1140 } 1141 ifp->if_ierrors++; 1142 continue; 1143 } 1144 1145 /* build mbuf chain: head, then remaining segments */ 1146 m_set_rcvif(m, ifp); 1147 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1148 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1149 m->m_pkthdr.len; 1150 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1151 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1152 for (seg = 1; seg < nsegs; seg++) { 1153 i = sc->jme_rx_cons; 1154 m = sc->jme_rxmbuf[i]; 1155 sc->jme_rxmbuf[i] = NULL; 1156 mmap = sc->jme_rxmbufm[i]; 1157 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1158 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1159 bus_dmamap_unload(sc->jme_dmatag, mmap); 1160 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1161 aprint_error_dev(sc->jme_dev, 1162 "can't add new mbuf: %d\n", error); 1163 m->m_flags &= ~M_PKTHDR; 1164 m_cat(mhead, m); 1165 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1166 } 1167 /* and adjust last mbuf's size */ 1168 if (nsegs > 1) { 1169 m->m_len = 1170 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1171 } 1172 ipackets++; 1173 1174 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1175 (flags & JME_RD_IPV4)) { 1176 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1177 if (!(flags & JME_RD_IPCSUM)) 1178 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1179 } 1180 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1181 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1182 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1183 if (!(flags & JME_RD_TCPCSUM)) 1184 mhead->m_pkthdr.csum_flags |= 1185 M_CSUM_TCP_UDP_BAD; 1186 } 1187 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1188 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1189 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1190 if (!(flags & JME_RD_UDPCSUM)) 1191 mhead->m_pkthdr.csum_flags |= 1192 M_CSUM_TCP_UDP_BAD; 1193 } 1194 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1195 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1196 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1197 if (!(flags & JME_RD_TCPCSUM)) 1198 mhead->m_pkthdr.csum_flags |= 1199 M_CSUM_TCP_UDP_BAD; 1200 } 1201 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1202 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1203 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1204 if (!(flags & JME_RD_UDPCSUM)) 1205 mhead->m_pkthdr.csum_flags |= 1206 M_CSUM_TCP_UDP_BAD; 1207 } 1208 if (flags & JME_RD_VLAN_TAG) { 1209 /* pass to vlan_input() */ 1210 vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK)); 1211 } 1212 if_percpuq_enqueue(ifp->if_percpuq, mhead); 1213 } 1214 if (ipackets) 1215 rnd_add_uint32(&sc->rnd_source, ipackets); 1216 } 1217 1218 static int 1219 jme_intr(void *v) 1220 { 1221 jme_softc_t *sc = v; 1222 uint32_t istatus; 1223 1224 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1225 JME_INTR_STATUS); 1226 if (istatus == 0 || istatus == 0xFFFFFFFF) 1227 return 0; 1228 /* Disable interrupts. */ 1229 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1230 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1231 again: 1232 /* and update istatus */ 1233 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1234 JME_INTR_STATUS); 1235 if ((istatus & JME_INTRS_CHECK) == 0) 1236 goto done; 1237 /* Reset PCC counter/timer and Ack interrupts. */ 1238 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1239 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1240 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1241 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1242 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1243 JME_INTR_STATUS, istatus); 1244 1245 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1246 goto done; 1247 #ifdef JMEDEBUG_RX 1248 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1249 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1250 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1251 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1252 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1253 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1254 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1255 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1256 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1257 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1258 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1259 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1260 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1261 #endif 1262 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1263 jme_intr_rx(sc); 1264 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1265 /* 1266 * Notify hardware availability of new Rx 1267 * buffers. 1268 * Reading RXCSR takes very long time under 1269 * heavy load so cache RXCSR value and writes 1270 * the ORed value with the kick command to 1271 * the RXCSR. This saves one register access 1272 * cycle. 1273 */ 1274 sc->jme_rx_cons = 0; 1275 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1276 JME_RXCSR, 1277 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1278 } 1279 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1280 jme_ifstart(&sc->jme_if); 1281 1282 goto again; 1283 1284 done: 1285 /* enable interrupts. */ 1286 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1287 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1288 return 1; 1289 } 1290 1291 1292 static int 1293 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1294 { 1295 struct jme_softc *sc = ifp->if_softc; 1296 int s, error; 1297 struct ifreq *ifr; 1298 struct ifcapreq *ifcr; 1299 1300 s = splnet(); 1301 /* 1302 * we can't support at the same time jumbo frames and 1303 * TX checksums offload/TSO 1304 */ 1305 switch (cmd) { 1306 case SIOCSIFMTU: 1307 ifr = data; 1308 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1309 (ifp->if_capenable & ( 1310 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1311 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1312 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1313 splx(s); 1314 return EINVAL; 1315 } 1316 break; 1317 case SIOCSIFCAP: 1318 ifcr = data; 1319 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1320 (ifcr->ifcr_capenable & ( 1321 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1322 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1323 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1324 splx(s); 1325 return EINVAL; 1326 } 1327 break; 1328 } 1329 1330 error = ether_ioctl(ifp, cmd, data); 1331 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1332 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1333 jme_set_filter(sc); 1334 error = 0; 1335 } else { 1336 error = jme_init(ifp, 0); 1337 } 1338 } 1339 splx(s); 1340 return error; 1341 } 1342 1343 static int 1344 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1345 { 1346 struct jme_desc *desc; 1347 struct mbuf *m; 1348 int error, i, prod, headdsc, nsegs; 1349 uint32_t cflags, tso_segsz; 1350 1351 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) 1352 != 0) { 1353 /* 1354 * Due to the adherence to NDIS specification JMC250 1355 * assumes upper stack computed TCP pseudo checksum 1356 * without including payload length. This breaks 1357 * checksum offload for TSO case so recompute TCP 1358 * pseudo checksum for JMC250. Hopefully this wouldn't 1359 * be much burden on modern CPUs. 1360 */ 1361 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1362 int iphl = v4 ? 1363 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1364 M_CSUM_DATA_IPv6_IPHL((*m_head)->m_pkthdr.csum_data); 1365 /* 1366 * note: we support vlan offloading, so we should never have 1367 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1368 * right. 1369 */ 1370 int hlen = ETHER_HDR_LEN + iphl; 1371 1372 if (__predict_false((*m_head)->m_len < 1373 (hlen + sizeof(struct tcphdr)))) { 1374 /* 1375 * TCP/IP headers are not in the first mbuf; we need 1376 * to do this the slow and painful way. Let's just 1377 * hope this doesn't happen very often. 1378 */ 1379 struct tcphdr th; 1380 1381 m_copydata((*m_head), hlen, sizeof(th), &th); 1382 if (v4) { 1383 struct ip ip; 1384 1385 m_copydata((*m_head), ETHER_HDR_LEN, 1386 sizeof(ip), &ip); 1387 ip.ip_len = 0; 1388 m_copyback((*m_head), 1389 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1390 sizeof(ip.ip_len), &ip.ip_len); 1391 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1392 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1393 } else { 1394 #if INET6 1395 struct ip6_hdr ip6; 1396 1397 m_copydata((*m_head), ETHER_HDR_LEN, 1398 sizeof(ip6), &ip6); 1399 ip6.ip6_plen = 0; 1400 m_copyback((*m_head), ETHER_HDR_LEN + 1401 offsetof(struct ip6_hdr, ip6_plen), 1402 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1403 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1404 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1405 #endif /* INET6 */ 1406 } 1407 m_copyback((*m_head), 1408 hlen + offsetof(struct tcphdr, th_sum), 1409 sizeof(th.th_sum), &th.th_sum); 1410 1411 hlen += th.th_off << 2; 1412 } else { 1413 /* 1414 * TCP/IP headers are in the first mbuf; we can do 1415 * this the easy way. 1416 */ 1417 struct tcphdr *th; 1418 1419 if (v4) { 1420 struct ip *ip = 1421 (void *)(mtod((*m_head), char *) + 1422 ETHER_HDR_LEN); 1423 th = (void *)(mtod((*m_head), char *) + hlen); 1424 1425 ip->ip_len = 0; 1426 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1427 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1428 } else { 1429 #if INET6 1430 struct ip6_hdr *ip6 = 1431 (void *)(mtod((*m_head), char *) + 1432 ETHER_HDR_LEN); 1433 th = (void *)(mtod((*m_head), char *) + hlen); 1434 1435 ip6->ip6_plen = 0; 1436 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1437 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1438 #endif /* INET6 */ 1439 } 1440 hlen += th->th_off << 2; 1441 } 1442 1443 } 1444 1445 prod = sc->jme_tx_prod; 1446 1447 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1448 *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1449 if (error) { 1450 if (error == EFBIG) { 1451 log(LOG_ERR, "%s: Tx packet consumes too many " 1452 "DMA segments, dropping...\n", 1453 device_xname(sc->jme_dev)); 1454 m_freem(*m_head); 1455 m_head = NULL; 1456 } 1457 return (error); 1458 } 1459 /* 1460 * Check descriptor overrun. Leave one free descriptor. 1461 * Since we always use 64bit address mode for transmitting, 1462 * each Tx request requires one more dummy descriptor. 1463 */ 1464 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1465 #ifdef JMEDEBUG_TX 1466 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1467 #endif 1468 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1469 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1470 return (ENOBUFS); 1471 } 1472 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1473 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1474 1475 m = *m_head; 1476 cflags = 0; 1477 tso_segsz = 0; 1478 /* Configure checksum offload and TSO. */ 1479 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1480 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1481 cflags |= JME_TD_TSO; 1482 } else { 1483 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1484 cflags |= JME_TD_IPCSUM; 1485 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) 1486 != 0) 1487 cflags |= JME_TD_TCPCSUM; 1488 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) 1489 != 0) 1490 cflags |= JME_TD_UDPCSUM; 1491 } 1492 /* Configure VLAN. */ 1493 if (vlan_has_tag(m)) { 1494 cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK); 1495 cflags |= JME_TD_VLAN_TAG; 1496 } 1497 1498 desc = &sc->jme_txring[prod]; 1499 desc->flags = htole32(cflags); 1500 desc->buflen = htole32(tso_segsz); 1501 desc->addr_hi = htole32(m->m_pkthdr.len); 1502 desc->addr_lo = 0; 1503 headdsc = prod; 1504 sc->jme_tx_cnt++; 1505 JME_DESC_INC(prod, JME_NBUFS); 1506 for (i = 0; i < nsegs; i++) { 1507 desc = &sc->jme_txring[prod]; 1508 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1509 desc->buflen = 1510 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1511 desc->addr_hi = htole32( 1512 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1513 desc->addr_lo = htole32( 1514 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1515 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1516 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1517 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1518 sc->jme_txmbuf[prod] = NULL; 1519 sc->jme_tx_cnt++; 1520 JME_DESC_INC(prod, JME_NBUFS); 1521 } 1522 1523 /* Update producer index. */ 1524 sc->jme_tx_prod = prod; 1525 #ifdef JMEDEBUG_TX 1526 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1527 #endif 1528 /* 1529 * Finally request interrupt and give the first descriptor 1530 * ownership to hardware. 1531 */ 1532 desc = &sc->jme_txring[headdsc]; 1533 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1534 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1535 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1536 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1537 1538 sc->jme_txmbuf[headdsc] = m; 1539 return (0); 1540 } 1541 1542 static void 1543 jme_txeof(struct jme_softc *sc) 1544 { 1545 struct ifnet *ifp; 1546 struct jme_desc *desc; 1547 uint32_t status; 1548 int cons, cons0, nsegs, seg; 1549 1550 ifp = &sc->jme_if; 1551 1552 #ifdef JMEDEBUG_TX 1553 printf("jme_txeof cons %d prod %d\n", 1554 sc->jme_tx_cons, sc->jme_tx_prod); 1555 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1556 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1557 "JME_TXTRHD 0x%x\n", 1558 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1559 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1560 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1561 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1562 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1563 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1564 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1565 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1566 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1567 desc = &sc->jme_txring[cons]; 1568 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1569 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1570 JME_DESC_INC(cons, JME_NBUFS); 1571 } 1572 #endif 1573 1574 cons = sc->jme_tx_cons; 1575 if (cons == sc->jme_tx_prod) 1576 return; 1577 1578 /* 1579 * Go through our Tx list and free mbufs for those 1580 * frames which have been transmitted. 1581 */ 1582 for (; cons != sc->jme_tx_prod;) { 1583 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1584 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1585 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1586 1587 desc = &sc->jme_txring[cons]; 1588 status = le32toh(desc->flags); 1589 #ifdef JMEDEBUG_TX 1590 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1591 sc->jme_txmbufm[cons]->dm_nsegs); 1592 #endif 1593 if (status & JME_TD_OWN) 1594 break; 1595 1596 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1597 ifp->if_oerrors++; 1598 else { 1599 ifp->if_opackets++; 1600 if ((status & JME_TD_COLLISION) != 0) 1601 ifp->if_collisions += 1602 le32toh(desc->buflen) & 1603 JME_TD_BUF_LEN_MASK; 1604 } 1605 /* 1606 * Only the first descriptor of multi-descriptor 1607 * transmission is updated so driver have to skip entire 1608 * chained buffers for the transmitted frame. In other 1609 * words, JME_TD_OWN bit is valid only at the first 1610 * descriptor of a multi-descriptor transmission. 1611 */ 1612 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1613 cons0 = cons; 1614 JME_DESC_INC(cons, JME_NBUFS); 1615 for (seg = 1; seg < nsegs + 1; seg++) { 1616 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1617 cons * sizeof(struct jme_desc), 1618 sizeof(struct jme_desc), 1619 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1620 sc->jme_txring[cons].flags = 0; 1621 JME_DESC_INC(cons, JME_NBUFS); 1622 } 1623 /* Reclaim transferred mbufs. */ 1624 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1625 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1626 BUS_DMASYNC_POSTWRITE); 1627 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1628 1629 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1630 m_freem(sc->jme_txmbuf[cons0]); 1631 sc->jme_txmbuf[cons0] = NULL; 1632 sc->jme_tx_cnt -= nsegs + 1; 1633 KASSERT(sc->jme_tx_cnt >= 0); 1634 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1635 } 1636 sc->jme_tx_cons = cons; 1637 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1638 if (sc->jme_tx_cnt == 0) 1639 ifp->if_timer = 0; 1640 #ifdef JMEDEBUG_TX 1641 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1642 #endif 1643 } 1644 1645 static void 1646 jme_ifstart(struct ifnet *ifp) 1647 { 1648 jme_softc_t *sc = ifp->if_softc; 1649 struct mbuf *mb_head; 1650 int enq; 1651 1652 /* 1653 * check if we can free some desc. 1654 * Clear TX interrupt status to reset TX coalescing counters. 1655 */ 1656 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1657 JME_INTR_STATUS, INTR_TXQ_COMP); 1658 jme_txeof(sc); 1659 1660 if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1661 return; 1662 for (enq = 0;; enq++) { 1663 nexttx: 1664 /* Grab a paquet for output */ 1665 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1666 if (mb_head == NULL) { 1667 #ifdef JMEDEBUG_TX 1668 printf("%s: nothing to send\n", __func__); 1669 #endif 1670 break; 1671 } 1672 /* try to add this mbuf to the TX ring */ 1673 if (jme_encap(sc, &mb_head)) { 1674 if (mb_head == NULL) { 1675 ifp->if_oerrors++; 1676 /* packet dropped, try next one */ 1677 goto nexttx; 1678 } 1679 /* resource shortage, try again later */ 1680 IF_PREPEND(&ifp->if_snd, mb_head); 1681 ifp->if_flags |= IFF_OACTIVE; 1682 break; 1683 } 1684 /* Pass packet to bpf if there is a listener */ 1685 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1686 } 1687 #ifdef JMEDEBUG_TX 1688 printf("jme_ifstart enq %d\n", enq); 1689 #endif 1690 if (enq) { 1691 /* 1692 * Set a 5 second timer just in case we don't hear from 1693 * the card again. 1694 */ 1695 ifp->if_timer = 5; 1696 /* 1697 * Reading TXCSR takes very long time under heavy load 1698 * so cache TXCSR value and writes the ORed value with 1699 * the kick command to the TXCSR. This saves one register 1700 * access cycle. 1701 */ 1702 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1703 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1704 #ifdef JMEDEBUG_TX 1705 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1706 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1707 "JME_TXTRHD 0x%x\n", 1708 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1709 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1710 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1711 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1712 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1713 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1714 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1715 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1716 #endif 1717 } 1718 } 1719 1720 static void 1721 jme_ifwatchdog(struct ifnet *ifp) 1722 { 1723 jme_softc_t *sc = ifp->if_softc; 1724 1725 if ((ifp->if_flags & IFF_RUNNING) == 0) 1726 return; 1727 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1728 ifp->if_oerrors++; 1729 jme_init(ifp, 0); 1730 } 1731 1732 static int 1733 jme_mediachange(struct ifnet *ifp) 1734 { 1735 int error; 1736 jme_softc_t *sc = ifp->if_softc; 1737 1738 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1739 error = 0; 1740 else if (error != 0) { 1741 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1742 return error; 1743 } 1744 return 0; 1745 } 1746 1747 static void 1748 jme_ticks(void *v) 1749 { 1750 jme_softc_t *sc = v; 1751 int s = splnet(); 1752 1753 /* Tick the MII. */ 1754 mii_tick(&sc->jme_mii); 1755 1756 /* every seconds */ 1757 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1758 splx(s); 1759 } 1760 1761 static void 1762 jme_mac_config(jme_softc_t *sc) 1763 { 1764 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1765 struct mii_data *mii = &sc->jme_mii; 1766 1767 ghc = 0; 1768 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1769 rxmac &= ~RXMAC_FC_ENB; 1770 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1771 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1772 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1773 txpause &= ~TXPFC_PAUSE_ENB; 1774 1775 if (mii->mii_media_active & IFM_FDX) { 1776 ghc |= GHC_FULL_DUPLEX; 1777 rxmac &= ~RXMAC_COLL_DET_ENB; 1778 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1779 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1780 TXMAC_FRAME_BURST); 1781 /* Disable retry transmit timer/retry limit. */ 1782 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1783 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1784 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1785 } else { 1786 rxmac |= RXMAC_COLL_DET_ENB; 1787 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1788 /* Enable retry transmit timer/retry limit. */ 1789 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1790 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1791 } 1792 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1793 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1794 case IFM_10_T: 1795 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1796 break; 1797 case IFM_100_TX: 1798 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1799 break; 1800 case IFM_1000_T: 1801 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1802 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1803 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1804 break; 1805 default: 1806 break; 1807 } 1808 if ((sc->jme_flags & JME_FLAG_GIGA) && 1809 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1810 /* 1811 * Workaround occasional packet loss issue of JMC250 A2 1812 * when it runs on half-duplex media. 1813 */ 1814 #ifdef JMEDEBUG 1815 printf("JME250 A2 workaround\n"); 1816 #endif 1817 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1818 JME_GPREG1); 1819 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1820 gpreg &= ~GPREG1_HDPX_FIX; 1821 else 1822 gpreg |= GPREG1_HDPX_FIX; 1823 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1824 JME_GPREG1, gpreg); 1825 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1826 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1827 /* Extend interface FIFO depth. */ 1828 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1829 0x1B, 0x0000); 1830 } else { 1831 /* Select default interface FIFO depth. */ 1832 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1833 0x1B, 0x0004); 1834 } 1835 } 1836 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1837 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1838 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1839 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1840 } 1841 1842 static void 1843 jme_set_filter(jme_softc_t *sc) 1844 { 1845 struct ethercom *ec = &sc->jme_ec; 1846 struct ifnet *ifp = &sc->jme_if; 1847 struct ether_multistep step; 1848 struct ether_multi *enm; 1849 uint32_t hash[2] = {0, 0}; 1850 int i; 1851 uint32_t rxcfg; 1852 1853 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1854 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1855 RXMAC_ALLMULTI); 1856 /* Always accept frames destined to our station address. */ 1857 rxcfg |= RXMAC_UNICAST; 1858 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1859 rxcfg |= RXMAC_BROADCAST; 1860 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1861 if ((ifp->if_flags & IFF_PROMISC) != 0) 1862 rxcfg |= RXMAC_PROMISC; 1863 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1864 rxcfg |= RXMAC_ALLMULTI; 1865 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1866 JME_MAR0, 0xFFFFFFFF); 1867 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1868 JME_MAR1, 0xFFFFFFFF); 1869 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1870 JME_RXMAC, rxcfg); 1871 return; 1872 } 1873 /* 1874 * Set up the multicast address filter by passing all multicast 1875 * addresses through a CRC generator, and then using the low-order 1876 * 6 bits as an index into the 64 bit multicast hash table. The 1877 * high order bits select the register, while the rest of the bits 1878 * select the bit within the register. 1879 */ 1880 rxcfg |= RXMAC_MULTICAST; 1881 memset(hash, 0, sizeof(hash)); 1882 1883 ETHER_LOCK(ec); 1884 ETHER_FIRST_MULTI(step, ec, enm); 1885 while (enm != NULL) { 1886 #ifdef JEMDBUG 1887 printf("%s: addrs %s %s\n", __func__, 1888 ether_sprintf(enm->enm_addrlo), 1889 ether_sprintf(enm->enm_addrhi)); 1890 #endif 1891 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1892 i = ether_crc32_be(enm->enm_addrlo, 6); 1893 /* Just want the 6 least significant bits. */ 1894 i &= 0x3f; 1895 hash[i / 32] |= 1 << (i%32); 1896 } else { 1897 hash[0] = hash[1] = 0xffffffff; 1898 sc->jme_if.if_flags |= IFF_ALLMULTI; 1899 break; 1900 } 1901 ETHER_NEXT_MULTI(step, enm); 1902 } 1903 ETHER_UNLOCK(ec); 1904 #ifdef JMEDEBUG 1905 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1906 #endif 1907 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1908 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1909 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1910 } 1911 1912 #if 0 1913 static int 1914 jme_multicast_hash(uint8_t *a) 1915 { 1916 int hash; 1917 1918 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1919 #define xor8(a,b,c,d,e,f,g,h) \ 1920 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1921 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1922 1923 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1924 DA(a,36), DA(a,42)); 1925 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1926 DA(a,37), DA(a,43)) << 1; 1927 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1928 DA(a,38), DA(a,44)) << 2; 1929 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1930 DA(a,39), DA(a,45)) << 3; 1931 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1932 DA(a,40), DA(a,46)) << 4; 1933 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1934 DA(a,41), DA(a,47)) << 5; 1935 1936 return hash; 1937 } 1938 #endif 1939 1940 static int 1941 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1942 { 1943 uint32_t reg; 1944 int i; 1945 1946 *val = 0; 1947 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1948 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1949 JME_SMBCSR); 1950 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1951 break; 1952 delay(10); 1953 } 1954 1955 if (i == 0) { 1956 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1957 return (ETIMEDOUT); 1958 } 1959 1960 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1961 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1962 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1963 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1964 delay(10); 1965 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1966 JME_SMBINTF); 1967 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1968 break; 1969 } 1970 1971 if (i == 0) { 1972 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1973 return (ETIMEDOUT); 1974 } 1975 1976 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1977 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1978 return (0); 1979 } 1980 1981 1982 static int 1983 jme_eeprom_macaddr(struct jme_softc *sc) 1984 { 1985 uint8_t eaddr[ETHER_ADDR_LEN]; 1986 uint8_t fup, reg, val; 1987 uint32_t offset; 1988 int match; 1989 1990 offset = 0; 1991 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1992 fup != JME_EEPROM_SIG0) 1993 return (ENOENT); 1994 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1995 fup != JME_EEPROM_SIG1) 1996 return (ENOENT); 1997 match = 0; 1998 do { 1999 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 2000 break; 2001 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 2002 == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 2003 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 2004 break; 2005 if (reg >= JME_PAR0 && 2006 reg < JME_PAR0 + ETHER_ADDR_LEN) { 2007 if (jme_eeprom_read_byte(sc, offset + 2, 2008 &val) != 0) 2009 break; 2010 eaddr[reg - JME_PAR0] = val; 2011 match++; 2012 } 2013 } 2014 if (fup & JME_EEPROM_DESC_END) 2015 break; 2016 2017 /* Try next eeprom descriptor. */ 2018 offset += JME_EEPROM_DESC_BYTES; 2019 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2020 2021 if (match == ETHER_ADDR_LEN) { 2022 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2023 return (0); 2024 } 2025 2026 return (ENOENT); 2027 } 2028 2029 static int 2030 jme_reg_macaddr(struct jme_softc *sc) 2031 { 2032 uint32_t par0, par1; 2033 2034 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2035 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2036 par1 &= 0xffff; 2037 if ((par0 == 0 && par1 == 0) || 2038 (par0 == 0xffffffff && par1 == 0xffff)) { 2039 return (ENOENT); 2040 } else { 2041 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2042 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2043 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2044 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2045 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2046 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2047 } 2048 return (0); 2049 } 2050 2051 /* 2052 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2053 * set up in jme_pci_attach() 2054 */ 2055 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2056 { 2057 int rc; 2058 const struct sysctlnode *node; 2059 2060 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2061 0, CTLTYPE_NODE, "jme", 2062 SYSCTL_DESCR("jme interface controls"), 2063 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2064 goto err; 2065 } 2066 2067 jme_root_num = node->sysctl_num; 2068 return; 2069 2070 err: 2071 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2072 } 2073 2074 static int 2075 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2076 { 2077 int error, t; 2078 struct sysctlnode node; 2079 struct jme_softc *sc; 2080 uint32_t reg; 2081 2082 node = *rnode; 2083 sc = node.sysctl_data; 2084 t = sc->jme_intrxto; 2085 node.sysctl_data = &t; 2086 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2087 if (error || newp == NULL) 2088 return error; 2089 2090 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2091 return EINVAL; 2092 2093 /* 2094 * update the softc with sysctl-changed value, and mark 2095 * for hardware update 2096 */ 2097 sc->jme_intrxto = t; 2098 /* Configure Rx queue 0 packet completion coalescing. */ 2099 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2100 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2101 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2102 return 0; 2103 } 2104 2105 static int 2106 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2107 { 2108 int error, t; 2109 struct sysctlnode node; 2110 struct jme_softc *sc; 2111 uint32_t reg; 2112 2113 node = *rnode; 2114 sc = node.sysctl_data; 2115 t = sc->jme_intrxct; 2116 node.sysctl_data = &t; 2117 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2118 if (error || newp == NULL) 2119 return error; 2120 2121 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2122 return EINVAL; 2123 2124 /* 2125 * update the softc with sysctl-changed value, and mark 2126 * for hardware update 2127 */ 2128 sc->jme_intrxct = t; 2129 /* Configure Rx queue 0 packet completion coalescing. */ 2130 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2131 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2132 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2133 return 0; 2134 } 2135 2136 static int 2137 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2138 { 2139 int error, t; 2140 struct sysctlnode node; 2141 struct jme_softc *sc; 2142 uint32_t reg; 2143 2144 node = *rnode; 2145 sc = node.sysctl_data; 2146 t = sc->jme_inttxto; 2147 node.sysctl_data = &t; 2148 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2149 if (error || newp == NULL) 2150 return error; 2151 2152 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2153 return EINVAL; 2154 2155 /* 2156 * update the softc with sysctl-changed value, and mark 2157 * for hardware update 2158 */ 2159 sc->jme_inttxto = t; 2160 /* Configure Tx queue 0 packet completion coalescing. */ 2161 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2162 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2163 reg |= PCCTX_COAL_TXQ0; 2164 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2165 return 0; 2166 } 2167 2168 static int 2169 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2170 { 2171 int error, t; 2172 struct sysctlnode node; 2173 struct jme_softc *sc; 2174 uint32_t reg; 2175 2176 node = *rnode; 2177 sc = node.sysctl_data; 2178 t = sc->jme_inttxct; 2179 node.sysctl_data = &t; 2180 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2181 if (error || newp == NULL) 2182 return error; 2183 2184 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2185 return EINVAL; 2186 2187 /* 2188 * update the softc with sysctl-changed value, and mark 2189 * for hardware update 2190 */ 2191 sc->jme_inttxct = t; 2192 /* Configure Tx queue 0 packet completion coalescing. */ 2193 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2194 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2195 reg |= PCCTX_COAL_TXQ0; 2196 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2197 return 0; 2198 } 2199